Commit | Line | Data |
---|---|---|
21335d02 | 1 | |
1da177e4 | 2 | /* |
1f729e06 | 3 | * (c) 2003-2006 Advanced Micro Devices, Inc. |
1da177e4 LT |
4 | * Your use of this code is subject to the terms and conditions of the |
5 | * GNU general public license version 2. See "COPYING" or | |
6 | * http://www.gnu.org/licenses/gpl.html | |
7 | * | |
065b807c | 8 | * Support : mark.langsdorf@amd.com |
1da177e4 LT |
9 | * |
10 | * Based on the powernow-k7.c module written by Dave Jones. | |
f4432c5c | 11 | * (C) 2003 Dave Jones on behalf of SuSE Labs |
1da177e4 LT |
12 | * (C) 2004 Dominik Brodowski <linux@brodo.de> |
13 | * (C) 2004 Pavel Machek <pavel@suse.cz> | |
14 | * Licensed under the terms of the GNU GPL License version 2. | |
15 | * Based upon datasheets & sample CPUs kindly provided by AMD. | |
16 | * | |
17 | * Valuable input gratefully received from Dave Jones, Pavel Machek, | |
1f729e06 | 18 | * Dominik Brodowski, Jacob Shin, and others. |
065b807c | 19 | * Originally developed by Paul Devriendt. |
1da177e4 LT |
20 | * Processor information obtained from Chapter 9 (Power and Thermal Management) |
21 | * of the "BIOS and Kernel Developer's Guide for the AMD Athlon 64 and AMD | |
22 | * Opteron Processors" available for download from www.amd.com | |
23 | * | |
2e3f8faa | 24 | * Tables for specific CPUs can be inferred from |
065b807c | 25 | * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/30430.pdf |
1da177e4 LT |
26 | */ |
27 | ||
28 | #include <linux/kernel.h> | |
29 | #include <linux/smp.h> | |
30 | #include <linux/module.h> | |
31 | #include <linux/init.h> | |
32 | #include <linux/cpufreq.h> | |
33 | #include <linux/slab.h> | |
34 | #include <linux/string.h> | |
065b807c | 35 | #include <linux/cpumask.h> |
4e57b681 | 36 | #include <linux/sched.h> /* for current / set_cpus_allowed() */ |
0e64a0c9 DJ |
37 | #include <linux/io.h> |
38 | #include <linux/delay.h> | |
1da177e4 LT |
39 | |
40 | #include <asm/msr.h> | |
1da177e4 | 41 | |
1da177e4 | 42 | #include <linux/acpi.h> |
14cc3e2b | 43 | #include <linux/mutex.h> |
1da177e4 | 44 | #include <acpi/processor.h> |
1da177e4 LT |
45 | |
46 | #define PFX "powernow-k8: " | |
c5829cd0 | 47 | #define VERSION "version 2.20.00" |
1da177e4 LT |
48 | #include "powernow-k8.h" |
49 | ||
50 | /* serialize freq changes */ | |
14cc3e2b | 51 | static DEFINE_MUTEX(fidvid_mutex); |
1da177e4 | 52 | |
2c6b8c03 | 53 | static DEFINE_PER_CPU(struct powernow_k8_data *, powernow_data); |
1da177e4 | 54 | |
1f729e06 DJ |
55 | static int cpu_family = CPU_OPTERON; |
56 | ||
065b807c | 57 | #ifndef CONFIG_SMP |
7ad728f9 RR |
58 | static inline const struct cpumask *cpu_core_mask(int cpu) |
59 | { | |
60 | return cpumask_of(0); | |
61 | } | |
065b807c DJ |
62 | #endif |
63 | ||
1da177e4 LT |
64 | /* Return a frequency in MHz, given an input fid */ |
65 | static u32 find_freq_from_fid(u32 fid) | |
66 | { | |
67 | return 800 + (fid * 100); | |
68 | } | |
69 | ||
70 | /* Return a frequency in KHz, given an input fid */ | |
71 | static u32 find_khz_freq_from_fid(u32 fid) | |
72 | { | |
73 | return 1000 * find_freq_from_fid(fid); | |
74 | } | |
75 | ||
0e64a0c9 DJ |
76 | static u32 find_khz_freq_from_pstate(struct cpufreq_frequency_table *data, |
77 | u32 pstate) | |
1f729e06 | 78 | { |
c5829cd0 | 79 | return data[pstate].frequency; |
1f729e06 DJ |
80 | } |
81 | ||
1da177e4 LT |
82 | /* Return the vco fid for an input fid |
83 | * | |
84 | * Each "low" fid has corresponding "high" fid, and you can get to "low" fids | |
85 | * only from corresponding high fids. This returns "high" fid corresponding to | |
86 | * "low" one. | |
87 | */ | |
88 | static u32 convert_fid_to_vco_fid(u32 fid) | |
89 | { | |
32ee8c3e | 90 | if (fid < HI_FID_TABLE_BOTTOM) |
1da177e4 | 91 | return 8 + (2 * fid); |
32ee8c3e | 92 | else |
1da177e4 | 93 | return fid; |
1da177e4 LT |
94 | } |
95 | ||
96 | /* | |
97 | * Return 1 if the pending bit is set. Unless we just instructed the processor | |
98 | * to transition to a new state, seeing this bit set is really bad news. | |
99 | */ | |
100 | static int pending_bit_stuck(void) | |
101 | { | |
102 | u32 lo, hi; | |
103 | ||
e7bdd7a5 | 104 | if (cpu_family == CPU_HW_PSTATE) |
1f729e06 DJ |
105 | return 0; |
106 | ||
1da177e4 LT |
107 | rdmsr(MSR_FIDVID_STATUS, lo, hi); |
108 | return lo & MSR_S_LO_CHANGE_PENDING ? 1 : 0; | |
109 | } | |
110 | ||
111 | /* | |
112 | * Update the global current fid / vid values from the status msr. | |
113 | * Returns 1 on error. | |
114 | */ | |
115 | static int query_current_values_with_pending_wait(struct powernow_k8_data *data) | |
116 | { | |
117 | u32 lo, hi; | |
118 | u32 i = 0; | |
119 | ||
e7bdd7a5 | 120 | if (cpu_family == CPU_HW_PSTATE) { |
532cfee6 NC |
121 | rdmsr(MSR_PSTATE_STATUS, lo, hi); |
122 | i = lo & HW_PSTATE_MASK; | |
123 | data->currpstate = i; | |
124 | ||
125 | /* | |
126 | * a workaround for family 11h erratum 311 might cause | |
127 | * an "out-of-range Pstate if the core is in Pstate-0 | |
128 | */ | |
129 | if ((boot_cpu_data.x86 == 0x11) && (i >= data->numps)) | |
130 | data->currpstate = HW_PSTATE_0; | |
131 | ||
1f729e06 DJ |
132 | return 0; |
133 | } | |
7153d961 | 134 | do { |
0213df74 DJ |
135 | if (i++ > 10000) { |
136 | dprintk("detected change pending stuck\n"); | |
1da177e4 LT |
137 | return 1; |
138 | } | |
139 | rdmsr(MSR_FIDVID_STATUS, lo, hi); | |
7153d961 | 140 | } while (lo & MSR_S_LO_CHANGE_PENDING); |
1da177e4 LT |
141 | |
142 | data->currvid = hi & MSR_S_HI_CURRENT_VID; | |
143 | data->currfid = lo & MSR_S_LO_CURRENT_FID; | |
144 | ||
145 | return 0; | |
146 | } | |
147 | ||
148 | /* the isochronous relief time */ | |
149 | static void count_off_irt(struct powernow_k8_data *data) | |
150 | { | |
151 | udelay((1 << data->irt) * 10); | |
152 | return; | |
153 | } | |
154 | ||
27b46d76 | 155 | /* the voltage stabilization time */ |
1da177e4 LT |
156 | static void count_off_vst(struct powernow_k8_data *data) |
157 | { | |
158 | udelay(data->vstable * VST_UNITS_20US); | |
159 | return; | |
160 | } | |
161 | ||
162 | /* need to init the control msr to a safe value (for each cpu) */ | |
163 | static void fidvid_msr_init(void) | |
164 | { | |
165 | u32 lo, hi; | |
166 | u8 fid, vid; | |
167 | ||
168 | rdmsr(MSR_FIDVID_STATUS, lo, hi); | |
169 | vid = hi & MSR_S_HI_CURRENT_VID; | |
170 | fid = lo & MSR_S_LO_CURRENT_FID; | |
171 | lo = fid | (vid << MSR_C_LO_VID_SHIFT); | |
172 | hi = MSR_C_HI_STP_GNT_BENIGN; | |
173 | dprintk("cpu%d, init lo 0x%x, hi 0x%x\n", smp_processor_id(), lo, hi); | |
174 | wrmsr(MSR_FIDVID_CTL, lo, hi); | |
175 | } | |
176 | ||
1da177e4 LT |
177 | /* write the new fid value along with the other control fields to the msr */ |
178 | static int write_new_fid(struct powernow_k8_data *data, u32 fid) | |
179 | { | |
180 | u32 lo; | |
181 | u32 savevid = data->currvid; | |
0213df74 | 182 | u32 i = 0; |
1da177e4 LT |
183 | |
184 | if ((fid & INVALID_FID_MASK) || (data->currvid & INVALID_VID_MASK)) { | |
185 | printk(KERN_ERR PFX "internal error - overflow on fid write\n"); | |
186 | return 1; | |
187 | } | |
188 | ||
0e64a0c9 DJ |
189 | lo = fid; |
190 | lo |= (data->currvid << MSR_C_LO_VID_SHIFT); | |
191 | lo |= MSR_C_LO_INIT_FID_VID; | |
1da177e4 LT |
192 | |
193 | dprintk("writing fid 0x%x, lo 0x%x, hi 0x%x\n", | |
194 | fid, lo, data->plllock * PLL_LOCK_CONVERSION); | |
195 | ||
0213df74 DJ |
196 | do { |
197 | wrmsr(MSR_FIDVID_CTL, lo, data->plllock * PLL_LOCK_CONVERSION); | |
198 | if (i++ > 100) { | |
0e64a0c9 DJ |
199 | printk(KERN_ERR PFX |
200 | "Hardware error - pending bit very stuck - " | |
201 | "no further pstate changes possible\n"); | |
63172cb3 | 202 | return 1; |
32ee8c3e | 203 | } |
0213df74 | 204 | } while (query_current_values_with_pending_wait(data)); |
1da177e4 LT |
205 | |
206 | count_off_irt(data); | |
207 | ||
208 | if (savevid != data->currvid) { | |
0e64a0c9 DJ |
209 | printk(KERN_ERR PFX |
210 | "vid change on fid trans, old 0x%x, new 0x%x\n", | |
211 | savevid, data->currvid); | |
1da177e4 LT |
212 | return 1; |
213 | } | |
214 | ||
215 | if (fid != data->currfid) { | |
0e64a0c9 DJ |
216 | printk(KERN_ERR PFX |
217 | "fid trans failed, fid 0x%x, curr 0x%x\n", fid, | |
218 | data->currfid); | |
1da177e4 LT |
219 | return 1; |
220 | } | |
221 | ||
222 | return 0; | |
223 | } | |
224 | ||
225 | /* Write a new vid to the hardware */ | |
226 | static int write_new_vid(struct powernow_k8_data *data, u32 vid) | |
227 | { | |
228 | u32 lo; | |
229 | u32 savefid = data->currfid; | |
0213df74 | 230 | int i = 0; |
1da177e4 LT |
231 | |
232 | if ((data->currfid & INVALID_FID_MASK) || (vid & INVALID_VID_MASK)) { | |
233 | printk(KERN_ERR PFX "internal error - overflow on vid write\n"); | |
234 | return 1; | |
235 | } | |
236 | ||
0e64a0c9 DJ |
237 | lo = data->currfid; |
238 | lo |= (vid << MSR_C_LO_VID_SHIFT); | |
239 | lo |= MSR_C_LO_INIT_FID_VID; | |
1da177e4 LT |
240 | |
241 | dprintk("writing vid 0x%x, lo 0x%x, hi 0x%x\n", | |
242 | vid, lo, STOP_GRANT_5NS); | |
243 | ||
0213df74 DJ |
244 | do { |
245 | wrmsr(MSR_FIDVID_CTL, lo, STOP_GRANT_5NS); | |
6df89006 | 246 | if (i++ > 100) { |
0e64a0c9 DJ |
247 | printk(KERN_ERR PFX "internal error - pending bit " |
248 | "very stuck - no further pstate " | |
249 | "changes possible\n"); | |
6df89006 DJ |
250 | return 1; |
251 | } | |
0213df74 | 252 | } while (query_current_values_with_pending_wait(data)); |
1da177e4 LT |
253 | |
254 | if (savefid != data->currfid) { | |
0e64a0c9 DJ |
255 | printk(KERN_ERR PFX "fid changed on vid trans, old " |
256 | "0x%x new 0x%x\n", | |
1da177e4 LT |
257 | savefid, data->currfid); |
258 | return 1; | |
259 | } | |
260 | ||
261 | if (vid != data->currvid) { | |
0e64a0c9 DJ |
262 | printk(KERN_ERR PFX "vid trans failed, vid 0x%x, " |
263 | "curr 0x%x\n", | |
264 | vid, data->currvid); | |
1da177e4 LT |
265 | return 1; |
266 | } | |
267 | ||
268 | return 0; | |
269 | } | |
270 | ||
271 | /* | |
272 | * Reduce the vid by the max of step or reqvid. | |
273 | * Decreasing vid codes represent increasing voltages: | |
841e40b3 | 274 | * vid of 0 is 1.550V, vid of 0x1e is 0.800V, vid of VID_OFF is off. |
1da177e4 | 275 | */ |
0e64a0c9 DJ |
276 | static int decrease_vid_code_by_step(struct powernow_k8_data *data, |
277 | u32 reqvid, u32 step) | |
1da177e4 LT |
278 | { |
279 | if ((data->currvid - reqvid) > step) | |
280 | reqvid = data->currvid - step; | |
281 | ||
282 | if (write_new_vid(data, reqvid)) | |
283 | return 1; | |
284 | ||
285 | count_off_vst(data); | |
286 | ||
287 | return 0; | |
288 | } | |
289 | ||
1f729e06 DJ |
290 | /* Change hardware pstate by single MSR write */ |
291 | static int transition_pstate(struct powernow_k8_data *data, u32 pstate) | |
292 | { | |
293 | wrmsr(MSR_PSTATE_CTRL, pstate, 0); | |
c5829cd0 | 294 | data->currpstate = pstate; |
1f729e06 DJ |
295 | return 0; |
296 | } | |
297 | ||
298 | /* Change Opteron/Athlon64 fid and vid, by the 3 phases. */ | |
0e64a0c9 DJ |
299 | static int transition_fid_vid(struct powernow_k8_data *data, |
300 | u32 reqfid, u32 reqvid) | |
1da177e4 | 301 | { |
a2e1b4c3 | 302 | if (core_voltage_pre_transition(data, reqvid, reqfid)) |
1da177e4 LT |
303 | return 1; |
304 | ||
305 | if (core_frequency_transition(data, reqfid)) | |
306 | return 1; | |
307 | ||
308 | if (core_voltage_post_transition(data, reqvid)) | |
309 | return 1; | |
310 | ||
311 | if (query_current_values_with_pending_wait(data)) | |
312 | return 1; | |
313 | ||
314 | if ((reqfid != data->currfid) || (reqvid != data->currvid)) { | |
0e64a0c9 DJ |
315 | printk(KERN_ERR PFX "failed (cpu%d): req 0x%x 0x%x, " |
316 | "curr 0x%x 0x%x\n", | |
1da177e4 LT |
317 | smp_processor_id(), |
318 | reqfid, reqvid, data->currfid, data->currvid); | |
319 | return 1; | |
320 | } | |
321 | ||
322 | dprintk("transitioned (cpu%d): new fid 0x%x, vid 0x%x\n", | |
323 | smp_processor_id(), data->currfid, data->currvid); | |
324 | ||
325 | return 0; | |
326 | } | |
327 | ||
328 | /* Phase 1 - core voltage transition ... setup voltage */ | |
0e64a0c9 | 329 | static int core_voltage_pre_transition(struct powernow_k8_data *data, |
a2e1b4c3 | 330 | u32 reqvid, u32 reqfid) |
1da177e4 LT |
331 | { |
332 | u32 rvosteps = data->rvo; | |
333 | u32 savefid = data->currfid; | |
a2e1b4c3 | 334 | u32 maxvid, lo, rvomult = 1; |
1da177e4 | 335 | |
0e64a0c9 DJ |
336 | dprintk("ph1 (cpu%d): start, currfid 0x%x, currvid 0x%x, " |
337 | "reqvid 0x%x, rvo 0x%x\n", | |
1da177e4 LT |
338 | smp_processor_id(), |
339 | data->currfid, data->currvid, reqvid, data->rvo); | |
340 | ||
a2e1b4c3 ML |
341 | if ((savefid < LO_FID_TABLE_TOP) && (reqfid < LO_FID_TABLE_TOP)) |
342 | rvomult = 2; | |
343 | rvosteps *= rvomult; | |
065b807c DJ |
344 | rdmsr(MSR_FIDVID_STATUS, lo, maxvid); |
345 | maxvid = 0x1f & (maxvid >> 16); | |
346 | dprintk("ph1 maxvid=0x%x\n", maxvid); | |
347 | if (reqvid < maxvid) /* lower numbers are higher voltages */ | |
348 | reqvid = maxvid; | |
349 | ||
1da177e4 LT |
350 | while (data->currvid > reqvid) { |
351 | dprintk("ph1: curr 0x%x, req vid 0x%x\n", | |
352 | data->currvid, reqvid); | |
353 | if (decrease_vid_code_by_step(data, reqvid, data->vidmvs)) | |
354 | return 1; | |
355 | } | |
356 | ||
a2e1b4c3 ML |
357 | while ((rvosteps > 0) && |
358 | ((rvomult * data->rvo + data->currvid) > reqvid)) { | |
065b807c | 359 | if (data->currvid == maxvid) { |
1da177e4 LT |
360 | rvosteps = 0; |
361 | } else { | |
362 | dprintk("ph1: changing vid for rvo, req 0x%x\n", | |
363 | data->currvid - 1); | |
0e64a0c9 | 364 | if (decrease_vid_code_by_step(data, data->currvid-1, 1)) |
1da177e4 LT |
365 | return 1; |
366 | rvosteps--; | |
367 | } | |
368 | } | |
369 | ||
370 | if (query_current_values_with_pending_wait(data)) | |
371 | return 1; | |
372 | ||
373 | if (savefid != data->currfid) { | |
0e64a0c9 DJ |
374 | printk(KERN_ERR PFX "ph1 err, currfid changed 0x%x\n", |
375 | data->currfid); | |
1da177e4 LT |
376 | return 1; |
377 | } | |
378 | ||
379 | dprintk("ph1 complete, currfid 0x%x, currvid 0x%x\n", | |
380 | data->currfid, data->currvid); | |
381 | ||
382 | return 0; | |
383 | } | |
384 | ||
385 | /* Phase 2 - core frequency transition */ | |
386 | static int core_frequency_transition(struct powernow_k8_data *data, u32 reqfid) | |
387 | { | |
0e64a0c9 DJ |
388 | u32 vcoreqfid, vcocurrfid, vcofiddiff; |
389 | u32 fid_interval, savevid = data->currvid; | |
1da177e4 | 390 | |
1da177e4 | 391 | if (data->currfid == reqfid) { |
0e64a0c9 DJ |
392 | printk(KERN_ERR PFX "ph2 null fid transition 0x%x\n", |
393 | data->currfid); | |
1da177e4 LT |
394 | return 0; |
395 | } | |
396 | ||
0e64a0c9 DJ |
397 | dprintk("ph2 (cpu%d): starting, currfid 0x%x, currvid 0x%x, " |
398 | "reqfid 0x%x\n", | |
1da177e4 LT |
399 | smp_processor_id(), |
400 | data->currfid, data->currvid, reqfid); | |
401 | ||
402 | vcoreqfid = convert_fid_to_vco_fid(reqfid); | |
403 | vcocurrfid = convert_fid_to_vco_fid(data->currfid); | |
404 | vcofiddiff = vcocurrfid > vcoreqfid ? vcocurrfid - vcoreqfid | |
405 | : vcoreqfid - vcocurrfid; | |
406 | ||
a2e1b4c3 ML |
407 | if ((reqfid <= LO_FID_TABLE_TOP) && (data->currfid <= LO_FID_TABLE_TOP)) |
408 | vcofiddiff = 0; | |
409 | ||
1da177e4 | 410 | while (vcofiddiff > 2) { |
019a61b9 LM |
411 | (data->currfid & 1) ? (fid_interval = 1) : (fid_interval = 2); |
412 | ||
1da177e4 LT |
413 | if (reqfid > data->currfid) { |
414 | if (data->currfid > LO_FID_TABLE_TOP) { | |
0e64a0c9 DJ |
415 | if (write_new_fid(data, |
416 | data->currfid + fid_interval)) | |
1da177e4 | 417 | return 1; |
1da177e4 LT |
418 | } else { |
419 | if (write_new_fid | |
0e64a0c9 DJ |
420 | (data, |
421 | 2 + convert_fid_to_vco_fid(data->currfid))) | |
1da177e4 | 422 | return 1; |
1da177e4 LT |
423 | } |
424 | } else { | |
019a61b9 | 425 | if (write_new_fid(data, data->currfid - fid_interval)) |
1da177e4 LT |
426 | return 1; |
427 | } | |
428 | ||
429 | vcocurrfid = convert_fid_to_vco_fid(data->currfid); | |
430 | vcofiddiff = vcocurrfid > vcoreqfid ? vcocurrfid - vcoreqfid | |
431 | : vcoreqfid - vcocurrfid; | |
432 | } | |
433 | ||
434 | if (write_new_fid(data, reqfid)) | |
435 | return 1; | |
436 | ||
437 | if (query_current_values_with_pending_wait(data)) | |
438 | return 1; | |
439 | ||
440 | if (data->currfid != reqfid) { | |
441 | printk(KERN_ERR PFX | |
0e64a0c9 DJ |
442 | "ph2: mismatch, failed fid transition, " |
443 | "curr 0x%x, req 0x%x\n", | |
1da177e4 LT |
444 | data->currfid, reqfid); |
445 | return 1; | |
446 | } | |
447 | ||
448 | if (savevid != data->currvid) { | |
449 | printk(KERN_ERR PFX "ph2: vid changed, save 0x%x, curr 0x%x\n", | |
450 | savevid, data->currvid); | |
451 | return 1; | |
452 | } | |
453 | ||
454 | dprintk("ph2 complete, currfid 0x%x, currvid 0x%x\n", | |
455 | data->currfid, data->currvid); | |
456 | ||
457 | return 0; | |
458 | } | |
459 | ||
460 | /* Phase 3 - core voltage transition flow ... jump to the final vid. */ | |
0e64a0c9 DJ |
461 | static int core_voltage_post_transition(struct powernow_k8_data *data, |
462 | u32 reqvid) | |
1da177e4 LT |
463 | { |
464 | u32 savefid = data->currfid; | |
465 | u32 savereqvid = reqvid; | |
466 | ||
467 | dprintk("ph3 (cpu%d): starting, currfid 0x%x, currvid 0x%x\n", | |
468 | smp_processor_id(), | |
469 | data->currfid, data->currvid); | |
470 | ||
471 | if (reqvid != data->currvid) { | |
472 | if (write_new_vid(data, reqvid)) | |
473 | return 1; | |
474 | ||
475 | if (savefid != data->currfid) { | |
476 | printk(KERN_ERR PFX | |
477 | "ph3: bad fid change, save 0x%x, curr 0x%x\n", | |
478 | savefid, data->currfid); | |
479 | return 1; | |
480 | } | |
481 | ||
482 | if (data->currvid != reqvid) { | |
483 | printk(KERN_ERR PFX | |
0e64a0c9 DJ |
484 | "ph3: failed vid transition\n, " |
485 | "req 0x%x, curr 0x%x", | |
1da177e4 LT |
486 | reqvid, data->currvid); |
487 | return 1; | |
488 | } | |
489 | } | |
490 | ||
491 | if (query_current_values_with_pending_wait(data)) | |
492 | return 1; | |
493 | ||
494 | if (savereqvid != data->currvid) { | |
495 | dprintk("ph3 failed, currvid 0x%x\n", data->currvid); | |
496 | return 1; | |
497 | } | |
498 | ||
499 | if (savefid != data->currfid) { | |
500 | dprintk("ph3 failed, currfid changed 0x%x\n", | |
501 | data->currfid); | |
502 | return 1; | |
503 | } | |
504 | ||
505 | dprintk("ph3 complete, currfid 0x%x, currvid 0x%x\n", | |
506 | data->currfid, data->currvid); | |
507 | ||
508 | return 0; | |
509 | } | |
510 | ||
1ff6e97f | 511 | static void check_supported_cpu(void *_rc) |
1da177e4 | 512 | { |
1da177e4 | 513 | u32 eax, ebx, ecx, edx; |
1ff6e97f | 514 | int *rc = _rc; |
1da177e4 | 515 | |
1ff6e97f | 516 | *rc = -ENODEV; |
1da177e4 LT |
517 | |
518 | if (current_cpu_data.x86_vendor != X86_VENDOR_AMD) | |
1ff6e97f | 519 | return; |
1da177e4 LT |
520 | |
521 | eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE); | |
1f729e06 DJ |
522 | if (((eax & CPUID_XFAM) != CPUID_XFAM_K8) && |
523 | ((eax & CPUID_XFAM) < CPUID_XFAM_10H)) | |
1ff6e97f | 524 | return; |
2c906ae6 | 525 | |
1f729e06 DJ |
526 | if ((eax & CPUID_XFAM) == CPUID_XFAM_K8) { |
527 | if (((eax & CPUID_USE_XFAM_XMOD) != CPUID_USE_XFAM_XMOD) || | |
99fbe1ac | 528 | ((eax & CPUID_XMOD) > CPUID_XMOD_REV_MASK)) { |
0e64a0c9 DJ |
529 | printk(KERN_INFO PFX |
530 | "Processor cpuid %x not supported\n", eax); | |
1ff6e97f | 531 | return; |
1f729e06 | 532 | } |
1da177e4 | 533 | |
1f729e06 DJ |
534 | eax = cpuid_eax(CPUID_GET_MAX_CAPABILITIES); |
535 | if (eax < CPUID_FREQ_VOLT_CAPABILITIES) { | |
536 | printk(KERN_INFO PFX | |
537 | "No frequency change capabilities detected\n"); | |
1ff6e97f | 538 | return; |
1f729e06 | 539 | } |
1da177e4 | 540 | |
1f729e06 | 541 | cpuid(CPUID_FREQ_VOLT_CAPABILITIES, &eax, &ebx, &ecx, &edx); |
0e64a0c9 DJ |
542 | if ((edx & P_STATE_TRANSITION_CAPABLE) |
543 | != P_STATE_TRANSITION_CAPABLE) { | |
544 | printk(KERN_INFO PFX | |
545 | "Power state transitions not supported\n"); | |
1ff6e97f | 546 | return; |
1f729e06 DJ |
547 | } |
548 | } else { /* must be a HW Pstate capable processor */ | |
549 | cpuid(CPUID_FREQ_VOLT_CAPABILITIES, &eax, &ebx, &ecx, &edx); | |
550 | if ((edx & USE_HW_PSTATE) == USE_HW_PSTATE) | |
551 | cpu_family = CPU_HW_PSTATE; | |
552 | else | |
1ff6e97f | 553 | return; |
1da177e4 LT |
554 | } |
555 | ||
1ff6e97f | 556 | *rc = 0; |
1da177e4 LT |
557 | } |
558 | ||
0e64a0c9 DJ |
559 | static int check_pst_table(struct powernow_k8_data *data, struct pst_s *pst, |
560 | u8 maxvid) | |
1da177e4 LT |
561 | { |
562 | unsigned int j; | |
563 | u8 lastfid = 0xff; | |
564 | ||
565 | for (j = 0; j < data->numps; j++) { | |
566 | if (pst[j].vid > LEAST_VID) { | |
2fd47094 TR |
567 | printk(KERN_ERR FW_BUG PFX "vid %d invalid : 0x%x\n", |
568 | j, pst[j].vid); | |
1da177e4 LT |
569 | return -EINVAL; |
570 | } | |
0e64a0c9 DJ |
571 | if (pst[j].vid < data->rvo) { |
572 | /* vid + rvo >= 0 */ | |
2fd47094 TR |
573 | printk(KERN_ERR FW_BUG PFX "0 vid exceeded with pstate" |
574 | " %d\n", j); | |
1da177e4 LT |
575 | return -ENODEV; |
576 | } | |
0e64a0c9 DJ |
577 | if (pst[j].vid < maxvid + data->rvo) { |
578 | /* vid + rvo >= maxvid */ | |
2fd47094 TR |
579 | printk(KERN_ERR FW_BUG PFX "maxvid exceeded with pstate" |
580 | " %d\n", j); | |
1da177e4 LT |
581 | return -ENODEV; |
582 | } | |
8aae8284 | 583 | if (pst[j].fid > MAX_FID) { |
2fd47094 TR |
584 | printk(KERN_ERR FW_BUG PFX "maxfid exceeded with pstate" |
585 | " %d\n", j); | |
8aae8284 JS |
586 | return -ENODEV; |
587 | } | |
8aae8284 | 588 | if (j && (pst[j].fid < HI_FID_TABLE_BOTTOM)) { |
1da177e4 | 589 | /* Only first fid is allowed to be in "low" range */ |
2fd47094 TR |
590 | printk(KERN_ERR FW_BUG PFX "two low fids - %d : " |
591 | "0x%x\n", j, pst[j].fid); | |
1da177e4 LT |
592 | return -EINVAL; |
593 | } | |
594 | if (pst[j].fid < lastfid) | |
595 | lastfid = pst[j].fid; | |
596 | } | |
597 | if (lastfid & 1) { | |
2fd47094 | 598 | printk(KERN_ERR FW_BUG PFX "lastfid invalid\n"); |
1da177e4 LT |
599 | return -EINVAL; |
600 | } | |
601 | if (lastfid > LO_FID_TABLE_TOP) | |
0e64a0c9 DJ |
602 | printk(KERN_INFO FW_BUG PFX |
603 | "first fid not from lo freq table\n"); | |
1da177e4 LT |
604 | |
605 | return 0; | |
606 | } | |
607 | ||
0e64a0c9 DJ |
608 | static void invalidate_entry(struct powernow_k8_data *data, unsigned int entry) |
609 | { | |
610 | data->powernow_table[entry].frequency = CPUFREQ_ENTRY_INVALID; | |
611 | } | |
612 | ||
1da177e4 LT |
613 | static void print_basics(struct powernow_k8_data *data) |
614 | { | |
615 | int j; | |
616 | for (j = 0; j < data->numps; j++) { | |
0e64a0c9 DJ |
617 | if (data->powernow_table[j].frequency != |
618 | CPUFREQ_ENTRY_INVALID) { | |
e7bdd7a5 | 619 | if (cpu_family == CPU_HW_PSTATE) { |
0e64a0c9 DJ |
620 | printk(KERN_INFO PFX |
621 | " %d : pstate %d (%d MHz)\n", j, | |
4ae5c49f | 622 | data->powernow_table[j].index, |
9a60ddbc | 623 | data->powernow_table[j].frequency/1000); |
1f729e06 | 624 | } else { |
0e64a0c9 DJ |
625 | printk(KERN_INFO PFX |
626 | " %d : fid 0x%x (%d MHz), vid 0x%x\n", | |
9a60ddbc DJ |
627 | j, |
628 | data->powernow_table[j].index & 0xff, | |
629 | data->powernow_table[j].frequency/1000, | |
630 | data->powernow_table[j].index >> 8); | |
1f729e06 DJ |
631 | } |
632 | } | |
1da177e4 LT |
633 | } |
634 | if (data->batps) | |
0e64a0c9 DJ |
635 | printk(KERN_INFO PFX "Only %d pstates on battery\n", |
636 | data->batps); | |
1da177e4 LT |
637 | } |
638 | ||
ca446d06 AH |
639 | static u32 freq_from_fid_did(u32 fid, u32 did) |
640 | { | |
641 | u32 mhz = 0; | |
642 | ||
643 | if (boot_cpu_data.x86 == 0x10) | |
644 | mhz = (100 * (fid + 0x10)) >> did; | |
645 | else if (boot_cpu_data.x86 == 0x11) | |
646 | mhz = (100 * (fid + 8)) >> did; | |
647 | else | |
648 | BUG(); | |
649 | ||
650 | return mhz * 1000; | |
651 | } | |
652 | ||
0e64a0c9 DJ |
653 | static int fill_powernow_table(struct powernow_k8_data *data, |
654 | struct pst_s *pst, u8 maxvid) | |
1da177e4 LT |
655 | { |
656 | struct cpufreq_frequency_table *powernow_table; | |
657 | unsigned int j; | |
658 | ||
0e64a0c9 DJ |
659 | if (data->batps) { |
660 | /* use ACPI support to get full speed on mains power */ | |
661 | printk(KERN_WARNING PFX | |
662 | "Only %d pstates usable (use ACPI driver for full " | |
663 | "range\n", data->batps); | |
1da177e4 LT |
664 | data->numps = data->batps; |
665 | } | |
666 | ||
0e64a0c9 | 667 | for (j = 1; j < data->numps; j++) { |
1da177e4 LT |
668 | if (pst[j-1].fid >= pst[j].fid) { |
669 | printk(KERN_ERR PFX "PST out of sequence\n"); | |
670 | return -EINVAL; | |
671 | } | |
672 | } | |
673 | ||
674 | if (data->numps < 2) { | |
675 | printk(KERN_ERR PFX "no p states to transition\n"); | |
676 | return -ENODEV; | |
677 | } | |
678 | ||
679 | if (check_pst_table(data, pst, maxvid)) | |
680 | return -EINVAL; | |
681 | ||
682 | powernow_table = kmalloc((sizeof(struct cpufreq_frequency_table) | |
683 | * (data->numps + 1)), GFP_KERNEL); | |
684 | if (!powernow_table) { | |
685 | printk(KERN_ERR PFX "powernow_table memory alloc failure\n"); | |
686 | return -ENOMEM; | |
687 | } | |
688 | ||
689 | for (j = 0; j < data->numps; j++) { | |
0e64a0c9 | 690 | int freq; |
1da177e4 LT |
691 | powernow_table[j].index = pst[j].fid; /* lower 8 bits */ |
692 | powernow_table[j].index |= (pst[j].vid << 8); /* upper 8 bits */ | |
0e64a0c9 DJ |
693 | freq = find_khz_freq_from_fid(pst[j].fid); |
694 | powernow_table[j].frequency = freq; | |
1da177e4 LT |
695 | } |
696 | powernow_table[data->numps].frequency = CPUFREQ_TABLE_END; | |
697 | powernow_table[data->numps].index = 0; | |
698 | ||
699 | if (query_current_values_with_pending_wait(data)) { | |
700 | kfree(powernow_table); | |
701 | return -EIO; | |
702 | } | |
703 | ||
704 | dprintk("cfid 0x%x, cvid 0x%x\n", data->currfid, data->currvid); | |
705 | data->powernow_table = powernow_table; | |
7ad728f9 | 706 | if (cpumask_first(cpu_core_mask(data->cpu)) == data->cpu) |
2e497620 | 707 | print_basics(data); |
1da177e4 LT |
708 | |
709 | for (j = 0; j < data->numps; j++) | |
0e64a0c9 DJ |
710 | if ((pst[j].fid == data->currfid) && |
711 | (pst[j].vid == data->currvid)) | |
1da177e4 LT |
712 | return 0; |
713 | ||
714 | dprintk("currfid/vid do not match PST, ignoring\n"); | |
715 | return 0; | |
716 | } | |
717 | ||
718 | /* Find and validate the PSB/PST table in BIOS. */ | |
719 | static int find_psb_table(struct powernow_k8_data *data) | |
720 | { | |
721 | struct psb_s *psb; | |
722 | unsigned int i; | |
723 | u32 mvs; | |
724 | u8 maxvid; | |
725 | u32 cpst = 0; | |
726 | u32 thiscpuid; | |
727 | ||
728 | for (i = 0xc0000; i < 0xffff0; i += 0x10) { | |
729 | /* Scan BIOS looking for the signature. */ | |
730 | /* It can not be at ffff0 - it is too big. */ | |
731 | ||
732 | psb = phys_to_virt(i); | |
733 | if (memcmp(psb, PSB_ID_STRING, PSB_ID_STRING_LEN) != 0) | |
734 | continue; | |
735 | ||
736 | dprintk("found PSB header at 0x%p\n", psb); | |
737 | ||
738 | dprintk("table vers: 0x%x\n", psb->tableversion); | |
739 | if (psb->tableversion != PSB_VERSION_1_4) { | |
2fd47094 | 740 | printk(KERN_ERR FW_BUG PFX "PSB table is not v1.4\n"); |
1da177e4 LT |
741 | return -ENODEV; |
742 | } | |
743 | ||
744 | dprintk("flags: 0x%x\n", psb->flags1); | |
745 | if (psb->flags1) { | |
2fd47094 | 746 | printk(KERN_ERR FW_BUG PFX "unknown flags\n"); |
1da177e4 LT |
747 | return -ENODEV; |
748 | } | |
749 | ||
750 | data->vstable = psb->vstable; | |
0e64a0c9 DJ |
751 | dprintk("voltage stabilization time: %d(*20us)\n", |
752 | data->vstable); | |
1da177e4 LT |
753 | |
754 | dprintk("flags2: 0x%x\n", psb->flags2); | |
755 | data->rvo = psb->flags2 & 3; | |
756 | data->irt = ((psb->flags2) >> 2) & 3; | |
757 | mvs = ((psb->flags2) >> 4) & 3; | |
758 | data->vidmvs = 1 << mvs; | |
759 | data->batps = ((psb->flags2) >> 6) & 3; | |
760 | ||
761 | dprintk("ramp voltage offset: %d\n", data->rvo); | |
762 | dprintk("isochronous relief time: %d\n", data->irt); | |
763 | dprintk("maximum voltage step: %d - 0x%x\n", mvs, data->vidmvs); | |
764 | ||
765 | dprintk("numpst: 0x%x\n", psb->num_tables); | |
766 | cpst = psb->num_tables; | |
0e64a0c9 DJ |
767 | if ((psb->cpuid == 0x00000fc0) || |
768 | (psb->cpuid == 0x00000fe0)) { | |
1da177e4 | 769 | thiscpuid = cpuid_eax(CPUID_PROCESSOR_SIGNATURE); |
0e64a0c9 DJ |
770 | if ((thiscpuid == 0x00000fc0) || |
771 | (thiscpuid == 0x00000fe0)) | |
1da177e4 | 772 | cpst = 1; |
1da177e4 LT |
773 | } |
774 | if (cpst != 1) { | |
2fd47094 | 775 | printk(KERN_ERR FW_BUG PFX "numpst must be 1\n"); |
1da177e4 LT |
776 | return -ENODEV; |
777 | } | |
778 | ||
779 | data->plllock = psb->plllocktime; | |
780 | dprintk("plllocktime: 0x%x (units 1us)\n", psb->plllocktime); | |
781 | dprintk("maxfid: 0x%x\n", psb->maxfid); | |
782 | dprintk("maxvid: 0x%x\n", psb->maxvid); | |
783 | maxvid = psb->maxvid; | |
784 | ||
785 | data->numps = psb->numps; | |
786 | dprintk("numpstates: 0x%x\n", data->numps); | |
0e64a0c9 DJ |
787 | return fill_powernow_table(data, |
788 | (struct pst_s *)(psb+1), maxvid); | |
1da177e4 LT |
789 | } |
790 | /* | |
791 | * If you see this message, complain to BIOS manufacturer. If | |
792 | * he tells you "we do not support Linux" or some similar | |
793 | * nonsense, remember that Windows 2000 uses the same legacy | |
794 | * mechanism that the old Linux PSB driver uses. Tell them it | |
795 | * is broken with Windows 2000. | |
796 | * | |
797 | * The reference to the AMD documentation is chapter 9 in the | |
798 | * BIOS and Kernel Developer's Guide, which is available on | |
799 | * www.amd.com | |
800 | */ | |
79cc56af | 801 | printk(KERN_ERR FW_BUG PFX "No PSB or ACPI _PSS objects\n"); |
1da177e4 LT |
802 | return -ENODEV; |
803 | } | |
804 | ||
0e64a0c9 DJ |
805 | static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, |
806 | unsigned int index) | |
1da177e4 | 807 | { |
0e64a0c9 DJ |
808 | acpi_integer control; |
809 | ||
f607e3a0 | 810 | if (!data->acpi_data.state_count || (cpu_family == CPU_HW_PSTATE)) |
1da177e4 LT |
811 | return; |
812 | ||
21335d02 LH |
813 | control = data->acpi_data.states[index].control; |
814 | data->irt = (control >> IRT_SHIFT) & IRT_MASK; | |
815 | data->rvo = (control >> RVO_SHIFT) & RVO_MASK; | |
816 | data->exttype = (control >> EXT_TYPE_SHIFT) & EXT_TYPE_MASK; | |
817 | data->plllock = (control >> PLL_L_SHIFT) & PLL_L_MASK; | |
818 | data->vidmvs = 1 << ((control >> MVS_SHIFT) & MVS_MASK); | |
819 | data->vstable = (control >> VST_SHIFT) & VST_MASK; | |
820 | } | |
1da177e4 LT |
821 | |
822 | static int powernow_k8_cpu_init_acpi(struct powernow_k8_data *data) | |
823 | { | |
1da177e4 | 824 | struct cpufreq_frequency_table *powernow_table; |
2fdf66b4 | 825 | int ret_val = -ENODEV; |
2c701b10 | 826 | acpi_integer control, status; |
1da177e4 | 827 | |
f607e3a0 | 828 | if (acpi_processor_register_performance(&data->acpi_data, data->cpu)) { |
065b807c | 829 | dprintk("register performance failed: bad ACPI data\n"); |
1da177e4 LT |
830 | return -EIO; |
831 | } | |
832 | ||
833 | /* verify the data contained in the ACPI structures */ | |
f607e3a0 | 834 | if (data->acpi_data.state_count <= 1) { |
1da177e4 LT |
835 | dprintk("No ACPI P-States\n"); |
836 | goto err_out; | |
837 | } | |
838 | ||
2c701b10 DJ |
839 | control = data->acpi_data.control_register.space_id; |
840 | status = data->acpi_data.status_register.space_id; | |
841 | ||
842 | if ((control != ACPI_ADR_SPACE_FIXED_HARDWARE) || | |
843 | (status != ACPI_ADR_SPACE_FIXED_HARDWARE)) { | |
1da177e4 | 844 | dprintk("Invalid control/status registers (%x - %x)\n", |
2c701b10 | 845 | control, status); |
1da177e4 LT |
846 | goto err_out; |
847 | } | |
848 | ||
849 | /* fill in data->powernow_table */ | |
850 | powernow_table = kmalloc((sizeof(struct cpufreq_frequency_table) | |
f607e3a0 | 851 | * (data->acpi_data.state_count + 1)), GFP_KERNEL); |
1da177e4 LT |
852 | if (!powernow_table) { |
853 | dprintk("powernow_table memory alloc failure\n"); | |
854 | goto err_out; | |
855 | } | |
856 | ||
e7bdd7a5 | 857 | if (cpu_family == CPU_HW_PSTATE) |
1f729e06 DJ |
858 | ret_val = fill_powernow_table_pstate(data, powernow_table); |
859 | else | |
860 | ret_val = fill_powernow_table_fidvid(data, powernow_table); | |
861 | if (ret_val) | |
862 | goto err_out_mem; | |
863 | ||
0e64a0c9 DJ |
864 | powernow_table[data->acpi_data.state_count].frequency = |
865 | CPUFREQ_TABLE_END; | |
f607e3a0 | 866 | powernow_table[data->acpi_data.state_count].index = 0; |
1f729e06 DJ |
867 | data->powernow_table = powernow_table; |
868 | ||
869 | /* fill in data */ | |
f607e3a0 | 870 | data->numps = data->acpi_data.state_count; |
7ad728f9 | 871 | if (cpumask_first(cpu_core_mask(data->cpu)) == data->cpu) |
2e497620 | 872 | print_basics(data); |
1f729e06 DJ |
873 | powernow_k8_acpi_pst_values(data, 0); |
874 | ||
875 | /* notify BIOS that we exist */ | |
876 | acpi_processor_notify_smm(THIS_MODULE); | |
877 | ||
eaa95840 | 878 | if (!zalloc_cpumask_var(&data->acpi_data.shared_cpu_map, GFP_KERNEL)) { |
2fdf66b4 RR |
879 | printk(KERN_ERR PFX |
880 | "unable to alloc powernow_k8_data cpumask\n"); | |
881 | ret_val = -ENOMEM; | |
882 | goto err_out_mem; | |
883 | } | |
884 | ||
1f729e06 DJ |
885 | return 0; |
886 | ||
887 | err_out_mem: | |
888 | kfree(powernow_table); | |
889 | ||
890 | err_out: | |
f607e3a0 | 891 | acpi_processor_unregister_performance(&data->acpi_data, data->cpu); |
1f729e06 | 892 | |
0e64a0c9 DJ |
893 | /* data->acpi_data.state_count informs us at ->exit() |
894 | * whether ACPI was used */ | |
f607e3a0 | 895 | data->acpi_data.state_count = 0; |
1f729e06 | 896 | |
2fdf66b4 | 897 | return ret_val; |
1f729e06 DJ |
898 | } |
899 | ||
0e64a0c9 DJ |
900 | static int fill_powernow_table_pstate(struct powernow_k8_data *data, |
901 | struct cpufreq_frequency_table *powernow_table) | |
1f729e06 DJ |
902 | { |
903 | int i; | |
c5829cd0 ML |
904 | u32 hi = 0, lo = 0; |
905 | rdmsr(MSR_PSTATE_CUR_LIMIT, hi, lo); | |
906 | data->max_hw_pstate = (hi & HW_PSTATE_MAX_MASK) >> HW_PSTATE_MAX_SHIFT; | |
1f729e06 | 907 | |
f607e3a0 | 908 | for (i = 0; i < data->acpi_data.state_count; i++) { |
1f729e06 | 909 | u32 index; |
1f729e06 | 910 | |
f607e3a0 | 911 | index = data->acpi_data.states[i].control & HW_PSTATE_MASK; |
c5829cd0 | 912 | if (index > data->max_hw_pstate) { |
0e64a0c9 DJ |
913 | printk(KERN_ERR PFX "invalid pstate %d - " |
914 | "bad value %d.\n", i, index); | |
915 | printk(KERN_ERR PFX "Please report to BIOS " | |
916 | "manufacturer\n"); | |
917 | invalidate_entry(data, i); | |
c5829cd0 | 918 | continue; |
1f729e06 DJ |
919 | } |
920 | rdmsr(MSR_PSTATE_DEF_BASE + index, lo, hi); | |
921 | if (!(hi & HW_PSTATE_VALID_MASK)) { | |
922 | dprintk("invalid pstate %d, ignoring\n", index); | |
0e64a0c9 | 923 | invalidate_entry(data, i); |
1f729e06 DJ |
924 | continue; |
925 | } | |
926 | ||
c5829cd0 | 927 | powernow_table[i].index = index; |
1f729e06 | 928 | |
ca446d06 AH |
929 | /* Frequency may be rounded for these */ |
930 | if (boot_cpu_data.x86 == 0x10 || boot_cpu_data.x86 == 0x11) { | |
931 | powernow_table[i].frequency = | |
932 | freq_from_fid_did(lo & 0x3f, (lo >> 6) & 7); | |
933 | } else | |
934 | powernow_table[i].frequency = | |
935 | data->acpi_data.states[i].core_frequency * 1000; | |
1f729e06 DJ |
936 | } |
937 | return 0; | |
938 | } | |
939 | ||
0e64a0c9 DJ |
940 | static int fill_powernow_table_fidvid(struct powernow_k8_data *data, |
941 | struct cpufreq_frequency_table *powernow_table) | |
1f729e06 DJ |
942 | { |
943 | int i; | |
944 | int cntlofreq = 0; | |
0e64a0c9 | 945 | |
f607e3a0 | 946 | for (i = 0; i < data->acpi_data.state_count; i++) { |
094ce7fd DJ |
947 | u32 fid; |
948 | u32 vid; | |
0e64a0c9 DJ |
949 | u32 freq, index; |
950 | acpi_integer status, control; | |
094ce7fd DJ |
951 | |
952 | if (data->exttype) { | |
0e64a0c9 DJ |
953 | status = data->acpi_data.states[i].status; |
954 | fid = status & EXT_FID_MASK; | |
955 | vid = (status >> VID_SHIFT) & EXT_VID_MASK; | |
841e40b3 | 956 | } else { |
0e64a0c9 DJ |
957 | control = data->acpi_data.states[i].control; |
958 | fid = control & FID_MASK; | |
959 | vid = (control >> VID_SHIFT) & VID_MASK; | |
841e40b3 | 960 | } |
1da177e4 LT |
961 | |
962 | dprintk(" %d : fid 0x%x, vid 0x%x\n", i, fid, vid); | |
963 | ||
0e64a0c9 DJ |
964 | index = fid | (vid<<8); |
965 | powernow_table[i].index = index; | |
966 | ||
967 | freq = find_khz_freq_from_fid(fid); | |
968 | powernow_table[i].frequency = freq; | |
1da177e4 LT |
969 | |
970 | /* verify frequency is OK */ | |
0e64a0c9 DJ |
971 | if ((freq > (MAX_FREQ * 1000)) || (freq < (MIN_FREQ * 1000))) { |
972 | dprintk("invalid freq %u kHz, ignoring\n", freq); | |
973 | invalidate_entry(data, i); | |
1da177e4 LT |
974 | continue; |
975 | } | |
976 | ||
0e64a0c9 DJ |
977 | /* verify voltage is OK - |
978 | * BIOSs are using "off" to indicate invalid */ | |
841e40b3 | 979 | if (vid == VID_OFF) { |
1da177e4 | 980 | dprintk("invalid vid %u, ignoring\n", vid); |
0e64a0c9 | 981 | invalidate_entry(data, i); |
1da177e4 LT |
982 | continue; |
983 | } | |
984 | ||
065b807c DJ |
985 | /* verify only 1 entry from the lo frequency table */ |
986 | if (fid < HI_FID_TABLE_BOTTOM) { | |
987 | if (cntlofreq) { | |
0e64a0c9 DJ |
988 | /* if both entries are the same, |
989 | * ignore this one ... */ | |
990 | if ((freq != powernow_table[cntlofreq].frequency) || | |
991 | (index != powernow_table[cntlofreq].index)) { | |
992 | printk(KERN_ERR PFX | |
993 | "Too many lo freq table " | |
994 | "entries\n"); | |
1f729e06 | 995 | return 1; |
065b807c DJ |
996 | } |
997 | ||
0e64a0c9 DJ |
998 | dprintk("double low frequency table entry, " |
999 | "ignoring it.\n"); | |
1000 | invalidate_entry(data, i); | |
065b807c DJ |
1001 | continue; |
1002 | } else | |
1003 | cntlofreq = i; | |
1da177e4 LT |
1004 | } |
1005 | ||
0e64a0c9 DJ |
1006 | if (freq != (data->acpi_data.states[i].core_frequency * 1000)) { |
1007 | printk(KERN_INFO PFX "invalid freq entries " | |
1008 | "%u kHz vs. %u kHz\n", freq, | |
1009 | (unsigned int) | |
1010 | (data->acpi_data.states[i].core_frequency | |
1011 | * 1000)); | |
1012 | invalidate_entry(data, i); | |
1da177e4 LT |
1013 | continue; |
1014 | } | |
1015 | } | |
1da177e4 | 1016 | return 0; |
1da177e4 LT |
1017 | } |
1018 | ||
1019 | static void powernow_k8_cpu_exit_acpi(struct powernow_k8_data *data) | |
1020 | { | |
f607e3a0 | 1021 | if (data->acpi_data.state_count) |
0e64a0c9 DJ |
1022 | acpi_processor_unregister_performance(&data->acpi_data, |
1023 | data->cpu); | |
2fdf66b4 | 1024 | free_cpumask_var(data->acpi_data.shared_cpu_map); |
1da177e4 LT |
1025 | } |
1026 | ||
732553e5 ML |
1027 | static int get_transition_latency(struct powernow_k8_data *data) |
1028 | { | |
1029 | int max_latency = 0; | |
1030 | int i; | |
1031 | for (i = 0; i < data->acpi_data.state_count; i++) { | |
1032 | int cur_latency = data->acpi_data.states[i].transition_latency | |
1033 | + data->acpi_data.states[i].bus_master_latency; | |
1034 | if (cur_latency > max_latency) | |
1035 | max_latency = cur_latency; | |
1036 | } | |
86e13684 TR |
1037 | if (max_latency == 0) { |
1038 | /* | |
1039 | * Fam 11h always returns 0 as transition latency. | |
1040 | * This is intended and means "very fast". While cpufreq core | |
1041 | * and governors currently can handle that gracefully, better | |
1042 | * set it to 1 to avoid problems in the future. | |
1043 | * For all others it's a BIOS bug. | |
1044 | */ | |
1045 | if (!boot_cpu_data.x86 == 0x11) | |
1046 | printk(KERN_ERR FW_WARN PFX "Invalid zero transition " | |
1047 | "latency\n"); | |
1048 | max_latency = 1; | |
1049 | } | |
732553e5 ML |
1050 | /* value in usecs, needs to be in nanoseconds */ |
1051 | return 1000 * max_latency; | |
1052 | } | |
1053 | ||
1da177e4 | 1054 | /* Take a frequency, and issue the fid/vid transition command */ |
0e64a0c9 DJ |
1055 | static int transition_frequency_fidvid(struct powernow_k8_data *data, |
1056 | unsigned int index) | |
1da177e4 | 1057 | { |
1f729e06 DJ |
1058 | u32 fid = 0; |
1059 | u32 vid = 0; | |
065b807c | 1060 | int res, i; |
1da177e4 LT |
1061 | struct cpufreq_freqs freqs; |
1062 | ||
1063 | dprintk("cpu %d transition to index %u\n", smp_processor_id(), index); | |
1064 | ||
1f729e06 | 1065 | /* fid/vid correctness check for k8 */ |
1da177e4 | 1066 | /* fid are the lower 8 bits of the index we stored into |
1f729e06 DJ |
1067 | * the cpufreq frequency table in find_psb_table, vid |
1068 | * are the upper 8 bits. | |
1da177e4 | 1069 | */ |
1da177e4 LT |
1070 | fid = data->powernow_table[index].index & 0xFF; |
1071 | vid = (data->powernow_table[index].index & 0xFF00) >> 8; | |
1072 | ||
1073 | dprintk("table matched fid 0x%x, giving vid 0x%x\n", fid, vid); | |
1074 | ||
1075 | if (query_current_values_with_pending_wait(data)) | |
1076 | return 1; | |
1077 | ||
1078 | if ((data->currvid == vid) && (data->currfid == fid)) { | |
1079 | dprintk("target matches current values (fid 0x%x, vid 0x%x)\n", | |
1080 | fid, vid); | |
1081 | return 0; | |
1082 | } | |
1083 | ||
1da177e4 LT |
1084 | dprintk("cpu %d, changing to fid 0x%x, vid 0x%x\n", |
1085 | smp_processor_id(), fid, vid); | |
1da177e4 LT |
1086 | freqs.old = find_khz_freq_from_fid(data->currfid); |
1087 | freqs.new = find_khz_freq_from_fid(fid); | |
1f729e06 | 1088 | |
8e7c2597 | 1089 | for_each_cpu(i, data->available_cores) { |
065b807c DJ |
1090 | freqs.cpu = i; |
1091 | cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); | |
1092 | } | |
1da177e4 | 1093 | |
1da177e4 | 1094 | res = transition_fid_vid(data, fid, vid); |
1da177e4 | 1095 | freqs.new = find_khz_freq_from_fid(data->currfid); |
1f729e06 | 1096 | |
8e7c2597 | 1097 | for_each_cpu(i, data->available_cores) { |
1f729e06 DJ |
1098 | freqs.cpu = i; |
1099 | cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); | |
1100 | } | |
1101 | return res; | |
1102 | } | |
1103 | ||
1104 | /* Take a frequency, and issue the hardware pstate transition command */ | |
0e64a0c9 DJ |
1105 | static int transition_frequency_pstate(struct powernow_k8_data *data, |
1106 | unsigned int index) | |
1f729e06 | 1107 | { |
1f729e06 DJ |
1108 | u32 pstate = 0; |
1109 | int res, i; | |
1110 | struct cpufreq_freqs freqs; | |
1111 | ||
1112 | dprintk("cpu %d transition to index %u\n", smp_processor_id(), index); | |
1113 | ||
c5829cd0 | 1114 | /* get MSR index for hardware pstate transition */ |
1f729e06 | 1115 | pstate = index & HW_PSTATE_MASK; |
c5829cd0 | 1116 | if (pstate > data->max_hw_pstate) |
1f729e06 | 1117 | return 0; |
0e64a0c9 DJ |
1118 | freqs.old = find_khz_freq_from_pstate(data->powernow_table, |
1119 | data->currpstate); | |
c5829cd0 | 1120 | freqs.new = find_khz_freq_from_pstate(data->powernow_table, pstate); |
1f729e06 | 1121 | |
8e7c2597 | 1122 | for_each_cpu(i, data->available_cores) { |
1f729e06 DJ |
1123 | freqs.cpu = i; |
1124 | cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); | |
1125 | } | |
1126 | ||
1127 | res = transition_pstate(data, pstate); | |
c5829cd0 | 1128 | freqs.new = find_khz_freq_from_pstate(data->powernow_table, pstate); |
1f729e06 | 1129 | |
8e7c2597 | 1130 | for_each_cpu(i, data->available_cores) { |
065b807c DJ |
1131 | freqs.cpu = i; |
1132 | cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); | |
2e3f8faa | 1133 | } |
1da177e4 LT |
1134 | return res; |
1135 | } | |
1136 | ||
1137 | /* Driver entry point to switch to the target frequency */ | |
0e64a0c9 DJ |
1138 | static int powernowk8_target(struct cpufreq_policy *pol, |
1139 | unsigned targfreq, unsigned relation) | |
1da177e4 | 1140 | { |
fc0e4748 | 1141 | cpumask_t oldmask; |
2c6b8c03 | 1142 | struct powernow_k8_data *data = per_cpu(powernow_data, pol->cpu); |
9180053c AB |
1143 | u32 checkfid; |
1144 | u32 checkvid; | |
1da177e4 LT |
1145 | unsigned int newstate; |
1146 | int ret = -EIO; | |
1147 | ||
4211a303 JS |
1148 | if (!data) |
1149 | return -EINVAL; | |
1150 | ||
9180053c AB |
1151 | checkfid = data->currfid; |
1152 | checkvid = data->currvid; | |
1153 | ||
1da177e4 LT |
1154 | /* only run on specific CPU from here on */ |
1155 | oldmask = current->cpus_allowed; | |
0bc3cc03 | 1156 | set_cpus_allowed_ptr(current, &cpumask_of_cpu(pol->cpu)); |
1da177e4 LT |
1157 | |
1158 | if (smp_processor_id() != pol->cpu) { | |
8aae8284 | 1159 | printk(KERN_ERR PFX "limiting to cpu %u failed\n", pol->cpu); |
1da177e4 LT |
1160 | goto err_out; |
1161 | } | |
1162 | ||
1163 | if (pending_bit_stuck()) { | |
1164 | printk(KERN_ERR PFX "failing targ, change pending bit set\n"); | |
1165 | goto err_out; | |
1166 | } | |
1167 | ||
1168 | dprintk("targ: cpu %d, %d kHz, min %d, max %d, relation %d\n", | |
1169 | pol->cpu, targfreq, pol->min, pol->max, relation); | |
1170 | ||
83844510 | 1171 | if (query_current_values_with_pending_wait(data)) |
1da177e4 | 1172 | goto err_out; |
1da177e4 | 1173 | |
c5829cd0 | 1174 | if (cpu_family != CPU_HW_PSTATE) { |
1f729e06 | 1175 | dprintk("targ: curr fid 0x%x, vid 0x%x\n", |
1da177e4 LT |
1176 | data->currfid, data->currvid); |
1177 | ||
0e64a0c9 DJ |
1178 | if ((checkvid != data->currvid) || |
1179 | (checkfid != data->currfid)) { | |
1f729e06 | 1180 | printk(KERN_INFO PFX |
0e64a0c9 DJ |
1181 | "error - out of sync, fix 0x%x 0x%x, " |
1182 | "vid 0x%x 0x%x\n", | |
1183 | checkfid, data->currfid, | |
1184 | checkvid, data->currvid); | |
1f729e06 | 1185 | } |
1da177e4 LT |
1186 | } |
1187 | ||
0e64a0c9 DJ |
1188 | if (cpufreq_frequency_table_target(pol, data->powernow_table, |
1189 | targfreq, relation, &newstate)) | |
1da177e4 LT |
1190 | goto err_out; |
1191 | ||
14cc3e2b | 1192 | mutex_lock(&fidvid_mutex); |
065b807c | 1193 | |
1da177e4 LT |
1194 | powernow_k8_acpi_pst_values(data, newstate); |
1195 | ||
e7bdd7a5 | 1196 | if (cpu_family == CPU_HW_PSTATE) |
1f729e06 DJ |
1197 | ret = transition_frequency_pstate(data, newstate); |
1198 | else | |
1199 | ret = transition_frequency_fidvid(data, newstate); | |
1200 | if (ret) { | |
1da177e4 LT |
1201 | printk(KERN_ERR PFX "transition frequency failed\n"); |
1202 | ret = 1; | |
14cc3e2b | 1203 | mutex_unlock(&fidvid_mutex); |
1da177e4 LT |
1204 | goto err_out; |
1205 | } | |
14cc3e2b | 1206 | mutex_unlock(&fidvid_mutex); |
065b807c | 1207 | |
e7bdd7a5 | 1208 | if (cpu_family == CPU_HW_PSTATE) |
0e64a0c9 DJ |
1209 | pol->cur = find_khz_freq_from_pstate(data->powernow_table, |
1210 | newstate); | |
1f729e06 DJ |
1211 | else |
1212 | pol->cur = find_khz_freq_from_fid(data->currfid); | |
1da177e4 LT |
1213 | ret = 0; |
1214 | ||
1215 | err_out: | |
fc0e4748 | 1216 | set_cpus_allowed_ptr(current, &oldmask); |
1da177e4 LT |
1217 | return ret; |
1218 | } | |
1219 | ||
1220 | /* Driver entry point to verify the policy and range of frequencies */ | |
1221 | static int powernowk8_verify(struct cpufreq_policy *pol) | |
1222 | { | |
2c6b8c03 | 1223 | struct powernow_k8_data *data = per_cpu(powernow_data, pol->cpu); |
1da177e4 | 1224 | |
4211a303 JS |
1225 | if (!data) |
1226 | return -EINVAL; | |
1227 | ||
1da177e4 LT |
1228 | return cpufreq_frequency_table_verify(pol, data->powernow_table); |
1229 | } | |
1230 | ||
1ff6e97f RR |
1231 | struct init_on_cpu { |
1232 | struct powernow_k8_data *data; | |
1233 | int rc; | |
1234 | }; | |
1235 | ||
1236 | static void __cpuinit powernowk8_cpu_init_on_cpu(void *_init_on_cpu) | |
1237 | { | |
1238 | struct init_on_cpu *init_on_cpu = _init_on_cpu; | |
1239 | ||
1240 | if (pending_bit_stuck()) { | |
1241 | printk(KERN_ERR PFX "failing init, change pending bit set\n"); | |
1242 | init_on_cpu->rc = -ENODEV; | |
1243 | return; | |
1244 | } | |
1245 | ||
1246 | if (query_current_values_with_pending_wait(init_on_cpu->data)) { | |
1247 | init_on_cpu->rc = -ENODEV; | |
1248 | return; | |
1249 | } | |
1250 | ||
1251 | if (cpu_family == CPU_OPTERON) | |
1252 | fidvid_msr_init(); | |
1253 | ||
1254 | init_on_cpu->rc = 0; | |
1255 | } | |
1256 | ||
1da177e4 | 1257 | /* per CPU init entry point to the driver */ |
aa41eb99 | 1258 | static int __cpuinit powernowk8_cpu_init(struct cpufreq_policy *pol) |
1da177e4 | 1259 | { |
b394f1df AM |
1260 | static const char ACPI_PSS_BIOS_BUG_MSG[] = |
1261 | KERN_ERR FW_BUG PFX "No compatible ACPI _PSS objects found.\n" | |
ad361c98 | 1262 | FW_BUG PFX "Try again with latest BIOS.\n"; |
1da177e4 | 1263 | struct powernow_k8_data *data; |
1ff6e97f | 1264 | struct init_on_cpu init_on_cpu; |
d7fa706c | 1265 | int rc; |
1da177e4 | 1266 | |
8aae8284 JS |
1267 | if (!cpu_online(pol->cpu)) |
1268 | return -ENODEV; | |
1269 | ||
1ff6e97f RR |
1270 | smp_call_function_single(pol->cpu, check_supported_cpu, &rc, 1); |
1271 | if (rc) | |
1da177e4 LT |
1272 | return -ENODEV; |
1273 | ||
bfdc708d | 1274 | data = kzalloc(sizeof(struct powernow_k8_data), GFP_KERNEL); |
1da177e4 LT |
1275 | if (!data) { |
1276 | printk(KERN_ERR PFX "unable to alloc powernow_k8_data"); | |
1277 | return -ENOMEM; | |
1278 | } | |
1da177e4 LT |
1279 | |
1280 | data->cpu = pol->cpu; | |
a266d9f1 | 1281 | data->currpstate = HW_PSTATE_INVALID; |
1da177e4 | 1282 | |
a0abd520 | 1283 | if (powernow_k8_cpu_init_acpi(data)) { |
1da177e4 LT |
1284 | /* |
1285 | * Use the PSB BIOS structure. This is only availabe on | |
1286 | * an UP version, and is deprecated by AMD. | |
1287 | */ | |
9ed059e1 | 1288 | if (num_online_cpus() != 1) { |
df182977 | 1289 | printk_once(ACPI_PSS_BIOS_BUG_MSG); |
0cb8bc25 | 1290 | goto err_out; |
1da177e4 LT |
1291 | } |
1292 | if (pol->cpu != 0) { | |
2fd47094 TR |
1293 | printk(KERN_ERR FW_BUG PFX "No ACPI _PSS objects for " |
1294 | "CPU other than CPU0. Complain to your BIOS " | |
1295 | "vendor.\n"); | |
0cb8bc25 | 1296 | goto err_out; |
1da177e4 LT |
1297 | } |
1298 | rc = find_psb_table(data); | |
0cb8bc25 DJ |
1299 | if (rc) |
1300 | goto err_out; | |
1301 | ||
732553e5 ML |
1302 | /* Take a crude guess here. |
1303 | * That guess was in microseconds, so multiply with 1000 */ | |
1304 | pol->cpuinfo.transition_latency = ( | |
1305 | ((data->rvo + 8) * data->vstable * VST_UNITS_20US) + | |
1306 | ((1 << data->irt) * 30)) * 1000; | |
1307 | } else /* ACPI _PSS objects available */ | |
1308 | pol->cpuinfo.transition_latency = get_transition_latency(data); | |
1da177e4 LT |
1309 | |
1310 | /* only run on specific CPU from here on */ | |
1ff6e97f RR |
1311 | init_on_cpu.data = data; |
1312 | smp_call_function_single(data->cpu, powernowk8_cpu_init_on_cpu, | |
1313 | &init_on_cpu, 1); | |
1314 | rc = init_on_cpu.rc; | |
1315 | if (rc != 0) | |
1316 | goto err_out_exit_acpi; | |
1da177e4 | 1317 | |
f607e3a0 | 1318 | if (cpu_family == CPU_HW_PSTATE) |
835481d9 | 1319 | cpumask_copy(pol->cpus, cpumask_of(pol->cpu)); |
f607e3a0 | 1320 | else |
7ad728f9 | 1321 | cpumask_copy(pol->cpus, cpu_core_mask(pol->cpu)); |
835481d9 | 1322 | data->available_cores = pol->cpus; |
1da177e4 | 1323 | |
e7bdd7a5 | 1324 | if (cpu_family == CPU_HW_PSTATE) |
0e64a0c9 DJ |
1325 | pol->cur = find_khz_freq_from_pstate(data->powernow_table, |
1326 | data->currpstate); | |
1f729e06 DJ |
1327 | else |
1328 | pol->cur = find_khz_freq_from_fid(data->currfid); | |
1da177e4 LT |
1329 | dprintk("policy current frequency %d kHz\n", pol->cur); |
1330 | ||
1331 | /* min/max the cpu is capable of */ | |
1332 | if (cpufreq_frequency_table_cpuinfo(pol, data->powernow_table)) { | |
2fd47094 | 1333 | printk(KERN_ERR FW_BUG PFX "invalid powernow_table\n"); |
1da177e4 LT |
1334 | powernow_k8_cpu_exit_acpi(data); |
1335 | kfree(data->powernow_table); | |
1336 | kfree(data); | |
1337 | return -EINVAL; | |
1338 | } | |
1339 | ||
1340 | cpufreq_frequency_table_get_attr(data->powernow_table, pol->cpu); | |
1341 | ||
e7bdd7a5 | 1342 | if (cpu_family == CPU_HW_PSTATE) |
0e64a0c9 DJ |
1343 | dprintk("cpu_init done, current pstate 0x%x\n", |
1344 | data->currpstate); | |
1f729e06 DJ |
1345 | else |
1346 | dprintk("cpu_init done, current fid 0x%x, vid 0x%x\n", | |
1347 | data->currfid, data->currvid); | |
1da177e4 | 1348 | |
2c6b8c03 | 1349 | per_cpu(powernow_data, pol->cpu) = data; |
1da177e4 LT |
1350 | |
1351 | return 0; | |
1352 | ||
1ff6e97f | 1353 | err_out_exit_acpi: |
1da177e4 LT |
1354 | powernow_k8_cpu_exit_acpi(data); |
1355 | ||
0cb8bc25 | 1356 | err_out: |
1da177e4 LT |
1357 | kfree(data); |
1358 | return -ENODEV; | |
1359 | } | |
1360 | ||
0e64a0c9 | 1361 | static int __devexit powernowk8_cpu_exit(struct cpufreq_policy *pol) |
1da177e4 | 1362 | { |
2c6b8c03 | 1363 | struct powernow_k8_data *data = per_cpu(powernow_data, pol->cpu); |
1da177e4 LT |
1364 | |
1365 | if (!data) | |
1366 | return -EINVAL; | |
1367 | ||
1368 | powernow_k8_cpu_exit_acpi(data); | |
1369 | ||
1370 | cpufreq_frequency_table_put_attr(pol->cpu); | |
1371 | ||
1372 | kfree(data->powernow_table); | |
1373 | kfree(data); | |
1374 | ||
1375 | return 0; | |
1376 | } | |
1377 | ||
1ff6e97f RR |
1378 | static void query_values_on_cpu(void *_err) |
1379 | { | |
1380 | int *err = _err; | |
1381 | struct powernow_k8_data *data = __get_cpu_var(powernow_data); | |
1382 | ||
1383 | *err = query_current_values_with_pending_wait(data); | |
1384 | } | |
1385 | ||
0e64a0c9 | 1386 | static unsigned int powernowk8_get(unsigned int cpu) |
1da177e4 | 1387 | { |
e15bc455 | 1388 | struct powernow_k8_data *data = per_cpu(powernow_data, cpu); |
1da177e4 | 1389 | unsigned int khz = 0; |
1ff6e97f | 1390 | int err; |
eef5167e | 1391 | |
1392 | if (!data) | |
1393 | return -EINVAL; | |
1394 | ||
1ff6e97f RR |
1395 | smp_call_function_single(cpu, query_values_on_cpu, &err, true); |
1396 | if (err) | |
1da177e4 LT |
1397 | goto out; |
1398 | ||
58389a86 | 1399 | if (cpu_family == CPU_HW_PSTATE) |
fc0e4748 MT |
1400 | khz = find_khz_freq_from_pstate(data->powernow_table, |
1401 | data->currpstate); | |
58389a86 JD |
1402 | else |
1403 | khz = find_khz_freq_from_fid(data->currfid); | |
1404 | ||
1da177e4 | 1405 | |
b9111b7b | 1406 | out: |
1da177e4 LT |
1407 | return khz; |
1408 | } | |
1409 | ||
0e64a0c9 | 1410 | static struct freq_attr *powernow_k8_attr[] = { |
1da177e4 LT |
1411 | &cpufreq_freq_attr_scaling_available_freqs, |
1412 | NULL, | |
1413 | }; | |
1414 | ||
221dee28 | 1415 | static struct cpufreq_driver cpufreq_amd64_driver = { |
1da177e4 LT |
1416 | .verify = powernowk8_verify, |
1417 | .target = powernowk8_target, | |
1418 | .init = powernowk8_cpu_init, | |
1419 | .exit = __devexit_p(powernowk8_cpu_exit), | |
1420 | .get = powernowk8_get, | |
1421 | .name = "powernow-k8", | |
1422 | .owner = THIS_MODULE, | |
1423 | .attr = powernow_k8_attr, | |
1424 | }; | |
1425 | ||
1426 | /* driver entry point for init */ | |
aa41eb99 | 1427 | static int __cpuinit powernowk8_init(void) |
1da177e4 LT |
1428 | { |
1429 | unsigned int i, supported_cpus = 0; | |
1430 | ||
a7201156 | 1431 | for_each_online_cpu(i) { |
1ff6e97f RR |
1432 | int rc; |
1433 | smp_call_function_single(i, check_supported_cpu, &rc, 1); | |
1434 | if (rc == 0) | |
1da177e4 LT |
1435 | supported_cpus++; |
1436 | } | |
1437 | ||
1438 | if (supported_cpus == num_online_cpus()) { | |
1f729e06 | 1439 | printk(KERN_INFO PFX "Found %d %s " |
904f7a3f | 1440 | "processors (%d cpu cores) (" VERSION ")\n", |
c925401b | 1441 | num_online_nodes(), |
904f7a3f | 1442 | boot_cpu_data.x86_model_id, supported_cpus); |
1da177e4 LT |
1443 | return cpufreq_register_driver(&cpufreq_amd64_driver); |
1444 | } | |
1445 | ||
1446 | return -ENODEV; | |
1447 | } | |
1448 | ||
1449 | /* driver entry point for term */ | |
1450 | static void __exit powernowk8_exit(void) | |
1451 | { | |
1452 | dprintk("exit\n"); | |
1453 | ||
1454 | cpufreq_unregister_driver(&cpufreq_amd64_driver); | |
1455 | } | |
1456 | ||
0e64a0c9 DJ |
1457 | MODULE_AUTHOR("Paul Devriendt <paul.devriendt@amd.com> and " |
1458 | "Mark Langsdorf <mark.langsdorf@amd.com>"); | |
1da177e4 LT |
1459 | MODULE_DESCRIPTION("AMD Athlon 64 and Opteron processor frequency driver."); |
1460 | MODULE_LICENSE("GPL"); | |
1461 | ||
1462 | late_initcall(powernowk8_init); | |
1463 | module_exit(powernowk8_exit); |