[deliverable/linux.git] / arch / x86 / kernel / cpu / cpufreq / speedstep-centrino.c

/*
 * cpufreq driver for Enhanced SpeedStep, as found in Intel's Pentium
 * M (part of the Centrino chipset).
 *
 * Since the original Pentium M, most new Intel CPUs support Enhanced
 * SpeedStep.
 *
 * Despite the "SpeedStep" in the name, this is almost entirely unlike
 * traditional SpeedStep.
 *
 * Modelled on speedstep.c
 *
 * Copyright (C) 2003 Jeremy Fitzhardinge <jeremy@goop.org>
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/cpufreq.h>
#include <linux/sched.h>	/* current */
#include <linux/delay.h>
#include <linux/compiler.h>

#include <asm/msr.h>
#include <asm/processor.h>
#include <asm/cpufeature.h>

#define PFX		"speedstep-centrino: "
#define MAINTAINER	"cpufreq@vger.kernel.org"

#define dprintk(msg...) \
	cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "speedstep-centrino", msg)

#define INTEL_MSR_RANGE	(0xffff)

struct cpu_id
{
	__u8	x86;            /* CPU family */
	__u8	x86_model;	/* model */
	__u8	x86_mask;	/* stepping */
};

enum {
	CPU_BANIAS,
	CPU_DOTHAN_A1,
	CPU_DOTHAN_A2,
	CPU_DOTHAN_B0,
	CPU_MP4HT_D0,
	CPU_MP4HT_E0,
};

static const struct cpu_id cpu_ids[] = {
	[CPU_BANIAS]	= { 6,  9, 5 },
	[CPU_DOTHAN_A1]	= { 6, 13, 1 },
	[CPU_DOTHAN_A2]	= { 6, 13, 2 },
	[CPU_DOTHAN_B0]	= { 6, 13, 6 },
	[CPU_MP4HT_D0]	= {15,  3, 4 },
	[CPU_MP4HT_E0]	= {15,  4, 1 },
};
#define N_IDS	ARRAY_SIZE(cpu_ids)

struct cpu_model
{
	const struct cpu_id *cpu_id;
	const char	*model_name;
	unsigned	max_freq; /* max clock in kHz */

	struct cpufreq_frequency_table *op_points; /* clock/voltage pairs */
};
static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c,
				  const struct cpu_id *x);

/* Operating points for current CPU */
static DEFINE_PER_CPU(struct cpu_model *, centrino_model);
static DEFINE_PER_CPU(const struct cpu_id *, centrino_cpu);

static struct cpufreq_driver centrino_driver;

#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE

/* Computes the correct form for IA32_PERF_CTL MSR for a particular
   frequency/voltage operating point; frequency in MHz, volts in mV.
   This is stored as "index" in the structure. */
#define OP(mhz, mv)							\
	{								\
		.frequency = (mhz) * 1000,				\
		.index = (((mhz)/100) << 8) | ((mv - 700) / 16)		\
	}

/*
 * These voltage tables were derived from the Intel Pentium M
 * datasheet, document 25261202.pdf, Table 5.  I have verified they
 * are consistent with my IBM ThinkPad X31, which has a 1.3GHz Pentium
 * M.
 */

/* Ultra Low Voltage Intel Pentium M processor 900MHz (Banias) */
static struct cpufreq_frequency_table banias_900[] =
{
	OP(600,  844),
	OP(800,  988),
	OP(900, 1004),
	{ .frequency = CPUFREQ_TABLE_END }
};

/* Ultra Low Voltage Intel Pentium M processor 1000MHz (Banias) */
static struct cpufreq_frequency_table banias_1000[] =
{
	OP(600,   844),
	OP(800,   972),
	OP(900,   988),
	OP(1000, 1004),
	{ .frequency = CPUFREQ_TABLE_END }
};

/* Low Voltage Intel Pentium M processor 1.10GHz (Banias) */
static struct cpufreq_frequency_table banias_1100[] =
{
	OP( 600,  956),
	OP( 800, 1020),
	OP( 900, 1100),
	OP(1000, 1164),
	OP(1100, 1180),
	{ .frequency = CPUFREQ_TABLE_END }
};


/* Low Voltage Intel Pentium M processor 1.20GHz (Banias) */
static struct cpufreq_frequency_table banias_1200[] =
{
	OP( 600,  956),
	OP( 800, 1004),
	OP( 900, 1020),
	OP(1000, 1100),
	OP(1100, 1164),
	OP(1200, 1180),
	{ .frequency = CPUFREQ_TABLE_END }
};

/* Intel Pentium M processor 1.30GHz (Banias) */
static struct cpufreq_frequency_table banias_1300[] =
{
	OP( 600,  956),
	OP( 800, 1260),
	OP(1000, 1292),
	OP(1200, 1356),
	OP(1300, 1388),
	{ .frequency = CPUFREQ_TABLE_END }
};

/* Intel Pentium M processor 1.40GHz (Banias) */
static struct cpufreq_frequency_table banias_1400[] =
{
	OP( 600,  956),
	OP( 800, 1180),
	OP(1000, 1308),
	OP(1200, 1436),
	OP(1400, 1484),
	{ .frequency = CPUFREQ_TABLE_END }
};

/* Intel Pentium M processor 1.50GHz (Banias) */
static struct cpufreq_frequency_table banias_1500[] =
{
	OP( 600,  956),
	OP( 800, 1116),
	OP(1000, 1228),
	OP(1200, 1356),
	OP(1400, 1452),
	OP(1500, 1484),
	{ .frequency = CPUFREQ_TABLE_END }
};

/* Intel Pentium M processor 1.60GHz (Banias) */
static struct cpufreq_frequency_table banias_1600[] =
{
	OP( 600,  956),
	OP( 800, 1036),
	OP(1000, 1164),
	OP(1200, 1276),
	OP(1400, 1420),
	OP(1600, 1484),
	{ .frequency = CPUFREQ_TABLE_END }
};

/* Intel Pentium M processor 1.70GHz (Banias) */
static struct cpufreq_frequency_table banias_1700[] =
{
	OP( 600,  956),
	OP( 800, 1004),
	OP(1000, 1116),
	OP(1200, 1228),
	OP(1400, 1308),
	OP(1700, 1484),
	{ .frequency = CPUFREQ_TABLE_END }
};
#undef OP

#define _BANIAS(cpuid, max, name)	\
{	.cpu_id		= cpuid,	\
	.model_name	= "Intel(R) Pentium(R) M processor " name "MHz", \
	.max_freq	= (max)*1000,	\
	.op_points	= banias_##max,	\
}
#define BANIAS(max)	_BANIAS(&cpu_ids[CPU_BANIAS], max, #max)

/* CPU models, their operating frequency range, and freq/voltage
   operating points */
static struct cpu_model models[] =
{
	_BANIAS(&cpu_ids[CPU_BANIAS], 900, " 900"),
	BANIAS(1000),
	BANIAS(1100),
	BANIAS(1200),
	BANIAS(1300),
	BANIAS(1400),
	BANIAS(1500),
	BANIAS(1600),
	BANIAS(1700),

	/* NULL model_name is a wildcard */
	{ &cpu_ids[CPU_DOTHAN_A1], NULL, 0, NULL },
	{ &cpu_ids[CPU_DOTHAN_A2], NULL, 0, NULL },
	{ &cpu_ids[CPU_DOTHAN_B0], NULL, 0, NULL },
	{ &cpu_ids[CPU_MP4HT_D0], NULL, 0, NULL },
	{ &cpu_ids[CPU_MP4HT_E0], NULL, 0, NULL },

	{ NULL, }
};
#undef _BANIAS
#undef BANIAS

static int centrino_cpu_init_table(struct cpufreq_policy *policy)
{
	struct cpuinfo_x86 *cpu = &cpu_data(policy->cpu);
	struct cpu_model *model;

	for(model = models; model->cpu_id != NULL; model++)
		if (centrino_verify_cpu_id(cpu, model->cpu_id) &&
		    (model->model_name == NULL ||
		     strcmp(cpu->x86_model_id, model->model_name) == 0))
			break;

	if (model->cpu_id == NULL) {
		/* No match at all */
		dprintk("no support for CPU model \"%s\": "
		       "send /proc/cpuinfo to " MAINTAINER "\n",
		       cpu->x86_model_id);
		return -ENOENT;
	}

	if (model->op_points == NULL) {
		/* Matched a non-match */
		dprintk("no table support for CPU model \"%s\"\n",
		       cpu->x86_model_id);
		dprintk("try using the acpi-cpufreq driver\n");
		return -ENOENT;
	}

	per_cpu(centrino_model, policy->cpu) = model;

	dprintk("found \"%s\": max frequency: %dkHz\n",
	       model->model_name, model->max_freq);

	return 0;
}

#else
static inline int centrino_cpu_init_table(struct cpufreq_policy *policy)
{
	return -ENODEV;
}
#endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE */

static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c,
				  const struct cpu_id *x)
{
	if ((c->x86 == x->x86) &&
	    (c->x86_model == x->x86_model) &&
	    (c->x86_mask == x->x86_mask))
		return 1;
	return 0;
}

/* To be called only after centrino_model is initialized */
static unsigned extract_clock(unsigned msr, unsigned int cpu, int failsafe)
{
	int i;

	/*
	 * Extract clock in kHz from PERF_CTL value
	 * for centrino, as some DSDTs are buggy.
	 * Ideally, this can be done using the acpi_data structure.
	 */
	if ((per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_BANIAS]) ||
	    (per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_DOTHAN_A1]) ||
	    (per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_DOTHAN_B0])) {
		msr = (msr >> 8) & 0xff;
		return msr * 100000;
	}

	if ((!per_cpu(centrino_model, cpu)) ||
	    (!per_cpu(centrino_model, cpu)->op_points))
		return 0;

	msr &= 0xffff;
	for (i = 0;
		per_cpu(centrino_model, cpu)->op_points[i].frequency
							!= CPUFREQ_TABLE_END;
	     i++) {
		if (msr == per_cpu(centrino_model, cpu)->op_points[i].index)
			return per_cpu(centrino_model, cpu)->
							op_points[i].frequency;
	}
	if (failsafe)
		return per_cpu(centrino_model, cpu)->op_points[i-1].frequency;
	else
		return 0;
}

/* Return the current CPU frequency in kHz */
static unsigned int get_cur_freq(unsigned int cpu)
{
	unsigned l, h;
	unsigned clock_freq;
	cpumask_t saved_mask;

	saved_mask = current->cpus_allowed;
	set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu));
	if (smp_processor_id() != cpu)
		return 0;

	rdmsr(MSR_IA32_PERF_STATUS, l, h);
	clock_freq = extract_clock(l, cpu, 0);

	if (unlikely(clock_freq == 0)) {
		/*
		 * On some CPUs, we can see transient MSR values (which are
		 * not present in _PSS), while CPU is doing some automatic
		 * P-state transition (like TM2). Get the last freq set 
		 * in PERF_CTL.
		 */
		rdmsr(MSR_IA32_PERF_CTL, l, h);
		clock_freq = extract_clock(l, cpu, 1);
	}

	set_cpus_allowed_ptr(current, &saved_mask);
	return clock_freq;
}


static int centrino_cpu_init(struct cpufreq_policy *policy)
{
	struct cpuinfo_x86 *cpu = &cpu_data(policy->cpu);
	unsigned freq;
	unsigned l, h;
	int ret;
	int i;

	/* Only Intel makes Enhanced Speedstep-capable CPUs */
	if (cpu->x86_vendor != X86_VENDOR_INTEL ||
	    !cpu_has(cpu, X86_FEATURE_EST))
		return -ENODEV;

	if (cpu_has(cpu, X86_FEATURE_CONSTANT_TSC))
		centrino_driver.flags |= CPUFREQ_CONST_LOOPS;

	if (policy->cpu != 0)
		return -ENODEV;

	for (i = 0; i < N_IDS; i++)
		if (centrino_verify_cpu_id(cpu, &cpu_ids[i]))
			break;

	if (i != N_IDS)
		per_cpu(centrino_cpu, policy->cpu) = &cpu_ids[i];

	if (!per_cpu(centrino_cpu, policy->cpu)) {
		dprintk("found unsupported CPU with "
		"Enhanced SpeedStep: send /proc/cpuinfo to "
		MAINTAINER "\n");
		return -ENODEV;
	}

	if (centrino_cpu_init_table(policy)) {
		return -ENODEV;
	}

	/* Check to see if Enhanced SpeedStep is enabled, and try to
	   enable it if not. */
	rdmsr(MSR_IA32_MISC_ENABLE, l, h);

	if (!(l & (1<<16))) {
		l |= (1<<16);
		dprintk("trying to enable Enhanced SpeedStep (%x)\n", l);
		wrmsr(MSR_IA32_MISC_ENABLE, l, h);

		/* check to see if it stuck */
		rdmsr(MSR_IA32_MISC_ENABLE, l, h);
		if (!(l & (1<<16))) {
			printk(KERN_INFO PFX
				"couldn't enable Enhanced SpeedStep\n");
			return -ENODEV;
		}
	}

	freq = get_cur_freq(policy->cpu);
	policy->cpuinfo.transition_latency = 10000;
						/* 10uS transition latency */
	policy->cur = freq;

	dprintk("centrino_cpu_init: cur=%dkHz\n", policy->cur);

	ret = cpufreq_frequency_table_cpuinfo(policy,
		per_cpu(centrino_model, policy->cpu)->op_points);
	if (ret)
		return (ret);

	cpufreq_frequency_table_get_attr(
		per_cpu(centrino_model, policy->cpu)->op_points, policy->cpu);

	return 0;
}

static int centrino_cpu_exit(struct cpufreq_policy *policy)
{
	unsigned int cpu = policy->cpu;

	if (!per_cpu(centrino_model, cpu))
		return -ENODEV;

	cpufreq_frequency_table_put_attr(cpu);

	per_cpu(centrino_model, cpu) = NULL;

	return 0;
}

/**
 * centrino_verify - verifies a new CPUFreq policy
 * @policy: new policy
 *
 * Limit must be within this model's frequency range at least one
 * border included.
 */
static int centrino_verify (struct cpufreq_policy *policy)
{
	return cpufreq_frequency_table_verify(policy,
			per_cpu(centrino_model, policy->cpu)->op_points);
}

/**
 * centrino_setpolicy - set a new CPUFreq policy
 * @policy: new policy
 * @target_freq: the target frequency
 * @relation: how that frequency relates to achieved frequency
 *	(CPUFREQ_RELATION_L or CPUFREQ_RELATION_H)
 *
 * Sets a new CPUFreq policy.
 */
struct allmasks {
	cpumask_t		online_policy_cpus;
	cpumask_t		saved_mask;
	cpumask_t		set_mask;
	cpumask_t		covered_cpus;
};

static int centrino_target (struct cpufreq_policy *policy,
			    unsigned int target_freq,
			    unsigned int relation)
{
	unsigned int    newstate = 0;
	unsigned int	msr, oldmsr = 0, h = 0, cpu = policy->cpu;
	struct cpufreq_freqs	freqs;
	int			retval = 0;
	unsigned int		j, k, first_cpu, tmp;
	CPUMASK_ALLOC(allmasks);
	CPUMASK_PTR(online_policy_cpus, allmasks);
	CPUMASK_PTR(saved_mask, allmasks);
	CPUMASK_PTR(set_mask, allmasks);
	CPUMASK_PTR(covered_cpus, allmasks);

	if (unlikely(allmasks == NULL))
		return -ENOMEM;

	if (unlikely(per_cpu(centrino_model, cpu) == NULL)) {
		retval = -ENODEV;
		goto out;
	}

	if (unlikely(cpufreq_frequency_table_target(policy,
			per_cpu(centrino_model, cpu)->op_points,
			target_freq,
			relation,
			&newstate))) {
		retval = -EINVAL;
		goto out;
	}

#ifdef CONFIG_HOTPLUG_CPU
	/* cpufreq holds the hotplug lock, so we are safe from here on */
	cpus_and(*online_policy_cpus, cpu_online_map, policy->cpus);
#else
	*online_policy_cpus = policy->cpus;
#endif

	*saved_mask = current->cpus_allowed;
	first_cpu = 1;
	cpus_clear(*covered_cpus);
	for_each_cpu_mask_nr(j, *online_policy_cpus) {
		/*
		 * Support for SMP systems.
		 * Make sure we are running on CPU that wants to change freq
		 */
		cpus_clear(*set_mask);
		if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
			cpus_or(*set_mask, *set_mask, *online_policy_cpus);
		else
			cpu_set(j, *set_mask);

		set_cpus_allowed_ptr(current, set_mask);
		preempt_disable();
		if (unlikely(!cpu_isset(smp_processor_id(), *set_mask))) {
			dprintk("couldn't limit to CPUs in this domain\n");
			retval = -EAGAIN;
			if (first_cpu) {
				/* We haven't started the transition yet. */
				goto migrate_end;
			}
			preempt_enable();
			break;
		}

		msr = per_cpu(centrino_model, cpu)->op_points[newstate].index;

		if (first_cpu) {
			rdmsr(MSR_IA32_PERF_CTL, oldmsr, h);
			if (msr == (oldmsr & 0xffff)) {
				dprintk("no change needed - msr was and needs "
					"to be %x\n", oldmsr);
				retval = 0;
				goto migrate_end;
			}

			freqs.old = extract_clock(oldmsr, cpu, 0);
			freqs.new = extract_clock(msr, cpu, 0);

			dprintk("target=%dkHz old=%d new=%d msr=%04x\n",
				target_freq, freqs.old, freqs.new, msr);

			for_each_cpu_mask_nr(k, *online_policy_cpus) {
				freqs.cpu = k;
				cpufreq_notify_transition(&freqs,
					CPUFREQ_PRECHANGE);
			}

			first_cpu = 0;
			/* all but 16 LSB are reserved, treat them with care */
			oldmsr &= ~0xffff;
			msr &= 0xffff;
			oldmsr |= msr;
		}

		wrmsr(MSR_IA32_PERF_CTL, oldmsr, h);
		if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY) {
			preempt_enable();
			break;
		}

		cpu_set(j, *covered_cpus);
		preempt_enable();
	}

	for_each_cpu_mask_nr(k, *online_policy_cpus) {
		freqs.cpu = k;
		cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
	}

	if (unlikely(retval)) {
		/*
		 * We have failed halfway through the frequency change.
		 * We have sent callbacks to policy->cpus and
		 * MSRs have already been written on coverd_cpus.
		 * Best effort undo..
		 */

		if (!cpus_empty(*covered_cpus))
			for_each_cpu_mask_nr(j, *covered_cpus) {
				set_cpus_allowed_ptr(current,
						     &cpumask_of_cpu(j));
				wrmsr(MSR_IA32_PERF_CTL, oldmsr, h);
			}

		tmp = freqs.new;
		freqs.new = freqs.old;
		freqs.old = tmp;
		for_each_cpu_mask_nr(j, *online_policy_cpus) {
			freqs.cpu = j;
			cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
			cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
		}
	}
	set_cpus_allowed_ptr(current, saved_mask);
	retval = 0;
	goto out;

migrate_end:
	preempt_enable();
	set_cpus_allowed_ptr(current, saved_mask);
out:
	CPUMASK_FREE(allmasks);
	return retval;
}

static struct freq_attr* centrino_attr[] = {
	&cpufreq_freq_attr_scaling_available_freqs,
	NULL,
};

static struct cpufreq_driver centrino_driver = {
	.name		= "centrino", /* should be speedstep-centrino,
					 but there's a 16 char limit */
	.init		= centrino_cpu_init,
	.exit		= centrino_cpu_exit,
	.verify		= centrino_verify,
	.target		= centrino_target,
	.get		= get_cur_freq,
	.attr           = centrino_attr,
	.owner		= THIS_MODULE,
};


/**
 * centrino_init - initializes the Enhanced SpeedStep CPUFreq driver
 *
 * Initializes the Enhanced SpeedStep support. Returns -ENODEV on
 * unsupported devices, -ENOENT if there's no voltage table for this
 * particular CPU model, -EINVAL on problems during initiatization,
 * and zero on success.
 *
 * This is quite picky.  Not only does the CPU have to advertise the
 * "est" flag in the cpuid capability flags, we look for a specific
 * CPU model and stepping, and we need to have the exact model name in
 * our voltage tables.  That is, be paranoid about not releasing
 * someone's valuable magic smoke.
 */
static int __init centrino_init(void)
{
	struct cpuinfo_x86 *cpu = &cpu_data(0);

	if (!cpu_has(cpu, X86_FEATURE_EST))
		return -ENODEV;

	return cpufreq_register_driver(&centrino_driver);
}

static void __exit centrino_exit(void)
{
	cpufreq_unregister_driver(&centrino_driver);
}

MODULE_AUTHOR ("Jeremy Fitzhardinge <jeremy@goop.org>");
MODULE_DESCRIPTION ("Enhanced SpeedStep driver for Intel Pentium M processors.");
MODULE_LICENSE ("GPL");

late_initcall(centrino_init);
module_exit(centrino_exit);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* cpufreq driver for Enhanced SpeedStep, as found in Intel's Pentium
	3	* M (part of the Centrino chipset).
	4	*
491b07c9 JF	5	* Since the original Pentium M, most new Intel CPUs support Enhanced
	6	* SpeedStep.
	7	*
1da177e4 LT	8	* Despite the "SpeedStep" in the name, this is almost entirely unlike
	9	* traditional SpeedStep.
	10	*
	11	* Modelled on speedstep.c
	12	*
	13	* Copyright (C) 2003 Jeremy Fitzhardinge <jeremy@goop.org>
1da177e4 LT	14	*/
	15
	16	#include <linux/kernel.h>
	17	#include <linux/module.h>
	18	#include <linux/init.h>
	19	#include <linux/cpufreq.h>
4e57b681	20	#include <linux/sched.h> /* current */
1da177e4 LT	21	#include <linux/delay.h>
	22	#include <linux/compiler.h>
	23
1da177e4 LT	24	#include <asm/msr.h>
	25	#include <asm/processor.h>
	26	#include <asm/cpufeature.h>
	27
1da177e4	28	#define PFX "speedstep-centrino: "
8d592257	29	#define MAINTAINER "cpufreq@vger.kernel.org"
1da177e4	30
c4762aba MT	31	#define dprintk(msg...) \
c4762aba MT	32	cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "speedstep-centrino", msg)
1da177e4	33
8b9c6671	34	#define INTEL_MSR_RANGE (0xffff)
1da177e4 LT	35
	36	struct cpu_id
	37	{
	38	__u8 x86; /* CPU family */
	39	__u8 x86_model; /* model */
	40	__u8 x86_mask; /* stepping */
	41	};
	42
	43	enum {
	44	CPU_BANIAS,
	45	CPU_DOTHAN_A1,
	46	CPU_DOTHAN_A2,
	47	CPU_DOTHAN_B0,
8282864a DJ	48	CPU_MP4HT_D0,
8282864a DJ	49	CPU_MP4HT_E0,
1da177e4 LT	50	};
	51
	52	static const struct cpu_id cpu_ids[] = {
	53	[CPU_BANIAS] = { 6, 9, 5 },
	54	[CPU_DOTHAN_A1] = { 6, 13, 1 },
	55	[CPU_DOTHAN_A2] = { 6, 13, 2 },
	56	[CPU_DOTHAN_B0] = { 6, 13, 6 },
8282864a DJ	57	[CPU_MP4HT_D0] = {15, 3, 4 },
8282864a DJ	58	[CPU_MP4HT_E0] = {15, 4, 1 },
1da177e4	59	};
38e548ee	60	#define N_IDS ARRAY_SIZE(cpu_ids)
1da177e4 LT	61
	62	struct cpu_model
	63	{
	64	const struct cpu_id *cpu_id;
	65	const char *model_name;
	66	unsigned max_freq; /* max clock in kHz */
	67
	68	struct cpufreq_frequency_table op_points; / clock/voltage pairs */
	69	};
c4762aba MT	70	static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c,
c4762aba MT	71	const struct cpu_id *x);
1da177e4 LT	72
1da177e4 LT	73	/* Operating points for current CPU */
c4762aba MT	74	static DEFINE_PER_CPU(struct cpu_model *, centrino_model);
c4762aba MT	75	static DEFINE_PER_CPU(const struct cpu_id *, centrino_cpu);
1da177e4 LT	76
	77	static struct cpufreq_driver centrino_driver;
	78
	79	#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE
	80
	81	/* Computes the correct form for IA32_PERF_CTL MSR for a particular
	82	frequency/voltage operating point; frequency in MHz, volts in mV.
	83	This is stored as "index" in the structure. */
	84	#define OP(mhz, mv) \
	85	{ \
	86	.frequency = (mhz) * 1000, \
	87	.index = (((mhz)/100) << 8) \| ((mv - 700) / 16) \
	88	}
	89
	90	/*
	91	* These voltage tables were derived from the Intel Pentium M
	92	* datasheet, document 25261202.pdf, Table 5. I have verified they
	93	* are consistent with my IBM ThinkPad X31, which has a 1.3GHz Pentium
	94	* M.
	95	*/
	96
	97	/* Ultra Low Voltage Intel Pentium M processor 900MHz (Banias) */
	98	static struct cpufreq_frequency_table banias_900[] =
	99	{
	100	OP(600, 844),
	101	OP(800, 988),
	102	OP(900, 1004),
	103	{ .frequency = CPUFREQ_TABLE_END }
	104	};
	105
	106	/* Ultra Low Voltage Intel Pentium M processor 1000MHz (Banias) */
	107	static struct cpufreq_frequency_table banias_1000[] =
	108	{
	109	OP(600, 844),
	110	OP(800, 972),
	111	OP(900, 988),
	112	OP(1000, 1004),
	113	{ .frequency = CPUFREQ_TABLE_END }
	114	};
	115
	116	/* Low Voltage Intel Pentium M processor 1.10GHz (Banias) */
	117	static struct cpufreq_frequency_table banias_1100[] =
	118	{
	119	OP( 600, 956),
	120	OP( 800, 1020),
	121	OP( 900, 1100),
	122	OP(1000, 1164),
	123	OP(1100, 1180),
	124	{ .frequency = CPUFREQ_TABLE_END }
	125	};
	126
	127
	128	/* Low Voltage Intel Pentium M processor 1.20GHz (Banias) */
	129	static struct cpufreq_frequency_table banias_1200[] =
	130	{
	131	OP( 600, 956),
	132	OP( 800, 1004),
	133	OP( 900, 1020),
	134	OP(1000, 1100),
	135	OP(1100, 1164),
	136	OP(1200, 1180),
	137	{ .frequency = CPUFREQ_TABLE_END }
	138	};
	139
140	/* Intel Pentium M processor 1.30GHz (Banias) */
141	static struct cpufreq_frequency_table banias_1300[] =
142	{
143	OP( 600, 956),
144	OP( 800, 1260),
145	OP(1000, 1292),
146	OP(1200, 1356),
147	OP(1300, 1388),
148	{ .frequency = CPUFREQ_TABLE_END }
149	};
150
151	/* Intel Pentium M processor 1.40GHz (Banias) */
152	static struct cpufreq_frequency_table banias_1400[] =
153	{
154	OP( 600, 956),
155	OP( 800, 1180),
156	OP(1000, 1308),
157	OP(1200, 1436),
158	OP(1400, 1484),
159	{ .frequency = CPUFREQ_TABLE_END }
160	};
161
162	/* Intel Pentium M processor 1.50GHz (Banias) */
163	static struct cpufreq_frequency_table banias_1500[] =
164	{
165	OP( 600, 956),
166	OP( 800, 1116),
167	OP(1000, 1228),
168	OP(1200, 1356),
169	OP(1400, 1452),
170	OP(1500, 1484),
171	{ .frequency = CPUFREQ_TABLE_END }
172	};
173
174	/* Intel Pentium M processor 1.60GHz (Banias) */
175	static struct cpufreq_frequency_table banias_1600[] =
176	{
177	OP( 600, 956),
178	OP( 800, 1036),
179	OP(1000, 1164),
180	OP(1200, 1276),
181	OP(1400, 1420),
182	OP(1600, 1484),
183	{ .frequency = CPUFREQ_TABLE_END }
184	};
185
186	/* Intel Pentium M processor 1.70GHz (Banias) */
187	static struct cpufreq_frequency_table banias_1700[] =
188	{
189	OP( 600, 956),
190	OP( 800, 1004),
191	OP(1000, 1116),
192	OP(1200, 1228),
193	OP(1400, 1308),
194	OP(1700, 1484),
195	{ .frequency = CPUFREQ_TABLE_END }
196	};
197	#undef OP
198
199	#define _BANIAS(cpuid, max, name) \
200	{ .cpu_id = cpuid, \
201	.model_name = "Intel(R) Pentium(R) M processor " name "MHz", \
202	.max_freq = (max)*1000, \
203	.op_points = banias_##max, \
204	}
205	#define BANIAS(max) _BANIAS(&cpu_ids[CPU_BANIAS], max, #max)
206
207	/* CPU models, their operating frequency range, and freq/voltage
208	operating points */
209	static struct cpu_model models[] =
210	{
211	_BANIAS(&cpu_ids[CPU_BANIAS], 900, " 900"),
212	BANIAS(1000),
213	BANIAS(1100),
214	BANIAS(1200),
215	BANIAS(1300),
216	BANIAS(1400),
217	BANIAS(1500),
218	BANIAS(1600),
219	BANIAS(1700),
220
221	/* NULL model_name is a wildcard */
222	{ &cpu_ids[CPU_DOTHAN_A1], NULL, 0, NULL },
223	{ &cpu_ids[CPU_DOTHAN_A2], NULL, 0, NULL },
224	{ &cpu_ids[CPU_DOTHAN_B0], NULL, 0, NULL },
8282864a DJ	225	{ &cpu_ids[CPU_MP4HT_D0], NULL, 0, NULL },
8282864a DJ	226	{ &cpu_ids[CPU_MP4HT_E0], NULL, 0, NULL },
1da177e4 LT	227
	228	{ NULL, }
	229	};
	230	#undef _BANIAS
	231	#undef BANIAS
	232
	233	static int centrino_cpu_init_table(struct cpufreq_policy *policy)
	234	{
92cb7612	235	struct cpuinfo_x86 *cpu = &cpu_data(policy->cpu);
1da177e4 LT	236	struct cpu_model *model;
	237
	238	for(model = models; model->cpu_id != NULL; model++)
	239	if (centrino_verify_cpu_id(cpu, model->cpu_id) &&
	240	(model->model_name == NULL \|\|
	241	strcmp(cpu->x86_model_id, model->model_name) == 0))
	242	break;
	243
	244	if (model->cpu_id == NULL) {
	245	/* No match at all */
8c362a5d	246	dprintk("no support for CPU model \"%s\": "
1da177e4 LT	247	"send /proc/cpuinfo to " MAINTAINER "\n",
	248	cpu->x86_model_id);
	249	return -ENOENT;
	250	}
	251
	252	if (model->op_points == NULL) {
	253	/* Matched a non-match */
8c362a5d	254	dprintk("no table support for CPU model \"%s\"\n",
1da177e4	255	cpu->x86_model_id);
68485695	256	dprintk("try using the acpi-cpufreq driver\n");
1da177e4 LT	257	return -ENOENT;
	258	}
	259
c4762aba	260	per_cpu(centrino_model, policy->cpu) = model;
1da177e4 LT	261
	262	dprintk("found \"%s\": max frequency: %dkHz\n",
	263	model->model_name, model->max_freq);
	264
	265	return 0;
	266	}
	267
	268	#else
c4762aba MT	269	static inline int centrino_cpu_init_table(struct cpufreq_policy *policy)
	270	{
	271	return -ENODEV;
	272	}
1da177e4 LT	273	#endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE */
1da177e4 LT	274
c4762aba MT	275	static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c,
c4762aba MT	276	const struct cpu_id *x)
1da177e4 LT	277	{
	278	if ((c->x86 == x->x86) &&
	279	(c->x86_model == x->x86_model) &&
	280	(c->x86_mask == x->x86_mask))
	281	return 1;
	282	return 0;
	283	}
	284
	285	/* To be called only after centrino_model is initialized */
	286	static unsigned extract_clock(unsigned msr, unsigned int cpu, int failsafe)
	287	{
	288	int i;
	289
	290	/*
	291	* Extract clock in kHz from PERF_CTL value
	292	* for centrino, as some DSDTs are buggy.
	293	* Ideally, this can be done using the acpi_data structure.
	294	*/
c4762aba MT	295	if ((per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_BANIAS]) \|\|
	296	(per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_DOTHAN_A1]) \|\|
	297	(per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_DOTHAN_B0])) {
1da177e4 LT	298	msr = (msr >> 8) & 0xff;
	299	return msr * 100000;
	300	}
	301
c4762aba MT	302	if ((!per_cpu(centrino_model, cpu)) \|\|
c4762aba MT	303	(!per_cpu(centrino_model, cpu)->op_points))
1da177e4 LT	304	return 0;
	305
	306	msr &= 0xffff;
c4762aba MT	307	for (i = 0;
	308	per_cpu(centrino_model, cpu)->op_points[i].frequency
	309	!= CPUFREQ_TABLE_END;
	310	i++) {
	311	if (msr == per_cpu(centrino_model, cpu)->op_points[i].index)
	312	return per_cpu(centrino_model, cpu)->
	313	op_points[i].frequency;
1da177e4 LT	314	}
1da177e4 LT	315	if (failsafe)
c4762aba	316	return per_cpu(centrino_model, cpu)->op_points[i-1].frequency;
1da177e4 LT	317	else
	318	return 0;
	319	}
	320
	321	/* Return the current CPU frequency in kHz */
	322	static unsigned int get_cur_freq(unsigned int cpu)
	323	{
	324	unsigned l, h;
	325	unsigned clock_freq;
	326	cpumask_t saved_mask;
	327
	328	saved_mask = current->cpus_allowed;
0bc3cc03	329	set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu));
1da177e4 LT	330	if (smp_processor_id() != cpu)
	331	return 0;
	332
	333	rdmsr(MSR_IA32_PERF_STATUS, l, h);
	334	clock_freq = extract_clock(l, cpu, 0);
	335
	336	if (unlikely(clock_freq == 0)) {
	337	/*
	338	* On some CPUs, we can see transient MSR values (which are
	339	* not present in _PSS), while CPU is doing some automatic
	340	* P-state transition (like TM2). Get the last freq set
	341	* in PERF_CTL.
	342	*/
	343	rdmsr(MSR_IA32_PERF_CTL, l, h);
	344	clock_freq = extract_clock(l, cpu, 1);
	345	}
	346
fc0e4748	347	set_cpus_allowed_ptr(current, &saved_mask);
1da177e4 LT	348	return clock_freq;
	349	}
	350
	351
1da177e4 LT	352	static int centrino_cpu_init(struct cpufreq_policy *policy)
1da177e4 LT	353	{
92cb7612	354	struct cpuinfo_x86 *cpu = &cpu_data(policy->cpu);
1da177e4 LT	355	unsigned freq;
	356	unsigned l, h;
	357	int ret;
	358	int i;
	359
	360	/* Only Intel makes Enhanced Speedstep-capable CPUs */
c4762aba MT	361	if (cpu->x86_vendor != X86_VENDOR_INTEL \|\|
c4762aba MT	362	!cpu_has(cpu, X86_FEATURE_EST))
1da177e4 LT	363	return -ENODEV;
1da177e4 LT	364
8ad5496d	365	if (cpu_has(cpu, X86_FEATURE_CONSTANT_TSC))
1da177e4	366	centrino_driver.flags \|= CPUFREQ_CONST_LOOPS;
1da177e4	367
68485695 AB	368	if (policy->cpu != 0)
68485695 AB	369	return -ENODEV;
1da177e4	370
68485695 AB	371	for (i = 0; i < N_IDS; i++)
	372	if (centrino_verify_cpu_id(cpu, &cpu_ids[i]))
	373	break;
f914be79	374
68485695	375	if (i != N_IDS)
c4762aba	376	per_cpu(centrino_cpu, policy->cpu) = &cpu_ids[i];
f914be79	377
c4762aba	378	if (!per_cpu(centrino_cpu, policy->cpu)) {
68485695 AB	379	dprintk("found unsupported CPU with "
	380	"Enhanced SpeedStep: send /proc/cpuinfo to "
	381	MAINTAINER "\n");
	382	return -ENODEV;
	383	}
1da177e4	384
68485695 AB	385	if (centrino_cpu_init_table(policy)) {
68485695 AB	386	return -ENODEV;
1da177e4 LT	387	}
	388
	389	/* Check to see if Enhanced SpeedStep is enabled, and try to
	390	enable it if not. */
	391	rdmsr(MSR_IA32_MISC_ENABLE, l, h);
	392
	393	if (!(l & (1<<16))) {
	394	l \|= (1<<16);
	395	dprintk("trying to enable Enhanced SpeedStep (%x)\n", l);
	396	wrmsr(MSR_IA32_MISC_ENABLE, l, h);
	397
	398	/* check to see if it stuck */
	399	rdmsr(MSR_IA32_MISC_ENABLE, l, h);
	400	if (!(l & (1<<16))) {
c4762aba MT	401	printk(KERN_INFO PFX
c4762aba MT	402	"couldn't enable Enhanced SpeedStep\n");
1da177e4 LT	403	return -ENODEV;
	404	}
	405	}
	406
	407	freq = get_cur_freq(policy->cpu);
c4762aba MT	408	policy->cpuinfo.transition_latency = 10000;
c4762aba MT	409	/* 10uS transition latency */
1da177e4 LT	410	policy->cur = freq;
	411
	412	dprintk("centrino_cpu_init: cur=%dkHz\n", policy->cur);
	413
c4762aba MT	414	ret = cpufreq_frequency_table_cpuinfo(policy,
c4762aba MT	415	per_cpu(centrino_model, policy->cpu)->op_points);
1da177e4 LT	416	if (ret)
	417	return (ret);
	418
c4762aba MT	419	cpufreq_frequency_table_get_attr(
c4762aba MT	420	per_cpu(centrino_model, policy->cpu)->op_points, policy->cpu);
1da177e4 LT	421
	422	return 0;
	423	}
	424
	425	static int centrino_cpu_exit(struct cpufreq_policy *policy)
	426	{
	427	unsigned int cpu = policy->cpu;
	428
c4762aba	429	if (!per_cpu(centrino_model, cpu))
1da177e4 LT	430	return -ENODEV;
	431
	432	cpufreq_frequency_table_put_attr(cpu);
	433
c4762aba	434	per_cpu(centrino_model, cpu) = NULL;
1da177e4 LT	435
	436	return 0;
	437	}
	438
	439	/**
	440	* centrino_verify - verifies a new CPUFreq policy
	441	* @policy: new policy
	442	*
	443	* Limit must be within this model's frequency range at least one
	444	* border included.
	445	*/
	446	static int centrino_verify (struct cpufreq_policy *policy)
	447	{
c4762aba MT	448	return cpufreq_frequency_table_verify(policy,
c4762aba MT	449	per_cpu(centrino_model, policy->cpu)->op_points);
1da177e4 LT	450	}
	451
	452	/**
	453	* centrino_setpolicy - set a new CPUFreq policy
	454	* @policy: new policy
	455	* @target_freq: the target frequency
c4762aba MT	456	* @relation: how that frequency relates to achieved frequency
c4762aba MT	457	* (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H)
1da177e4 LT	458	*
	459	* Sets a new CPUFreq policy.
	460	*/
eb53fac5 MT	461	struct allmasks {
	462	cpumask_t online_policy_cpus;
	463	cpumask_t saved_mask;
	464	cpumask_t set_mask;
	465	cpumask_t covered_cpus;
	466	};
	467
1da177e4 LT	468	static int centrino_target (struct cpufreq_policy *policy,
	469	unsigned int target_freq,
	470	unsigned int relation)
	471	{
	472	unsigned int newstate = 0;
c52851b6	473	unsigned int msr, oldmsr = 0, h = 0, cpu = policy->cpu;
1da177e4	474	struct cpufreq_freqs freqs;
c52851b6 VP	475	int retval = 0;
c52851b6 VP	476	unsigned int j, k, first_cpu, tmp;
eb53fac5	477	CPUMASK_ALLOC(allmasks);
c4762aba MT	478	CPUMASK_PTR(online_policy_cpus, allmasks);
	479	CPUMASK_PTR(saved_mask, allmasks);
	480	CPUMASK_PTR(set_mask, allmasks);
	481	CPUMASK_PTR(covered_cpus, allmasks);
eb53fac5 MT	482
	483	if (unlikely(allmasks == NULL))
	484	return -ENOMEM;
	485
c4762aba	486	if (unlikely(per_cpu(centrino_model, cpu) == NULL)) {
eb53fac5 MT	487	retval = -ENODEV;
	488	goto out;
	489	}
1da177e4	490
c52851b6	491	if (unlikely(cpufreq_frequency_table_target(policy,
c4762aba	492	per_cpu(centrino_model, cpu)->op_points,
c52851b6 VP	493	target_freq,
	494	relation,
	495	&newstate))) {
eb53fac5 MT	496	retval = -EINVAL;
eb53fac5 MT	497	goto out;
1da177e4 LT	498	}
1da177e4 LT	499
7e1f19e5	500	#ifdef CONFIG_HOTPLUG_CPU
c52851b6	501	/* cpufreq holds the hotplug lock, so we are safe from here on */
eb53fac5	502	cpus_and(*online_policy_cpus, cpu_online_map, policy->cpus);
7e1f19e5	503	#else
eb53fac5	504	*online_policy_cpus = policy->cpus;
7e1f19e5	505	#endif
1da177e4	506
eb53fac5	507	*saved_mask = current->cpus_allowed;
c52851b6	508	first_cpu = 1;
eb53fac5 MT	509	cpus_clear(*covered_cpus);
eb53fac5 MT	510	for_each_cpu_mask_nr(j, *online_policy_cpus) {
c52851b6 VP	511	/*
	512	* Support for SMP systems.
	513	* Make sure we are running on CPU that wants to change freq
	514	*/
eb53fac5	515	cpus_clear(*set_mask);
c52851b6	516	if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
eb53fac5	517	cpus_or(set_mask, set_mask, *online_policy_cpus);
c52851b6	518	else
eb53fac5	519	cpu_set(j, *set_mask);
c52851b6	520
eb53fac5	521	set_cpus_allowed_ptr(current, set_mask);
e8e49190	522	preempt_disable();
eb53fac5	523	if (unlikely(!cpu_isset(smp_processor_id(), *set_mask))) {
c52851b6 VP	524	dprintk("couldn't limit to CPUs in this domain\n");
	525	retval = -EAGAIN;
	526	if (first_cpu) {
	527	/* We haven't started the transition yet. */
	528	goto migrate_end;
	529	}
e8e49190	530	preempt_enable();
c52851b6 VP	531	break;
c52851b6 VP	532	}
1da177e4	533
c4762aba	534	msr = per_cpu(centrino_model, cpu)->op_points[newstate].index;
c52851b6 VP	535
	536	if (first_cpu) {
	537	rdmsr(MSR_IA32_PERF_CTL, oldmsr, h);
	538	if (msr == (oldmsr & 0xffff)) {
	539	dprintk("no change needed - msr was and needs "
	540	"to be %x\n", oldmsr);
	541	retval = 0;
	542	goto migrate_end;
	543	}
	544
	545	freqs.old = extract_clock(oldmsr, cpu, 0);
	546	freqs.new = extract_clock(msr, cpu, 0);
	547
	548	dprintk("target=%dkHz old=%d new=%d msr=%04x\n",
	549	target_freq, freqs.old, freqs.new, msr);
	550
eb53fac5	551	for_each_cpu_mask_nr(k, *online_policy_cpus) {
c52851b6 VP	552	freqs.cpu = k;
	553	cpufreq_notify_transition(&freqs,
	554	CPUFREQ_PRECHANGE);
	555	}
	556
	557	first_cpu = 0;
	558	/* all but 16 LSB are reserved, treat them with care */
	559	oldmsr &= ~0xffff;
	560	msr &= 0xffff;
	561	oldmsr \|= msr;
	562	}
1da177e4	563
c52851b6	564	wrmsr(MSR_IA32_PERF_CTL, oldmsr, h);
e8e49190 DJ	565	if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY) {
e8e49190 DJ	566	preempt_enable();
c52851b6	567	break;
e8e49190	568	}
1da177e4	569
eb53fac5	570	cpu_set(j, *covered_cpus);
e8e49190	571	preempt_enable();
c52851b6	572	}
1da177e4	573
eb53fac5	574	for_each_cpu_mask_nr(k, *online_policy_cpus) {
c52851b6 VP	575	freqs.cpu = k;
	576	cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
	577	}
1da177e4	578
c52851b6 VP	579	if (unlikely(retval)) {
	580	/*
	581	* We have failed halfway through the frequency change.
	582	* We have sent callbacks to policy->cpus and
	583	* MSRs have already been written on coverd_cpus.
	584	* Best effort undo..
	585	*/
1da177e4	586
0bc3cc03	587	if (!cpus_empty(*covered_cpus))
eb53fac5	588	for_each_cpu_mask_nr(j, *covered_cpus) {
0bc3cc03 MT	589	set_cpus_allowed_ptr(current,
0bc3cc03 MT	590	&cpumask_of_cpu(j));
c52851b6 VP	591	wrmsr(MSR_IA32_PERF_CTL, oldmsr, h);
c52851b6 VP	592	}
1da177e4	593
c52851b6 VP	594	tmp = freqs.new;
	595	freqs.new = freqs.old;
	596	freqs.old = tmp;
eb53fac5	597	for_each_cpu_mask_nr(j, *online_policy_cpus) {
c52851b6 VP	598	freqs.cpu = j;
	599	cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
	600	cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
	601	}
	602	}
eb53fac5 MT	603	set_cpus_allowed_ptr(current, saved_mask);
	604	retval = 0;
	605	goto out;
1da177e4	606
1da177e4	607	migrate_end:
e8e49190	608	preempt_enable();
eb53fac5 MT	609	set_cpus_allowed_ptr(current, saved_mask);
	610	out:
	611	CPUMASK_FREE(allmasks);
	612	return retval;
1da177e4 LT	613	}
	614
	615	static struct freq_attr* centrino_attr[] = {
	616	&cpufreq_freq_attr_scaling_available_freqs,
	617	NULL,
	618	};
	619
	620	static struct cpufreq_driver centrino_driver = {
	621	.name = "centrino", /* should be speedstep-centrino,
	622	but there's a 16 char limit */
	623	.init = centrino_cpu_init,
	624	.exit = centrino_cpu_exit,
	625	.verify = centrino_verify,
	626	.target = centrino_target,
	627	.get = get_cur_freq,
	628	.attr = centrino_attr,
	629	.owner = THIS_MODULE,
	630	};
	631
	632
	633	/**
	634	* centrino_init - initializes the Enhanced SpeedStep CPUFreq driver
	635	*
	636	* Initializes the Enhanced SpeedStep support. Returns -ENODEV on
	637	* unsupported devices, -ENOENT if there's no voltage table for this
	638	* particular CPU model, -EINVAL on problems during initiatization,
	639	* and zero on success.
	640	*
	641	* This is quite picky. Not only does the CPU have to advertise the
	642	* "est" flag in the cpuid capability flags, we look for a specific
	643	* CPU model and stepping, and we need to have the exact model name in
	644	* our voltage tables. That is, be paranoid about not releasing
	645	* someone's valuable magic smoke.
	646	*/
	647	static int __init centrino_init(void)
	648	{
92cb7612	649	struct cpuinfo_x86 *cpu = &cpu_data(0);
1da177e4 LT	650
	651	if (!cpu_has(cpu, X86_FEATURE_EST))
	652	return -ENODEV;
	653
	654	return cpufreq_register_driver(&centrino_driver);
	655	}
	656
	657	static void __exit centrino_exit(void)
	658	{
	659	cpufreq_unregister_driver(&centrino_driver);
	660	}
	661
	662	MODULE_AUTHOR ("Jeremy Fitzhardinge <jeremy@goop.org>");
	663	MODULE_DESCRIPTION ("Enhanced SpeedStep driver for Intel Pentium M processors.");
	664	MODULE_LICENSE ("GPL");
	665
	666	late_initcall(centrino_init);
	667	module_exit(centrino_exit);