[deliverable/linux.git] / arch / x86 / kernel / cpu / cpufreq / speedstep-lib.c

/*
 * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
 *
 *  Licensed under the terms of the GNU GPL License version 2.
 *
 *  Library for common functions for Intel SpeedStep v.1 and v.2 support
 *
 *  BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/cpufreq.h>
#include <linux/slab.h>

#include <asm/msr.h>
#include "speedstep-lib.h"

#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, \
		"speedstep-lib", msg)

#define PFX "speedstep-lib: "

#ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
static int relaxed_check;
#else
#define relaxed_check 0
#endif

/*********************************************************************
 *                   GET PROCESSOR CORE SPEED IN KHZ                 *
 *********************************************************************/

static unsigned int pentium3_get_frequency(unsigned int processor)
{
	/* See table 14 of p3_ds.pdf and table 22 of 29834003.pdf */
	struct {
		unsigned int ratio;	/* Frequency Multiplier (x10) */
		u8 bitmap;		/* power on configuration bits
					[27, 25:22] (in MSR 0x2a) */
	} msr_decode_mult[] = {
		{ 30, 0x01 },
		{ 35, 0x05 },
		{ 40, 0x02 },
		{ 45, 0x06 },
		{ 50, 0x00 },
		{ 55, 0x04 },
		{ 60, 0x0b },
		{ 65, 0x0f },
		{ 70, 0x09 },
		{ 75, 0x0d },
		{ 80, 0x0a },
		{ 85, 0x26 },
		{ 90, 0x20 },
		{ 100, 0x2b },
		{ 0, 0xff }	/* error or unknown value */
	};

	/* PIII(-M) FSB settings: see table b1-b of 24547206.pdf */
	struct {
		unsigned int value;	/* Front Side Bus speed in MHz */
		u8 bitmap;		/* power on configuration bits [18: 19]
					(in MSR 0x2a) */
	} msr_decode_fsb[] = {
		{  66, 0x0 },
		{ 100, 0x2 },
		{ 133, 0x1 },
		{   0, 0xff}
	};

	u32 msr_lo, msr_tmp;
	int i = 0, j = 0;

	/* read MSR 0x2a - we only need the low 32 bits */
	rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
	dprintk("P3 - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
	msr_tmp = msr_lo;

	/* decode the FSB */
	msr_tmp &= 0x00c0000;
	msr_tmp >>= 18;
	while (msr_tmp != msr_decode_fsb[i].bitmap) {
		if (msr_decode_fsb[i].bitmap == 0xff)
			return 0;
		i++;
	}

	/* decode the multiplier */
	if (processor == SPEEDSTEP_CPU_PIII_C_EARLY) {
		dprintk("workaround for early PIIIs\n");
		msr_lo &= 0x03c00000;
	} else
		msr_lo &= 0x0bc00000;
	msr_lo >>= 22;
	while (msr_lo != msr_decode_mult[j].bitmap) {
		if (msr_decode_mult[j].bitmap == 0xff)
			return 0;
		j++;
	}

	dprintk("speed is %u\n",
		(msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100));

	return msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100;
}


static unsigned int pentiumM_get_frequency(void)
{
	u32 msr_lo, msr_tmp;

	rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
	dprintk("PM - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);

	/* see table B-2 of 24547212.pdf */
	if (msr_lo & 0x00040000) {
		printk(KERN_DEBUG PFX "PM - invalid FSB: 0x%x 0x%x\n",
				msr_lo, msr_tmp);
		return 0;
	}

	msr_tmp = (msr_lo >> 22) & 0x1f;
	dprintk("bits 22-26 are 0x%x, speed is %u\n",
			msr_tmp, (msr_tmp * 100 * 1000));

	return msr_tmp * 100 * 1000;
}

static unsigned int pentium_core_get_frequency(void)
{
	u32 fsb = 0;
	u32 msr_lo, msr_tmp;
	int ret;

	rdmsr(MSR_FSB_FREQ, msr_lo, msr_tmp);
	/* see table B-2 of 25366920.pdf */
	switch (msr_lo & 0x07) {
	case 5:
		fsb = 100000;
		break;
	case 1:
		fsb = 133333;
		break;
	case 3:
		fsb = 166667;
		break;
	case 2:
		fsb = 200000;
		break;
	case 0:
		fsb = 266667;
		break;
	case 4:
		fsb = 333333;
		break;
	default:
		printk(KERN_ERR "PCORE - MSR_FSB_FREQ undefined value");
	}

	rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
	dprintk("PCORE - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n",
			msr_lo, msr_tmp);

	msr_tmp = (msr_lo >> 22) & 0x1f;
	dprintk("bits 22-26 are 0x%x, speed is %u\n",
			msr_tmp, (msr_tmp * fsb));

	ret = (msr_tmp * fsb);
	return ret;
}


static unsigned int pentium4_get_frequency(void)
{
	struct cpuinfo_x86 *c = &boot_cpu_data;
	u32 msr_lo, msr_hi, mult;
	unsigned int fsb = 0;
	unsigned int ret;

	rdmsr(0x2c, msr_lo, msr_hi);

	dprintk("P4 - MSR_EBC_FREQUENCY_ID: 0x%x 0x%x\n", msr_lo, msr_hi);

	/* decode the FSB: see IA-32 Intel (C) Architecture Software
	 * Developer's Manual, Volume 3: System Prgramming Guide,
	 * revision #12 in Table B-1: MSRs in the Pentium 4 and
	 * Intel Xeon Processors, on page B-4 and B-5.
	 */
	if (c->x86_model < 2)
		fsb = 100 * 1000;
	else {
		u8 fsb_code = (msr_lo >> 16) & 0x7;
		switch (fsb_code) {
		case 0:
			fsb = 100 * 1000;
			break;
		case 1:
			fsb = 13333 * 10;
			break;
		case 2:
			fsb = 200 * 1000;
			break;
		}
	}

	if (!fsb)
		printk(KERN_DEBUG PFX "couldn't detect FSB speed. "
				"Please send an e-mail to <linux@brodo.de>\n");

	/* Multiplier. */
	mult = msr_lo >> 24;

	dprintk("P4 - FSB %u kHz; Multiplier %u; Speed %u kHz\n",
			fsb, mult, (fsb * mult));

	ret = (fsb * mult);
	return ret;
}


unsigned int speedstep_get_frequency(unsigned int processor)
{
	switch (processor) {
	case SPEEDSTEP_CPU_PCORE:
		return pentium_core_get_frequency();
	case SPEEDSTEP_CPU_PM:
		return pentiumM_get_frequency();
	case SPEEDSTEP_CPU_P4D:
	case SPEEDSTEP_CPU_P4M:
		return pentium4_get_frequency();
	case SPEEDSTEP_CPU_PIII_T:
	case SPEEDSTEP_CPU_PIII_C:
	case SPEEDSTEP_CPU_PIII_C_EARLY:
		return pentium3_get_frequency(processor);
	default:
		return 0;
	};
	return 0;
}
EXPORT_SYMBOL_GPL(speedstep_get_frequency);


/*********************************************************************
 *                 DETECT SPEEDSTEP-CAPABLE PROCESSOR                *
 *********************************************************************/

unsigned int speedstep_detect_processor(void)
{
	struct cpuinfo_x86 *c = &cpu_data(0);
	u32 ebx, msr_lo, msr_hi;

	dprintk("x86: %x, model: %x\n", c->x86, c->x86_model);

	if ((c->x86_vendor != X86_VENDOR_INTEL) ||
	    ((c->x86 != 6) && (c->x86 != 0xF)))
		return 0;

	if (c->x86 == 0xF) {
		/* Intel Mobile Pentium 4-M
		 * or Intel Mobile Pentium 4 with 533 MHz FSB */
		if (c->x86_model != 2)
			return 0;

		ebx = cpuid_ebx(0x00000001);
		ebx &= 0x000000FF;

		dprintk("ebx value is %x, x86_mask is %x\n", ebx, c->x86_mask);

		switch (c->x86_mask) {
		case 4:
			/*
			 * B-stepping [M-P4-M]
			 * sample has ebx = 0x0f, production has 0x0e.
			 */
			if ((ebx == 0x0e) || (ebx == 0x0f))
				return SPEEDSTEP_CPU_P4M;
			break;
		case 7:
			/*
			 * C-stepping [M-P4-M]
			 * needs to have ebx=0x0e, else it's a celeron:
			 * cf. 25130917.pdf / page 7, footnote 5 even
			 * though 25072120.pdf / page 7 doesn't say
			 * samples are only of B-stepping...
			 */
			if (ebx == 0x0e)
				return SPEEDSTEP_CPU_P4M;
			break;
		case 9:
			/*
			 * D-stepping [M-P4-M or M-P4/533]
			 *
			 * this is totally strange: CPUID 0x0F29 is
			 * used by M-P4-M, M-P4/533 and(!) Celeron CPUs.
			 * The latter need to be sorted out as they don't
			 * support speedstep.
			 * Celerons with CPUID 0x0F29 may have either
			 * ebx=0x8 or 0xf -- 25130917.pdf doesn't say anything
			 * specific.
			 * M-P4-Ms may have either ebx=0xe or 0xf [see above]
			 * M-P4/533 have either ebx=0xe or 0xf. [25317607.pdf]
			 * also, M-P4M HTs have ebx=0x8, too
			 * For now, they are distinguished by the model_id
			 * string
			 */
			if ((ebx == 0x0e) ||
				(strstr(c->x86_model_id,
				    "Mobile Intel(R) Pentium(R) 4") != NULL))
				return SPEEDSTEP_CPU_P4M;
			break;
		default:
			break;
		}
		return 0;
	}

	switch (c->x86_model) {
	case 0x0B: /* Intel PIII [Tualatin] */
		/* cpuid_ebx(1) is 0x04 for desktop PIII,
		 * 0x06 for mobile PIII-M */
		ebx = cpuid_ebx(0x00000001);
		dprintk("ebx is %x\n", ebx);

		ebx &= 0x000000FF;

		if (ebx != 0x06)
			return 0;

		/* So far all PIII-M processors support SpeedStep. See
		 * Intel's 24540640.pdf of June 2003
		 */
		return SPEEDSTEP_CPU_PIII_T;

	case 0x08: /* Intel PIII [Coppermine] */

		/* all mobile PIII Coppermines have FSB 100 MHz
		 * ==> sort out a few desktop PIIIs. */
		rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_hi);
		dprintk("Coppermine: MSR_IA32_EBL_CR_POWERON is 0x%x, 0x%x\n",
				msr_lo, msr_hi);
		msr_lo &= 0x00c0000;
		if (msr_lo != 0x0080000)
			return 0;

		/*
		 * If the processor is a mobile version,
		 * platform ID has bit 50 set
		 * it has SpeedStep technology if either
		 * bit 56 or 57 is set
		 */
		rdmsr(MSR_IA32_PLATFORM_ID, msr_lo, msr_hi);
		dprintk("Coppermine: MSR_IA32_PLATFORM ID is 0x%x, 0x%x\n",
				msr_lo, msr_hi);
		if ((msr_hi & (1<<18)) &&
		    (relaxed_check ? 1 : (msr_hi & (3<<24)))) {
			if (c->x86_mask == 0x01) {
				dprintk("early PIII version\n");
				return SPEEDSTEP_CPU_PIII_C_EARLY;
			} else
				return SPEEDSTEP_CPU_PIII_C;
		}

	default:
		return 0;
	}
}
EXPORT_SYMBOL_GPL(speedstep_detect_processor);


/*********************************************************************
 *                     DETECT SPEEDSTEP SPEEDS                       *
 *********************************************************************/

unsigned int speedstep_get_freqs(unsigned int processor,
				  unsigned int *low_speed,
				  unsigned int *high_speed,
				  unsigned int *transition_latency,
				  void (*set_state) (unsigned int state))
{
	unsigned int prev_speed;
	unsigned int ret = 0;
	unsigned long flags;
	struct timeval tv1, tv2;

	if ((!processor) || (!low_speed) || (!high_speed) || (!set_state))
		return -EINVAL;

	dprintk("trying to determine both speeds\n");

	/* get current speed */
	prev_speed = speedstep_get_frequency(processor);
	if (!prev_speed)
		return -EIO;

	dprintk("previous speed is %u\n", prev_speed);

	local_irq_save(flags);

	/* switch to low state */
	set_state(SPEEDSTEP_LOW);
	*low_speed = speedstep_get_frequency(processor);
	if (!*low_speed) {
		ret = -EIO;
		goto out;
	}

	dprintk("low speed is %u\n", *low_speed);

	/* start latency measurement */
	if (transition_latency)
		do_gettimeofday(&tv1);

	/* switch to high state */
	set_state(SPEEDSTEP_HIGH);

	/* end latency measurement */
	if (transition_latency)
		do_gettimeofday(&tv2);

	*high_speed = speedstep_get_frequency(processor);
	if (!*high_speed) {
		ret = -EIO;
		goto out;
	}

	dprintk("high speed is %u\n", *high_speed);

	if (*low_speed == *high_speed) {
		ret = -ENODEV;
		goto out;
	}

	/* switch to previous state, if necessary */
	if (*high_speed != prev_speed)
		set_state(SPEEDSTEP_LOW);

	if (transition_latency) {
		*transition_latency = (tv2.tv_sec - tv1.tv_sec) * USEC_PER_SEC +
			tv2.tv_usec - tv1.tv_usec;
		dprintk("transition latency is %u uSec\n", *transition_latency);

		/* convert uSec to nSec and add 20% for safety reasons */
		*transition_latency *= 1200;

		/* check if the latency measurement is too high or too low
		 * and set it to a safe value (500uSec) in that case
		 */
		if (*transition_latency > 10000000 ||
		    *transition_latency < 50000) {
			printk(KERN_WARNING PFX "frequency transition "
					"measured seems out of range (%u "
					"nSec), falling back to a safe one of"
					"%u nSec.\n",
					*transition_latency, 500000);
			*transition_latency = 500000;
		}
	}

out:
	local_irq_restore(flags);
	return ret;
}
EXPORT_SYMBOL_GPL(speedstep_get_freqs);

#ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
module_param(relaxed_check, int, 0444);
MODULE_PARM_DESC(relaxed_check,
		"Don't do all checks for speedstep capability.");
#endif

MODULE_AUTHOR("Dominik Brodowski <linux@brodo.de>");
MODULE_DESCRIPTION("Library for Intel SpeedStep 1 or 2 cpufreq drivers.");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
	3	*
	4	* Licensed under the terms of the GNU GPL License version 2.
	5	*
	6	* Library for common functions for Intel SpeedStep v.1 and v.2 support
	7	*
	8	* BIG FAT DISCLAIMER: Work in progress code. Possibly dangerous
	9	*/
	10
	11	#include <linux/kernel.h>
32ee8c3e	12	#include <linux/module.h>
1da177e4 LT	13	#include <linux/moduleparam.h>
	14	#include <linux/init.h>
	15	#include <linux/cpufreq.h>
1da177e4 LT	16	#include <linux/slab.h>
	17
	18	#include <asm/msr.h>
	19	#include "speedstep-lib.h"
	20
bbfebd66 DJ	21	#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, \
	22	"speedstep-lib", msg)
	23
	24	#define PFX "speedstep-lib: "
1da177e4 LT	25
1da177e4 LT	26	#ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
bbfebd66	27	static int relaxed_check;
1da177e4 LT	28	#else
	29	#define relaxed_check 0
	30	#endif
	31
	32	/*********************************************************************
	33	* GET PROCESSOR CORE SPEED IN KHZ *
	34	*********************************************************************/
	35
bbfebd66	36	static unsigned int pentium3_get_frequency(unsigned int processor)
1da177e4	37	{
bbfebd66	38	/* See table 14 of p3_ds.pdf and table 22 of 29834003.pdf */
1da177e4 LT	39	struct {
1da177e4 LT	40	unsigned int ratio; /* Frequency Multiplier (x10) */
32ee8c3e DJ	41	u8 bitmap; /* power on configuration bits
32ee8c3e DJ	42	[27, 25:22] (in MSR 0x2a) */
bbfebd66	43	} msr_decode_mult[] = {
1da177e4 LT	44	{ 30, 0x01 },
	45	{ 35, 0x05 },
	46	{ 40, 0x02 },
	47	{ 45, 0x06 },
	48	{ 50, 0x00 },
	49	{ 55, 0x04 },
	50	{ 60, 0x0b },
	51	{ 65, 0x0f },
	52	{ 70, 0x09 },
	53	{ 75, 0x0d },
	54	{ 80, 0x0a },
	55	{ 85, 0x26 },
	56	{ 90, 0x20 },
	57	{ 100, 0x2b },
bbfebd66	58	{ 0, 0xff } /* error or unknown value */
1da177e4 LT	59	};
	60
	61	/* PIII(-M) FSB settings: see table b1-b of 24547206.pdf */
	62	struct {
32ee8c3e DJ	63	unsigned int value; /* Front Side Bus speed in MHz */
	64	u8 bitmap; /* power on configuration bits [18: 19]
	65	(in MSR 0x2a) */
bbfebd66	66	} msr_decode_fsb[] = {
1da177e4 LT	67	{ 66, 0x0 },
	68	{ 100, 0x2 },
	69	{ 133, 0x1 },
	70	{ 0, 0xff}
	71	};
	72
32ee8c3e DJ	73	u32 msr_lo, msr_tmp;
32ee8c3e DJ	74	int i = 0, j = 0;
1da177e4 LT	75
	76	/* read MSR 0x2a - we only need the low 32 bits */
	77	rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
	78	dprintk("P3 - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
	79	msr_tmp = msr_lo;
	80
	81	/* decode the FSB */
	82	msr_tmp &= 0x00c0000;
	83	msr_tmp >>= 18;
	84	while (msr_tmp != msr_decode_fsb[i].bitmap) {
	85	if (msr_decode_fsb[i].bitmap == 0xff)
	86	return 0;
	87	i++;
	88	}
	89
	90	/* decode the multiplier */
bbfebd66	91	if (processor == SPEEDSTEP_CPU_PIII_C_EARLY) {
1da177e4 LT	92	dprintk("workaround for early PIIIs\n");
	93	msr_lo &= 0x03c00000;
	94	} else
	95	msr_lo &= 0x0bc00000;
	96	msr_lo >>= 22;
	97	while (msr_lo != msr_decode_mult[j].bitmap) {
	98	if (msr_decode_mult[j].bitmap == 0xff)
	99	return 0;
	100	j++;
	101	}
	102
bbfebd66 DJ	103	dprintk("speed is %u\n",
bbfebd66 DJ	104	(msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100));
1da177e4	105
bbfebd66	106	return msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100;
1da177e4 LT	107	}
	108
	109
	110	static unsigned int pentiumM_get_frequency(void)
	111	{
32ee8c3e	112	u32 msr_lo, msr_tmp;
1da177e4 LT	113
	114	rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
	115	dprintk("PM - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
	116
	117	/* see table B-2 of 24547212.pdf */
	118	if (msr_lo & 0x00040000) {
bbfebd66 DJ	119	printk(KERN_DEBUG PFX "PM - invalid FSB: 0x%x 0x%x\n",
bbfebd66 DJ	120	msr_lo, msr_tmp);
1da177e4 LT	121	return 0;
	122	}
	123
	124	msr_tmp = (msr_lo >> 22) & 0x1f;
bbfebd66 DJ	125	dprintk("bits 22-26 are 0x%x, speed is %u\n",
bbfebd66 DJ	126	msr_tmp, (msr_tmp * 100 * 1000));
1da177e4	127
bbfebd66	128	return msr_tmp * 100 * 1000;
1da177e4 LT	129	}
1da177e4 LT	130
4e74663c DB	131	static unsigned int pentium_core_get_frequency(void)
	132	{
	133	u32 fsb = 0;
	134	u32 msr_lo, msr_tmp;
bbfebd66	135	int ret;
4e74663c DB	136
4e74663c DB	137	rdmsr(MSR_FSB_FREQ, msr_lo, msr_tmp);
e11952b9	138	/* see table B-2 of 25366920.pdf */
4e74663c DB	139	switch (msr_lo & 0x07) {
4e74663c DB	140	case 5:
e11952b9	141	fsb = 100000;
4e74663c DB	142	break;
4e74663c DB	143	case 1:
e11952b9	144	fsb = 133333;
4e74663c DB	145	break;
4e74663c DB	146	case 3:
e11952b9	147	fsb = 166667;
4e74663c	148	break;
c60e19eb HRK	149	case 2:
	150	fsb = 200000;
	151	break;
	152	case 0:
	153	fsb = 266667;
	154	break;
	155	case 4:
	156	fsb = 333333;
	157	break;
4e74663c DB	158	default:
	159	printk(KERN_ERR "PCORE - MSR_FSB_FREQ undefined value");
	160	}
	161
	162	rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
bbfebd66 DJ	163	dprintk("PCORE - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n",
bbfebd66 DJ	164	msr_lo, msr_tmp);
4e74663c DB	165
4e74663c DB	166	msr_tmp = (msr_lo >> 22) & 0x1f;
bbfebd66 DJ	167	dprintk("bits 22-26 are 0x%x, speed is %u\n",
bbfebd66 DJ	168	msr_tmp, (msr_tmp * fsb));
4e74663c	169
bbfebd66 DJ	170	ret = (msr_tmp * fsb);
bbfebd66 DJ	171	return ret;
4e74663c	172	}
e11952b9	173
1da177e4 LT	174
	175	static unsigned int pentium4_get_frequency(void)
	176	{
	177	struct cpuinfo_x86 *c = &boot_cpu_data;
	178	u32 msr_lo, msr_hi, mult;
	179	unsigned int fsb = 0;
bbfebd66	180	unsigned int ret;
1da177e4 LT	181
	182	rdmsr(0x2c, msr_lo, msr_hi);
	183
	184	dprintk("P4 - MSR_EBC_FREQUENCY_ID: 0x%x 0x%x\n", msr_lo, msr_hi);
	185
32ee8c3e	186	/* decode the FSB: see IA-32 Intel (C) Architecture Software
1da177e4 LT	187	* Developer's Manual, Volume 3: System Prgramming Guide,
	188	* revision #12 in Table B-1: MSRs in the Pentium 4 and
	189	* Intel Xeon Processors, on page B-4 and B-5.
	190	*/
	191	if (c->x86_model < 2)
	192	fsb = 100 * 1000;
	193	else {
	194	u8 fsb_code = (msr_lo >> 16) & 0x7;
	195	switch (fsb_code) {
	196	case 0:
	197	fsb = 100 * 1000;
	198	break;
	199	case 1:
	200	fsb = 13333 * 10;
	201	break;
	202	case 2:
	203	fsb = 200 * 1000;
	204	break;
	205	}
	206	}
	207
	208	if (!fsb)
bbfebd66 DJ	209	printk(KERN_DEBUG PFX "couldn't detect FSB speed. "
bbfebd66 DJ	210	"Please send an e-mail to <linux@brodo.de>\n");
1da177e4 LT	211
1da177e4 LT	212	/* Multiplier. */
ed9cbcd4	213	mult = msr_lo >> 24;
1da177e4	214
bbfebd66 DJ	215	dprintk("P4 - FSB %u kHz; Multiplier %u; Speed %u kHz\n",
bbfebd66 DJ	216	fsb, mult, (fsb * mult));
1da177e4	217
bbfebd66 DJ	218	ret = (fsb * mult);
bbfebd66 DJ	219	return ret;
1da177e4 LT	220	}
1da177e4 LT	221
32ee8c3e	222
bbfebd66	223	unsigned int speedstep_get_frequency(unsigned int processor)
1da177e4 LT	224	{
1da177e4 LT	225	switch (processor) {
bbfebd66	226	case SPEEDSTEP_CPU_PCORE:
4e74663c	227	return pentium_core_get_frequency();
bbfebd66	228	case SPEEDSTEP_CPU_PM:
1da177e4	229	return pentiumM_get_frequency();
bbfebd66 DJ	230	case SPEEDSTEP_CPU_P4D:
bbfebd66 DJ	231	case SPEEDSTEP_CPU_P4M:
1da177e4	232	return pentium4_get_frequency();
bbfebd66 DJ	233	case SPEEDSTEP_CPU_PIII_T:
	234	case SPEEDSTEP_CPU_PIII_C:
	235	case SPEEDSTEP_CPU_PIII_C_EARLY:
1da177e4 LT	236	return pentium3_get_frequency(processor);
	237	default:
	238	return 0;
	239	};
	240	return 0;
	241	}
bbfebd66	242	EXPORT_SYMBOL_GPL(speedstep_get_frequency);
1da177e4 LT	243
	244
	245	/*********************************************************************
	246	* DETECT SPEEDSTEP-CAPABLE PROCESSOR *
	247	*********************************************************************/
	248
bbfebd66	249	unsigned int speedstep_detect_processor(void)
1da177e4	250	{
92cb7612	251	struct cpuinfo_x86 *c = &cpu_data(0);
32ee8c3e	252	u32 ebx, msr_lo, msr_hi;
1da177e4 LT	253
	254	dprintk("x86: %x, model: %x\n", c->x86, c->x86_model);
	255
32ee8c3e	256	if ((c->x86_vendor != X86_VENDOR_INTEL) \|\|
1da177e4 LT	257	((c->x86 != 6) && (c->x86 != 0xF)))
	258	return 0;
	259
	260	if (c->x86 == 0xF) {
	261	/* Intel Mobile Pentium 4-M
	262	* or Intel Mobile Pentium 4 with 533 MHz FSB */
	263	if (c->x86_model != 2)
	264	return 0;
	265
	266	ebx = cpuid_ebx(0x00000001);
	267	ebx &= 0x000000FF;
	268
	269	dprintk("ebx value is %x, x86_mask is %x\n", ebx, c->x86_mask);
	270
	271	switch (c->x86_mask) {
32ee8c3e	272	case 4:
1da177e4	273	/*
32ee8c3e	274	* B-stepping [M-P4-M]
1da177e4 LT	275	* sample has ebx = 0x0f, production has 0x0e.
	276	*/
	277	if ((ebx == 0x0e) \|\| (ebx == 0x0f))
bbfebd66	278	return SPEEDSTEP_CPU_P4M;
1da177e4	279	break;
32ee8c3e	280	case 7:
1da177e4 LT	281	/*
	282	* C-stepping [M-P4-M]
	283	* needs to have ebx=0x0e, else it's a celeron:
	284	* cf. 25130917.pdf / page 7, footnote 5 even
	285	* though 25072120.pdf / page 7 doesn't say
	286	* samples are only of B-stepping...
	287	*/
	288	if (ebx == 0x0e)
bbfebd66	289	return SPEEDSTEP_CPU_P4M;
1da177e4 LT	290	break;
	291	case 9:
	292	/*
	293	* D-stepping [M-P4-M or M-P4/533]
	294	*
	295	* this is totally strange: CPUID 0x0F29 is
	296	* used by M-P4-M, M-P4/533 and(!) Celeron CPUs.
	297	* The latter need to be sorted out as they don't
	298	* support speedstep.
	299	* Celerons with CPUID 0x0F29 may have either
	300	* ebx=0x8 or 0xf -- 25130917.pdf doesn't say anything
	301	* specific.
	302	* M-P4-Ms may have either ebx=0xe or 0xf [see above]
	303	* M-P4/533 have either ebx=0xe or 0xf. [25317607.pdf]
	304	* also, M-P4M HTs have ebx=0x8, too
bbfebd66 DJ	305	* For now, they are distinguished by the model_id
bbfebd66 DJ	306	* string
1da177e4	307	*/
bbfebd66 DJ	308	if ((ebx == 0x0e) \|\|
	309	(strstr(c->x86_model_id,
	310	"Mobile Intel(R) Pentium(R) 4") != NULL))
	311	return SPEEDSTEP_CPU_P4M;
1da177e4 LT	312	break;
	313	default:
	314	break;
	315	}
	316	return 0;
	317	}
	318
	319	switch (c->x86_model) {
	320	case 0x0B: /* Intel PIII [Tualatin] */
bbfebd66 DJ	321	/* cpuid_ebx(1) is 0x04 for desktop PIII,
bbfebd66 DJ	322	* 0x06 for mobile PIII-M */
1da177e4 LT	323	ebx = cpuid_ebx(0x00000001);
	324	dprintk("ebx is %x\n", ebx);
	325
	326	ebx &= 0x000000FF;
	327
	328	if (ebx != 0x06)
	329	return 0;
	330
	331	/* So far all PIII-M processors support SpeedStep. See
32ee8c3e	332	* Intel's 24540640.pdf of June 2003
1da177e4	333	*/
bbfebd66	334	return SPEEDSTEP_CPU_PIII_T;
1da177e4 LT	335
	336	case 0x08: /* Intel PIII [Coppermine] */
	337
	338	/* all mobile PIII Coppermines have FSB 100 MHz
	339	* ==> sort out a few desktop PIIIs. */
	340	rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_hi);
bbfebd66 DJ	341	dprintk("Coppermine: MSR_IA32_EBL_CR_POWERON is 0x%x, 0x%x\n",
bbfebd66 DJ	342	msr_lo, msr_hi);
1da177e4 LT	343	msr_lo &= 0x00c0000;
	344	if (msr_lo != 0x0080000)
	345	return 0;
	346
	347	/*
	348	* If the processor is a mobile version,
	349	* platform ID has bit 50 set
	350	* it has SpeedStep technology if either
	351	* bit 56 or 57 is set
	352	*/
	353	rdmsr(MSR_IA32_PLATFORM_ID, msr_lo, msr_hi);
bbfebd66 DJ	354	dprintk("Coppermine: MSR_IA32_PLATFORM ID is 0x%x, 0x%x\n",
	355	msr_lo, msr_hi);
	356	if ((msr_hi & (1<<18)) &&
	357	(relaxed_check ? 1 : (msr_hi & (3<<24)))) {
1da177e4 LT	358	if (c->x86_mask == 0x01) {
1da177e4 LT	359	dprintk("early PIII version\n");
bbfebd66	360	return SPEEDSTEP_CPU_PIII_C_EARLY;
1da177e4	361	} else
bbfebd66	362	return SPEEDSTEP_CPU_PIII_C;
1da177e4 LT	363	}
	364
	365	default:
	366	return 0;
	367	}
	368	}
	369	EXPORT_SYMBOL_GPL(speedstep_detect_processor);
	370
	371
	372	/*********************************************************************
	373	* DETECT SPEEDSTEP SPEEDS *
	374	*********************************************************************/
	375
	376	unsigned int speedstep_get_freqs(unsigned int processor,
	377	unsigned int *low_speed,
	378	unsigned int *high_speed,
1a10760c	379	unsigned int *transition_latency,
1da177e4 LT	380	void (*set_state) (unsigned int state))
	381	{
	382	unsigned int prev_speed;
	383	unsigned int ret = 0;
	384	unsigned long flags;
1a10760c	385	struct timeval tv1, tv2;
1da177e4 LT	386
	387	if ((!processor) \|\| (!low_speed) \|\| (!high_speed) \|\| (!set_state))
	388	return -EINVAL;
	389
	390	dprintk("trying to determine both speeds\n");
	391
	392	/* get current speed */
bbfebd66	393	prev_speed = speedstep_get_frequency(processor);
1da177e4 LT	394	if (!prev_speed)
	395	return -EIO;
	396
f94ea640	397	dprintk("previous speed is %u\n", prev_speed);
1a10760c	398
1da177e4 LT	399	local_irq_save(flags);
	400
	401	/* switch to low state */
	402	set_state(SPEEDSTEP_LOW);
bbfebd66	403	*low_speed = speedstep_get_frequency(processor);
1da177e4 LT	404	if (!*low_speed) {
	405	ret = -EIO;
	406	goto out;
	407	}
	408
f94ea640	409	dprintk("low speed is %u\n", *low_speed);
1da177e4	410
1a10760c MD	411	/* start latency measurement */
	412	if (transition_latency)
	413	do_gettimeofday(&tv1);
	414
1da177e4 LT	415	/* switch to high state */
1da177e4 LT	416	set_state(SPEEDSTEP_HIGH);
1a10760c MD	417
	418	/* end latency measurement */
	419	if (transition_latency)
	420	do_gettimeofday(&tv2);
	421
bbfebd66	422	*high_speed = speedstep_get_frequency(processor);
1da177e4 LT	423	if (!*high_speed) {
	424	ret = -EIO;
	425	goto out;
	426	}
	427
f94ea640	428	dprintk("high speed is %u\n", *high_speed);
1da177e4 LT	429
	430	if (low_speed == high_speed) {
	431	ret = -ENODEV;
	432	goto out;
	433	}
	434
	435	/* switch to previous state, if necessary */
	436	if (*high_speed != prev_speed)
	437	set_state(SPEEDSTEP_LOW);
	438
1a10760c MD	439	if (transition_latency) {
	440	transition_latency = (tv2.tv_sec - tv1.tv_sec) USEC_PER_SEC +
	441	tv2.tv_usec - tv1.tv_usec;
	442	dprintk("transition latency is %u uSec\n", *transition_latency);
	443
	444	/* convert uSec to nSec and add 20% for safety reasons */
	445	transition_latency = 1200;
	446
	447	/* check if the latency measurement is too high or too low
	448	* and set it to a safe value (500uSec) in that case
	449	*/
bbfebd66 DJ	450	if (*transition_latency > 10000000 \|\|
	451	*transition_latency < 50000) {
	452	printk(KERN_WARNING PFX "frequency transition "
	453	"measured seems out of range (%u "
	454	"nSec), falling back to a safe one of"
	455	"%u nSec.\n",
1a10760c MD	456	*transition_latency, 500000);
	457	*transition_latency = 500000;
	458	}
	459	}
	460
32ee8c3e	461	out:
1da177e4	462	local_irq_restore(flags);
bbfebd66	463	return ret;
1da177e4 LT	464	}
	465	EXPORT_SYMBOL_GPL(speedstep_get_freqs);
	466
	467	#ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
	468	module_param(relaxed_check, int, 0444);
bbfebd66 DJ	469	MODULE_PARM_DESC(relaxed_check,
bbfebd66 DJ	470	"Don't do all checks for speedstep capability.");
1da177e4 LT	471	#endif
1da177e4 LT	472
bbfebd66 DJ	473	MODULE_AUTHOR("Dominik Brodowski <linux@brodo.de>");
	474	MODULE_DESCRIPTION("Library for Intel SpeedStep 1 or 2 cpufreq drivers.");
	475	MODULE_LICENSE("GPL");