[deliverable/linux.git] / arch / x86 / kernel / cpu / cpufreq / speedstep-lib.c

/*
 * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
 *
 *  Licensed under the terms of the GNU GPL License version 2.
 *
 *  Library for common functions for Intel SpeedStep v.1 and v.2 support
 *
 *  BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/cpufreq.h>
#include <linux/slab.h>

#include <asm/msr.h>
#include "speedstep-lib.h"

#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "speedstep-lib", msg)

#ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
static int relaxed_check = 0;
#else
#define relaxed_check 0
#endif

/*********************************************************************
 *                   GET PROCESSOR CORE SPEED IN KHZ                 *
 *********************************************************************/

static unsigned int pentium3_get_frequency (unsigned int processor)
{
        /* See table 14 of p3_ds.pdf and table 22 of 29834003.pdf */
	struct {
		unsigned int ratio;	/* Frequency Multiplier (x10) */
		u8 bitmap;		/* power on configuration bits
					[27, 25:22] (in MSR 0x2a) */
	} msr_decode_mult [] = {
		{ 30, 0x01 },
		{ 35, 0x05 },
		{ 40, 0x02 },
		{ 45, 0x06 },
		{ 50, 0x00 },
		{ 55, 0x04 },
		{ 60, 0x0b },
		{ 65, 0x0f },
		{ 70, 0x09 },
		{ 75, 0x0d },
		{ 80, 0x0a },
		{ 85, 0x26 },
		{ 90, 0x20 },
		{ 100, 0x2b },
		{ 0, 0xff }     /* error or unknown value */
	};

	/* PIII(-M) FSB settings: see table b1-b of 24547206.pdf */
	struct {
		unsigned int value;	/* Front Side Bus speed in MHz */
		u8 bitmap;		/* power on configuration bits [18: 19]
					(in MSR 0x2a) */
	} msr_decode_fsb [] = {
		{  66, 0x0 },
		{ 100, 0x2 },
		{ 133, 0x1 },
		{   0, 0xff}
	};

	u32 msr_lo, msr_tmp;
	int i = 0, j = 0;

	/* read MSR 0x2a - we only need the low 32 bits */
	rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
	dprintk("P3 - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
	msr_tmp = msr_lo;

	/* decode the FSB */
	msr_tmp &= 0x00c0000;
	msr_tmp >>= 18;
	while (msr_tmp != msr_decode_fsb[i].bitmap) {
		if (msr_decode_fsb[i].bitmap == 0xff)
			return 0;
		i++;
	}

	/* decode the multiplier */
	if (processor == SPEEDSTEP_PROCESSOR_PIII_C_EARLY) {
		dprintk("workaround for early PIIIs\n");
		msr_lo &= 0x03c00000;
	} else
		msr_lo &= 0x0bc00000;
	msr_lo >>= 22;
	while (msr_lo != msr_decode_mult[j].bitmap) {
		if (msr_decode_mult[j].bitmap == 0xff)
			return 0;
		j++;
	}

	dprintk("speed is %u\n", (msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100));

	return (msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100);
}


static unsigned int pentiumM_get_frequency(void)
{
	u32 msr_lo, msr_tmp;

	rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
	dprintk("PM - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);

	/* see table B-2 of 24547212.pdf */
	if (msr_lo & 0x00040000) {
		printk(KERN_DEBUG "speedstep-lib: PM - invalid FSB: 0x%x 0x%x\n", msr_lo, msr_tmp);
		return 0;
	}

	msr_tmp = (msr_lo >> 22) & 0x1f;
	dprintk("bits 22-26 are 0x%x, speed is %u\n", msr_tmp, (msr_tmp * 100 * 1000));

	return (msr_tmp * 100 * 1000);
}

static unsigned int pentium_core_get_frequency(void)
{
	u32 fsb = 0;
	u32 msr_lo, msr_tmp;

	rdmsr(MSR_FSB_FREQ, msr_lo, msr_tmp);
	/* see table B-2 of 25366920.pdf */
	switch (msr_lo & 0x07) {
	case 5:
		fsb = 100000;
		break;
	case 1:
		fsb = 133333;
		break;
	case 3:
		fsb = 166667;
		break;
	default:
		printk(KERN_ERR "PCORE - MSR_FSB_FREQ undefined value");
	}

	rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
	dprintk("PCORE - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);

	msr_tmp = (msr_lo >> 22) & 0x1f;
	dprintk("bits 22-26 are 0x%x, speed is %u\n", msr_tmp, (msr_tmp * fsb));

	return (msr_tmp * fsb);
}


static unsigned int pentium4_get_frequency(void)
{
	struct cpuinfo_x86 *c = &boot_cpu_data;
	u32 msr_lo, msr_hi, mult;
	unsigned int fsb = 0;

	rdmsr(0x2c, msr_lo, msr_hi);

	dprintk("P4 - MSR_EBC_FREQUENCY_ID: 0x%x 0x%x\n", msr_lo, msr_hi);

	/* decode the FSB: see IA-32 Intel (C) Architecture Software
	 * Developer's Manual, Volume 3: System Prgramming Guide,
	 * revision #12 in Table B-1: MSRs in the Pentium 4 and
	 * Intel Xeon Processors, on page B-4 and B-5.
	 */
	if (c->x86_model < 2)
		fsb = 100 * 1000;
	else {
		u8 fsb_code = (msr_lo >> 16) & 0x7;
		switch (fsb_code) {
		case 0:
			fsb = 100 * 1000;
			break;
		case 1:
			fsb = 13333 * 10;
			break;
		case 2:
			fsb = 200 * 1000;
			break;
		}
	}

	if (!fsb)
		printk(KERN_DEBUG "speedstep-lib: couldn't detect FSB speed. Please send an e-mail to <linux@brodo.de>\n");

	/* Multiplier. */
	mult = msr_lo >> 24;

	dprintk("P4 - FSB %u kHz; Multiplier %u; Speed %u kHz\n", fsb, mult, (fsb * mult));

	return (fsb * mult);
}


unsigned int speedstep_get_processor_frequency(unsigned int processor)
{
	switch (processor) {
	case SPEEDSTEP_PROCESSOR_PCORE:
		return pentium_core_get_frequency();
	case SPEEDSTEP_PROCESSOR_PM:
		return pentiumM_get_frequency();
	case SPEEDSTEP_PROCESSOR_P4D:
	case SPEEDSTEP_PROCESSOR_P4M:
		return pentium4_get_frequency();
	case SPEEDSTEP_PROCESSOR_PIII_T:
	case SPEEDSTEP_PROCESSOR_PIII_C:
	case SPEEDSTEP_PROCESSOR_PIII_C_EARLY:
		return pentium3_get_frequency(processor);
	default:
		return 0;
	};
	return 0;
}
EXPORT_SYMBOL_GPL(speedstep_get_processor_frequency);


/*********************************************************************
 *                 DETECT SPEEDSTEP-CAPABLE PROCESSOR                *
 *********************************************************************/

unsigned int speedstep_detect_processor (void)
{
	struct cpuinfo_x86 *c = &cpu_data(0);
	u32 ebx, msr_lo, msr_hi;

	dprintk("x86: %x, model: %x\n", c->x86, c->x86_model);

	if ((c->x86_vendor != X86_VENDOR_INTEL) ||
	    ((c->x86 != 6) && (c->x86 != 0xF)))
		return 0;

	if (c->x86 == 0xF) {
		/* Intel Mobile Pentium 4-M
		 * or Intel Mobile Pentium 4 with 533 MHz FSB */
		if (c->x86_model != 2)
			return 0;

		ebx = cpuid_ebx(0x00000001);
		ebx &= 0x000000FF;

		dprintk("ebx value is %x, x86_mask is %x\n", ebx, c->x86_mask);

		switch (c->x86_mask) {
		case 4:
			/*
			 * B-stepping [M-P4-M]
			 * sample has ebx = 0x0f, production has 0x0e.
			 */
			if ((ebx == 0x0e) || (ebx == 0x0f))
				return SPEEDSTEP_PROCESSOR_P4M;
			break;
		case 7:
			/*
			 * C-stepping [M-P4-M]
			 * needs to have ebx=0x0e, else it's a celeron:
			 * cf. 25130917.pdf / page 7, footnote 5 even
			 * though 25072120.pdf / page 7 doesn't say
			 * samples are only of B-stepping...
			 */
			if (ebx == 0x0e)
				return SPEEDSTEP_PROCESSOR_P4M;
			break;
		case 9:
			/*
			 * D-stepping [M-P4-M or M-P4/533]
			 *
			 * this is totally strange: CPUID 0x0F29 is
			 * used by M-P4-M, M-P4/533 and(!) Celeron CPUs.
			 * The latter need to be sorted out as they don't
			 * support speedstep.
			 * Celerons with CPUID 0x0F29 may have either
			 * ebx=0x8 or 0xf -- 25130917.pdf doesn't say anything
			 * specific.
			 * M-P4-Ms may have either ebx=0xe or 0xf [see above]
			 * M-P4/533 have either ebx=0xe or 0xf. [25317607.pdf]
			 * also, M-P4M HTs have ebx=0x8, too
			 * For now, they are distinguished by the model_id string
			 */
			if ((ebx == 0x0e) || (strstr(c->x86_model_id,"Mobile Intel(R) Pentium(R) 4") != NULL))
				return SPEEDSTEP_PROCESSOR_P4M;
			break;
		default:
			break;
		}
		return 0;
	}

	switch (c->x86_model) {
	case 0x0B: /* Intel PIII [Tualatin] */
		/* cpuid_ebx(1) is 0x04 for desktop PIII, 0x06 for mobile PIII-M */
		ebx = cpuid_ebx(0x00000001);
		dprintk("ebx is %x\n", ebx);

		ebx &= 0x000000FF;

		if (ebx != 0x06)
			return 0;

		/* So far all PIII-M processors support SpeedStep. See
		 * Intel's 24540640.pdf of June 2003
		 */
		return SPEEDSTEP_PROCESSOR_PIII_T;

	case 0x08: /* Intel PIII [Coppermine] */

		/* all mobile PIII Coppermines have FSB 100 MHz
		 * ==> sort out a few desktop PIIIs. */
		rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_hi);
		dprintk("Coppermine: MSR_IA32_EBL_CR_POWERON is 0x%x, 0x%x\n", msr_lo, msr_hi);
		msr_lo &= 0x00c0000;
		if (msr_lo != 0x0080000)
			return 0;

		/*
		 * If the processor is a mobile version,
		 * platform ID has bit 50 set
		 * it has SpeedStep technology if either
		 * bit 56 or 57 is set
		 */
		rdmsr(MSR_IA32_PLATFORM_ID, msr_lo, msr_hi);
		dprintk("Coppermine: MSR_IA32_PLATFORM ID is 0x%x, 0x%x\n", msr_lo, msr_hi);
		if ((msr_hi & (1<<18)) && (relaxed_check ? 1 : (msr_hi & (3<<24)))) {
			if (c->x86_mask == 0x01) {
				dprintk("early PIII version\n");
				return SPEEDSTEP_PROCESSOR_PIII_C_EARLY;
			} else
				return SPEEDSTEP_PROCESSOR_PIII_C;
		}

	default:
		return 0;
	}
}
EXPORT_SYMBOL_GPL(speedstep_detect_processor);


/*********************************************************************
 *                     DETECT SPEEDSTEP SPEEDS                       *
 *********************************************************************/

unsigned int speedstep_get_freqs(unsigned int processor,
				  unsigned int *low_speed,
				  unsigned int *high_speed,
				  unsigned int *transition_latency,
				  void (*set_state) (unsigned int state))
{
	unsigned int prev_speed;
	unsigned int ret = 0;
	unsigned long flags;
	struct timeval tv1, tv2;

	if ((!processor) || (!low_speed) || (!high_speed) || (!set_state))
		return -EINVAL;

	dprintk("trying to determine both speeds\n");

	/* get current speed */
	prev_speed = speedstep_get_processor_frequency(processor);
	if (!prev_speed)
		return -EIO;

	dprintk("previous speed is %u\n", prev_speed);

	local_irq_save(flags);

	/* switch to low state */
	set_state(SPEEDSTEP_LOW);
	*low_speed = speedstep_get_processor_frequency(processor);
	if (!*low_speed) {
		ret = -EIO;
		goto out;
	}

	dprintk("low speed is %u\n", *low_speed);

	/* start latency measurement */
	if (transition_latency)
		do_gettimeofday(&tv1);

	/* switch to high state */
	set_state(SPEEDSTEP_HIGH);

	/* end latency measurement */
	if (transition_latency)
		do_gettimeofday(&tv2);

	*high_speed = speedstep_get_processor_frequency(processor);
	if (!*high_speed) {
		ret = -EIO;
		goto out;
	}

	dprintk("high speed is %u\n", *high_speed);

	if (*low_speed == *high_speed) {
		ret = -ENODEV;
		goto out;
	}

	/* switch to previous state, if necessary */
	if (*high_speed != prev_speed)
		set_state(SPEEDSTEP_LOW);

	if (transition_latency) {
		*transition_latency = (tv2.tv_sec - tv1.tv_sec) * USEC_PER_SEC +
			tv2.tv_usec - tv1.tv_usec;
		dprintk("transition latency is %u uSec\n", *transition_latency);

		/* convert uSec to nSec and add 20% for safety reasons */
		*transition_latency *= 1200;

		/* check if the latency measurement is too high or too low
		 * and set it to a safe value (500uSec) in that case
		 */
		if (*transition_latency > 10000000 || *transition_latency < 50000) {
			printk (KERN_WARNING "speedstep: frequency transition measured seems out of "
					"range (%u nSec), falling back to a safe one of %u nSec.\n",
					*transition_latency, 500000);
			*transition_latency = 500000;
		}
	}

out:
	local_irq_restore(flags);
	return (ret);
}
EXPORT_SYMBOL_GPL(speedstep_get_freqs);

#ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
module_param(relaxed_check, int, 0444);
MODULE_PARM_DESC(relaxed_check, "Don't do all checks for speedstep capability.");
#endif

MODULE_AUTHOR ("Dominik Brodowski <linux@brodo.de>");
MODULE_DESCRIPTION ("Library for Intel SpeedStep 1 or 2 cpufreq drivers.");
MODULE_LICENSE ("GPL");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
	3	*
	4	* Licensed under the terms of the GNU GPL License version 2.
	5	*
	6	* Library for common functions for Intel SpeedStep v.1 and v.2 support
	7	*
	8	* BIG FAT DISCLAIMER: Work in progress code. Possibly dangerous
	9	*/
	10
	11	#include <linux/kernel.h>
32ee8c3e	12	#include <linux/module.h>
1da177e4 LT	13	#include <linux/moduleparam.h>
	14	#include <linux/init.h>
	15	#include <linux/cpufreq.h>
1da177e4 LT	16	#include <linux/slab.h>
	17
	18	#include <asm/msr.h>
	19	#include "speedstep-lib.h"
	20
	21	#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "speedstep-lib", msg)
	22
	23	#ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
	24	static int relaxed_check = 0;
	25	#else
	26	#define relaxed_check 0
	27	#endif
	28
	29	/*********************************************************************
	30	* GET PROCESSOR CORE SPEED IN KHZ *
	31	*********************************************************************/
	32
	33	static unsigned int pentium3_get_frequency (unsigned int processor)
	34	{
	35	/* See table 14 of p3_ds.pdf and table 22 of 29834003.pdf */
	36	struct {
	37	unsigned int ratio; /* Frequency Multiplier (x10) */
32ee8c3e DJ	38	u8 bitmap; /* power on configuration bits
32ee8c3e DJ	39	[27, 25:22] (in MSR 0x2a) */
1da177e4 LT	40	} msr_decode_mult [] = {
	41	{ 30, 0x01 },
	42	{ 35, 0x05 },
	43	{ 40, 0x02 },
	44	{ 45, 0x06 },
	45	{ 50, 0x00 },
	46	{ 55, 0x04 },
	47	{ 60, 0x0b },
	48	{ 65, 0x0f },
	49	{ 70, 0x09 },
	50	{ 75, 0x0d },
	51	{ 80, 0x0a },
	52	{ 85, 0x26 },
	53	{ 90, 0x20 },
	54	{ 100, 0x2b },
	55	{ 0, 0xff } /* error or unknown value */
	56	};
	57
	58	/* PIII(-M) FSB settings: see table b1-b of 24547206.pdf */
	59	struct {
32ee8c3e DJ	60	unsigned int value; /* Front Side Bus speed in MHz */
	61	u8 bitmap; /* power on configuration bits [18: 19]
	62	(in MSR 0x2a) */
1da177e4 LT	63	} msr_decode_fsb [] = {
	64	{ 66, 0x0 },
	65	{ 100, 0x2 },
	66	{ 133, 0x1 },
	67	{ 0, 0xff}
	68	};
	69
32ee8c3e DJ	70	u32 msr_lo, msr_tmp;
32ee8c3e DJ	71	int i = 0, j = 0;
1da177e4 LT	72
	73	/* read MSR 0x2a - we only need the low 32 bits */
	74	rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
	75	dprintk("P3 - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
	76	msr_tmp = msr_lo;
	77
	78	/* decode the FSB */
	79	msr_tmp &= 0x00c0000;
	80	msr_tmp >>= 18;
	81	while (msr_tmp != msr_decode_fsb[i].bitmap) {
	82	if (msr_decode_fsb[i].bitmap == 0xff)
	83	return 0;
	84	i++;
	85	}
	86
	87	/* decode the multiplier */
	88	if (processor == SPEEDSTEP_PROCESSOR_PIII_C_EARLY) {
	89	dprintk("workaround for early PIIIs\n");
	90	msr_lo &= 0x03c00000;
	91	} else
	92	msr_lo &= 0x0bc00000;
	93	msr_lo >>= 22;
	94	while (msr_lo != msr_decode_mult[j].bitmap) {
	95	if (msr_decode_mult[j].bitmap == 0xff)
	96	return 0;
	97	j++;
	98	}
	99
	100	dprintk("speed is %u\n", (msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100));
	101
	102	return (msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100);
	103	}
	104
	105
	106	static unsigned int pentiumM_get_frequency(void)
	107	{
32ee8c3e	108	u32 msr_lo, msr_tmp;
1da177e4 LT	109
	110	rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
	111	dprintk("PM - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
	112
	113	/* see table B-2 of 24547212.pdf */
	114	if (msr_lo & 0x00040000) {
	115	printk(KERN_DEBUG "speedstep-lib: PM - invalid FSB: 0x%x 0x%x\n", msr_lo, msr_tmp);
	116	return 0;
	117	}
	118
	119	msr_tmp = (msr_lo >> 22) & 0x1f;
	120	dprintk("bits 22-26 are 0x%x, speed is %u\n", msr_tmp, (msr_tmp * 100 * 1000));
	121
	122	return (msr_tmp * 100 * 1000);
	123	}
	124
4e74663c DB	125	static unsigned int pentium_core_get_frequency(void)
	126	{
	127	u32 fsb = 0;
	128	u32 msr_lo, msr_tmp;
	129
	130	rdmsr(MSR_FSB_FREQ, msr_lo, msr_tmp);
e11952b9	131	/* see table B-2 of 25366920.pdf */
4e74663c DB	132	switch (msr_lo & 0x07) {
4e74663c DB	133	case 5:
e11952b9	134	fsb = 100000;
4e74663c DB	135	break;
4e74663c DB	136	case 1:
e11952b9	137	fsb = 133333;
4e74663c DB	138	break;
4e74663c DB	139	case 3:
e11952b9	140	fsb = 166667;
4e74663c DB	141	break;
	142	default:
	143	printk(KERN_ERR "PCORE - MSR_FSB_FREQ undefined value");
	144	}
	145
	146	rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
	147	dprintk("PCORE - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
	148
	149	msr_tmp = (msr_lo >> 22) & 0x1f;
e11952b9	150	dprintk("bits 22-26 are 0x%x, speed is %u\n", msr_tmp, (msr_tmp * fsb));
4e74663c	151
e11952b9	152	return (msr_tmp * fsb);
4e74663c	153	}
e11952b9	154
1da177e4 LT	155
	156	static unsigned int pentium4_get_frequency(void)
	157	{
	158	struct cpuinfo_x86 *c = &boot_cpu_data;
	159	u32 msr_lo, msr_hi, mult;
	160	unsigned int fsb = 0;
	161
	162	rdmsr(0x2c, msr_lo, msr_hi);
	163
	164	dprintk("P4 - MSR_EBC_FREQUENCY_ID: 0x%x 0x%x\n", msr_lo, msr_hi);
	165
32ee8c3e	166	/* decode the FSB: see IA-32 Intel (C) Architecture Software
1da177e4 LT	167	* Developer's Manual, Volume 3: System Prgramming Guide,
	168	* revision #12 in Table B-1: MSRs in the Pentium 4 and
	169	* Intel Xeon Processors, on page B-4 and B-5.
	170	*/
	171	if (c->x86_model < 2)
	172	fsb = 100 * 1000;
	173	else {
	174	u8 fsb_code = (msr_lo >> 16) & 0x7;
	175	switch (fsb_code) {
	176	case 0:
	177	fsb = 100 * 1000;
	178	break;
	179	case 1:
	180	fsb = 13333 * 10;
	181	break;
	182	case 2:
	183	fsb = 200 * 1000;
	184	break;
	185	}
	186	}
	187
	188	if (!fsb)
	189	printk(KERN_DEBUG "speedstep-lib: couldn't detect FSB speed. Please send an e-mail to <linux@brodo.de>\n");
	190
	191	/* Multiplier. */
ed9cbcd4	192	mult = msr_lo >> 24;
1da177e4 LT	193
	194	dprintk("P4 - FSB %u kHz; Multiplier %u; Speed %u kHz\n", fsb, mult, (fsb * mult));
	195
	196	return (fsb * mult);
	197	}
	198
32ee8c3e	199
1da177e4 LT	200	unsigned int speedstep_get_processor_frequency(unsigned int processor)
	201	{
	202	switch (processor) {
4e74663c DB	203	case SPEEDSTEP_PROCESSOR_PCORE:
4e74663c DB	204	return pentium_core_get_frequency();
1da177e4 LT	205	case SPEEDSTEP_PROCESSOR_PM:
	206	return pentiumM_get_frequency();
	207	case SPEEDSTEP_PROCESSOR_P4D:
	208	case SPEEDSTEP_PROCESSOR_P4M:
	209	return pentium4_get_frequency();
	210	case SPEEDSTEP_PROCESSOR_PIII_T:
	211	case SPEEDSTEP_PROCESSOR_PIII_C:
	212	case SPEEDSTEP_PROCESSOR_PIII_C_EARLY:
	213	return pentium3_get_frequency(processor);
	214	default:
	215	return 0;
	216	};
	217	return 0;
	218	}
	219	EXPORT_SYMBOL_GPL(speedstep_get_processor_frequency);
	220
	221
	222	/*********************************************************************
	223	* DETECT SPEEDSTEP-CAPABLE PROCESSOR *
	224	*********************************************************************/
	225
	226	unsigned int speedstep_detect_processor (void)
	227	{
92cb7612	228	struct cpuinfo_x86 *c = &cpu_data(0);
32ee8c3e	229	u32 ebx, msr_lo, msr_hi;
1da177e4 LT	230
	231	dprintk("x86: %x, model: %x\n", c->x86, c->x86_model);
	232
32ee8c3e	233	if ((c->x86_vendor != X86_VENDOR_INTEL) \|\|
1da177e4 LT	234	((c->x86 != 6) && (c->x86 != 0xF)))
	235	return 0;
	236
	237	if (c->x86 == 0xF) {
	238	/* Intel Mobile Pentium 4-M
	239	* or Intel Mobile Pentium 4 with 533 MHz FSB */
	240	if (c->x86_model != 2)
	241	return 0;
	242
	243	ebx = cpuid_ebx(0x00000001);
	244	ebx &= 0x000000FF;
	245
	246	dprintk("ebx value is %x, x86_mask is %x\n", ebx, c->x86_mask);
	247
	248	switch (c->x86_mask) {
32ee8c3e	249	case 4:
1da177e4	250	/*
32ee8c3e	251	* B-stepping [M-P4-M]
1da177e4 LT	252	* sample has ebx = 0x0f, production has 0x0e.
	253	*/
	254	if ((ebx == 0x0e) \|\| (ebx == 0x0f))
	255	return SPEEDSTEP_PROCESSOR_P4M;
	256	break;
32ee8c3e	257	case 7:
1da177e4 LT	258	/*
	259	* C-stepping [M-P4-M]
	260	* needs to have ebx=0x0e, else it's a celeron:
	261	* cf. 25130917.pdf / page 7, footnote 5 even
	262	* though 25072120.pdf / page 7 doesn't say
	263	* samples are only of B-stepping...
	264	*/
	265	if (ebx == 0x0e)
	266	return SPEEDSTEP_PROCESSOR_P4M;
	267	break;
	268	case 9:
	269	/*
	270	* D-stepping [M-P4-M or M-P4/533]
	271	*
	272	* this is totally strange: CPUID 0x0F29 is
	273	* used by M-P4-M, M-P4/533 and(!) Celeron CPUs.
	274	* The latter need to be sorted out as they don't
	275	* support speedstep.
	276	* Celerons with CPUID 0x0F29 may have either
	277	* ebx=0x8 or 0xf -- 25130917.pdf doesn't say anything
	278	* specific.
	279	* M-P4-Ms may have either ebx=0xe or 0xf [see above]
	280	* M-P4/533 have either ebx=0xe or 0xf. [25317607.pdf]
	281	* also, M-P4M HTs have ebx=0x8, too
	282	* For now, they are distinguished by the model_id string
	283	*/
32ee8c3e	284	if ((ebx == 0x0e) \|\| (strstr(c->x86_model_id,"Mobile Intel(R) Pentium(R) 4") != NULL))
1da177e4 LT	285	return SPEEDSTEP_PROCESSOR_P4M;
	286	break;
	287	default:
	288	break;
	289	}
	290	return 0;
	291	}
	292
	293	switch (c->x86_model) {
	294	case 0x0B: /* Intel PIII [Tualatin] */
32ee8c3e	295	/* cpuid_ebx(1) is 0x04 for desktop PIII, 0x06 for mobile PIII-M */
1da177e4 LT	296	ebx = cpuid_ebx(0x00000001);
	297	dprintk("ebx is %x\n", ebx);
	298
	299	ebx &= 0x000000FF;
	300
	301	if (ebx != 0x06)
	302	return 0;
	303
	304	/* So far all PIII-M processors support SpeedStep. See
32ee8c3e	305	* Intel's 24540640.pdf of June 2003
1da177e4	306	*/
1da177e4 LT	307	return SPEEDSTEP_PROCESSOR_PIII_T;
	308
	309	case 0x08: /* Intel PIII [Coppermine] */
	310
	311	/* all mobile PIII Coppermines have FSB 100 MHz
	312	* ==> sort out a few desktop PIIIs. */
	313	rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_hi);
	314	dprintk("Coppermine: MSR_IA32_EBL_CR_POWERON is 0x%x, 0x%x\n", msr_lo, msr_hi);
	315	msr_lo &= 0x00c0000;
	316	if (msr_lo != 0x0080000)
	317	return 0;
	318
	319	/*
	320	* If the processor is a mobile version,
	321	* platform ID has bit 50 set
	322	* it has SpeedStep technology if either
	323	* bit 56 or 57 is set
	324	*/
	325	rdmsr(MSR_IA32_PLATFORM_ID, msr_lo, msr_hi);
	326	dprintk("Coppermine: MSR_IA32_PLATFORM ID is 0x%x, 0x%x\n", msr_lo, msr_hi);
	327	if ((msr_hi & (1<<18)) && (relaxed_check ? 1 : (msr_hi & (3<<24)))) {
	328	if (c->x86_mask == 0x01) {
	329	dprintk("early PIII version\n");
	330	return SPEEDSTEP_PROCESSOR_PIII_C_EARLY;
	331	} else
	332	return SPEEDSTEP_PROCESSOR_PIII_C;
	333	}
	334
	335	default:
	336	return 0;
	337	}
	338	}
	339	EXPORT_SYMBOL_GPL(speedstep_detect_processor);
	340
	341
	342	/*********************************************************************
	343	* DETECT SPEEDSTEP SPEEDS *
	344	*********************************************************************/
	345
	346	unsigned int speedstep_get_freqs(unsigned int processor,
	347	unsigned int *low_speed,
	348	unsigned int *high_speed,
1a10760c	349	unsigned int *transition_latency,
1da177e4 LT	350	void (*set_state) (unsigned int state))
	351	{
	352	unsigned int prev_speed;
	353	unsigned int ret = 0;
	354	unsigned long flags;
1a10760c	355	struct timeval tv1, tv2;
1da177e4 LT	356
	357	if ((!processor) \|\| (!low_speed) \|\| (!high_speed) \|\| (!set_state))
	358	return -EINVAL;
	359
	360	dprintk("trying to determine both speeds\n");
	361
	362	/* get current speed */
	363	prev_speed = speedstep_get_processor_frequency(processor);
	364	if (!prev_speed)
	365	return -EIO;
	366
f94ea640	367	dprintk("previous speed is %u\n", prev_speed);
1a10760c	368
1da177e4 LT	369	local_irq_save(flags);
	370
	371	/* switch to low state */
	372	set_state(SPEEDSTEP_LOW);
	373	*low_speed = speedstep_get_processor_frequency(processor);
	374	if (!*low_speed) {
	375	ret = -EIO;
	376	goto out;
	377	}
	378
f94ea640	379	dprintk("low speed is %u\n", *low_speed);
1da177e4	380
1a10760c MD	381	/* start latency measurement */
	382	if (transition_latency)
	383	do_gettimeofday(&tv1);
	384
1da177e4 LT	385	/* switch to high state */
1da177e4 LT	386	set_state(SPEEDSTEP_HIGH);
1a10760c MD	387
	388	/* end latency measurement */
	389	if (transition_latency)
	390	do_gettimeofday(&tv2);
	391
1da177e4 LT	392	*high_speed = speedstep_get_processor_frequency(processor);
	393	if (!*high_speed) {
	394	ret = -EIO;
	395	goto out;
	396	}
	397
f94ea640	398	dprintk("high speed is %u\n", *high_speed);
1da177e4 LT	399
	400	if (low_speed == high_speed) {
	401	ret = -ENODEV;
	402	goto out;
	403	}
	404
	405	/* switch to previous state, if necessary */
	406	if (*high_speed != prev_speed)
	407	set_state(SPEEDSTEP_LOW);
	408
1a10760c MD	409	if (transition_latency) {
	410	transition_latency = (tv2.tv_sec - tv1.tv_sec) USEC_PER_SEC +
	411	tv2.tv_usec - tv1.tv_usec;
	412	dprintk("transition latency is %u uSec\n", *transition_latency);
	413
	414	/* convert uSec to nSec and add 20% for safety reasons */
	415	transition_latency = 1200;
	416
	417	/* check if the latency measurement is too high or too low
	418	* and set it to a safe value (500uSec) in that case
	419	*/
	420	if (transition_latency > 10000000 \|\| transition_latency < 50000) {
	421	printk (KERN_WARNING "speedstep: frequency transition measured seems out of "
	422	"range (%u nSec), falling back to a safe one of %u nSec.\n",
	423	*transition_latency, 500000);
	424	*transition_latency = 500000;
	425	}
	426	}
	427
32ee8c3e	428	out:
1da177e4 LT	429	local_irq_restore(flags);
	430	return (ret);
	431	}
	432	EXPORT_SYMBOL_GPL(speedstep_get_freqs);
	433
	434	#ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
	435	module_param(relaxed_check, int, 0444);
	436	MODULE_PARM_DESC(relaxed_check, "Don't do all checks for speedstep capability.");
	437	#endif
	438
	439	MODULE_AUTHOR ("Dominik Brodowski <linux@brodo.de>");
	440	MODULE_DESCRIPTION ("Library for Intel SpeedStep 1 or 2 cpufreq drivers.");
	441	MODULE_LICENSE ("GPL");