Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
f4432c5c DJ |
2 | * Athlon specific Machine Check Exception Reporting |
3 | * (C) Copyright 2002 Dave Jones <davej@redhat.com> | |
1da177e4 | 4 | */ |
1da177e4 | 5 | #include <linux/interrupt.h> |
efee4ca8 IM |
6 | #include <linux/kernel.h> |
7 | #include <linux/types.h> | |
8 | #include <linux/init.h> | |
1da177e4 LT |
9 | #include <linux/smp.h> |
10 | ||
5175676a | 11 | #include <asm/processor.h> |
1da177e4 | 12 | #include <asm/system.h> |
9e55e44e | 13 | #include <asm/mce.h> |
1da177e4 LT |
14 | #include <asm/msr.h> |
15 | ||
efee4ca8 | 16 | /* Machine Check Handler For AMD Athlon/Duron: */ |
5175676a | 17 | static void k7_machine_check(struct pt_regs *regs, long error_code) |
1da177e4 | 18 | { |
1da177e4 LT |
19 | u32 alow, ahigh, high, low; |
20 | u32 mcgstl, mcgsth; | |
efee4ca8 | 21 | int recover = 1; |
1da177e4 LT |
22 | int i; |
23 | ||
5175676a | 24 | rdmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth); |
1da177e4 | 25 | if (mcgstl & (1<<0)) /* Recoverable ? */ |
5175676a | 26 | recover = 0; |
1da177e4 | 27 | |
b912a1c7 | 28 | printk(KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x\n", |
1da177e4 LT |
29 | smp_processor_id(), mcgsth, mcgstl); |
30 | ||
b912a1c7 | 31 | for (i = 1; i < nr_mce_banks; i++) { |
72713393 | 32 | rdmsr(MSR_IA32_MC0_STATUS+i*4, low, high); |
efee4ca8 | 33 | if (high & (1<<31)) { |
9e8b6d90 MZ |
34 | char misc[20]; |
35 | char addr[24]; | |
efee4ca8 IM |
36 | |
37 | misc[0] = '\0'; | |
38 | addr[0] = '\0'; | |
39 | ||
1da177e4 LT |
40 | if (high & (1<<29)) |
41 | recover |= 1; | |
42 | if (high & (1<<25)) | |
43 | recover |= 2; | |
1da177e4 | 44 | high &= ~(1<<31); |
efee4ca8 | 45 | |
1da177e4 | 46 | if (high & (1<<27)) { |
b912a1c7 AM |
47 | rdmsr(MSR_IA32_MC0_MISC+i*4, alow, ahigh); |
48 | snprintf(misc, 20, "[%08x%08x]", ahigh, alow); | |
1da177e4 LT |
49 | } |
50 | if (high & (1<<26)) { | |
b912a1c7 AM |
51 | rdmsr(MSR_IA32_MC0_ADDR+i*4, alow, ahigh); |
52 | snprintf(addr, 24, " at %08x%08x", ahigh, alow); | |
1da177e4 | 53 | } |
efee4ca8 | 54 | |
b912a1c7 | 55 | printk(KERN_EMERG "CPU %d: Bank %d: %08x%08x%s%s\n", |
9e8b6d90 | 56 | smp_processor_id(), i, high, low, misc, addr); |
efee4ca8 IM |
57 | |
58 | /* Clear it: */ | |
b912a1c7 | 59 | wrmsr(MSR_IA32_MC0_STATUS+i*4, 0UL, 0UL); |
efee4ca8 | 60 | /* Serialize: */ |
1da177e4 LT |
61 | wmb(); |
62 | add_taint(TAINT_MACHINE_CHECK); | |
63 | } | |
64 | } | |
65 | ||
efee4ca8 | 66 | if (recover & 2) |
5175676a | 67 | panic("CPU context corrupt"); |
efee4ca8 | 68 | if (recover & 1) |
5175676a | 69 | panic("Unable to continue"); |
efee4ca8 | 70 | |
5175676a | 71 | printk(KERN_EMERG "Attempting to continue.\n"); |
efee4ca8 | 72 | |
1da177e4 | 73 | mcgstl &= ~(1<<2); |
5175676a | 74 | wrmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth); |
1da177e4 LT |
75 | } |
76 | ||
77 | ||
efee4ca8 | 78 | /* AMD K7 machine check is Intel like: */ |
31ab269a | 79 | void amd_mcheck_init(struct cpuinfo_x86 *c) |
1da177e4 LT |
80 | { |
81 | u32 l, h; | |
82 | int i; | |
83 | ||
2f3c30e6 JD |
84 | if (!cpu_has(c, X86_FEATURE_MCE)) |
85 | return; | |
86 | ||
c12ceb76 | 87 | machine_check_vector = k7_machine_check; |
efee4ca8 | 88 | /* Make sure the vector pointer is visible before we enable MCEs: */ |
c12ceb76 AK |
89 | wmb(); |
90 | ||
5175676a | 91 | printk(KERN_INFO "Intel machine check architecture supported.\n"); |
efee4ca8 | 92 | |
5175676a | 93 | rdmsr(MSR_IA32_MCG_CAP, l, h); |
1da177e4 | 94 | if (l & (1<<8)) /* Control register present ? */ |
5175676a | 95 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); |
1da177e4 LT |
96 | nr_mce_banks = l & 0xff; |
97 | ||
efee4ca8 IM |
98 | /* |
99 | * Clear status for MC index 0 separately, we don't touch CTL, | |
100 | * as some K7 Athlons cause spurious MCEs when its enabled: | |
101 | */ | |
de90c5ce | 102 | if (boot_cpu_data.x86 == 6) { |
5175676a | 103 | wrmsr(MSR_IA32_MC0_STATUS, 0x0, 0x0); |
de90c5ce AK |
104 | i = 1; |
105 | } else | |
106 | i = 0; | |
efee4ca8 | 107 | |
5175676a PC |
108 | for (; i < nr_mce_banks; i++) { |
109 | wrmsr(MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff); | |
110 | wrmsr(MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0); | |
1da177e4 LT |
111 | } |
112 | ||
5175676a PC |
113 | set_in_cr4(X86_CR4_MCE); |
114 | printk(KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n", | |
1da177e4 LT |
115 | smp_processor_id()); |
116 | } |