Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Machine check handler. | |
e9eee03e | 3 | * |
1da177e4 | 4 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. |
d88203d1 TG |
5 | * Rest from unknown author(s). |
6 | * 2004 Andi Kleen. Rewrote most of it. | |
b79109c3 AK |
7 | * Copyright 2008 Intel Corporation |
8 | * Author: Andi Kleen | |
1da177e4 | 9 | */ |
e9eee03e IM |
10 | #include <linux/thread_info.h> |
11 | #include <linux/capability.h> | |
12 | #include <linux/miscdevice.h> | |
13 | #include <linux/ratelimit.h> | |
14 | #include <linux/kallsyms.h> | |
15 | #include <linux/rcupdate.h> | |
e9eee03e | 16 | #include <linux/kobject.h> |
14a02530 | 17 | #include <linux/uaccess.h> |
e9eee03e IM |
18 | #include <linux/kdebug.h> |
19 | #include <linux/kernel.h> | |
20 | #include <linux/percpu.h> | |
1da177e4 | 21 | #include <linux/string.h> |
1da177e4 | 22 | #include <linux/sysdev.h> |
f3c6ea1b | 23 | #include <linux/syscore_ops.h> |
3c079792 | 24 | #include <linux/delay.h> |
8c566ef5 | 25 | #include <linux/ctype.h> |
e9eee03e | 26 | #include <linux/sched.h> |
0d7482e3 | 27 | #include <linux/sysfs.h> |
e9eee03e | 28 | #include <linux/types.h> |
5a0e3ad6 | 29 | #include <linux/slab.h> |
e9eee03e IM |
30 | #include <linux/init.h> |
31 | #include <linux/kmod.h> | |
32 | #include <linux/poll.h> | |
3c079792 | 33 | #include <linux/nmi.h> |
e9eee03e | 34 | #include <linux/cpu.h> |
14a02530 | 35 | #include <linux/smp.h> |
e9eee03e | 36 | #include <linux/fs.h> |
9b1beaf2 | 37 | #include <linux/mm.h> |
5be9ed25 | 38 | #include <linux/debugfs.h> |
b77e70bf | 39 | #include <linux/irq_work.h> |
69c60c88 | 40 | #include <linux/export.h> |
e9eee03e | 41 | |
d88203d1 | 42 | #include <asm/processor.h> |
e9eee03e IM |
43 | #include <asm/mce.h> |
44 | #include <asm/msr.h> | |
1da177e4 | 45 | |
bd19a5e6 | 46 | #include "mce-internal.h" |
711c2e48 | 47 | |
93b62c3c | 48 | static DEFINE_MUTEX(mce_chrdev_read_mutex); |
2aa2b50d | 49 | |
f56e8a07 | 50 | #define rcu_dereference_check_mce(p) \ |
ec8c27e0 | 51 | rcu_dereference_index_check((p), \ |
f56e8a07 | 52 | rcu_read_lock_sched_held() || \ |
93b62c3c | 53 | lockdep_is_held(&mce_chrdev_read_mutex)) |
f56e8a07 | 54 | |
8968f9d3 HS |
55 | #define CREATE_TRACE_POINTS |
56 | #include <trace/events/mce.h> | |
57 | ||
4e5b3e69 | 58 | int mce_disabled __read_mostly; |
04b2b1a4 | 59 | |
e9eee03e | 60 | #define MISC_MCELOG_MINOR 227 |
0d7482e3 | 61 | |
3c079792 AK |
62 | #define SPINUNIT 100 /* 100ns */ |
63 | ||
553f265f AK |
64 | atomic_t mce_entry; |
65 | ||
01ca79f1 AK |
66 | DEFINE_PER_CPU(unsigned, mce_exception_count); |
67 | ||
bd78432c TH |
68 | /* |
69 | * Tolerant levels: | |
70 | * 0: always panic on uncorrected errors, log corrected errors | |
71 | * 1: panic or SIGBUS on uncorrected errors, log corrected errors | |
72 | * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors | |
73 | * 3: never panic or SIGBUS, log all errors (for testing only) | |
74 | */ | |
4e5b3e69 HS |
75 | static int tolerant __read_mostly = 1; |
76 | static int banks __read_mostly; | |
4e5b3e69 HS |
77 | static int rip_msr __read_mostly; |
78 | static int mce_bootlog __read_mostly = -1; | |
79 | static int monarch_timeout __read_mostly = -1; | |
80 | static int mce_panic_timeout __read_mostly; | |
81 | static int mce_dont_log_ce __read_mostly; | |
82 | int mce_cmci_disabled __read_mostly; | |
83 | int mce_ignore_ce __read_mostly; | |
84 | int mce_ser __read_mostly; | |
a98f0dd3 | 85 | |
cebe1820 AK |
86 | struct mce_bank *mce_banks __read_mostly; |
87 | ||
1020bcbc HS |
88 | /* User mode helper program triggered by machine check event */ |
89 | static unsigned long mce_need_notify; | |
90 | static char mce_helper[128]; | |
91 | static char *mce_helper_argv[2] = { mce_helper, NULL }; | |
1da177e4 | 92 | |
93b62c3c HS |
93 | static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait); |
94 | ||
3c079792 AK |
95 | static DEFINE_PER_CPU(struct mce, mces_seen); |
96 | static int cpu_missing; | |
97 | ||
ee031c31 AK |
98 | /* MCA banks polled by the period polling timer for corrected events */ |
99 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { | |
100 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL | |
101 | }; | |
102 | ||
9b1beaf2 AK |
103 | static DEFINE_PER_CPU(struct work_struct, mce_work); |
104 | ||
3653ada5 BP |
105 | /* |
106 | * CPU/chipset specific EDAC code can register a notifier call here to print | |
107 | * MCE errors in a human-readable form. | |
108 | */ | |
109 | ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain); | |
110 | ||
b5f2fa4e AK |
111 | /* Do initial initialization of a struct mce */ |
112 | void mce_setup(struct mce *m) | |
113 | { | |
114 | memset(m, 0, sizeof(struct mce)); | |
d620c67f | 115 | m->cpu = m->extcpu = smp_processor_id(); |
b5f2fa4e | 116 | rdtscll(m->tsc); |
8ee08347 AK |
117 | /* We hope get_seconds stays lockless */ |
118 | m->time = get_seconds(); | |
119 | m->cpuvendor = boot_cpu_data.x86_vendor; | |
120 | m->cpuid = cpuid_eax(1); | |
121 | #ifdef CONFIG_SMP | |
122 | m->socketid = cpu_data(m->extcpu).phys_proc_id; | |
123 | #endif | |
124 | m->apicid = cpu_data(m->extcpu).initial_apicid; | |
125 | rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap); | |
b5f2fa4e AK |
126 | } |
127 | ||
ea149b36 AK |
128 | DEFINE_PER_CPU(struct mce, injectm); |
129 | EXPORT_PER_CPU_SYMBOL_GPL(injectm); | |
130 | ||
1da177e4 LT |
131 | /* |
132 | * Lockless MCE logging infrastructure. | |
133 | * This avoids deadlocks on printk locks without having to break locks. Also | |
134 | * separate MCEs from kernel messages to avoid bogus bug reports. | |
135 | */ | |
136 | ||
231fd906 | 137 | static struct mce_log mcelog = { |
f6fb0ac0 AK |
138 | .signature = MCE_LOG_SIGNATURE, |
139 | .len = MCE_LOG_LEN, | |
140 | .recordlen = sizeof(struct mce), | |
d88203d1 | 141 | }; |
1da177e4 LT |
142 | |
143 | void mce_log(struct mce *mce) | |
144 | { | |
145 | unsigned next, entry; | |
f0cb5452 | 146 | int ret = 0; |
e9eee03e | 147 | |
8968f9d3 HS |
148 | /* Emit the trace record: */ |
149 | trace_mce_record(mce); | |
150 | ||
f0cb5452 BP |
151 | ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, mce); |
152 | if (ret == NOTIFY_STOP) | |
153 | return; | |
154 | ||
1da177e4 | 155 | mce->finished = 0; |
7644143c | 156 | wmb(); |
1da177e4 | 157 | for (;;) { |
f56e8a07 | 158 | entry = rcu_dereference_check_mce(mcelog.next); |
673242c1 | 159 | for (;;) { |
696e409d | 160 | |
e9eee03e IM |
161 | /* |
162 | * When the buffer fills up discard new entries. | |
163 | * Assume that the earlier errors are the more | |
164 | * interesting ones: | |
165 | */ | |
673242c1 | 166 | if (entry >= MCE_LOG_LEN) { |
14a02530 HS |
167 | set_bit(MCE_OVERFLOW, |
168 | (unsigned long *)&mcelog.flags); | |
673242c1 AK |
169 | return; |
170 | } | |
e9eee03e | 171 | /* Old left over entry. Skip: */ |
673242c1 AK |
172 | if (mcelog.entry[entry].finished) { |
173 | entry++; | |
174 | continue; | |
175 | } | |
7644143c | 176 | break; |
1da177e4 | 177 | } |
1da177e4 LT |
178 | smp_rmb(); |
179 | next = entry + 1; | |
180 | if (cmpxchg(&mcelog.next, entry, next) == entry) | |
181 | break; | |
182 | } | |
183 | memcpy(mcelog.entry + entry, mce, sizeof(struct mce)); | |
7644143c | 184 | wmb(); |
1da177e4 | 185 | mcelog.entry[entry].finished = 1; |
7644143c | 186 | wmb(); |
1da177e4 | 187 | |
a0189c70 | 188 | mce->finished = 1; |
1020bcbc | 189 | set_bit(0, &mce_need_notify); |
1da177e4 LT |
190 | } |
191 | ||
3653ada5 BP |
192 | void mce_register_decode_chain(struct notifier_block *nb) |
193 | { | |
194 | atomic_notifier_chain_register(&x86_mce_decoder_chain, nb); | |
195 | } | |
196 | EXPORT_SYMBOL_GPL(mce_register_decode_chain); | |
197 | ||
198 | void mce_unregister_decode_chain(struct notifier_block *nb) | |
199 | { | |
200 | atomic_notifier_chain_unregister(&x86_mce_decoder_chain, nb); | |
201 | } | |
202 | EXPORT_SYMBOL_GPL(mce_unregister_decode_chain); | |
203 | ||
77e26cca | 204 | static void print_mce(struct mce *m) |
1da177e4 | 205 | { |
dffa4b2f BP |
206 | int ret = 0; |
207 | ||
a2d7b0d4 | 208 | pr_emerg(HW_ERR "CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n", |
d620c67f | 209 | m->extcpu, m->mcgstatus, m->bank, m->status); |
f436f8bb | 210 | |
65ea5b03 | 211 | if (m->ip) { |
a2d7b0d4 | 212 | pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ", |
f436f8bb IM |
213 | !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", |
214 | m->cs, m->ip); | |
215 | ||
1da177e4 | 216 | if (m->cs == __KERNEL_CS) |
65ea5b03 | 217 | print_symbol("{%s}", m->ip); |
f436f8bb | 218 | pr_cont("\n"); |
1da177e4 | 219 | } |
f436f8bb | 220 | |
a2d7b0d4 | 221 | pr_emerg(HW_ERR "TSC %llx ", m->tsc); |
1da177e4 | 222 | if (m->addr) |
f436f8bb | 223 | pr_cont("ADDR %llx ", m->addr); |
1da177e4 | 224 | if (m->misc) |
f436f8bb | 225 | pr_cont("MISC %llx ", m->misc); |
549d042d | 226 | |
f436f8bb | 227 | pr_cont("\n"); |
506ed6b5 AK |
228 | /* |
229 | * Note this output is parsed by external tools and old fields | |
230 | * should not be changed. | |
231 | */ | |
881e23e5 | 232 | pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n", |
506ed6b5 AK |
233 | m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid, |
234 | cpu_data(m->extcpu).microcode); | |
f436f8bb IM |
235 | |
236 | /* | |
237 | * Print out human-readable details about the MCE error, | |
fb253195 | 238 | * (if the CPU has an implementation for that) |
f436f8bb | 239 | */ |
dffa4b2f BP |
240 | ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m); |
241 | if (ret == NOTIFY_STOP) | |
242 | return; | |
243 | ||
244 | pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n"); | |
86503560 AK |
245 | } |
246 | ||
f94b61c2 AK |
247 | #define PANIC_TIMEOUT 5 /* 5 seconds */ |
248 | ||
249 | static atomic_t mce_paniced; | |
250 | ||
bf783f9f HY |
251 | static int fake_panic; |
252 | static atomic_t mce_fake_paniced; | |
253 | ||
f94b61c2 AK |
254 | /* Panic in progress. Enable interrupts and wait for final IPI */ |
255 | static void wait_for_panic(void) | |
256 | { | |
257 | long timeout = PANIC_TIMEOUT*USEC_PER_SEC; | |
f436f8bb | 258 | |
f94b61c2 AK |
259 | preempt_disable(); |
260 | local_irq_enable(); | |
261 | while (timeout-- > 0) | |
262 | udelay(1); | |
29b0f591 AK |
263 | if (panic_timeout == 0) |
264 | panic_timeout = mce_panic_timeout; | |
f94b61c2 AK |
265 | panic("Panicing machine check CPU died"); |
266 | } | |
267 | ||
bd19a5e6 | 268 | static void mce_panic(char *msg, struct mce *final, char *exp) |
d88203d1 | 269 | { |
482908b4 | 270 | int i, apei_err = 0; |
e02e68d3 | 271 | |
bf783f9f HY |
272 | if (!fake_panic) { |
273 | /* | |
274 | * Make sure only one CPU runs in machine check panic | |
275 | */ | |
276 | if (atomic_inc_return(&mce_paniced) > 1) | |
277 | wait_for_panic(); | |
278 | barrier(); | |
f94b61c2 | 279 | |
bf783f9f HY |
280 | bust_spinlocks(1); |
281 | console_verbose(); | |
282 | } else { | |
283 | /* Don't log too much for fake panic */ | |
284 | if (atomic_inc_return(&mce_fake_paniced) > 1) | |
285 | return; | |
286 | } | |
a0189c70 | 287 | /* First print corrected ones that are still unlogged */ |
1da177e4 | 288 | for (i = 0; i < MCE_LOG_LEN; i++) { |
a0189c70 | 289 | struct mce *m = &mcelog.entry[i]; |
77e26cca HS |
290 | if (!(m->status & MCI_STATUS_VAL)) |
291 | continue; | |
482908b4 | 292 | if (!(m->status & MCI_STATUS_UC)) { |
77e26cca | 293 | print_mce(m); |
482908b4 HY |
294 | if (!apei_err) |
295 | apei_err = apei_write_mce(m); | |
296 | } | |
a0189c70 AK |
297 | } |
298 | /* Now print uncorrected but with the final one last */ | |
299 | for (i = 0; i < MCE_LOG_LEN; i++) { | |
300 | struct mce *m = &mcelog.entry[i]; | |
301 | if (!(m->status & MCI_STATUS_VAL)) | |
1da177e4 | 302 | continue; |
77e26cca HS |
303 | if (!(m->status & MCI_STATUS_UC)) |
304 | continue; | |
482908b4 | 305 | if (!final || memcmp(m, final, sizeof(struct mce))) { |
77e26cca | 306 | print_mce(m); |
482908b4 HY |
307 | if (!apei_err) |
308 | apei_err = apei_write_mce(m); | |
309 | } | |
1da177e4 | 310 | } |
482908b4 | 311 | if (final) { |
77e26cca | 312 | print_mce(final); |
482908b4 HY |
313 | if (!apei_err) |
314 | apei_err = apei_write_mce(final); | |
315 | } | |
3c079792 | 316 | if (cpu_missing) |
a2d7b0d4 | 317 | pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n"); |
bd19a5e6 | 318 | if (exp) |
a2d7b0d4 | 319 | pr_emerg(HW_ERR "Machine check: %s\n", exp); |
bf783f9f HY |
320 | if (!fake_panic) { |
321 | if (panic_timeout == 0) | |
322 | panic_timeout = mce_panic_timeout; | |
323 | panic(msg); | |
324 | } else | |
a2d7b0d4 | 325 | pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg); |
d88203d1 | 326 | } |
1da177e4 | 327 | |
ea149b36 AK |
328 | /* Support code for software error injection */ |
329 | ||
330 | static int msr_to_offset(u32 msr) | |
331 | { | |
0a3aee0d | 332 | unsigned bank = __this_cpu_read(injectm.bank); |
f436f8bb | 333 | |
ea149b36 AK |
334 | if (msr == rip_msr) |
335 | return offsetof(struct mce, ip); | |
a2d32bcb | 336 | if (msr == MSR_IA32_MCx_STATUS(bank)) |
ea149b36 | 337 | return offsetof(struct mce, status); |
a2d32bcb | 338 | if (msr == MSR_IA32_MCx_ADDR(bank)) |
ea149b36 | 339 | return offsetof(struct mce, addr); |
a2d32bcb | 340 | if (msr == MSR_IA32_MCx_MISC(bank)) |
ea149b36 AK |
341 | return offsetof(struct mce, misc); |
342 | if (msr == MSR_IA32_MCG_STATUS) | |
343 | return offsetof(struct mce, mcgstatus); | |
344 | return -1; | |
345 | } | |
346 | ||
5f8c1a54 AK |
347 | /* MSR access wrappers used for error injection */ |
348 | static u64 mce_rdmsrl(u32 msr) | |
349 | { | |
350 | u64 v; | |
11868a2d | 351 | |
0a3aee0d | 352 | if (__this_cpu_read(injectm.finished)) { |
ea149b36 | 353 | int offset = msr_to_offset(msr); |
11868a2d | 354 | |
ea149b36 AK |
355 | if (offset < 0) |
356 | return 0; | |
357 | return *(u64 *)((char *)&__get_cpu_var(injectm) + offset); | |
358 | } | |
11868a2d IM |
359 | |
360 | if (rdmsrl_safe(msr, &v)) { | |
361 | WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr); | |
362 | /* | |
363 | * Return zero in case the access faulted. This should | |
364 | * not happen normally but can happen if the CPU does | |
365 | * something weird, or if the code is buggy. | |
366 | */ | |
367 | v = 0; | |
368 | } | |
369 | ||
5f8c1a54 AK |
370 | return v; |
371 | } | |
372 | ||
373 | static void mce_wrmsrl(u32 msr, u64 v) | |
374 | { | |
0a3aee0d | 375 | if (__this_cpu_read(injectm.finished)) { |
ea149b36 | 376 | int offset = msr_to_offset(msr); |
11868a2d | 377 | |
ea149b36 AK |
378 | if (offset >= 0) |
379 | *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v; | |
380 | return; | |
381 | } | |
5f8c1a54 AK |
382 | wrmsrl(msr, v); |
383 | } | |
384 | ||
b8325c5b HS |
385 | /* |
386 | * Collect all global (w.r.t. this processor) status about this machine | |
387 | * check into our "mce" struct so that we can use it later to assess | |
388 | * the severity of the problem as we read per-bank specific details. | |
389 | */ | |
390 | static inline void mce_gather_info(struct mce *m, struct pt_regs *regs) | |
391 | { | |
392 | mce_setup(m); | |
393 | ||
394 | m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); | |
395 | if (regs) { | |
396 | /* | |
397 | * Get the address of the instruction at the time of | |
398 | * the machine check error. | |
399 | */ | |
400 | if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) { | |
401 | m->ip = regs->ip; | |
402 | m->cs = regs->cs; | |
403 | } | |
404 | /* Use accurate RIP reporting if available. */ | |
405 | if (rip_msr) | |
406 | m->ip = mce_rdmsrl(rip_msr); | |
407 | } | |
408 | } | |
409 | ||
9b1beaf2 AK |
410 | /* |
411 | * Simple lockless ring to communicate PFNs from the exception handler with the | |
412 | * process context work function. This is vastly simplified because there's | |
413 | * only a single reader and a single writer. | |
414 | */ | |
415 | #define MCE_RING_SIZE 16 /* we use one entry less */ | |
416 | ||
417 | struct mce_ring { | |
418 | unsigned short start; | |
419 | unsigned short end; | |
420 | unsigned long ring[MCE_RING_SIZE]; | |
421 | }; | |
422 | static DEFINE_PER_CPU(struct mce_ring, mce_ring); | |
423 | ||
424 | /* Runs with CPU affinity in workqueue */ | |
425 | static int mce_ring_empty(void) | |
426 | { | |
427 | struct mce_ring *r = &__get_cpu_var(mce_ring); | |
428 | ||
429 | return r->start == r->end; | |
430 | } | |
431 | ||
432 | static int mce_ring_get(unsigned long *pfn) | |
433 | { | |
434 | struct mce_ring *r; | |
435 | int ret = 0; | |
436 | ||
437 | *pfn = 0; | |
438 | get_cpu(); | |
439 | r = &__get_cpu_var(mce_ring); | |
440 | if (r->start == r->end) | |
441 | goto out; | |
442 | *pfn = r->ring[r->start]; | |
443 | r->start = (r->start + 1) % MCE_RING_SIZE; | |
444 | ret = 1; | |
445 | out: | |
446 | put_cpu(); | |
447 | return ret; | |
448 | } | |
449 | ||
450 | /* Always runs in MCE context with preempt off */ | |
451 | static int mce_ring_add(unsigned long pfn) | |
452 | { | |
453 | struct mce_ring *r = &__get_cpu_var(mce_ring); | |
454 | unsigned next; | |
455 | ||
456 | next = (r->end + 1) % MCE_RING_SIZE; | |
457 | if (next == r->start) | |
458 | return -1; | |
459 | r->ring[r->end] = pfn; | |
460 | wmb(); | |
461 | r->end = next; | |
462 | return 0; | |
463 | } | |
464 | ||
88ccbedd | 465 | int mce_available(struct cpuinfo_x86 *c) |
1da177e4 | 466 | { |
04b2b1a4 | 467 | if (mce_disabled) |
5b4408fd | 468 | return 0; |
3d1712c9 | 469 | return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); |
1da177e4 LT |
470 | } |
471 | ||
9b1beaf2 AK |
472 | static void mce_schedule_work(void) |
473 | { | |
474 | if (!mce_ring_empty()) { | |
475 | struct work_struct *work = &__get_cpu_var(mce_work); | |
476 | if (!work_pending(work)) | |
477 | schedule_work(work); | |
478 | } | |
479 | } | |
480 | ||
b77e70bf HS |
481 | DEFINE_PER_CPU(struct irq_work, mce_irq_work); |
482 | ||
483 | static void mce_irq_work_cb(struct irq_work *entry) | |
ccc3c319 | 484 | { |
9ff36ee9 | 485 | mce_notify_irq(); |
9b1beaf2 | 486 | mce_schedule_work(); |
ccc3c319 | 487 | } |
ccc3c319 AK |
488 | |
489 | static void mce_report_event(struct pt_regs *regs) | |
490 | { | |
491 | if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) { | |
9ff36ee9 | 492 | mce_notify_irq(); |
9b1beaf2 AK |
493 | /* |
494 | * Triggering the work queue here is just an insurance | |
495 | * policy in case the syscall exit notify handler | |
496 | * doesn't run soon enough or ends up running on the | |
497 | * wrong CPU (can happen when audit sleeps) | |
498 | */ | |
499 | mce_schedule_work(); | |
ccc3c319 AK |
500 | return; |
501 | } | |
502 | ||
b77e70bf | 503 | irq_work_queue(&__get_cpu_var(mce_irq_work)); |
ccc3c319 AK |
504 | } |
505 | ||
ca84f696 AK |
506 | DEFINE_PER_CPU(unsigned, mce_poll_count); |
507 | ||
d88203d1 | 508 | /* |
b79109c3 AK |
509 | * Poll for corrected events or events that happened before reset. |
510 | * Those are just logged through /dev/mcelog. | |
511 | * | |
512 | * This is executed in standard interrupt context. | |
ed7290d0 AK |
513 | * |
514 | * Note: spec recommends to panic for fatal unsignalled | |
515 | * errors here. However this would be quite problematic -- | |
516 | * we would need to reimplement the Monarch handling and | |
517 | * it would mess up the exclusion between exception handler | |
518 | * and poll hander -- * so we skip this for now. | |
519 | * These cases should not happen anyways, or only when the CPU | |
520 | * is already totally * confused. In this case it's likely it will | |
521 | * not fully execute the machine check handler either. | |
b79109c3 | 522 | */ |
ee031c31 | 523 | void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) |
b79109c3 AK |
524 | { |
525 | struct mce m; | |
526 | int i; | |
527 | ||
402af0d7 | 528 | percpu_inc(mce_poll_count); |
ca84f696 | 529 | |
b8325c5b | 530 | mce_gather_info(&m, NULL); |
b79109c3 | 531 | |
b79109c3 | 532 | for (i = 0; i < banks; i++) { |
cebe1820 | 533 | if (!mce_banks[i].ctl || !test_bit(i, *b)) |
b79109c3 AK |
534 | continue; |
535 | ||
536 | m.misc = 0; | |
537 | m.addr = 0; | |
538 | m.bank = i; | |
539 | m.tsc = 0; | |
540 | ||
541 | barrier(); | |
a2d32bcb | 542 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
b79109c3 AK |
543 | if (!(m.status & MCI_STATUS_VAL)) |
544 | continue; | |
545 | ||
546 | /* | |
ed7290d0 AK |
547 | * Uncorrected or signalled events are handled by the exception |
548 | * handler when it is enabled, so don't process those here. | |
b79109c3 AK |
549 | * |
550 | * TBD do the same check for MCI_STATUS_EN here? | |
551 | */ | |
ed7290d0 AK |
552 | if (!(flags & MCP_UC) && |
553 | (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC))) | |
b79109c3 AK |
554 | continue; |
555 | ||
556 | if (m.status & MCI_STATUS_MISCV) | |
a2d32bcb | 557 | m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i)); |
b79109c3 | 558 | if (m.status & MCI_STATUS_ADDRV) |
a2d32bcb | 559 | m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i)); |
b79109c3 AK |
560 | |
561 | if (!(flags & MCP_TIMESTAMP)) | |
562 | m.tsc = 0; | |
563 | /* | |
564 | * Don't get the IP here because it's unlikely to | |
565 | * have anything to do with the actual error location. | |
566 | */ | |
f0cb5452 | 567 | if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) |
5679af4c | 568 | mce_log(&m); |
b79109c3 AK |
569 | |
570 | /* | |
571 | * Clear state for this bank. | |
572 | */ | |
a2d32bcb | 573 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
b79109c3 AK |
574 | } |
575 | ||
576 | /* | |
577 | * Don't clear MCG_STATUS here because it's only defined for | |
578 | * exceptions. | |
579 | */ | |
88921be3 AK |
580 | |
581 | sync_core(); | |
b79109c3 | 582 | } |
ea149b36 | 583 | EXPORT_SYMBOL_GPL(machine_check_poll); |
b79109c3 | 584 | |
bd19a5e6 AK |
585 | /* |
586 | * Do a quick check if any of the events requires a panic. | |
587 | * This decides if we keep the events around or clear them. | |
588 | */ | |
589 | static int mce_no_way_out(struct mce *m, char **msg) | |
590 | { | |
591 | int i; | |
592 | ||
593 | for (i = 0; i < banks; i++) { | |
a2d32bcb | 594 | m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
bd19a5e6 AK |
595 | if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY) |
596 | return 1; | |
597 | } | |
598 | return 0; | |
599 | } | |
600 | ||
3c079792 AK |
601 | /* |
602 | * Variable to establish order between CPUs while scanning. | |
603 | * Each CPU spins initially until executing is equal its number. | |
604 | */ | |
605 | static atomic_t mce_executing; | |
606 | ||
607 | /* | |
608 | * Defines order of CPUs on entry. First CPU becomes Monarch. | |
609 | */ | |
610 | static atomic_t mce_callin; | |
611 | ||
612 | /* | |
613 | * Check if a timeout waiting for other CPUs happened. | |
614 | */ | |
615 | static int mce_timed_out(u64 *t) | |
616 | { | |
617 | /* | |
618 | * The others already did panic for some reason. | |
619 | * Bail out like in a timeout. | |
620 | * rmb() to tell the compiler that system_state | |
621 | * might have been modified by someone else. | |
622 | */ | |
623 | rmb(); | |
624 | if (atomic_read(&mce_paniced)) | |
625 | wait_for_panic(); | |
626 | if (!monarch_timeout) | |
627 | goto out; | |
628 | if ((s64)*t < SPINUNIT) { | |
629 | /* CHECKME: Make panic default for 1 too? */ | |
630 | if (tolerant < 1) | |
631 | mce_panic("Timeout synchronizing machine check over CPUs", | |
632 | NULL, NULL); | |
633 | cpu_missing = 1; | |
634 | return 1; | |
635 | } | |
636 | *t -= SPINUNIT; | |
637 | out: | |
638 | touch_nmi_watchdog(); | |
639 | return 0; | |
640 | } | |
641 | ||
642 | /* | |
643 | * The Monarch's reign. The Monarch is the CPU who entered | |
644 | * the machine check handler first. It waits for the others to | |
645 | * raise the exception too and then grades them. When any | |
646 | * error is fatal panic. Only then let the others continue. | |
647 | * | |
648 | * The other CPUs entering the MCE handler will be controlled by the | |
649 | * Monarch. They are called Subjects. | |
650 | * | |
651 | * This way we prevent any potential data corruption in a unrecoverable case | |
652 | * and also makes sure always all CPU's errors are examined. | |
653 | * | |
680b6cfd | 654 | * Also this detects the case of a machine check event coming from outer |
3c079792 AK |
655 | * space (not detected by any CPUs) In this case some external agent wants |
656 | * us to shut down, so panic too. | |
657 | * | |
658 | * The other CPUs might still decide to panic if the handler happens | |
659 | * in a unrecoverable place, but in this case the system is in a semi-stable | |
660 | * state and won't corrupt anything by itself. It's ok to let the others | |
661 | * continue for a bit first. | |
662 | * | |
663 | * All the spin loops have timeouts; when a timeout happens a CPU | |
664 | * typically elects itself to be Monarch. | |
665 | */ | |
666 | static void mce_reign(void) | |
667 | { | |
668 | int cpu; | |
669 | struct mce *m = NULL; | |
670 | int global_worst = 0; | |
671 | char *msg = NULL; | |
672 | char *nmsg = NULL; | |
673 | ||
674 | /* | |
675 | * This CPU is the Monarch and the other CPUs have run | |
676 | * through their handlers. | |
677 | * Grade the severity of the errors of all the CPUs. | |
678 | */ | |
679 | for_each_possible_cpu(cpu) { | |
680 | int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant, | |
681 | &nmsg); | |
682 | if (severity > global_worst) { | |
683 | msg = nmsg; | |
684 | global_worst = severity; | |
685 | m = &per_cpu(mces_seen, cpu); | |
686 | } | |
687 | } | |
688 | ||
689 | /* | |
690 | * Cannot recover? Panic here then. | |
691 | * This dumps all the mces in the log buffer and stops the | |
692 | * other CPUs. | |
693 | */ | |
694 | if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3) | |
ac960375 | 695 | mce_panic("Fatal Machine check", m, msg); |
3c079792 AK |
696 | |
697 | /* | |
698 | * For UC somewhere we let the CPU who detects it handle it. | |
699 | * Also must let continue the others, otherwise the handling | |
700 | * CPU could deadlock on a lock. | |
701 | */ | |
702 | ||
703 | /* | |
704 | * No machine check event found. Must be some external | |
705 | * source or one CPU is hung. Panic. | |
706 | */ | |
680b6cfd | 707 | if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3) |
3c079792 AK |
708 | mce_panic("Machine check from unknown source", NULL, NULL); |
709 | ||
710 | /* | |
711 | * Now clear all the mces_seen so that they don't reappear on | |
712 | * the next mce. | |
713 | */ | |
714 | for_each_possible_cpu(cpu) | |
715 | memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce)); | |
716 | } | |
717 | ||
718 | static atomic_t global_nwo; | |
719 | ||
720 | /* | |
721 | * Start of Monarch synchronization. This waits until all CPUs have | |
722 | * entered the exception handler and then determines if any of them | |
723 | * saw a fatal event that requires panic. Then it executes them | |
724 | * in the entry order. | |
725 | * TBD double check parallel CPU hotunplug | |
726 | */ | |
7fb06fc9 | 727 | static int mce_start(int *no_way_out) |
3c079792 | 728 | { |
7fb06fc9 | 729 | int order; |
3c079792 AK |
730 | int cpus = num_online_cpus(); |
731 | u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC; | |
732 | ||
7fb06fc9 HS |
733 | if (!timeout) |
734 | return -1; | |
3c079792 | 735 | |
7fb06fc9 | 736 | atomic_add(*no_way_out, &global_nwo); |
184e1fdf HY |
737 | /* |
738 | * global_nwo should be updated before mce_callin | |
739 | */ | |
740 | smp_wmb(); | |
a95436e4 | 741 | order = atomic_inc_return(&mce_callin); |
3c079792 AK |
742 | |
743 | /* | |
744 | * Wait for everyone. | |
745 | */ | |
746 | while (atomic_read(&mce_callin) != cpus) { | |
747 | if (mce_timed_out(&timeout)) { | |
748 | atomic_set(&global_nwo, 0); | |
7fb06fc9 | 749 | return -1; |
3c079792 AK |
750 | } |
751 | ndelay(SPINUNIT); | |
752 | } | |
753 | ||
184e1fdf HY |
754 | /* |
755 | * mce_callin should be read before global_nwo | |
756 | */ | |
757 | smp_rmb(); | |
3c079792 | 758 | |
7fb06fc9 HS |
759 | if (order == 1) { |
760 | /* | |
761 | * Monarch: Starts executing now, the others wait. | |
762 | */ | |
3c079792 | 763 | atomic_set(&mce_executing, 1); |
7fb06fc9 HS |
764 | } else { |
765 | /* | |
766 | * Subject: Now start the scanning loop one by one in | |
767 | * the original callin order. | |
768 | * This way when there are any shared banks it will be | |
769 | * only seen by one CPU before cleared, avoiding duplicates. | |
770 | */ | |
771 | while (atomic_read(&mce_executing) < order) { | |
772 | if (mce_timed_out(&timeout)) { | |
773 | atomic_set(&global_nwo, 0); | |
774 | return -1; | |
775 | } | |
776 | ndelay(SPINUNIT); | |
777 | } | |
3c079792 AK |
778 | } |
779 | ||
780 | /* | |
7fb06fc9 | 781 | * Cache the global no_way_out state. |
3c079792 | 782 | */ |
7fb06fc9 HS |
783 | *no_way_out = atomic_read(&global_nwo); |
784 | ||
785 | return order; | |
3c079792 AK |
786 | } |
787 | ||
788 | /* | |
789 | * Synchronize between CPUs after main scanning loop. | |
790 | * This invokes the bulk of the Monarch processing. | |
791 | */ | |
792 | static int mce_end(int order) | |
793 | { | |
794 | int ret = -1; | |
795 | u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC; | |
796 | ||
797 | if (!timeout) | |
798 | goto reset; | |
799 | if (order < 0) | |
800 | goto reset; | |
801 | ||
802 | /* | |
803 | * Allow others to run. | |
804 | */ | |
805 | atomic_inc(&mce_executing); | |
806 | ||
807 | if (order == 1) { | |
808 | /* CHECKME: Can this race with a parallel hotplug? */ | |
809 | int cpus = num_online_cpus(); | |
810 | ||
811 | /* | |
812 | * Monarch: Wait for everyone to go through their scanning | |
813 | * loops. | |
814 | */ | |
815 | while (atomic_read(&mce_executing) <= cpus) { | |
816 | if (mce_timed_out(&timeout)) | |
817 | goto reset; | |
818 | ndelay(SPINUNIT); | |
819 | } | |
820 | ||
821 | mce_reign(); | |
822 | barrier(); | |
823 | ret = 0; | |
824 | } else { | |
825 | /* | |
826 | * Subject: Wait for Monarch to finish. | |
827 | */ | |
828 | while (atomic_read(&mce_executing) != 0) { | |
829 | if (mce_timed_out(&timeout)) | |
830 | goto reset; | |
831 | ndelay(SPINUNIT); | |
832 | } | |
833 | ||
834 | /* | |
835 | * Don't reset anything. That's done by the Monarch. | |
836 | */ | |
837 | return 0; | |
838 | } | |
839 | ||
840 | /* | |
841 | * Reset all global state. | |
842 | */ | |
843 | reset: | |
844 | atomic_set(&global_nwo, 0); | |
845 | atomic_set(&mce_callin, 0); | |
846 | barrier(); | |
847 | ||
848 | /* | |
849 | * Let others run again. | |
850 | */ | |
851 | atomic_set(&mce_executing, 0); | |
852 | return ret; | |
853 | } | |
854 | ||
9b1beaf2 AK |
855 | /* |
856 | * Check if the address reported by the CPU is in a format we can parse. | |
857 | * It would be possible to add code for most other cases, but all would | |
858 | * be somewhat complicated (e.g. segment offset would require an instruction | |
0d2eb44f | 859 | * parser). So only support physical addresses up to page granuality for now. |
9b1beaf2 AK |
860 | */ |
861 | static int mce_usable_address(struct mce *m) | |
862 | { | |
863 | if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV)) | |
864 | return 0; | |
2b90e77e | 865 | if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT) |
9b1beaf2 | 866 | return 0; |
2b90e77e | 867 | if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS) |
9b1beaf2 AK |
868 | return 0; |
869 | return 1; | |
870 | } | |
871 | ||
3c079792 AK |
872 | static void mce_clear_state(unsigned long *toclear) |
873 | { | |
874 | int i; | |
875 | ||
876 | for (i = 0; i < banks; i++) { | |
877 | if (test_bit(i, toclear)) | |
a2d32bcb | 878 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
3c079792 AK |
879 | } |
880 | } | |
881 | ||
b79109c3 AK |
882 | /* |
883 | * The actual machine check handler. This only handles real | |
884 | * exceptions when something got corrupted coming in through int 18. | |
885 | * | |
886 | * This is executed in NMI context not subject to normal locking rules. This | |
887 | * implies that most kernel services cannot be safely used. Don't even | |
888 | * think about putting a printk in there! | |
3c079792 AK |
889 | * |
890 | * On Intel systems this is entered on all CPUs in parallel through | |
891 | * MCE broadcast. However some CPUs might be broken beyond repair, | |
892 | * so be always careful when synchronizing with others. | |
1da177e4 | 893 | */ |
e9eee03e | 894 | void do_machine_check(struct pt_regs *regs, long error_code) |
1da177e4 | 895 | { |
3c079792 | 896 | struct mce m, *final; |
1da177e4 | 897 | int i; |
3c079792 AK |
898 | int worst = 0; |
899 | int severity; | |
900 | /* | |
901 | * Establish sequential order between the CPUs entering the machine | |
902 | * check handler. | |
903 | */ | |
7fb06fc9 | 904 | int order; |
bd78432c TH |
905 | /* |
906 | * If no_way_out gets set, there is no safe way to recover from this | |
907 | * MCE. If tolerant is cranked up, we'll try anyway. | |
908 | */ | |
909 | int no_way_out = 0; | |
910 | /* | |
911 | * If kill_it gets set, there might be a way to recover from this | |
912 | * error. | |
913 | */ | |
914 | int kill_it = 0; | |
b79109c3 | 915 | DECLARE_BITMAP(toclear, MAX_NR_BANKS); |
bd19a5e6 | 916 | char *msg = "Unknown"; |
1da177e4 | 917 | |
553f265f AK |
918 | atomic_inc(&mce_entry); |
919 | ||
402af0d7 | 920 | percpu_inc(mce_exception_count); |
01ca79f1 | 921 | |
b79109c3 | 922 | if (!banks) |
32561696 | 923 | goto out; |
1da177e4 | 924 | |
b8325c5b | 925 | mce_gather_info(&m, regs); |
b5f2fa4e | 926 | |
3c079792 AK |
927 | final = &__get_cpu_var(mces_seen); |
928 | *final = m; | |
929 | ||
680b6cfd HS |
930 | no_way_out = mce_no_way_out(&m, &msg); |
931 | ||
1da177e4 LT |
932 | barrier(); |
933 | ||
ed7290d0 AK |
934 | /* |
935 | * When no restart IP must always kill or panic. | |
936 | */ | |
937 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) | |
938 | kill_it = 1; | |
939 | ||
3c079792 AK |
940 | /* |
941 | * Go through all the banks in exclusion of the other CPUs. | |
942 | * This way we don't report duplicated events on shared banks | |
943 | * because the first one to see it will clear it. | |
944 | */ | |
7fb06fc9 | 945 | order = mce_start(&no_way_out); |
1da177e4 | 946 | for (i = 0; i < banks; i++) { |
b79109c3 | 947 | __clear_bit(i, toclear); |
cebe1820 | 948 | if (!mce_banks[i].ctl) |
1da177e4 | 949 | continue; |
d88203d1 TG |
950 | |
951 | m.misc = 0; | |
1da177e4 LT |
952 | m.addr = 0; |
953 | m.bank = i; | |
1da177e4 | 954 | |
a2d32bcb | 955 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
1da177e4 LT |
956 | if ((m.status & MCI_STATUS_VAL) == 0) |
957 | continue; | |
958 | ||
b79109c3 | 959 | /* |
ed7290d0 AK |
960 | * Non uncorrected or non signaled errors are handled by |
961 | * machine_check_poll. Leave them alone, unless this panics. | |
b79109c3 | 962 | */ |
ed7290d0 AK |
963 | if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) && |
964 | !no_way_out) | |
b79109c3 AK |
965 | continue; |
966 | ||
967 | /* | |
968 | * Set taint even when machine check was not enabled. | |
969 | */ | |
970 | add_taint(TAINT_MACHINE_CHECK); | |
971 | ||
ed7290d0 | 972 | severity = mce_severity(&m, tolerant, NULL); |
b79109c3 | 973 | |
ed7290d0 AK |
974 | /* |
975 | * When machine check was for corrected handler don't touch, | |
976 | * unless we're panicing. | |
977 | */ | |
978 | if (severity == MCE_KEEP_SEVERITY && !no_way_out) | |
979 | continue; | |
980 | __set_bit(i, toclear); | |
981 | if (severity == MCE_NO_SEVERITY) { | |
b79109c3 AK |
982 | /* |
983 | * Machine check event was not enabled. Clear, but | |
984 | * ignore. | |
985 | */ | |
986 | continue; | |
1da177e4 LT |
987 | } |
988 | ||
ed7290d0 AK |
989 | /* |
990 | * Kill on action required. | |
991 | */ | |
992 | if (severity == MCE_AR_SEVERITY) | |
993 | kill_it = 1; | |
994 | ||
1da177e4 | 995 | if (m.status & MCI_STATUS_MISCV) |
a2d32bcb | 996 | m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i)); |
1da177e4 | 997 | if (m.status & MCI_STATUS_ADDRV) |
a2d32bcb | 998 | m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i)); |
1da177e4 | 999 | |
9b1beaf2 AK |
1000 | /* |
1001 | * Action optional error. Queue address for later processing. | |
1002 | * When the ring overflows we just ignore the AO error. | |
1003 | * RED-PEN add some logging mechanism when | |
1004 | * usable_address or mce_add_ring fails. | |
1005 | * RED-PEN don't ignore overflow for tolerant == 0 | |
1006 | */ | |
1007 | if (severity == MCE_AO_SEVERITY && mce_usable_address(&m)) | |
1008 | mce_ring_add(m.addr >> PAGE_SHIFT); | |
1009 | ||
b79109c3 | 1010 | mce_log(&m); |
1da177e4 | 1011 | |
3c079792 AK |
1012 | if (severity > worst) { |
1013 | *final = m; | |
1014 | worst = severity; | |
1da177e4 | 1015 | } |
1da177e4 LT |
1016 | } |
1017 | ||
3c079792 AK |
1018 | if (!no_way_out) |
1019 | mce_clear_state(toclear); | |
1020 | ||
e9eee03e | 1021 | /* |
3c079792 AK |
1022 | * Do most of the synchronization with other CPUs. |
1023 | * When there's any problem use only local no_way_out state. | |
e9eee03e | 1024 | */ |
3c079792 AK |
1025 | if (mce_end(order) < 0) |
1026 | no_way_out = worst >= MCE_PANIC_SEVERITY; | |
bd78432c TH |
1027 | |
1028 | /* | |
1029 | * If we have decided that we just CAN'T continue, and the user | |
e9eee03e | 1030 | * has not set tolerant to an insane level, give up and die. |
3c079792 AK |
1031 | * |
1032 | * This is mainly used in the case when the system doesn't | |
1033 | * support MCE broadcasting or it has been disabled. | |
bd78432c TH |
1034 | */ |
1035 | if (no_way_out && tolerant < 3) | |
ac960375 | 1036 | mce_panic("Fatal machine check on current CPU", final, msg); |
bd78432c TH |
1037 | |
1038 | /* | |
1039 | * If the error seems to be unrecoverable, something should be | |
1040 | * done. Try to kill as little as possible. If we can kill just | |
1041 | * one task, do that. If the user has set the tolerance very | |
1042 | * high, don't try to do anything at all. | |
1043 | */ | |
bd78432c | 1044 | |
ed7290d0 AK |
1045 | if (kill_it && tolerant < 3) |
1046 | force_sig(SIGBUS, current); | |
1da177e4 | 1047 | |
e02e68d3 TH |
1048 | /* notify userspace ASAP */ |
1049 | set_thread_flag(TIF_MCE_NOTIFY); | |
1050 | ||
3c079792 AK |
1051 | if (worst > 0) |
1052 | mce_report_event(regs); | |
5f8c1a54 | 1053 | mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); |
32561696 | 1054 | out: |
553f265f | 1055 | atomic_dec(&mce_entry); |
88921be3 | 1056 | sync_core(); |
1da177e4 | 1057 | } |
ea149b36 | 1058 | EXPORT_SYMBOL_GPL(do_machine_check); |
1da177e4 | 1059 | |
9b1beaf2 AK |
1060 | /* dummy to break dependency. actual code is in mm/memory-failure.c */ |
1061 | void __attribute__((weak)) memory_failure(unsigned long pfn, int vector) | |
1062 | { | |
1063 | printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn); | |
1064 | } | |
1065 | ||
1066 | /* | |
1067 | * Called after mce notification in process context. This code | |
1068 | * is allowed to sleep. Call the high level VM handler to process | |
1069 | * any corrupted pages. | |
1070 | * Assume that the work queue code only calls this one at a time | |
1071 | * per CPU. | |
1072 | * Note we don't disable preemption, so this code might run on the wrong | |
1073 | * CPU. In this case the event is picked up by the scheduled work queue. | |
1074 | * This is merely a fast path to expedite processing in some common | |
1075 | * cases. | |
1076 | */ | |
1077 | void mce_notify_process(void) | |
1078 | { | |
1079 | unsigned long pfn; | |
1080 | mce_notify_irq(); | |
1081 | while (mce_ring_get(&pfn)) | |
1082 | memory_failure(pfn, MCE_VECTOR); | |
1083 | } | |
1084 | ||
1085 | static void mce_process_work(struct work_struct *dummy) | |
1086 | { | |
1087 | mce_notify_process(); | |
1088 | } | |
1089 | ||
15d5f839 DZ |
1090 | #ifdef CONFIG_X86_MCE_INTEL |
1091 | /*** | |
1092 | * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog | |
676b1855 | 1093 | * @cpu: The CPU on which the event occurred. |
15d5f839 DZ |
1094 | * @status: Event status information |
1095 | * | |
1096 | * This function should be called by the thermal interrupt after the | |
1097 | * event has been processed and the decision was made to log the event | |
1098 | * further. | |
1099 | * | |
1100 | * The status parameter will be saved to the 'status' field of 'struct mce' | |
1101 | * and historically has been the register value of the | |
1102 | * MSR_IA32_THERMAL_STATUS (Intel) msr. | |
1103 | */ | |
b5f2fa4e | 1104 | void mce_log_therm_throt_event(__u64 status) |
15d5f839 DZ |
1105 | { |
1106 | struct mce m; | |
1107 | ||
b5f2fa4e | 1108 | mce_setup(&m); |
15d5f839 DZ |
1109 | m.bank = MCE_THERMAL_BANK; |
1110 | m.status = status; | |
15d5f839 DZ |
1111 | mce_log(&m); |
1112 | } | |
1113 | #endif /* CONFIG_X86_MCE_INTEL */ | |
1114 | ||
1da177e4 | 1115 | /* |
8a336b0a TH |
1116 | * Periodic polling timer for "silent" machine check errors. If the |
1117 | * poller finds an MCE, poll 2x faster. When the poller finds no more | |
1118 | * errors, poll 2x slower (up to check_interval seconds). | |
1da177e4 | 1119 | */ |
1da177e4 | 1120 | static int check_interval = 5 * 60; /* 5 minutes */ |
e9eee03e | 1121 | |
245b2e70 | 1122 | static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */ |
52d168e2 | 1123 | static DEFINE_PER_CPU(struct timer_list, mce_timer); |
1da177e4 | 1124 | |
5e09954a | 1125 | static void mce_start_timer(unsigned long data) |
1da177e4 | 1126 | { |
52d168e2 | 1127 | struct timer_list *t = &per_cpu(mce_timer, data); |
6298c512 | 1128 | int *n; |
52d168e2 AK |
1129 | |
1130 | WARN_ON(smp_processor_id() != data); | |
1131 | ||
7b543a53 | 1132 | if (mce_available(__this_cpu_ptr(&cpu_info))) { |
ee031c31 AK |
1133 | machine_check_poll(MCP_TIMESTAMP, |
1134 | &__get_cpu_var(mce_poll_banks)); | |
e9eee03e | 1135 | } |
1da177e4 LT |
1136 | |
1137 | /* | |
e02e68d3 TH |
1138 | * Alert userspace if needed. If we logged an MCE, reduce the |
1139 | * polling interval, otherwise increase the polling interval. | |
1da177e4 | 1140 | */ |
245b2e70 | 1141 | n = &__get_cpu_var(mce_next_interval); |
9ff36ee9 | 1142 | if (mce_notify_irq()) |
6298c512 | 1143 | *n = max(*n/2, HZ/100); |
14a02530 | 1144 | else |
6298c512 | 1145 | *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ)); |
e02e68d3 | 1146 | |
6298c512 | 1147 | t->expires = jiffies + *n; |
5be6066a | 1148 | add_timer_on(t, smp_processor_id()); |
e02e68d3 TH |
1149 | } |
1150 | ||
9aaef96f HS |
1151 | /* Must not be called in IRQ context where del_timer_sync() can deadlock */ |
1152 | static void mce_timer_delete_all(void) | |
1153 | { | |
1154 | int cpu; | |
1155 | ||
1156 | for_each_online_cpu(cpu) | |
1157 | del_timer_sync(&per_cpu(mce_timer, cpu)); | |
1158 | } | |
1159 | ||
9bd98405 AK |
1160 | static void mce_do_trigger(struct work_struct *work) |
1161 | { | |
1020bcbc | 1162 | call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT); |
9bd98405 AK |
1163 | } |
1164 | ||
1165 | static DECLARE_WORK(mce_trigger_work, mce_do_trigger); | |
1166 | ||
e02e68d3 | 1167 | /* |
9bd98405 AK |
1168 | * Notify the user(s) about new machine check events. |
1169 | * Can be called from interrupt context, but not from machine check/NMI | |
1170 | * context. | |
e02e68d3 | 1171 | */ |
9ff36ee9 | 1172 | int mce_notify_irq(void) |
e02e68d3 | 1173 | { |
8457c84d AK |
1174 | /* Not more than two messages every minute */ |
1175 | static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); | |
1176 | ||
e02e68d3 | 1177 | clear_thread_flag(TIF_MCE_NOTIFY); |
e9eee03e | 1178 | |
1020bcbc | 1179 | if (test_and_clear_bit(0, &mce_need_notify)) { |
93b62c3c HS |
1180 | /* wake processes polling /dev/mcelog */ |
1181 | wake_up_interruptible(&mce_chrdev_wait); | |
9bd98405 AK |
1182 | |
1183 | /* | |
1184 | * There is no risk of missing notifications because | |
1185 | * work_pending is always cleared before the function is | |
1186 | * executed. | |
1187 | */ | |
1020bcbc | 1188 | if (mce_helper[0] && !work_pending(&mce_trigger_work)) |
9bd98405 | 1189 | schedule_work(&mce_trigger_work); |
e02e68d3 | 1190 | |
8457c84d | 1191 | if (__ratelimit(&ratelimit)) |
a2d7b0d4 | 1192 | pr_info(HW_ERR "Machine check events logged\n"); |
e02e68d3 TH |
1193 | |
1194 | return 1; | |
1da177e4 | 1195 | } |
e02e68d3 TH |
1196 | return 0; |
1197 | } | |
9ff36ee9 | 1198 | EXPORT_SYMBOL_GPL(mce_notify_irq); |
8a336b0a | 1199 | |
cffd377e | 1200 | static int __cpuinit __mcheck_cpu_mce_banks_init(void) |
cebe1820 AK |
1201 | { |
1202 | int i; | |
1203 | ||
1204 | mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL); | |
1205 | if (!mce_banks) | |
1206 | return -ENOMEM; | |
1207 | for (i = 0; i < banks; i++) { | |
1208 | struct mce_bank *b = &mce_banks[i]; | |
11868a2d | 1209 | |
cebe1820 AK |
1210 | b->ctl = -1ULL; |
1211 | b->init = 1; | |
1212 | } | |
1213 | return 0; | |
1214 | } | |
1215 | ||
d88203d1 | 1216 | /* |
1da177e4 LT |
1217 | * Initialize Machine Checks for a CPU. |
1218 | */ | |
5e09954a | 1219 | static int __cpuinit __mcheck_cpu_cap_init(void) |
1da177e4 | 1220 | { |
0d7482e3 | 1221 | unsigned b; |
e9eee03e | 1222 | u64 cap; |
1da177e4 LT |
1223 | |
1224 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
01c6680a TG |
1225 | |
1226 | b = cap & MCG_BANKCNT_MASK; | |
93ae5012 RD |
1227 | if (!banks) |
1228 | printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b); | |
b659294b | 1229 | |
0d7482e3 AK |
1230 | if (b > MAX_NR_BANKS) { |
1231 | printk(KERN_WARNING | |
1232 | "MCE: Using only %u machine check banks out of %u\n", | |
1233 | MAX_NR_BANKS, b); | |
1234 | b = MAX_NR_BANKS; | |
1235 | } | |
1236 | ||
1237 | /* Don't support asymmetric configurations today */ | |
1238 | WARN_ON(banks != 0 && b != banks); | |
1239 | banks = b; | |
cebe1820 | 1240 | if (!mce_banks) { |
cffd377e | 1241 | int err = __mcheck_cpu_mce_banks_init(); |
11868a2d | 1242 | |
cebe1820 AK |
1243 | if (err) |
1244 | return err; | |
1da177e4 | 1245 | } |
0d7482e3 | 1246 | |
94ad8474 | 1247 | /* Use accurate RIP reporting if available. */ |
01c6680a | 1248 | if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) |
94ad8474 | 1249 | rip_msr = MSR_IA32_MCG_EIP; |
1da177e4 | 1250 | |
ed7290d0 AK |
1251 | if (cap & MCG_SER_P) |
1252 | mce_ser = 1; | |
1253 | ||
0d7482e3 AK |
1254 | return 0; |
1255 | } | |
1256 | ||
5e09954a | 1257 | static void __mcheck_cpu_init_generic(void) |
0d7482e3 | 1258 | { |
e9eee03e | 1259 | mce_banks_t all_banks; |
0d7482e3 AK |
1260 | u64 cap; |
1261 | int i; | |
1262 | ||
b79109c3 AK |
1263 | /* |
1264 | * Log the machine checks left over from the previous reset. | |
1265 | */ | |
ee031c31 | 1266 | bitmap_fill(all_banks, MAX_NR_BANKS); |
5679af4c | 1267 | machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks); |
1da177e4 LT |
1268 | |
1269 | set_in_cr4(X86_CR4_MCE); | |
1270 | ||
0d7482e3 | 1271 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
1da177e4 LT |
1272 | if (cap & MCG_CTL_P) |
1273 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); | |
1274 | ||
1275 | for (i = 0; i < banks; i++) { | |
cebe1820 | 1276 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1277 | |
cebe1820 | 1278 | if (!b->init) |
06b7a7a5 | 1279 | continue; |
a2d32bcb AK |
1280 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
1281 | wrmsrl(MSR_IA32_MCx_STATUS(i), 0); | |
d88203d1 | 1282 | } |
1da177e4 LT |
1283 | } |
1284 | ||
1285 | /* Add per CPU specific workarounds here */ | |
5e09954a | 1286 | static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) |
d88203d1 | 1287 | { |
e412cd25 IM |
1288 | if (c->x86_vendor == X86_VENDOR_UNKNOWN) { |
1289 | pr_info("MCE: unknown CPU type - not enabling MCE support.\n"); | |
1290 | return -EOPNOTSUPP; | |
1291 | } | |
1292 | ||
1da177e4 | 1293 | /* This should be disabled by the BIOS, but isn't always */ |
911f6a7b | 1294 | if (c->x86_vendor == X86_VENDOR_AMD) { |
e9eee03e IM |
1295 | if (c->x86 == 15 && banks > 4) { |
1296 | /* | |
1297 | * disable GART TBL walk error reporting, which | |
1298 | * trips off incorrectly with the IOMMU & 3ware | |
1299 | * & Cerberus: | |
1300 | */ | |
cebe1820 | 1301 | clear_bit(10, (unsigned long *)&mce_banks[4].ctl); |
e9eee03e IM |
1302 | } |
1303 | if (c->x86 <= 17 && mce_bootlog < 0) { | |
1304 | /* | |
1305 | * Lots of broken BIOS around that don't clear them | |
1306 | * by default and leave crap in there. Don't log: | |
1307 | */ | |
911f6a7b | 1308 | mce_bootlog = 0; |
e9eee03e | 1309 | } |
2e6f694f AK |
1310 | /* |
1311 | * Various K7s with broken bank 0 around. Always disable | |
1312 | * by default. | |
1313 | */ | |
203abd67 | 1314 | if (c->x86 == 6 && banks > 0) |
cebe1820 | 1315 | mce_banks[0].ctl = 0; |
1da177e4 | 1316 | } |
e583538f | 1317 | |
06b7a7a5 AK |
1318 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
1319 | /* | |
1320 | * SDM documents that on family 6 bank 0 should not be written | |
1321 | * because it aliases to another special BIOS controlled | |
1322 | * register. | |
1323 | * But it's not aliased anymore on model 0x1a+ | |
1324 | * Don't ignore bank 0 completely because there could be a | |
1325 | * valid event later, merely don't write CTL0. | |
1326 | */ | |
1327 | ||
cebe1820 AK |
1328 | if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0) |
1329 | mce_banks[0].init = 0; | |
3c079792 AK |
1330 | |
1331 | /* | |
1332 | * All newer Intel systems support MCE broadcasting. Enable | |
1333 | * synchronization with a one second timeout. | |
1334 | */ | |
1335 | if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && | |
1336 | monarch_timeout < 0) | |
1337 | monarch_timeout = USEC_PER_SEC; | |
c7f6fa44 | 1338 | |
e412cd25 IM |
1339 | /* |
1340 | * There are also broken BIOSes on some Pentium M and | |
1341 | * earlier systems: | |
1342 | */ | |
1343 | if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0) | |
c7f6fa44 | 1344 | mce_bootlog = 0; |
06b7a7a5 | 1345 | } |
3c079792 AK |
1346 | if (monarch_timeout < 0) |
1347 | monarch_timeout = 0; | |
29b0f591 AK |
1348 | if (mce_bootlog != 0) |
1349 | mce_panic_timeout = 30; | |
e412cd25 IM |
1350 | |
1351 | return 0; | |
d88203d1 | 1352 | } |
1da177e4 | 1353 | |
3a97fc34 | 1354 | static int __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) |
4efc0670 AK |
1355 | { |
1356 | if (c->x86 != 5) | |
3a97fc34 HS |
1357 | return 0; |
1358 | ||
4efc0670 AK |
1359 | switch (c->x86_vendor) { |
1360 | case X86_VENDOR_INTEL: | |
c6978369 | 1361 | intel_p5_mcheck_init(c); |
3a97fc34 | 1362 | return 1; |
4efc0670 AK |
1363 | break; |
1364 | case X86_VENDOR_CENTAUR: | |
1365 | winchip_mcheck_init(c); | |
3a97fc34 | 1366 | return 1; |
4efc0670 AK |
1367 | break; |
1368 | } | |
3a97fc34 HS |
1369 | |
1370 | return 0; | |
4efc0670 AK |
1371 | } |
1372 | ||
5e09954a | 1373 | static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
1374 | { |
1375 | switch (c->x86_vendor) { | |
1376 | case X86_VENDOR_INTEL: | |
1377 | mce_intel_feature_init(c); | |
1378 | break; | |
89b831ef JS |
1379 | case X86_VENDOR_AMD: |
1380 | mce_amd_feature_init(c); | |
1381 | break; | |
1da177e4 LT |
1382 | default: |
1383 | break; | |
1384 | } | |
1385 | } | |
1386 | ||
5e09954a | 1387 | static void __mcheck_cpu_init_timer(void) |
52d168e2 AK |
1388 | { |
1389 | struct timer_list *t = &__get_cpu_var(mce_timer); | |
245b2e70 | 1390 | int *n = &__get_cpu_var(mce_next_interval); |
52d168e2 | 1391 | |
bc09effa JB |
1392 | setup_timer(t, mce_start_timer, smp_processor_id()); |
1393 | ||
62fdac59 HS |
1394 | if (mce_ignore_ce) |
1395 | return; | |
1396 | ||
6298c512 AK |
1397 | *n = check_interval * HZ; |
1398 | if (!*n) | |
52d168e2 | 1399 | return; |
6298c512 | 1400 | t->expires = round_jiffies(jiffies + *n); |
5be6066a | 1401 | add_timer_on(t, smp_processor_id()); |
52d168e2 AK |
1402 | } |
1403 | ||
9eda8cb3 AK |
1404 | /* Handle unconfigured int18 (should never happen) */ |
1405 | static void unexpected_machine_check(struct pt_regs *regs, long error_code) | |
1406 | { | |
1407 | printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n", | |
1408 | smp_processor_id()); | |
1409 | } | |
1410 | ||
1411 | /* Call the installed machine check handler for this CPU setup. */ | |
1412 | void (*machine_check_vector)(struct pt_regs *, long error_code) = | |
1413 | unexpected_machine_check; | |
1414 | ||
d88203d1 | 1415 | /* |
1da177e4 | 1416 | * Called for each booted CPU to set up machine checks. |
e9eee03e | 1417 | * Must be called with preempt off: |
1da177e4 | 1418 | */ |
5e09954a | 1419 | void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c) |
1da177e4 | 1420 | { |
4efc0670 AK |
1421 | if (mce_disabled) |
1422 | return; | |
1423 | ||
3a97fc34 HS |
1424 | if (__mcheck_cpu_ancient_init(c)) |
1425 | return; | |
4efc0670 | 1426 | |
5b4408fd | 1427 | if (!mce_available(c)) |
1da177e4 LT |
1428 | return; |
1429 | ||
5e09954a | 1430 | if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) { |
04b2b1a4 | 1431 | mce_disabled = 1; |
0d7482e3 AK |
1432 | return; |
1433 | } | |
0d7482e3 | 1434 | |
5d727926 AK |
1435 | machine_check_vector = do_machine_check; |
1436 | ||
5e09954a BP |
1437 | __mcheck_cpu_init_generic(); |
1438 | __mcheck_cpu_init_vendor(c); | |
1439 | __mcheck_cpu_init_timer(); | |
9b1beaf2 | 1440 | INIT_WORK(&__get_cpu_var(mce_work), mce_process_work); |
b77e70bf | 1441 | init_irq_work(&__get_cpu_var(mce_irq_work), &mce_irq_work_cb); |
1da177e4 LT |
1442 | } |
1443 | ||
1444 | /* | |
93b62c3c | 1445 | * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log. |
1da177e4 LT |
1446 | */ |
1447 | ||
93b62c3c HS |
1448 | static DEFINE_SPINLOCK(mce_chrdev_state_lock); |
1449 | static int mce_chrdev_open_count; /* #times opened */ | |
1450 | static int mce_chrdev_open_exclu; /* already open exclusive? */ | |
f528e7ba | 1451 | |
93b62c3c | 1452 | static int mce_chrdev_open(struct inode *inode, struct file *file) |
f528e7ba | 1453 | { |
93b62c3c | 1454 | spin_lock(&mce_chrdev_state_lock); |
f528e7ba | 1455 | |
93b62c3c HS |
1456 | if (mce_chrdev_open_exclu || |
1457 | (mce_chrdev_open_count && (file->f_flags & O_EXCL))) { | |
1458 | spin_unlock(&mce_chrdev_state_lock); | |
e9eee03e | 1459 | |
f528e7ba TH |
1460 | return -EBUSY; |
1461 | } | |
1462 | ||
1463 | if (file->f_flags & O_EXCL) | |
93b62c3c HS |
1464 | mce_chrdev_open_exclu = 1; |
1465 | mce_chrdev_open_count++; | |
f528e7ba | 1466 | |
93b62c3c | 1467 | spin_unlock(&mce_chrdev_state_lock); |
f528e7ba | 1468 | |
bd78432c | 1469 | return nonseekable_open(inode, file); |
f528e7ba TH |
1470 | } |
1471 | ||
93b62c3c | 1472 | static int mce_chrdev_release(struct inode *inode, struct file *file) |
f528e7ba | 1473 | { |
93b62c3c | 1474 | spin_lock(&mce_chrdev_state_lock); |
f528e7ba | 1475 | |
93b62c3c HS |
1476 | mce_chrdev_open_count--; |
1477 | mce_chrdev_open_exclu = 0; | |
f528e7ba | 1478 | |
93b62c3c | 1479 | spin_unlock(&mce_chrdev_state_lock); |
f528e7ba TH |
1480 | |
1481 | return 0; | |
1482 | } | |
1483 | ||
d88203d1 TG |
1484 | static void collect_tscs(void *data) |
1485 | { | |
1da177e4 | 1486 | unsigned long *cpu_tsc = (unsigned long *)data; |
d88203d1 | 1487 | |
1da177e4 | 1488 | rdtscll(cpu_tsc[smp_processor_id()]); |
d88203d1 | 1489 | } |
1da177e4 | 1490 | |
482908b4 HY |
1491 | static int mce_apei_read_done; |
1492 | ||
1493 | /* Collect MCE record of previous boot in persistent storage via APEI ERST. */ | |
1494 | static int __mce_read_apei(char __user **ubuf, size_t usize) | |
1495 | { | |
1496 | int rc; | |
1497 | u64 record_id; | |
1498 | struct mce m; | |
1499 | ||
1500 | if (usize < sizeof(struct mce)) | |
1501 | return -EINVAL; | |
1502 | ||
1503 | rc = apei_read_mce(&m, &record_id); | |
1504 | /* Error or no more MCE record */ | |
1505 | if (rc <= 0) { | |
1506 | mce_apei_read_done = 1; | |
1507 | return rc; | |
1508 | } | |
1509 | rc = -EFAULT; | |
1510 | if (copy_to_user(*ubuf, &m, sizeof(struct mce))) | |
1511 | return rc; | |
1512 | /* | |
1513 | * In fact, we should have cleared the record after that has | |
1514 | * been flushed to the disk or sent to network in | |
1515 | * /sbin/mcelog, but we have no interface to support that now, | |
1516 | * so just clear it to avoid duplication. | |
1517 | */ | |
1518 | rc = apei_clear_mce(record_id); | |
1519 | if (rc) { | |
1520 | mce_apei_read_done = 1; | |
1521 | return rc; | |
1522 | } | |
1523 | *ubuf += sizeof(struct mce); | |
1524 | ||
1525 | return 0; | |
1526 | } | |
1527 | ||
93b62c3c HS |
1528 | static ssize_t mce_chrdev_read(struct file *filp, char __user *ubuf, |
1529 | size_t usize, loff_t *off) | |
1da177e4 | 1530 | { |
e9eee03e | 1531 | char __user *buf = ubuf; |
f0de53bb | 1532 | unsigned long *cpu_tsc; |
ef41df43 | 1533 | unsigned prev, next; |
1da177e4 LT |
1534 | int i, err; |
1535 | ||
6bca67f9 | 1536 | cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL); |
f0de53bb AK |
1537 | if (!cpu_tsc) |
1538 | return -ENOMEM; | |
1539 | ||
93b62c3c | 1540 | mutex_lock(&mce_chrdev_read_mutex); |
482908b4 HY |
1541 | |
1542 | if (!mce_apei_read_done) { | |
1543 | err = __mce_read_apei(&buf, usize); | |
1544 | if (err || buf != ubuf) | |
1545 | goto out; | |
1546 | } | |
1547 | ||
f56e8a07 | 1548 | next = rcu_dereference_check_mce(mcelog.next); |
1da177e4 LT |
1549 | |
1550 | /* Only supports full reads right now */ | |
482908b4 HY |
1551 | err = -EINVAL; |
1552 | if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) | |
1553 | goto out; | |
1da177e4 LT |
1554 | |
1555 | err = 0; | |
ef41df43 HY |
1556 | prev = 0; |
1557 | do { | |
1558 | for (i = prev; i < next; i++) { | |
1559 | unsigned long start = jiffies; | |
559faa6b | 1560 | struct mce *m = &mcelog.entry[i]; |
ef41df43 | 1561 | |
559faa6b | 1562 | while (!m->finished) { |
ef41df43 | 1563 | if (time_after_eq(jiffies, start + 2)) { |
559faa6b | 1564 | memset(m, 0, sizeof(*m)); |
ef41df43 HY |
1565 | goto timeout; |
1566 | } | |
1567 | cpu_relax(); | |
673242c1 | 1568 | } |
ef41df43 | 1569 | smp_rmb(); |
559faa6b HS |
1570 | err |= copy_to_user(buf, m, sizeof(*m)); |
1571 | buf += sizeof(*m); | |
ef41df43 HY |
1572 | timeout: |
1573 | ; | |
673242c1 | 1574 | } |
1da177e4 | 1575 | |
ef41df43 HY |
1576 | memset(mcelog.entry + prev, 0, |
1577 | (next - prev) * sizeof(struct mce)); | |
1578 | prev = next; | |
1579 | next = cmpxchg(&mcelog.next, prev, 0); | |
1580 | } while (next != prev); | |
1da177e4 | 1581 | |
b2b18660 | 1582 | synchronize_sched(); |
1da177e4 | 1583 | |
d88203d1 TG |
1584 | /* |
1585 | * Collect entries that were still getting written before the | |
1586 | * synchronize. | |
1587 | */ | |
15c8b6c1 | 1588 | on_each_cpu(collect_tscs, cpu_tsc, 1); |
e9eee03e | 1589 | |
d88203d1 | 1590 | for (i = next; i < MCE_LOG_LEN; i++) { |
559faa6b HS |
1591 | struct mce *m = &mcelog.entry[i]; |
1592 | ||
1593 | if (m->finished && m->tsc < cpu_tsc[m->cpu]) { | |
1594 | err |= copy_to_user(buf, m, sizeof(*m)); | |
1da177e4 | 1595 | smp_rmb(); |
559faa6b HS |
1596 | buf += sizeof(*m); |
1597 | memset(m, 0, sizeof(*m)); | |
1da177e4 | 1598 | } |
d88203d1 | 1599 | } |
482908b4 HY |
1600 | |
1601 | if (err) | |
1602 | err = -EFAULT; | |
1603 | ||
1604 | out: | |
93b62c3c | 1605 | mutex_unlock(&mce_chrdev_read_mutex); |
f0de53bb | 1606 | kfree(cpu_tsc); |
e9eee03e | 1607 | |
482908b4 | 1608 | return err ? err : buf - ubuf; |
1da177e4 LT |
1609 | } |
1610 | ||
93b62c3c | 1611 | static unsigned int mce_chrdev_poll(struct file *file, poll_table *wait) |
e02e68d3 | 1612 | { |
93b62c3c | 1613 | poll_wait(file, &mce_chrdev_wait, wait); |
a4dd9925 | 1614 | if (rcu_access_index(mcelog.next)) |
e02e68d3 | 1615 | return POLLIN | POLLRDNORM; |
482908b4 HY |
1616 | if (!mce_apei_read_done && apei_check_mce()) |
1617 | return POLLIN | POLLRDNORM; | |
e02e68d3 TH |
1618 | return 0; |
1619 | } | |
1620 | ||
93b62c3c HS |
1621 | static long mce_chrdev_ioctl(struct file *f, unsigned int cmd, |
1622 | unsigned long arg) | |
1da177e4 LT |
1623 | { |
1624 | int __user *p = (int __user *)arg; | |
d88203d1 | 1625 | |
1da177e4 | 1626 | if (!capable(CAP_SYS_ADMIN)) |
d88203d1 | 1627 | return -EPERM; |
e9eee03e | 1628 | |
1da177e4 | 1629 | switch (cmd) { |
d88203d1 | 1630 | case MCE_GET_RECORD_LEN: |
1da177e4 LT |
1631 | return put_user(sizeof(struct mce), p); |
1632 | case MCE_GET_LOG_LEN: | |
d88203d1 | 1633 | return put_user(MCE_LOG_LEN, p); |
1da177e4 LT |
1634 | case MCE_GETCLEAR_FLAGS: { |
1635 | unsigned flags; | |
d88203d1 TG |
1636 | |
1637 | do { | |
1da177e4 | 1638 | flags = mcelog.flags; |
d88203d1 | 1639 | } while (cmpxchg(&mcelog.flags, flags, 0) != flags); |
e9eee03e | 1640 | |
d88203d1 | 1641 | return put_user(flags, p); |
1da177e4 LT |
1642 | } |
1643 | default: | |
d88203d1 TG |
1644 | return -ENOTTY; |
1645 | } | |
1da177e4 LT |
1646 | } |
1647 | ||
66f5ddf3 LT |
1648 | static ssize_t (*mce_write)(struct file *filp, const char __user *ubuf, |
1649 | size_t usize, loff_t *off); | |
1650 | ||
1651 | void register_mce_write_callback(ssize_t (*fn)(struct file *filp, | |
1652 | const char __user *ubuf, | |
1653 | size_t usize, loff_t *off)) | |
1654 | { | |
1655 | mce_write = fn; | |
1656 | } | |
1657 | EXPORT_SYMBOL_GPL(register_mce_write_callback); | |
1658 | ||
1659 | ssize_t mce_chrdev_write(struct file *filp, const char __user *ubuf, | |
1660 | size_t usize, loff_t *off) | |
1661 | { | |
1662 | if (mce_write) | |
1663 | return mce_write(filp, ubuf, usize, off); | |
1664 | else | |
1665 | return -EINVAL; | |
1666 | } | |
1667 | ||
1668 | static const struct file_operations mce_chrdev_ops = { | |
93b62c3c HS |
1669 | .open = mce_chrdev_open, |
1670 | .release = mce_chrdev_release, | |
1671 | .read = mce_chrdev_read, | |
66f5ddf3 | 1672 | .write = mce_chrdev_write, |
93b62c3c HS |
1673 | .poll = mce_chrdev_poll, |
1674 | .unlocked_ioctl = mce_chrdev_ioctl, | |
1675 | .llseek = no_llseek, | |
1da177e4 LT |
1676 | }; |
1677 | ||
93b62c3c | 1678 | static struct miscdevice mce_chrdev_device = { |
1da177e4 LT |
1679 | MISC_MCELOG_MINOR, |
1680 | "mcelog", | |
1681 | &mce_chrdev_ops, | |
1682 | }; | |
1683 | ||
13503fa9 | 1684 | /* |
62fdac59 HS |
1685 | * mce=off Disables machine check |
1686 | * mce=no_cmci Disables CMCI | |
1687 | * mce=dont_log_ce Clears corrected events silently, no log created for CEs. | |
1688 | * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared. | |
3c079792 AK |
1689 | * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above) |
1690 | * monarchtimeout is how long to wait for other CPUs on machine | |
1691 | * check, or 0 to not wait | |
13503fa9 HS |
1692 | * mce=bootlog Log MCEs from before booting. Disabled by default on AMD. |
1693 | * mce=nobootlog Don't log MCEs from before booting. | |
1694 | */ | |
1da177e4 LT |
1695 | static int __init mcheck_enable(char *str) |
1696 | { | |
e3346fc4 | 1697 | if (*str == 0) { |
4efc0670 | 1698 | enable_p5_mce(); |
e3346fc4 BZ |
1699 | return 1; |
1700 | } | |
4efc0670 AK |
1701 | if (*str == '=') |
1702 | str++; | |
1da177e4 | 1703 | if (!strcmp(str, "off")) |
04b2b1a4 | 1704 | mce_disabled = 1; |
62fdac59 HS |
1705 | else if (!strcmp(str, "no_cmci")) |
1706 | mce_cmci_disabled = 1; | |
1707 | else if (!strcmp(str, "dont_log_ce")) | |
1708 | mce_dont_log_ce = 1; | |
1709 | else if (!strcmp(str, "ignore_ce")) | |
1710 | mce_ignore_ce = 1; | |
13503fa9 HS |
1711 | else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) |
1712 | mce_bootlog = (str[0] == 'b'); | |
3c079792 | 1713 | else if (isdigit(str[0])) { |
8c566ef5 | 1714 | get_option(&str, &tolerant); |
3c079792 AK |
1715 | if (*str == ',') { |
1716 | ++str; | |
1717 | get_option(&str, &monarch_timeout); | |
1718 | } | |
1719 | } else { | |
4efc0670 | 1720 | printk(KERN_INFO "mce argument %s ignored. Please use /sys\n", |
13503fa9 HS |
1721 | str); |
1722 | return 0; | |
1723 | } | |
9b41046c | 1724 | return 1; |
1da177e4 | 1725 | } |
4efc0670 | 1726 | __setup("mce", mcheck_enable); |
1da177e4 | 1727 | |
a2202aa2 | 1728 | int __init mcheck_init(void) |
b33a6363 | 1729 | { |
a2202aa2 YW |
1730 | mcheck_intel_therm_init(); |
1731 | ||
b33a6363 BP |
1732 | return 0; |
1733 | } | |
b33a6363 | 1734 | |
d88203d1 | 1735 | /* |
c7cece89 | 1736 | * mce_syscore: PM support |
d88203d1 | 1737 | */ |
1da177e4 | 1738 | |
973a2dd1 AK |
1739 | /* |
1740 | * Disable machine checks on suspend and shutdown. We can't really handle | |
1741 | * them later. | |
1742 | */ | |
5e09954a | 1743 | static int mce_disable_error_reporting(void) |
973a2dd1 AK |
1744 | { |
1745 | int i; | |
1746 | ||
06b7a7a5 | 1747 | for (i = 0; i < banks; i++) { |
cebe1820 | 1748 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1749 | |
cebe1820 | 1750 | if (b->init) |
a2d32bcb | 1751 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 1752 | } |
973a2dd1 AK |
1753 | return 0; |
1754 | } | |
1755 | ||
c7cece89 | 1756 | static int mce_syscore_suspend(void) |
973a2dd1 | 1757 | { |
5e09954a | 1758 | return mce_disable_error_reporting(); |
973a2dd1 AK |
1759 | } |
1760 | ||
c7cece89 | 1761 | static void mce_syscore_shutdown(void) |
973a2dd1 | 1762 | { |
f3c6ea1b | 1763 | mce_disable_error_reporting(); |
973a2dd1 AK |
1764 | } |
1765 | ||
e9eee03e IM |
1766 | /* |
1767 | * On resume clear all MCE state. Don't want to see leftovers from the BIOS. | |
1768 | * Only one CPU is active at this time, the others get re-added later using | |
1769 | * CPU hotplug: | |
1770 | */ | |
c7cece89 | 1771 | static void mce_syscore_resume(void) |
1da177e4 | 1772 | { |
5e09954a | 1773 | __mcheck_cpu_init_generic(); |
7b543a53 | 1774 | __mcheck_cpu_init_vendor(__this_cpu_ptr(&cpu_info)); |
1da177e4 LT |
1775 | } |
1776 | ||
f3c6ea1b | 1777 | static struct syscore_ops mce_syscore_ops = { |
c7cece89 HS |
1778 | .suspend = mce_syscore_suspend, |
1779 | .shutdown = mce_syscore_shutdown, | |
1780 | .resume = mce_syscore_resume, | |
f3c6ea1b RW |
1781 | }; |
1782 | ||
c7cece89 HS |
1783 | /* |
1784 | * mce_sysdev: Sysfs support | |
1785 | */ | |
1786 | ||
52d168e2 AK |
1787 | static void mce_cpu_restart(void *data) |
1788 | { | |
7b543a53 | 1789 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
33edbf02 | 1790 | return; |
5e09954a BP |
1791 | __mcheck_cpu_init_generic(); |
1792 | __mcheck_cpu_init_timer(); | |
52d168e2 AK |
1793 | } |
1794 | ||
1da177e4 | 1795 | /* Reinit MCEs after user configuration changes */ |
d88203d1 TG |
1796 | static void mce_restart(void) |
1797 | { | |
9aaef96f | 1798 | mce_timer_delete_all(); |
52d168e2 | 1799 | on_each_cpu(mce_cpu_restart, NULL, 1); |
1da177e4 LT |
1800 | } |
1801 | ||
9af43b54 | 1802 | /* Toggle features for corrected errors */ |
9aaef96f | 1803 | static void mce_disable_cmci(void *data) |
9af43b54 | 1804 | { |
7b543a53 | 1805 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
9af43b54 | 1806 | return; |
9af43b54 HS |
1807 | cmci_clear(); |
1808 | } | |
1809 | ||
1810 | static void mce_enable_ce(void *all) | |
1811 | { | |
7b543a53 | 1812 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
9af43b54 HS |
1813 | return; |
1814 | cmci_reenable(); | |
1815 | cmci_recheck(); | |
1816 | if (all) | |
5e09954a | 1817 | __mcheck_cpu_init_timer(); |
9af43b54 HS |
1818 | } |
1819 | ||
c7cece89 | 1820 | static struct sysdev_class mce_sysdev_class = { |
e9eee03e | 1821 | .name = "machinecheck", |
1da177e4 LT |
1822 | }; |
1823 | ||
c7cece89 | 1824 | DEFINE_PER_CPU(struct sys_device, mce_sysdev); |
e9eee03e IM |
1825 | |
1826 | __cpuinitdata | |
1827 | void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); | |
1da177e4 | 1828 | |
cebe1820 AK |
1829 | static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr) |
1830 | { | |
1831 | return container_of(attr, struct mce_bank, attr); | |
1832 | } | |
0d7482e3 AK |
1833 | |
1834 | static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
1835 | char *buf) | |
1836 | { | |
cebe1820 | 1837 | return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl); |
0d7482e3 AK |
1838 | } |
1839 | ||
1840 | static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
9319cec8 | 1841 | const char *buf, size_t size) |
0d7482e3 | 1842 | { |
9319cec8 | 1843 | u64 new; |
e9eee03e | 1844 | |
9319cec8 | 1845 | if (strict_strtoull(buf, 0, &new) < 0) |
0d7482e3 | 1846 | return -EINVAL; |
e9eee03e | 1847 | |
cebe1820 | 1848 | attr_to_bank(attr)->ctl = new; |
0d7482e3 | 1849 | mce_restart(); |
e9eee03e | 1850 | |
9319cec8 | 1851 | return size; |
0d7482e3 | 1852 | } |
a98f0dd3 | 1853 | |
e9eee03e IM |
1854 | static ssize_t |
1855 | show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf) | |
a98f0dd3 | 1856 | { |
1020bcbc | 1857 | strcpy(buf, mce_helper); |
a98f0dd3 | 1858 | strcat(buf, "\n"); |
1020bcbc | 1859 | return strlen(mce_helper) + 1; |
a98f0dd3 AK |
1860 | } |
1861 | ||
4a0b2b4d | 1862 | static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr, |
e9eee03e | 1863 | const char *buf, size_t siz) |
a98f0dd3 AK |
1864 | { |
1865 | char *p; | |
e9eee03e | 1866 | |
1020bcbc HS |
1867 | strncpy(mce_helper, buf, sizeof(mce_helper)); |
1868 | mce_helper[sizeof(mce_helper)-1] = 0; | |
1020bcbc | 1869 | p = strchr(mce_helper, '\n'); |
e9eee03e | 1870 | |
e9084ec9 | 1871 | if (p) |
e9eee03e IM |
1872 | *p = 0; |
1873 | ||
e9084ec9 | 1874 | return strlen(mce_helper) + !!p; |
a98f0dd3 AK |
1875 | } |
1876 | ||
9af43b54 HS |
1877 | static ssize_t set_ignore_ce(struct sys_device *s, |
1878 | struct sysdev_attribute *attr, | |
1879 | const char *buf, size_t size) | |
1880 | { | |
1881 | u64 new; | |
1882 | ||
1883 | if (strict_strtoull(buf, 0, &new) < 0) | |
1884 | return -EINVAL; | |
1885 | ||
1886 | if (mce_ignore_ce ^ !!new) { | |
1887 | if (new) { | |
1888 | /* disable ce features */ | |
9aaef96f HS |
1889 | mce_timer_delete_all(); |
1890 | on_each_cpu(mce_disable_cmci, NULL, 1); | |
9af43b54 HS |
1891 | mce_ignore_ce = 1; |
1892 | } else { | |
1893 | /* enable ce features */ | |
1894 | mce_ignore_ce = 0; | |
1895 | on_each_cpu(mce_enable_ce, (void *)1, 1); | |
1896 | } | |
1897 | } | |
1898 | return size; | |
1899 | } | |
1900 | ||
1901 | static ssize_t set_cmci_disabled(struct sys_device *s, | |
1902 | struct sysdev_attribute *attr, | |
1903 | const char *buf, size_t size) | |
1904 | { | |
1905 | u64 new; | |
1906 | ||
1907 | if (strict_strtoull(buf, 0, &new) < 0) | |
1908 | return -EINVAL; | |
1909 | ||
1910 | if (mce_cmci_disabled ^ !!new) { | |
1911 | if (new) { | |
1912 | /* disable cmci */ | |
9aaef96f | 1913 | on_each_cpu(mce_disable_cmci, NULL, 1); |
9af43b54 HS |
1914 | mce_cmci_disabled = 1; |
1915 | } else { | |
1916 | /* enable cmci */ | |
1917 | mce_cmci_disabled = 0; | |
1918 | on_each_cpu(mce_enable_ce, NULL, 1); | |
1919 | } | |
1920 | } | |
1921 | return size; | |
1922 | } | |
1923 | ||
b56f642d AK |
1924 | static ssize_t store_int_with_restart(struct sys_device *s, |
1925 | struct sysdev_attribute *attr, | |
1926 | const char *buf, size_t size) | |
1927 | { | |
1928 | ssize_t ret = sysdev_store_int(s, attr, buf, size); | |
1929 | mce_restart(); | |
1930 | return ret; | |
1931 | } | |
1932 | ||
a98f0dd3 | 1933 | static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger); |
d95d62c0 | 1934 | static SYSDEV_INT_ATTR(tolerant, 0644, tolerant); |
3c079792 | 1935 | static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout); |
9af43b54 | 1936 | static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce); |
e9eee03e | 1937 | |
b56f642d AK |
1938 | static struct sysdev_ext_attribute attr_check_interval = { |
1939 | _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int, | |
1940 | store_int_with_restart), | |
1941 | &check_interval | |
1942 | }; | |
e9eee03e | 1943 | |
9af43b54 HS |
1944 | static struct sysdev_ext_attribute attr_ignore_ce = { |
1945 | _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce), | |
1946 | &mce_ignore_ce | |
1947 | }; | |
1948 | ||
1949 | static struct sysdev_ext_attribute attr_cmci_disabled = { | |
74b602c7 | 1950 | _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled), |
9af43b54 HS |
1951 | &mce_cmci_disabled |
1952 | }; | |
1953 | ||
c7cece89 | 1954 | static struct sysdev_attribute *mce_sysdev_attrs[] = { |
9af43b54 HS |
1955 | &attr_tolerant.attr, |
1956 | &attr_check_interval.attr, | |
1957 | &attr_trigger, | |
3c079792 | 1958 | &attr_monarch_timeout.attr, |
9af43b54 HS |
1959 | &attr_dont_log_ce.attr, |
1960 | &attr_ignore_ce.attr, | |
1961 | &attr_cmci_disabled.attr, | |
a98f0dd3 AK |
1962 | NULL |
1963 | }; | |
1da177e4 | 1964 | |
c7cece89 | 1965 | static cpumask_var_t mce_sysdev_initialized; |
bae19fe0 | 1966 | |
e9eee03e | 1967 | /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */ |
c7cece89 | 1968 | static __cpuinit int mce_sysdev_create(unsigned int cpu) |
1da177e4 | 1969 | { |
c7cece89 | 1970 | struct sys_device *sysdev = &per_cpu(mce_sysdev, cpu); |
1da177e4 | 1971 | int err; |
b1f49f95 | 1972 | int i, j; |
92cb7612 | 1973 | |
90367556 | 1974 | if (!mce_available(&boot_cpu_data)) |
91c6d400 AK |
1975 | return -EIO; |
1976 | ||
f6783c42 HS |
1977 | memset(&sysdev->kobj, 0, sizeof(struct kobject)); |
1978 | sysdev->id = cpu; | |
c7cece89 | 1979 | sysdev->cls = &mce_sysdev_class; |
91c6d400 | 1980 | |
f6783c42 | 1981 | err = sysdev_register(sysdev); |
d435d862 AM |
1982 | if (err) |
1983 | return err; | |
1984 | ||
c7cece89 HS |
1985 | for (i = 0; mce_sysdev_attrs[i]; i++) { |
1986 | err = sysdev_create_file(sysdev, mce_sysdev_attrs[i]); | |
d435d862 AM |
1987 | if (err) |
1988 | goto error; | |
1989 | } | |
b1f49f95 | 1990 | for (j = 0; j < banks; j++) { |
f6783c42 | 1991 | err = sysdev_create_file(sysdev, &mce_banks[j].attr); |
0d7482e3 AK |
1992 | if (err) |
1993 | goto error2; | |
1994 | } | |
c7cece89 | 1995 | cpumask_set_cpu(cpu, mce_sysdev_initialized); |
91c6d400 | 1996 | |
d435d862 | 1997 | return 0; |
0d7482e3 | 1998 | error2: |
b1f49f95 | 1999 | while (--j >= 0) |
f6783c42 | 2000 | sysdev_remove_file(sysdev, &mce_banks[j].attr); |
d435d862 | 2001 | error: |
cb491fca | 2002 | while (--i >= 0) |
c7cece89 | 2003 | sysdev_remove_file(sysdev, mce_sysdev_attrs[i]); |
cb491fca | 2004 | |
f6783c42 | 2005 | sysdev_unregister(sysdev); |
d435d862 | 2006 | |
91c6d400 AK |
2007 | return err; |
2008 | } | |
2009 | ||
c7cece89 | 2010 | static __cpuinit void mce_sysdev_remove(unsigned int cpu) |
91c6d400 | 2011 | { |
c7cece89 | 2012 | struct sys_device *sysdev = &per_cpu(mce_sysdev, cpu); |
73ca5358 SL |
2013 | int i; |
2014 | ||
c7cece89 | 2015 | if (!cpumask_test_cpu(cpu, mce_sysdev_initialized)) |
bae19fe0 AH |
2016 | return; |
2017 | ||
c7cece89 HS |
2018 | for (i = 0; mce_sysdev_attrs[i]; i++) |
2019 | sysdev_remove_file(sysdev, mce_sysdev_attrs[i]); | |
cb491fca | 2020 | |
0d7482e3 | 2021 | for (i = 0; i < banks; i++) |
f6783c42 | 2022 | sysdev_remove_file(sysdev, &mce_banks[i].attr); |
cb491fca | 2023 | |
f6783c42 | 2024 | sysdev_unregister(sysdev); |
c7cece89 | 2025 | cpumask_clear_cpu(cpu, mce_sysdev_initialized); |
91c6d400 | 2026 | } |
91c6d400 | 2027 | |
d6b75584 | 2028 | /* Make sure there are no machine checks on offlined CPUs. */ |
767df1bd | 2029 | static void __cpuinit mce_disable_cpu(void *h) |
d6b75584 | 2030 | { |
88ccbedd | 2031 | unsigned long action = *(unsigned long *)h; |
cb491fca | 2032 | int i; |
d6b75584 | 2033 | |
7b543a53 | 2034 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
d6b75584 | 2035 | return; |
767df1bd | 2036 | |
88ccbedd AK |
2037 | if (!(action & CPU_TASKS_FROZEN)) |
2038 | cmci_clear(); | |
06b7a7a5 | 2039 | for (i = 0; i < banks; i++) { |
cebe1820 | 2040 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2041 | |
cebe1820 | 2042 | if (b->init) |
a2d32bcb | 2043 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 2044 | } |
d6b75584 AK |
2045 | } |
2046 | ||
767df1bd | 2047 | static void __cpuinit mce_reenable_cpu(void *h) |
d6b75584 | 2048 | { |
88ccbedd | 2049 | unsigned long action = *(unsigned long *)h; |
e9eee03e | 2050 | int i; |
d6b75584 | 2051 | |
7b543a53 | 2052 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
d6b75584 | 2053 | return; |
e9eee03e | 2054 | |
88ccbedd AK |
2055 | if (!(action & CPU_TASKS_FROZEN)) |
2056 | cmci_reenable(); | |
06b7a7a5 | 2057 | for (i = 0; i < banks; i++) { |
cebe1820 | 2058 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2059 | |
cebe1820 | 2060 | if (b->init) |
a2d32bcb | 2061 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
06b7a7a5 | 2062 | } |
d6b75584 AK |
2063 | } |
2064 | ||
91c6d400 | 2065 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ |
e9eee03e IM |
2066 | static int __cpuinit |
2067 | mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) | |
91c6d400 AK |
2068 | { |
2069 | unsigned int cpu = (unsigned long)hcpu; | |
52d168e2 | 2070 | struct timer_list *t = &per_cpu(mce_timer, cpu); |
91c6d400 AK |
2071 | |
2072 | switch (action) { | |
bae19fe0 AH |
2073 | case CPU_ONLINE: |
2074 | case CPU_ONLINE_FROZEN: | |
c7cece89 | 2075 | mce_sysdev_create(cpu); |
8735728e RW |
2076 | if (threshold_cpu_callback) |
2077 | threshold_cpu_callback(action, cpu); | |
91c6d400 | 2078 | break; |
91c6d400 | 2079 | case CPU_DEAD: |
8bb78442 | 2080 | case CPU_DEAD_FROZEN: |
8735728e RW |
2081 | if (threshold_cpu_callback) |
2082 | threshold_cpu_callback(action, cpu); | |
c7cece89 | 2083 | mce_sysdev_remove(cpu); |
91c6d400 | 2084 | break; |
52d168e2 AK |
2085 | case CPU_DOWN_PREPARE: |
2086 | case CPU_DOWN_PREPARE_FROZEN: | |
2087 | del_timer_sync(t); | |
88ccbedd | 2088 | smp_call_function_single(cpu, mce_disable_cpu, &action, 1); |
52d168e2 AK |
2089 | break; |
2090 | case CPU_DOWN_FAILED: | |
2091 | case CPU_DOWN_FAILED_FROZEN: | |
fe5ed91d HS |
2092 | if (!mce_ignore_ce && check_interval) { |
2093 | t->expires = round_jiffies(jiffies + | |
245b2e70 | 2094 | __get_cpu_var(mce_next_interval)); |
fe5ed91d HS |
2095 | add_timer_on(t, cpu); |
2096 | } | |
88ccbedd AK |
2097 | smp_call_function_single(cpu, mce_reenable_cpu, &action, 1); |
2098 | break; | |
2099 | case CPU_POST_DEAD: | |
2100 | /* intentionally ignoring frozen here */ | |
2101 | cmci_rediscover(cpu); | |
52d168e2 | 2102 | break; |
91c6d400 | 2103 | } |
bae19fe0 | 2104 | return NOTIFY_OK; |
91c6d400 AK |
2105 | } |
2106 | ||
1e35669d | 2107 | static struct notifier_block mce_cpu_notifier __cpuinitdata = { |
91c6d400 AK |
2108 | .notifier_call = mce_cpu_callback, |
2109 | }; | |
2110 | ||
cebe1820 | 2111 | static __init void mce_init_banks(void) |
0d7482e3 AK |
2112 | { |
2113 | int i; | |
2114 | ||
0d7482e3 | 2115 | for (i = 0; i < banks; i++) { |
cebe1820 AK |
2116 | struct mce_bank *b = &mce_banks[i]; |
2117 | struct sysdev_attribute *a = &b->attr; | |
e9eee03e | 2118 | |
a07e4156 | 2119 | sysfs_attr_init(&a->attr); |
cebe1820 AK |
2120 | a->attr.name = b->attrname; |
2121 | snprintf(b->attrname, ATTR_LEN, "bank%d", i); | |
e9eee03e IM |
2122 | |
2123 | a->attr.mode = 0644; | |
2124 | a->show = show_bank; | |
2125 | a->store = set_bank; | |
0d7482e3 | 2126 | } |
0d7482e3 AK |
2127 | } |
2128 | ||
5e09954a | 2129 | static __init int mcheck_init_device(void) |
91c6d400 AK |
2130 | { |
2131 | int err; | |
2132 | int i = 0; | |
2133 | ||
1da177e4 LT |
2134 | if (!mce_available(&boot_cpu_data)) |
2135 | return -EIO; | |
0d7482e3 | 2136 | |
c7cece89 | 2137 | zalloc_cpumask_var(&mce_sysdev_initialized, GFP_KERNEL); |
996867d0 | 2138 | |
cebe1820 | 2139 | mce_init_banks(); |
0d7482e3 | 2140 | |
c7cece89 | 2141 | err = sysdev_class_register(&mce_sysdev_class); |
d435d862 AM |
2142 | if (err) |
2143 | return err; | |
91c6d400 AK |
2144 | |
2145 | for_each_online_cpu(i) { | |
c7cece89 | 2146 | err = mce_sysdev_create(i); |
d435d862 AM |
2147 | if (err) |
2148 | return err; | |
91c6d400 AK |
2149 | } |
2150 | ||
f3c6ea1b | 2151 | register_syscore_ops(&mce_syscore_ops); |
be6b5a35 | 2152 | register_hotcpu_notifier(&mce_cpu_notifier); |
93b62c3c HS |
2153 | |
2154 | /* register character device /dev/mcelog */ | |
2155 | misc_register(&mce_chrdev_device); | |
e9eee03e | 2156 | |
1da177e4 | 2157 | return err; |
1da177e4 | 2158 | } |
5e09954a | 2159 | device_initcall(mcheck_init_device); |
a988d334 | 2160 | |
d7c3c9a6 AK |
2161 | /* |
2162 | * Old style boot options parsing. Only for compatibility. | |
2163 | */ | |
2164 | static int __init mcheck_disable(char *str) | |
2165 | { | |
2166 | mce_disabled = 1; | |
2167 | return 1; | |
2168 | } | |
2169 | __setup("nomce", mcheck_disable); | |
a988d334 | 2170 | |
5be9ed25 HY |
2171 | #ifdef CONFIG_DEBUG_FS |
2172 | struct dentry *mce_get_debugfs_dir(void) | |
a988d334 | 2173 | { |
5be9ed25 | 2174 | static struct dentry *dmce; |
a988d334 | 2175 | |
5be9ed25 HY |
2176 | if (!dmce) |
2177 | dmce = debugfs_create_dir("mce", NULL); | |
a988d334 | 2178 | |
5be9ed25 HY |
2179 | return dmce; |
2180 | } | |
a988d334 | 2181 | |
bf783f9f HY |
2182 | static void mce_reset(void) |
2183 | { | |
2184 | cpu_missing = 0; | |
2185 | atomic_set(&mce_fake_paniced, 0); | |
2186 | atomic_set(&mce_executing, 0); | |
2187 | atomic_set(&mce_callin, 0); | |
2188 | atomic_set(&global_nwo, 0); | |
2189 | } | |
a988d334 | 2190 | |
bf783f9f HY |
2191 | static int fake_panic_get(void *data, u64 *val) |
2192 | { | |
2193 | *val = fake_panic; | |
2194 | return 0; | |
a988d334 IM |
2195 | } |
2196 | ||
bf783f9f | 2197 | static int fake_panic_set(void *data, u64 val) |
a988d334 | 2198 | { |
bf783f9f HY |
2199 | mce_reset(); |
2200 | fake_panic = val; | |
2201 | return 0; | |
a988d334 | 2202 | } |
a988d334 | 2203 | |
bf783f9f HY |
2204 | DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get, |
2205 | fake_panic_set, "%llu\n"); | |
d7c3c9a6 | 2206 | |
5e09954a | 2207 | static int __init mcheck_debugfs_init(void) |
d7c3c9a6 | 2208 | { |
bf783f9f HY |
2209 | struct dentry *dmce, *ffake_panic; |
2210 | ||
2211 | dmce = mce_get_debugfs_dir(); | |
2212 | if (!dmce) | |
2213 | return -ENOMEM; | |
2214 | ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL, | |
2215 | &fake_panic_fops); | |
2216 | if (!ffake_panic) | |
2217 | return -ENOMEM; | |
2218 | ||
2219 | return 0; | |
d7c3c9a6 | 2220 | } |
5e09954a | 2221 | late_initcall(mcheck_debugfs_init); |
5be9ed25 | 2222 | #endif |