Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Machine check handler. | |
e9eee03e | 3 | * |
1da177e4 | 4 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. |
d88203d1 TG |
5 | * Rest from unknown author(s). |
6 | * 2004 Andi Kleen. Rewrote most of it. | |
b79109c3 AK |
7 | * Copyright 2008 Intel Corporation |
8 | * Author: Andi Kleen | |
1da177e4 | 9 | */ |
e9eee03e IM |
10 | #include <linux/thread_info.h> |
11 | #include <linux/capability.h> | |
12 | #include <linux/miscdevice.h> | |
13 | #include <linux/ratelimit.h> | |
14 | #include <linux/kallsyms.h> | |
15 | #include <linux/rcupdate.h> | |
e9eee03e | 16 | #include <linux/kobject.h> |
14a02530 | 17 | #include <linux/uaccess.h> |
e9eee03e IM |
18 | #include <linux/kdebug.h> |
19 | #include <linux/kernel.h> | |
20 | #include <linux/percpu.h> | |
1da177e4 | 21 | #include <linux/string.h> |
8a25a2fd | 22 | #include <linux/device.h> |
f3c6ea1b | 23 | #include <linux/syscore_ops.h> |
3c079792 | 24 | #include <linux/delay.h> |
8c566ef5 | 25 | #include <linux/ctype.h> |
e9eee03e | 26 | #include <linux/sched.h> |
0d7482e3 | 27 | #include <linux/sysfs.h> |
e9eee03e | 28 | #include <linux/types.h> |
5a0e3ad6 | 29 | #include <linux/slab.h> |
e9eee03e IM |
30 | #include <linux/init.h> |
31 | #include <linux/kmod.h> | |
32 | #include <linux/poll.h> | |
3c079792 | 33 | #include <linux/nmi.h> |
e9eee03e | 34 | #include <linux/cpu.h> |
14a02530 | 35 | #include <linux/smp.h> |
e9eee03e | 36 | #include <linux/fs.h> |
9b1beaf2 | 37 | #include <linux/mm.h> |
5be9ed25 | 38 | #include <linux/debugfs.h> |
b77e70bf | 39 | #include <linux/irq_work.h> |
69c60c88 | 40 | #include <linux/export.h> |
e9eee03e | 41 | |
d88203d1 | 42 | #include <asm/processor.h> |
e9eee03e IM |
43 | #include <asm/mce.h> |
44 | #include <asm/msr.h> | |
1da177e4 | 45 | |
bd19a5e6 | 46 | #include "mce-internal.h" |
711c2e48 | 47 | |
93b62c3c | 48 | static DEFINE_MUTEX(mce_chrdev_read_mutex); |
2aa2b50d | 49 | |
f56e8a07 | 50 | #define rcu_dereference_check_mce(p) \ |
ec8c27e0 | 51 | rcu_dereference_index_check((p), \ |
f56e8a07 | 52 | rcu_read_lock_sched_held() || \ |
93b62c3c | 53 | lockdep_is_held(&mce_chrdev_read_mutex)) |
f56e8a07 | 54 | |
8968f9d3 HS |
55 | #define CREATE_TRACE_POINTS |
56 | #include <trace/events/mce.h> | |
57 | ||
4e5b3e69 | 58 | int mce_disabled __read_mostly; |
04b2b1a4 | 59 | |
e9eee03e | 60 | #define MISC_MCELOG_MINOR 227 |
0d7482e3 | 61 | |
3c079792 AK |
62 | #define SPINUNIT 100 /* 100ns */ |
63 | ||
553f265f AK |
64 | atomic_t mce_entry; |
65 | ||
01ca79f1 AK |
66 | DEFINE_PER_CPU(unsigned, mce_exception_count); |
67 | ||
bd78432c TH |
68 | /* |
69 | * Tolerant levels: | |
70 | * 0: always panic on uncorrected errors, log corrected errors | |
71 | * 1: panic or SIGBUS on uncorrected errors, log corrected errors | |
72 | * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors | |
73 | * 3: never panic or SIGBUS, log all errors (for testing only) | |
74 | */ | |
4e5b3e69 HS |
75 | static int tolerant __read_mostly = 1; |
76 | static int banks __read_mostly; | |
4e5b3e69 HS |
77 | static int rip_msr __read_mostly; |
78 | static int mce_bootlog __read_mostly = -1; | |
79 | static int monarch_timeout __read_mostly = -1; | |
80 | static int mce_panic_timeout __read_mostly; | |
81 | static int mce_dont_log_ce __read_mostly; | |
82 | int mce_cmci_disabled __read_mostly; | |
83 | int mce_ignore_ce __read_mostly; | |
84 | int mce_ser __read_mostly; | |
a98f0dd3 | 85 | |
cebe1820 AK |
86 | struct mce_bank *mce_banks __read_mostly; |
87 | ||
1020bcbc HS |
88 | /* User mode helper program triggered by machine check event */ |
89 | static unsigned long mce_need_notify; | |
90 | static char mce_helper[128]; | |
91 | static char *mce_helper_argv[2] = { mce_helper, NULL }; | |
1da177e4 | 92 | |
93b62c3c HS |
93 | static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait); |
94 | ||
3c079792 AK |
95 | static DEFINE_PER_CPU(struct mce, mces_seen); |
96 | static int cpu_missing; | |
97 | ||
ee031c31 AK |
98 | /* MCA banks polled by the period polling timer for corrected events */ |
99 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { | |
100 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL | |
101 | }; | |
102 | ||
9b1beaf2 AK |
103 | static DEFINE_PER_CPU(struct work_struct, mce_work); |
104 | ||
3653ada5 BP |
105 | /* |
106 | * CPU/chipset specific EDAC code can register a notifier call here to print | |
107 | * MCE errors in a human-readable form. | |
108 | */ | |
109 | ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain); | |
110 | ||
b5f2fa4e AK |
111 | /* Do initial initialization of a struct mce */ |
112 | void mce_setup(struct mce *m) | |
113 | { | |
114 | memset(m, 0, sizeof(struct mce)); | |
d620c67f | 115 | m->cpu = m->extcpu = smp_processor_id(); |
b5f2fa4e | 116 | rdtscll(m->tsc); |
8ee08347 AK |
117 | /* We hope get_seconds stays lockless */ |
118 | m->time = get_seconds(); | |
119 | m->cpuvendor = boot_cpu_data.x86_vendor; | |
120 | m->cpuid = cpuid_eax(1); | |
8ee08347 | 121 | m->socketid = cpu_data(m->extcpu).phys_proc_id; |
8ee08347 AK |
122 | m->apicid = cpu_data(m->extcpu).initial_apicid; |
123 | rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap); | |
b5f2fa4e AK |
124 | } |
125 | ||
ea149b36 AK |
126 | DEFINE_PER_CPU(struct mce, injectm); |
127 | EXPORT_PER_CPU_SYMBOL_GPL(injectm); | |
128 | ||
1da177e4 LT |
129 | /* |
130 | * Lockless MCE logging infrastructure. | |
131 | * This avoids deadlocks on printk locks without having to break locks. Also | |
132 | * separate MCEs from kernel messages to avoid bogus bug reports. | |
133 | */ | |
134 | ||
231fd906 | 135 | static struct mce_log mcelog = { |
f6fb0ac0 AK |
136 | .signature = MCE_LOG_SIGNATURE, |
137 | .len = MCE_LOG_LEN, | |
138 | .recordlen = sizeof(struct mce), | |
d88203d1 | 139 | }; |
1da177e4 LT |
140 | |
141 | void mce_log(struct mce *mce) | |
142 | { | |
143 | unsigned next, entry; | |
f0cb5452 | 144 | int ret = 0; |
e9eee03e | 145 | |
8968f9d3 HS |
146 | /* Emit the trace record: */ |
147 | trace_mce_record(mce); | |
148 | ||
f0cb5452 BP |
149 | ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, mce); |
150 | if (ret == NOTIFY_STOP) | |
151 | return; | |
152 | ||
1da177e4 | 153 | mce->finished = 0; |
7644143c | 154 | wmb(); |
1da177e4 | 155 | for (;;) { |
f56e8a07 | 156 | entry = rcu_dereference_check_mce(mcelog.next); |
673242c1 | 157 | for (;;) { |
696e409d | 158 | |
e9eee03e IM |
159 | /* |
160 | * When the buffer fills up discard new entries. | |
161 | * Assume that the earlier errors are the more | |
162 | * interesting ones: | |
163 | */ | |
673242c1 | 164 | if (entry >= MCE_LOG_LEN) { |
14a02530 HS |
165 | set_bit(MCE_OVERFLOW, |
166 | (unsigned long *)&mcelog.flags); | |
673242c1 AK |
167 | return; |
168 | } | |
e9eee03e | 169 | /* Old left over entry. Skip: */ |
673242c1 AK |
170 | if (mcelog.entry[entry].finished) { |
171 | entry++; | |
172 | continue; | |
173 | } | |
7644143c | 174 | break; |
1da177e4 | 175 | } |
1da177e4 LT |
176 | smp_rmb(); |
177 | next = entry + 1; | |
178 | if (cmpxchg(&mcelog.next, entry, next) == entry) | |
179 | break; | |
180 | } | |
181 | memcpy(mcelog.entry + entry, mce, sizeof(struct mce)); | |
7644143c | 182 | wmb(); |
1da177e4 | 183 | mcelog.entry[entry].finished = 1; |
7644143c | 184 | wmb(); |
1da177e4 | 185 | |
a0189c70 | 186 | mce->finished = 1; |
1020bcbc | 187 | set_bit(0, &mce_need_notify); |
1da177e4 LT |
188 | } |
189 | ||
09371957 BP |
190 | static void drain_mcelog_buffer(void) |
191 | { | |
192 | unsigned int next, i, prev = 0; | |
193 | ||
194 | next = rcu_dereference_check_mce(mcelog.next); | |
195 | ||
196 | do { | |
197 | struct mce *m; | |
198 | ||
199 | /* drain what was logged during boot */ | |
200 | for (i = prev; i < next; i++) { | |
201 | unsigned long start = jiffies; | |
202 | unsigned retries = 1; | |
203 | ||
204 | m = &mcelog.entry[i]; | |
205 | ||
206 | while (!m->finished) { | |
207 | if (time_after_eq(jiffies, start + 2*retries)) | |
208 | retries++; | |
209 | ||
210 | cpu_relax(); | |
211 | ||
212 | if (!m->finished && retries >= 4) { | |
213 | pr_err("MCE: skipping error being logged currently!\n"); | |
214 | break; | |
215 | } | |
216 | } | |
217 | smp_rmb(); | |
218 | atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m); | |
219 | } | |
220 | ||
221 | memset(mcelog.entry + prev, 0, (next - prev) * sizeof(*m)); | |
222 | prev = next; | |
223 | next = cmpxchg(&mcelog.next, prev, 0); | |
224 | } while (next != prev); | |
225 | } | |
226 | ||
227 | ||
3653ada5 BP |
228 | void mce_register_decode_chain(struct notifier_block *nb) |
229 | { | |
230 | atomic_notifier_chain_register(&x86_mce_decoder_chain, nb); | |
09371957 | 231 | drain_mcelog_buffer(); |
3653ada5 BP |
232 | } |
233 | EXPORT_SYMBOL_GPL(mce_register_decode_chain); | |
234 | ||
235 | void mce_unregister_decode_chain(struct notifier_block *nb) | |
236 | { | |
237 | atomic_notifier_chain_unregister(&x86_mce_decoder_chain, nb); | |
238 | } | |
239 | EXPORT_SYMBOL_GPL(mce_unregister_decode_chain); | |
240 | ||
77e26cca | 241 | static void print_mce(struct mce *m) |
1da177e4 | 242 | { |
dffa4b2f BP |
243 | int ret = 0; |
244 | ||
a2d7b0d4 | 245 | pr_emerg(HW_ERR "CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n", |
d620c67f | 246 | m->extcpu, m->mcgstatus, m->bank, m->status); |
f436f8bb | 247 | |
65ea5b03 | 248 | if (m->ip) { |
a2d7b0d4 | 249 | pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ", |
f436f8bb IM |
250 | !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", |
251 | m->cs, m->ip); | |
252 | ||
1da177e4 | 253 | if (m->cs == __KERNEL_CS) |
65ea5b03 | 254 | print_symbol("{%s}", m->ip); |
f436f8bb | 255 | pr_cont("\n"); |
1da177e4 | 256 | } |
f436f8bb | 257 | |
a2d7b0d4 | 258 | pr_emerg(HW_ERR "TSC %llx ", m->tsc); |
1da177e4 | 259 | if (m->addr) |
f436f8bb | 260 | pr_cont("ADDR %llx ", m->addr); |
1da177e4 | 261 | if (m->misc) |
f436f8bb | 262 | pr_cont("MISC %llx ", m->misc); |
549d042d | 263 | |
f436f8bb | 264 | pr_cont("\n"); |
506ed6b5 AK |
265 | /* |
266 | * Note this output is parsed by external tools and old fields | |
267 | * should not be changed. | |
268 | */ | |
881e23e5 | 269 | pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n", |
506ed6b5 AK |
270 | m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid, |
271 | cpu_data(m->extcpu).microcode); | |
f436f8bb IM |
272 | |
273 | /* | |
274 | * Print out human-readable details about the MCE error, | |
fb253195 | 275 | * (if the CPU has an implementation for that) |
f436f8bb | 276 | */ |
dffa4b2f BP |
277 | ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m); |
278 | if (ret == NOTIFY_STOP) | |
279 | return; | |
280 | ||
281 | pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n"); | |
86503560 AK |
282 | } |
283 | ||
f94b61c2 AK |
284 | #define PANIC_TIMEOUT 5 /* 5 seconds */ |
285 | ||
286 | static atomic_t mce_paniced; | |
287 | ||
bf783f9f HY |
288 | static int fake_panic; |
289 | static atomic_t mce_fake_paniced; | |
290 | ||
f94b61c2 AK |
291 | /* Panic in progress. Enable interrupts and wait for final IPI */ |
292 | static void wait_for_panic(void) | |
293 | { | |
294 | long timeout = PANIC_TIMEOUT*USEC_PER_SEC; | |
f436f8bb | 295 | |
f94b61c2 AK |
296 | preempt_disable(); |
297 | local_irq_enable(); | |
298 | while (timeout-- > 0) | |
299 | udelay(1); | |
29b0f591 AK |
300 | if (panic_timeout == 0) |
301 | panic_timeout = mce_panic_timeout; | |
f94b61c2 AK |
302 | panic("Panicing machine check CPU died"); |
303 | } | |
304 | ||
bd19a5e6 | 305 | static void mce_panic(char *msg, struct mce *final, char *exp) |
d88203d1 | 306 | { |
482908b4 | 307 | int i, apei_err = 0; |
e02e68d3 | 308 | |
bf783f9f HY |
309 | if (!fake_panic) { |
310 | /* | |
311 | * Make sure only one CPU runs in machine check panic | |
312 | */ | |
313 | if (atomic_inc_return(&mce_paniced) > 1) | |
314 | wait_for_panic(); | |
315 | barrier(); | |
f94b61c2 | 316 | |
bf783f9f HY |
317 | bust_spinlocks(1); |
318 | console_verbose(); | |
319 | } else { | |
320 | /* Don't log too much for fake panic */ | |
321 | if (atomic_inc_return(&mce_fake_paniced) > 1) | |
322 | return; | |
323 | } | |
a0189c70 | 324 | /* First print corrected ones that are still unlogged */ |
1da177e4 | 325 | for (i = 0; i < MCE_LOG_LEN; i++) { |
a0189c70 | 326 | struct mce *m = &mcelog.entry[i]; |
77e26cca HS |
327 | if (!(m->status & MCI_STATUS_VAL)) |
328 | continue; | |
482908b4 | 329 | if (!(m->status & MCI_STATUS_UC)) { |
77e26cca | 330 | print_mce(m); |
482908b4 HY |
331 | if (!apei_err) |
332 | apei_err = apei_write_mce(m); | |
333 | } | |
a0189c70 AK |
334 | } |
335 | /* Now print uncorrected but with the final one last */ | |
336 | for (i = 0; i < MCE_LOG_LEN; i++) { | |
337 | struct mce *m = &mcelog.entry[i]; | |
338 | if (!(m->status & MCI_STATUS_VAL)) | |
1da177e4 | 339 | continue; |
77e26cca HS |
340 | if (!(m->status & MCI_STATUS_UC)) |
341 | continue; | |
482908b4 | 342 | if (!final || memcmp(m, final, sizeof(struct mce))) { |
77e26cca | 343 | print_mce(m); |
482908b4 HY |
344 | if (!apei_err) |
345 | apei_err = apei_write_mce(m); | |
346 | } | |
1da177e4 | 347 | } |
482908b4 | 348 | if (final) { |
77e26cca | 349 | print_mce(final); |
482908b4 HY |
350 | if (!apei_err) |
351 | apei_err = apei_write_mce(final); | |
352 | } | |
3c079792 | 353 | if (cpu_missing) |
a2d7b0d4 | 354 | pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n"); |
bd19a5e6 | 355 | if (exp) |
a2d7b0d4 | 356 | pr_emerg(HW_ERR "Machine check: %s\n", exp); |
bf783f9f HY |
357 | if (!fake_panic) { |
358 | if (panic_timeout == 0) | |
359 | panic_timeout = mce_panic_timeout; | |
360 | panic(msg); | |
361 | } else | |
a2d7b0d4 | 362 | pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg); |
d88203d1 | 363 | } |
1da177e4 | 364 | |
ea149b36 AK |
365 | /* Support code for software error injection */ |
366 | ||
367 | static int msr_to_offset(u32 msr) | |
368 | { | |
0a3aee0d | 369 | unsigned bank = __this_cpu_read(injectm.bank); |
f436f8bb | 370 | |
ea149b36 AK |
371 | if (msr == rip_msr) |
372 | return offsetof(struct mce, ip); | |
a2d32bcb | 373 | if (msr == MSR_IA32_MCx_STATUS(bank)) |
ea149b36 | 374 | return offsetof(struct mce, status); |
a2d32bcb | 375 | if (msr == MSR_IA32_MCx_ADDR(bank)) |
ea149b36 | 376 | return offsetof(struct mce, addr); |
a2d32bcb | 377 | if (msr == MSR_IA32_MCx_MISC(bank)) |
ea149b36 AK |
378 | return offsetof(struct mce, misc); |
379 | if (msr == MSR_IA32_MCG_STATUS) | |
380 | return offsetof(struct mce, mcgstatus); | |
381 | return -1; | |
382 | } | |
383 | ||
5f8c1a54 AK |
384 | /* MSR access wrappers used for error injection */ |
385 | static u64 mce_rdmsrl(u32 msr) | |
386 | { | |
387 | u64 v; | |
11868a2d | 388 | |
0a3aee0d | 389 | if (__this_cpu_read(injectm.finished)) { |
ea149b36 | 390 | int offset = msr_to_offset(msr); |
11868a2d | 391 | |
ea149b36 AK |
392 | if (offset < 0) |
393 | return 0; | |
394 | return *(u64 *)((char *)&__get_cpu_var(injectm) + offset); | |
395 | } | |
11868a2d IM |
396 | |
397 | if (rdmsrl_safe(msr, &v)) { | |
398 | WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr); | |
399 | /* | |
400 | * Return zero in case the access faulted. This should | |
401 | * not happen normally but can happen if the CPU does | |
402 | * something weird, or if the code is buggy. | |
403 | */ | |
404 | v = 0; | |
405 | } | |
406 | ||
5f8c1a54 AK |
407 | return v; |
408 | } | |
409 | ||
410 | static void mce_wrmsrl(u32 msr, u64 v) | |
411 | { | |
0a3aee0d | 412 | if (__this_cpu_read(injectm.finished)) { |
ea149b36 | 413 | int offset = msr_to_offset(msr); |
11868a2d | 414 | |
ea149b36 AK |
415 | if (offset >= 0) |
416 | *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v; | |
417 | return; | |
418 | } | |
5f8c1a54 AK |
419 | wrmsrl(msr, v); |
420 | } | |
421 | ||
b8325c5b HS |
422 | /* |
423 | * Collect all global (w.r.t. this processor) status about this machine | |
424 | * check into our "mce" struct so that we can use it later to assess | |
425 | * the severity of the problem as we read per-bank specific details. | |
426 | */ | |
427 | static inline void mce_gather_info(struct mce *m, struct pt_regs *regs) | |
428 | { | |
429 | mce_setup(m); | |
430 | ||
431 | m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); | |
432 | if (regs) { | |
433 | /* | |
434 | * Get the address of the instruction at the time of | |
435 | * the machine check error. | |
436 | */ | |
437 | if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) { | |
438 | m->ip = regs->ip; | |
439 | m->cs = regs->cs; | |
440 | } | |
441 | /* Use accurate RIP reporting if available. */ | |
442 | if (rip_msr) | |
443 | m->ip = mce_rdmsrl(rip_msr); | |
444 | } | |
445 | } | |
446 | ||
9b1beaf2 AK |
447 | /* |
448 | * Simple lockless ring to communicate PFNs from the exception handler with the | |
449 | * process context work function. This is vastly simplified because there's | |
450 | * only a single reader and a single writer. | |
451 | */ | |
452 | #define MCE_RING_SIZE 16 /* we use one entry less */ | |
453 | ||
454 | struct mce_ring { | |
455 | unsigned short start; | |
456 | unsigned short end; | |
457 | unsigned long ring[MCE_RING_SIZE]; | |
458 | }; | |
459 | static DEFINE_PER_CPU(struct mce_ring, mce_ring); | |
460 | ||
461 | /* Runs with CPU affinity in workqueue */ | |
462 | static int mce_ring_empty(void) | |
463 | { | |
464 | struct mce_ring *r = &__get_cpu_var(mce_ring); | |
465 | ||
466 | return r->start == r->end; | |
467 | } | |
468 | ||
469 | static int mce_ring_get(unsigned long *pfn) | |
470 | { | |
471 | struct mce_ring *r; | |
472 | int ret = 0; | |
473 | ||
474 | *pfn = 0; | |
475 | get_cpu(); | |
476 | r = &__get_cpu_var(mce_ring); | |
477 | if (r->start == r->end) | |
478 | goto out; | |
479 | *pfn = r->ring[r->start]; | |
480 | r->start = (r->start + 1) % MCE_RING_SIZE; | |
481 | ret = 1; | |
482 | out: | |
483 | put_cpu(); | |
484 | return ret; | |
485 | } | |
486 | ||
487 | /* Always runs in MCE context with preempt off */ | |
488 | static int mce_ring_add(unsigned long pfn) | |
489 | { | |
490 | struct mce_ring *r = &__get_cpu_var(mce_ring); | |
491 | unsigned next; | |
492 | ||
493 | next = (r->end + 1) % MCE_RING_SIZE; | |
494 | if (next == r->start) | |
495 | return -1; | |
496 | r->ring[r->end] = pfn; | |
497 | wmb(); | |
498 | r->end = next; | |
499 | return 0; | |
500 | } | |
501 | ||
88ccbedd | 502 | int mce_available(struct cpuinfo_x86 *c) |
1da177e4 | 503 | { |
04b2b1a4 | 504 | if (mce_disabled) |
5b4408fd | 505 | return 0; |
3d1712c9 | 506 | return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); |
1da177e4 LT |
507 | } |
508 | ||
9b1beaf2 AK |
509 | static void mce_schedule_work(void) |
510 | { | |
511 | if (!mce_ring_empty()) { | |
512 | struct work_struct *work = &__get_cpu_var(mce_work); | |
513 | if (!work_pending(work)) | |
514 | schedule_work(work); | |
515 | } | |
516 | } | |
517 | ||
b77e70bf HS |
518 | DEFINE_PER_CPU(struct irq_work, mce_irq_work); |
519 | ||
520 | static void mce_irq_work_cb(struct irq_work *entry) | |
ccc3c319 | 521 | { |
9ff36ee9 | 522 | mce_notify_irq(); |
9b1beaf2 | 523 | mce_schedule_work(); |
ccc3c319 | 524 | } |
ccc3c319 AK |
525 | |
526 | static void mce_report_event(struct pt_regs *regs) | |
527 | { | |
528 | if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) { | |
9ff36ee9 | 529 | mce_notify_irq(); |
9b1beaf2 AK |
530 | /* |
531 | * Triggering the work queue here is just an insurance | |
532 | * policy in case the syscall exit notify handler | |
533 | * doesn't run soon enough or ends up running on the | |
534 | * wrong CPU (can happen when audit sleeps) | |
535 | */ | |
536 | mce_schedule_work(); | |
ccc3c319 AK |
537 | return; |
538 | } | |
539 | ||
b77e70bf | 540 | irq_work_queue(&__get_cpu_var(mce_irq_work)); |
ccc3c319 AK |
541 | } |
542 | ||
ca84f696 AK |
543 | DEFINE_PER_CPU(unsigned, mce_poll_count); |
544 | ||
d88203d1 | 545 | /* |
b79109c3 AK |
546 | * Poll for corrected events or events that happened before reset. |
547 | * Those are just logged through /dev/mcelog. | |
548 | * | |
549 | * This is executed in standard interrupt context. | |
ed7290d0 AK |
550 | * |
551 | * Note: spec recommends to panic for fatal unsignalled | |
552 | * errors here. However this would be quite problematic -- | |
553 | * we would need to reimplement the Monarch handling and | |
554 | * it would mess up the exclusion between exception handler | |
555 | * and poll hander -- * so we skip this for now. | |
556 | * These cases should not happen anyways, or only when the CPU | |
557 | * is already totally * confused. In this case it's likely it will | |
558 | * not fully execute the machine check handler either. | |
b79109c3 | 559 | */ |
ee031c31 | 560 | void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) |
b79109c3 AK |
561 | { |
562 | struct mce m; | |
563 | int i; | |
564 | ||
402af0d7 | 565 | percpu_inc(mce_poll_count); |
ca84f696 | 566 | |
b8325c5b | 567 | mce_gather_info(&m, NULL); |
b79109c3 | 568 | |
b79109c3 | 569 | for (i = 0; i < banks; i++) { |
cebe1820 | 570 | if (!mce_banks[i].ctl || !test_bit(i, *b)) |
b79109c3 AK |
571 | continue; |
572 | ||
573 | m.misc = 0; | |
574 | m.addr = 0; | |
575 | m.bank = i; | |
576 | m.tsc = 0; | |
577 | ||
578 | barrier(); | |
a2d32bcb | 579 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
b79109c3 AK |
580 | if (!(m.status & MCI_STATUS_VAL)) |
581 | continue; | |
582 | ||
583 | /* | |
ed7290d0 AK |
584 | * Uncorrected or signalled events are handled by the exception |
585 | * handler when it is enabled, so don't process those here. | |
b79109c3 AK |
586 | * |
587 | * TBD do the same check for MCI_STATUS_EN here? | |
588 | */ | |
ed7290d0 AK |
589 | if (!(flags & MCP_UC) && |
590 | (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC))) | |
b79109c3 AK |
591 | continue; |
592 | ||
593 | if (m.status & MCI_STATUS_MISCV) | |
a2d32bcb | 594 | m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i)); |
b79109c3 | 595 | if (m.status & MCI_STATUS_ADDRV) |
a2d32bcb | 596 | m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i)); |
b79109c3 AK |
597 | |
598 | if (!(flags & MCP_TIMESTAMP)) | |
599 | m.tsc = 0; | |
600 | /* | |
601 | * Don't get the IP here because it's unlikely to | |
602 | * have anything to do with the actual error location. | |
603 | */ | |
f0cb5452 | 604 | if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) |
5679af4c | 605 | mce_log(&m); |
b79109c3 AK |
606 | |
607 | /* | |
608 | * Clear state for this bank. | |
609 | */ | |
a2d32bcb | 610 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
b79109c3 AK |
611 | } |
612 | ||
613 | /* | |
614 | * Don't clear MCG_STATUS here because it's only defined for | |
615 | * exceptions. | |
616 | */ | |
88921be3 AK |
617 | |
618 | sync_core(); | |
b79109c3 | 619 | } |
ea149b36 | 620 | EXPORT_SYMBOL_GPL(machine_check_poll); |
b79109c3 | 621 | |
bd19a5e6 AK |
622 | /* |
623 | * Do a quick check if any of the events requires a panic. | |
624 | * This decides if we keep the events around or clear them. | |
625 | */ | |
626 | static int mce_no_way_out(struct mce *m, char **msg) | |
627 | { | |
628 | int i; | |
629 | ||
630 | for (i = 0; i < banks; i++) { | |
a2d32bcb | 631 | m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
bd19a5e6 AK |
632 | if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY) |
633 | return 1; | |
634 | } | |
635 | return 0; | |
636 | } | |
637 | ||
3c079792 AK |
638 | /* |
639 | * Variable to establish order between CPUs while scanning. | |
640 | * Each CPU spins initially until executing is equal its number. | |
641 | */ | |
642 | static atomic_t mce_executing; | |
643 | ||
644 | /* | |
645 | * Defines order of CPUs on entry. First CPU becomes Monarch. | |
646 | */ | |
647 | static atomic_t mce_callin; | |
648 | ||
649 | /* | |
650 | * Check if a timeout waiting for other CPUs happened. | |
651 | */ | |
652 | static int mce_timed_out(u64 *t) | |
653 | { | |
654 | /* | |
655 | * The others already did panic for some reason. | |
656 | * Bail out like in a timeout. | |
657 | * rmb() to tell the compiler that system_state | |
658 | * might have been modified by someone else. | |
659 | */ | |
660 | rmb(); | |
661 | if (atomic_read(&mce_paniced)) | |
662 | wait_for_panic(); | |
663 | if (!monarch_timeout) | |
664 | goto out; | |
665 | if ((s64)*t < SPINUNIT) { | |
666 | /* CHECKME: Make panic default for 1 too? */ | |
667 | if (tolerant < 1) | |
668 | mce_panic("Timeout synchronizing machine check over CPUs", | |
669 | NULL, NULL); | |
670 | cpu_missing = 1; | |
671 | return 1; | |
672 | } | |
673 | *t -= SPINUNIT; | |
674 | out: | |
675 | touch_nmi_watchdog(); | |
676 | return 0; | |
677 | } | |
678 | ||
679 | /* | |
680 | * The Monarch's reign. The Monarch is the CPU who entered | |
681 | * the machine check handler first. It waits for the others to | |
682 | * raise the exception too and then grades them. When any | |
683 | * error is fatal panic. Only then let the others continue. | |
684 | * | |
685 | * The other CPUs entering the MCE handler will be controlled by the | |
686 | * Monarch. They are called Subjects. | |
687 | * | |
688 | * This way we prevent any potential data corruption in a unrecoverable case | |
689 | * and also makes sure always all CPU's errors are examined. | |
690 | * | |
680b6cfd | 691 | * Also this detects the case of a machine check event coming from outer |
3c079792 AK |
692 | * space (not detected by any CPUs) In this case some external agent wants |
693 | * us to shut down, so panic too. | |
694 | * | |
695 | * The other CPUs might still decide to panic if the handler happens | |
696 | * in a unrecoverable place, but in this case the system is in a semi-stable | |
697 | * state and won't corrupt anything by itself. It's ok to let the others | |
698 | * continue for a bit first. | |
699 | * | |
700 | * All the spin loops have timeouts; when a timeout happens a CPU | |
701 | * typically elects itself to be Monarch. | |
702 | */ | |
703 | static void mce_reign(void) | |
704 | { | |
705 | int cpu; | |
706 | struct mce *m = NULL; | |
707 | int global_worst = 0; | |
708 | char *msg = NULL; | |
709 | char *nmsg = NULL; | |
710 | ||
711 | /* | |
712 | * This CPU is the Monarch and the other CPUs have run | |
713 | * through their handlers. | |
714 | * Grade the severity of the errors of all the CPUs. | |
715 | */ | |
716 | for_each_possible_cpu(cpu) { | |
717 | int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant, | |
718 | &nmsg); | |
719 | if (severity > global_worst) { | |
720 | msg = nmsg; | |
721 | global_worst = severity; | |
722 | m = &per_cpu(mces_seen, cpu); | |
723 | } | |
724 | } | |
725 | ||
726 | /* | |
727 | * Cannot recover? Panic here then. | |
728 | * This dumps all the mces in the log buffer and stops the | |
729 | * other CPUs. | |
730 | */ | |
731 | if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3) | |
ac960375 | 732 | mce_panic("Fatal Machine check", m, msg); |
3c079792 AK |
733 | |
734 | /* | |
735 | * For UC somewhere we let the CPU who detects it handle it. | |
736 | * Also must let continue the others, otherwise the handling | |
737 | * CPU could deadlock on a lock. | |
738 | */ | |
739 | ||
740 | /* | |
741 | * No machine check event found. Must be some external | |
742 | * source or one CPU is hung. Panic. | |
743 | */ | |
680b6cfd | 744 | if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3) |
3c079792 AK |
745 | mce_panic("Machine check from unknown source", NULL, NULL); |
746 | ||
747 | /* | |
748 | * Now clear all the mces_seen so that they don't reappear on | |
749 | * the next mce. | |
750 | */ | |
751 | for_each_possible_cpu(cpu) | |
752 | memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce)); | |
753 | } | |
754 | ||
755 | static atomic_t global_nwo; | |
756 | ||
757 | /* | |
758 | * Start of Monarch synchronization. This waits until all CPUs have | |
759 | * entered the exception handler and then determines if any of them | |
760 | * saw a fatal event that requires panic. Then it executes them | |
761 | * in the entry order. | |
762 | * TBD double check parallel CPU hotunplug | |
763 | */ | |
7fb06fc9 | 764 | static int mce_start(int *no_way_out) |
3c079792 | 765 | { |
7fb06fc9 | 766 | int order; |
3c079792 AK |
767 | int cpus = num_online_cpus(); |
768 | u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC; | |
769 | ||
7fb06fc9 HS |
770 | if (!timeout) |
771 | return -1; | |
3c079792 | 772 | |
7fb06fc9 | 773 | atomic_add(*no_way_out, &global_nwo); |
184e1fdf HY |
774 | /* |
775 | * global_nwo should be updated before mce_callin | |
776 | */ | |
777 | smp_wmb(); | |
a95436e4 | 778 | order = atomic_inc_return(&mce_callin); |
3c079792 AK |
779 | |
780 | /* | |
781 | * Wait for everyone. | |
782 | */ | |
783 | while (atomic_read(&mce_callin) != cpus) { | |
784 | if (mce_timed_out(&timeout)) { | |
785 | atomic_set(&global_nwo, 0); | |
7fb06fc9 | 786 | return -1; |
3c079792 AK |
787 | } |
788 | ndelay(SPINUNIT); | |
789 | } | |
790 | ||
184e1fdf HY |
791 | /* |
792 | * mce_callin should be read before global_nwo | |
793 | */ | |
794 | smp_rmb(); | |
3c079792 | 795 | |
7fb06fc9 HS |
796 | if (order == 1) { |
797 | /* | |
798 | * Monarch: Starts executing now, the others wait. | |
799 | */ | |
3c079792 | 800 | atomic_set(&mce_executing, 1); |
7fb06fc9 HS |
801 | } else { |
802 | /* | |
803 | * Subject: Now start the scanning loop one by one in | |
804 | * the original callin order. | |
805 | * This way when there are any shared banks it will be | |
806 | * only seen by one CPU before cleared, avoiding duplicates. | |
807 | */ | |
808 | while (atomic_read(&mce_executing) < order) { | |
809 | if (mce_timed_out(&timeout)) { | |
810 | atomic_set(&global_nwo, 0); | |
811 | return -1; | |
812 | } | |
813 | ndelay(SPINUNIT); | |
814 | } | |
3c079792 AK |
815 | } |
816 | ||
817 | /* | |
7fb06fc9 | 818 | * Cache the global no_way_out state. |
3c079792 | 819 | */ |
7fb06fc9 HS |
820 | *no_way_out = atomic_read(&global_nwo); |
821 | ||
822 | return order; | |
3c079792 AK |
823 | } |
824 | ||
825 | /* | |
826 | * Synchronize between CPUs after main scanning loop. | |
827 | * This invokes the bulk of the Monarch processing. | |
828 | */ | |
829 | static int mce_end(int order) | |
830 | { | |
831 | int ret = -1; | |
832 | u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC; | |
833 | ||
834 | if (!timeout) | |
835 | goto reset; | |
836 | if (order < 0) | |
837 | goto reset; | |
838 | ||
839 | /* | |
840 | * Allow others to run. | |
841 | */ | |
842 | atomic_inc(&mce_executing); | |
843 | ||
844 | if (order == 1) { | |
845 | /* CHECKME: Can this race with a parallel hotplug? */ | |
846 | int cpus = num_online_cpus(); | |
847 | ||
848 | /* | |
849 | * Monarch: Wait for everyone to go through their scanning | |
850 | * loops. | |
851 | */ | |
852 | while (atomic_read(&mce_executing) <= cpus) { | |
853 | if (mce_timed_out(&timeout)) | |
854 | goto reset; | |
855 | ndelay(SPINUNIT); | |
856 | } | |
857 | ||
858 | mce_reign(); | |
859 | barrier(); | |
860 | ret = 0; | |
861 | } else { | |
862 | /* | |
863 | * Subject: Wait for Monarch to finish. | |
864 | */ | |
865 | while (atomic_read(&mce_executing) != 0) { | |
866 | if (mce_timed_out(&timeout)) | |
867 | goto reset; | |
868 | ndelay(SPINUNIT); | |
869 | } | |
870 | ||
871 | /* | |
872 | * Don't reset anything. That's done by the Monarch. | |
873 | */ | |
874 | return 0; | |
875 | } | |
876 | ||
877 | /* | |
878 | * Reset all global state. | |
879 | */ | |
880 | reset: | |
881 | atomic_set(&global_nwo, 0); | |
882 | atomic_set(&mce_callin, 0); | |
883 | barrier(); | |
884 | ||
885 | /* | |
886 | * Let others run again. | |
887 | */ | |
888 | atomic_set(&mce_executing, 0); | |
889 | return ret; | |
890 | } | |
891 | ||
9b1beaf2 AK |
892 | /* |
893 | * Check if the address reported by the CPU is in a format we can parse. | |
894 | * It would be possible to add code for most other cases, but all would | |
895 | * be somewhat complicated (e.g. segment offset would require an instruction | |
0d2eb44f | 896 | * parser). So only support physical addresses up to page granuality for now. |
9b1beaf2 AK |
897 | */ |
898 | static int mce_usable_address(struct mce *m) | |
899 | { | |
900 | if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV)) | |
901 | return 0; | |
2b90e77e | 902 | if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT) |
9b1beaf2 | 903 | return 0; |
2b90e77e | 904 | if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS) |
9b1beaf2 AK |
905 | return 0; |
906 | return 1; | |
907 | } | |
908 | ||
3c079792 AK |
909 | static void mce_clear_state(unsigned long *toclear) |
910 | { | |
911 | int i; | |
912 | ||
913 | for (i = 0; i < banks; i++) { | |
914 | if (test_bit(i, toclear)) | |
a2d32bcb | 915 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
3c079792 AK |
916 | } |
917 | } | |
918 | ||
b79109c3 AK |
919 | /* |
920 | * The actual machine check handler. This only handles real | |
921 | * exceptions when something got corrupted coming in through int 18. | |
922 | * | |
923 | * This is executed in NMI context not subject to normal locking rules. This | |
924 | * implies that most kernel services cannot be safely used. Don't even | |
925 | * think about putting a printk in there! | |
3c079792 AK |
926 | * |
927 | * On Intel systems this is entered on all CPUs in parallel through | |
928 | * MCE broadcast. However some CPUs might be broken beyond repair, | |
929 | * so be always careful when synchronizing with others. | |
1da177e4 | 930 | */ |
e9eee03e | 931 | void do_machine_check(struct pt_regs *regs, long error_code) |
1da177e4 | 932 | { |
3c079792 | 933 | struct mce m, *final; |
1da177e4 | 934 | int i; |
3c079792 AK |
935 | int worst = 0; |
936 | int severity; | |
937 | /* | |
938 | * Establish sequential order between the CPUs entering the machine | |
939 | * check handler. | |
940 | */ | |
7fb06fc9 | 941 | int order; |
bd78432c TH |
942 | /* |
943 | * If no_way_out gets set, there is no safe way to recover from this | |
944 | * MCE. If tolerant is cranked up, we'll try anyway. | |
945 | */ | |
946 | int no_way_out = 0; | |
947 | /* | |
948 | * If kill_it gets set, there might be a way to recover from this | |
949 | * error. | |
950 | */ | |
951 | int kill_it = 0; | |
b79109c3 | 952 | DECLARE_BITMAP(toclear, MAX_NR_BANKS); |
bd19a5e6 | 953 | char *msg = "Unknown"; |
1da177e4 | 954 | |
553f265f AK |
955 | atomic_inc(&mce_entry); |
956 | ||
402af0d7 | 957 | percpu_inc(mce_exception_count); |
01ca79f1 | 958 | |
b79109c3 | 959 | if (!banks) |
32561696 | 960 | goto out; |
1da177e4 | 961 | |
b8325c5b | 962 | mce_gather_info(&m, regs); |
b5f2fa4e | 963 | |
3c079792 AK |
964 | final = &__get_cpu_var(mces_seen); |
965 | *final = m; | |
966 | ||
680b6cfd HS |
967 | no_way_out = mce_no_way_out(&m, &msg); |
968 | ||
1da177e4 LT |
969 | barrier(); |
970 | ||
ed7290d0 AK |
971 | /* |
972 | * When no restart IP must always kill or panic. | |
973 | */ | |
974 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) | |
975 | kill_it = 1; | |
976 | ||
3c079792 AK |
977 | /* |
978 | * Go through all the banks in exclusion of the other CPUs. | |
979 | * This way we don't report duplicated events on shared banks | |
980 | * because the first one to see it will clear it. | |
981 | */ | |
7fb06fc9 | 982 | order = mce_start(&no_way_out); |
1da177e4 | 983 | for (i = 0; i < banks; i++) { |
b79109c3 | 984 | __clear_bit(i, toclear); |
cebe1820 | 985 | if (!mce_banks[i].ctl) |
1da177e4 | 986 | continue; |
d88203d1 TG |
987 | |
988 | m.misc = 0; | |
1da177e4 LT |
989 | m.addr = 0; |
990 | m.bank = i; | |
1da177e4 | 991 | |
a2d32bcb | 992 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
1da177e4 LT |
993 | if ((m.status & MCI_STATUS_VAL) == 0) |
994 | continue; | |
995 | ||
b79109c3 | 996 | /* |
ed7290d0 AK |
997 | * Non uncorrected or non signaled errors are handled by |
998 | * machine_check_poll. Leave them alone, unless this panics. | |
b79109c3 | 999 | */ |
ed7290d0 AK |
1000 | if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) && |
1001 | !no_way_out) | |
b79109c3 AK |
1002 | continue; |
1003 | ||
1004 | /* | |
1005 | * Set taint even when machine check was not enabled. | |
1006 | */ | |
1007 | add_taint(TAINT_MACHINE_CHECK); | |
1008 | ||
ed7290d0 | 1009 | severity = mce_severity(&m, tolerant, NULL); |
b79109c3 | 1010 | |
ed7290d0 AK |
1011 | /* |
1012 | * When machine check was for corrected handler don't touch, | |
1013 | * unless we're panicing. | |
1014 | */ | |
1015 | if (severity == MCE_KEEP_SEVERITY && !no_way_out) | |
1016 | continue; | |
1017 | __set_bit(i, toclear); | |
1018 | if (severity == MCE_NO_SEVERITY) { | |
b79109c3 AK |
1019 | /* |
1020 | * Machine check event was not enabled. Clear, but | |
1021 | * ignore. | |
1022 | */ | |
1023 | continue; | |
1da177e4 LT |
1024 | } |
1025 | ||
ed7290d0 AK |
1026 | /* |
1027 | * Kill on action required. | |
1028 | */ | |
1029 | if (severity == MCE_AR_SEVERITY) | |
1030 | kill_it = 1; | |
1031 | ||
1da177e4 | 1032 | if (m.status & MCI_STATUS_MISCV) |
a2d32bcb | 1033 | m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i)); |
1da177e4 | 1034 | if (m.status & MCI_STATUS_ADDRV) |
a2d32bcb | 1035 | m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i)); |
1da177e4 | 1036 | |
9b1beaf2 AK |
1037 | /* |
1038 | * Action optional error. Queue address for later processing. | |
1039 | * When the ring overflows we just ignore the AO error. | |
1040 | * RED-PEN add some logging mechanism when | |
1041 | * usable_address or mce_add_ring fails. | |
1042 | * RED-PEN don't ignore overflow for tolerant == 0 | |
1043 | */ | |
1044 | if (severity == MCE_AO_SEVERITY && mce_usable_address(&m)) | |
1045 | mce_ring_add(m.addr >> PAGE_SHIFT); | |
1046 | ||
b79109c3 | 1047 | mce_log(&m); |
1da177e4 | 1048 | |
3c079792 AK |
1049 | if (severity > worst) { |
1050 | *final = m; | |
1051 | worst = severity; | |
1da177e4 | 1052 | } |
1da177e4 LT |
1053 | } |
1054 | ||
3c079792 AK |
1055 | if (!no_way_out) |
1056 | mce_clear_state(toclear); | |
1057 | ||
e9eee03e | 1058 | /* |
3c079792 AK |
1059 | * Do most of the synchronization with other CPUs. |
1060 | * When there's any problem use only local no_way_out state. | |
e9eee03e | 1061 | */ |
3c079792 AK |
1062 | if (mce_end(order) < 0) |
1063 | no_way_out = worst >= MCE_PANIC_SEVERITY; | |
bd78432c TH |
1064 | |
1065 | /* | |
1066 | * If we have decided that we just CAN'T continue, and the user | |
e9eee03e | 1067 | * has not set tolerant to an insane level, give up and die. |
3c079792 AK |
1068 | * |
1069 | * This is mainly used in the case when the system doesn't | |
1070 | * support MCE broadcasting or it has been disabled. | |
bd78432c TH |
1071 | */ |
1072 | if (no_way_out && tolerant < 3) | |
ac960375 | 1073 | mce_panic("Fatal machine check on current CPU", final, msg); |
bd78432c TH |
1074 | |
1075 | /* | |
1076 | * If the error seems to be unrecoverable, something should be | |
1077 | * done. Try to kill as little as possible. If we can kill just | |
1078 | * one task, do that. If the user has set the tolerance very | |
1079 | * high, don't try to do anything at all. | |
1080 | */ | |
bd78432c | 1081 | |
ed7290d0 AK |
1082 | if (kill_it && tolerant < 3) |
1083 | force_sig(SIGBUS, current); | |
1da177e4 | 1084 | |
e02e68d3 TH |
1085 | /* notify userspace ASAP */ |
1086 | set_thread_flag(TIF_MCE_NOTIFY); | |
1087 | ||
3c079792 AK |
1088 | if (worst > 0) |
1089 | mce_report_event(regs); | |
5f8c1a54 | 1090 | mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); |
32561696 | 1091 | out: |
553f265f | 1092 | atomic_dec(&mce_entry); |
88921be3 | 1093 | sync_core(); |
1da177e4 | 1094 | } |
ea149b36 | 1095 | EXPORT_SYMBOL_GPL(do_machine_check); |
1da177e4 | 1096 | |
9b1beaf2 AK |
1097 | /* dummy to break dependency. actual code is in mm/memory-failure.c */ |
1098 | void __attribute__((weak)) memory_failure(unsigned long pfn, int vector) | |
1099 | { | |
1100 | printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn); | |
1101 | } | |
1102 | ||
1103 | /* | |
1104 | * Called after mce notification in process context. This code | |
1105 | * is allowed to sleep. Call the high level VM handler to process | |
1106 | * any corrupted pages. | |
1107 | * Assume that the work queue code only calls this one at a time | |
1108 | * per CPU. | |
1109 | * Note we don't disable preemption, so this code might run on the wrong | |
1110 | * CPU. In this case the event is picked up by the scheduled work queue. | |
1111 | * This is merely a fast path to expedite processing in some common | |
1112 | * cases. | |
1113 | */ | |
1114 | void mce_notify_process(void) | |
1115 | { | |
1116 | unsigned long pfn; | |
1117 | mce_notify_irq(); | |
1118 | while (mce_ring_get(&pfn)) | |
1119 | memory_failure(pfn, MCE_VECTOR); | |
1120 | } | |
1121 | ||
1122 | static void mce_process_work(struct work_struct *dummy) | |
1123 | { | |
1124 | mce_notify_process(); | |
1125 | } | |
1126 | ||
15d5f839 DZ |
1127 | #ifdef CONFIG_X86_MCE_INTEL |
1128 | /*** | |
1129 | * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog | |
676b1855 | 1130 | * @cpu: The CPU on which the event occurred. |
15d5f839 DZ |
1131 | * @status: Event status information |
1132 | * | |
1133 | * This function should be called by the thermal interrupt after the | |
1134 | * event has been processed and the decision was made to log the event | |
1135 | * further. | |
1136 | * | |
1137 | * The status parameter will be saved to the 'status' field of 'struct mce' | |
1138 | * and historically has been the register value of the | |
1139 | * MSR_IA32_THERMAL_STATUS (Intel) msr. | |
1140 | */ | |
b5f2fa4e | 1141 | void mce_log_therm_throt_event(__u64 status) |
15d5f839 DZ |
1142 | { |
1143 | struct mce m; | |
1144 | ||
b5f2fa4e | 1145 | mce_setup(&m); |
15d5f839 DZ |
1146 | m.bank = MCE_THERMAL_BANK; |
1147 | m.status = status; | |
15d5f839 DZ |
1148 | mce_log(&m); |
1149 | } | |
1150 | #endif /* CONFIG_X86_MCE_INTEL */ | |
1151 | ||
1da177e4 | 1152 | /* |
8a336b0a TH |
1153 | * Periodic polling timer for "silent" machine check errors. If the |
1154 | * poller finds an MCE, poll 2x faster. When the poller finds no more | |
1155 | * errors, poll 2x slower (up to check_interval seconds). | |
1da177e4 | 1156 | */ |
1da177e4 | 1157 | static int check_interval = 5 * 60; /* 5 minutes */ |
e9eee03e | 1158 | |
245b2e70 | 1159 | static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */ |
52d168e2 | 1160 | static DEFINE_PER_CPU(struct timer_list, mce_timer); |
1da177e4 | 1161 | |
5e09954a | 1162 | static void mce_start_timer(unsigned long data) |
1da177e4 | 1163 | { |
52d168e2 | 1164 | struct timer_list *t = &per_cpu(mce_timer, data); |
6298c512 | 1165 | int *n; |
52d168e2 AK |
1166 | |
1167 | WARN_ON(smp_processor_id() != data); | |
1168 | ||
7b543a53 | 1169 | if (mce_available(__this_cpu_ptr(&cpu_info))) { |
ee031c31 AK |
1170 | machine_check_poll(MCP_TIMESTAMP, |
1171 | &__get_cpu_var(mce_poll_banks)); | |
e9eee03e | 1172 | } |
1da177e4 LT |
1173 | |
1174 | /* | |
e02e68d3 TH |
1175 | * Alert userspace if needed. If we logged an MCE, reduce the |
1176 | * polling interval, otherwise increase the polling interval. | |
1da177e4 | 1177 | */ |
245b2e70 | 1178 | n = &__get_cpu_var(mce_next_interval); |
9ff36ee9 | 1179 | if (mce_notify_irq()) |
6298c512 | 1180 | *n = max(*n/2, HZ/100); |
14a02530 | 1181 | else |
6298c512 | 1182 | *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ)); |
e02e68d3 | 1183 | |
6298c512 | 1184 | t->expires = jiffies + *n; |
5be6066a | 1185 | add_timer_on(t, smp_processor_id()); |
e02e68d3 TH |
1186 | } |
1187 | ||
9aaef96f HS |
1188 | /* Must not be called in IRQ context where del_timer_sync() can deadlock */ |
1189 | static void mce_timer_delete_all(void) | |
1190 | { | |
1191 | int cpu; | |
1192 | ||
1193 | for_each_online_cpu(cpu) | |
1194 | del_timer_sync(&per_cpu(mce_timer, cpu)); | |
1195 | } | |
1196 | ||
9bd98405 AK |
1197 | static void mce_do_trigger(struct work_struct *work) |
1198 | { | |
1020bcbc | 1199 | call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT); |
9bd98405 AK |
1200 | } |
1201 | ||
1202 | static DECLARE_WORK(mce_trigger_work, mce_do_trigger); | |
1203 | ||
e02e68d3 | 1204 | /* |
9bd98405 AK |
1205 | * Notify the user(s) about new machine check events. |
1206 | * Can be called from interrupt context, but not from machine check/NMI | |
1207 | * context. | |
e02e68d3 | 1208 | */ |
9ff36ee9 | 1209 | int mce_notify_irq(void) |
e02e68d3 | 1210 | { |
8457c84d AK |
1211 | /* Not more than two messages every minute */ |
1212 | static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); | |
1213 | ||
e02e68d3 | 1214 | clear_thread_flag(TIF_MCE_NOTIFY); |
e9eee03e | 1215 | |
1020bcbc | 1216 | if (test_and_clear_bit(0, &mce_need_notify)) { |
93b62c3c HS |
1217 | /* wake processes polling /dev/mcelog */ |
1218 | wake_up_interruptible(&mce_chrdev_wait); | |
9bd98405 AK |
1219 | |
1220 | /* | |
1221 | * There is no risk of missing notifications because | |
1222 | * work_pending is always cleared before the function is | |
1223 | * executed. | |
1224 | */ | |
1020bcbc | 1225 | if (mce_helper[0] && !work_pending(&mce_trigger_work)) |
9bd98405 | 1226 | schedule_work(&mce_trigger_work); |
e02e68d3 | 1227 | |
8457c84d | 1228 | if (__ratelimit(&ratelimit)) |
a2d7b0d4 | 1229 | pr_info(HW_ERR "Machine check events logged\n"); |
e02e68d3 TH |
1230 | |
1231 | return 1; | |
1da177e4 | 1232 | } |
e02e68d3 TH |
1233 | return 0; |
1234 | } | |
9ff36ee9 | 1235 | EXPORT_SYMBOL_GPL(mce_notify_irq); |
8a336b0a | 1236 | |
cffd377e | 1237 | static int __cpuinit __mcheck_cpu_mce_banks_init(void) |
cebe1820 AK |
1238 | { |
1239 | int i; | |
1240 | ||
1241 | mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL); | |
1242 | if (!mce_banks) | |
1243 | return -ENOMEM; | |
1244 | for (i = 0; i < banks; i++) { | |
1245 | struct mce_bank *b = &mce_banks[i]; | |
11868a2d | 1246 | |
cebe1820 AK |
1247 | b->ctl = -1ULL; |
1248 | b->init = 1; | |
1249 | } | |
1250 | return 0; | |
1251 | } | |
1252 | ||
d88203d1 | 1253 | /* |
1da177e4 LT |
1254 | * Initialize Machine Checks for a CPU. |
1255 | */ | |
5e09954a | 1256 | static int __cpuinit __mcheck_cpu_cap_init(void) |
1da177e4 | 1257 | { |
0d7482e3 | 1258 | unsigned b; |
e9eee03e | 1259 | u64 cap; |
1da177e4 LT |
1260 | |
1261 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
01c6680a TG |
1262 | |
1263 | b = cap & MCG_BANKCNT_MASK; | |
93ae5012 RD |
1264 | if (!banks) |
1265 | printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b); | |
b659294b | 1266 | |
0d7482e3 AK |
1267 | if (b > MAX_NR_BANKS) { |
1268 | printk(KERN_WARNING | |
1269 | "MCE: Using only %u machine check banks out of %u\n", | |
1270 | MAX_NR_BANKS, b); | |
1271 | b = MAX_NR_BANKS; | |
1272 | } | |
1273 | ||
1274 | /* Don't support asymmetric configurations today */ | |
1275 | WARN_ON(banks != 0 && b != banks); | |
1276 | banks = b; | |
cebe1820 | 1277 | if (!mce_banks) { |
cffd377e | 1278 | int err = __mcheck_cpu_mce_banks_init(); |
11868a2d | 1279 | |
cebe1820 AK |
1280 | if (err) |
1281 | return err; | |
1da177e4 | 1282 | } |
0d7482e3 | 1283 | |
94ad8474 | 1284 | /* Use accurate RIP reporting if available. */ |
01c6680a | 1285 | if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) |
94ad8474 | 1286 | rip_msr = MSR_IA32_MCG_EIP; |
1da177e4 | 1287 | |
ed7290d0 AK |
1288 | if (cap & MCG_SER_P) |
1289 | mce_ser = 1; | |
1290 | ||
0d7482e3 AK |
1291 | return 0; |
1292 | } | |
1293 | ||
5e09954a | 1294 | static void __mcheck_cpu_init_generic(void) |
0d7482e3 | 1295 | { |
e9eee03e | 1296 | mce_banks_t all_banks; |
0d7482e3 AK |
1297 | u64 cap; |
1298 | int i; | |
1299 | ||
b79109c3 AK |
1300 | /* |
1301 | * Log the machine checks left over from the previous reset. | |
1302 | */ | |
ee031c31 | 1303 | bitmap_fill(all_banks, MAX_NR_BANKS); |
5679af4c | 1304 | machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks); |
1da177e4 LT |
1305 | |
1306 | set_in_cr4(X86_CR4_MCE); | |
1307 | ||
0d7482e3 | 1308 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
1da177e4 LT |
1309 | if (cap & MCG_CTL_P) |
1310 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); | |
1311 | ||
1312 | for (i = 0; i < banks; i++) { | |
cebe1820 | 1313 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1314 | |
cebe1820 | 1315 | if (!b->init) |
06b7a7a5 | 1316 | continue; |
a2d32bcb AK |
1317 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
1318 | wrmsrl(MSR_IA32_MCx_STATUS(i), 0); | |
d88203d1 | 1319 | } |
1da177e4 LT |
1320 | } |
1321 | ||
1322 | /* Add per CPU specific workarounds here */ | |
5e09954a | 1323 | static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) |
d88203d1 | 1324 | { |
e412cd25 IM |
1325 | if (c->x86_vendor == X86_VENDOR_UNKNOWN) { |
1326 | pr_info("MCE: unknown CPU type - not enabling MCE support.\n"); | |
1327 | return -EOPNOTSUPP; | |
1328 | } | |
1329 | ||
1da177e4 | 1330 | /* This should be disabled by the BIOS, but isn't always */ |
911f6a7b | 1331 | if (c->x86_vendor == X86_VENDOR_AMD) { |
e9eee03e IM |
1332 | if (c->x86 == 15 && banks > 4) { |
1333 | /* | |
1334 | * disable GART TBL walk error reporting, which | |
1335 | * trips off incorrectly with the IOMMU & 3ware | |
1336 | * & Cerberus: | |
1337 | */ | |
cebe1820 | 1338 | clear_bit(10, (unsigned long *)&mce_banks[4].ctl); |
e9eee03e IM |
1339 | } |
1340 | if (c->x86 <= 17 && mce_bootlog < 0) { | |
1341 | /* | |
1342 | * Lots of broken BIOS around that don't clear them | |
1343 | * by default and leave crap in there. Don't log: | |
1344 | */ | |
911f6a7b | 1345 | mce_bootlog = 0; |
e9eee03e | 1346 | } |
2e6f694f AK |
1347 | /* |
1348 | * Various K7s with broken bank 0 around. Always disable | |
1349 | * by default. | |
1350 | */ | |
203abd67 | 1351 | if (c->x86 == 6 && banks > 0) |
cebe1820 | 1352 | mce_banks[0].ctl = 0; |
1da177e4 | 1353 | } |
e583538f | 1354 | |
06b7a7a5 AK |
1355 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
1356 | /* | |
1357 | * SDM documents that on family 6 bank 0 should not be written | |
1358 | * because it aliases to another special BIOS controlled | |
1359 | * register. | |
1360 | * But it's not aliased anymore on model 0x1a+ | |
1361 | * Don't ignore bank 0 completely because there could be a | |
1362 | * valid event later, merely don't write CTL0. | |
1363 | */ | |
1364 | ||
cebe1820 AK |
1365 | if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0) |
1366 | mce_banks[0].init = 0; | |
3c079792 AK |
1367 | |
1368 | /* | |
1369 | * All newer Intel systems support MCE broadcasting. Enable | |
1370 | * synchronization with a one second timeout. | |
1371 | */ | |
1372 | if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && | |
1373 | monarch_timeout < 0) | |
1374 | monarch_timeout = USEC_PER_SEC; | |
c7f6fa44 | 1375 | |
e412cd25 IM |
1376 | /* |
1377 | * There are also broken BIOSes on some Pentium M and | |
1378 | * earlier systems: | |
1379 | */ | |
1380 | if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0) | |
c7f6fa44 | 1381 | mce_bootlog = 0; |
06b7a7a5 | 1382 | } |
3c079792 AK |
1383 | if (monarch_timeout < 0) |
1384 | monarch_timeout = 0; | |
29b0f591 AK |
1385 | if (mce_bootlog != 0) |
1386 | mce_panic_timeout = 30; | |
e412cd25 IM |
1387 | |
1388 | return 0; | |
d88203d1 | 1389 | } |
1da177e4 | 1390 | |
3a97fc34 | 1391 | static int __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) |
4efc0670 AK |
1392 | { |
1393 | if (c->x86 != 5) | |
3a97fc34 HS |
1394 | return 0; |
1395 | ||
4efc0670 AK |
1396 | switch (c->x86_vendor) { |
1397 | case X86_VENDOR_INTEL: | |
c6978369 | 1398 | intel_p5_mcheck_init(c); |
3a97fc34 | 1399 | return 1; |
4efc0670 AK |
1400 | break; |
1401 | case X86_VENDOR_CENTAUR: | |
1402 | winchip_mcheck_init(c); | |
3a97fc34 | 1403 | return 1; |
4efc0670 AK |
1404 | break; |
1405 | } | |
3a97fc34 HS |
1406 | |
1407 | return 0; | |
4efc0670 AK |
1408 | } |
1409 | ||
5e09954a | 1410 | static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
1411 | { |
1412 | switch (c->x86_vendor) { | |
1413 | case X86_VENDOR_INTEL: | |
1414 | mce_intel_feature_init(c); | |
1415 | break; | |
89b831ef JS |
1416 | case X86_VENDOR_AMD: |
1417 | mce_amd_feature_init(c); | |
1418 | break; | |
1da177e4 LT |
1419 | default: |
1420 | break; | |
1421 | } | |
1422 | } | |
1423 | ||
5e09954a | 1424 | static void __mcheck_cpu_init_timer(void) |
52d168e2 AK |
1425 | { |
1426 | struct timer_list *t = &__get_cpu_var(mce_timer); | |
245b2e70 | 1427 | int *n = &__get_cpu_var(mce_next_interval); |
52d168e2 | 1428 | |
bc09effa JB |
1429 | setup_timer(t, mce_start_timer, smp_processor_id()); |
1430 | ||
62fdac59 HS |
1431 | if (mce_ignore_ce) |
1432 | return; | |
1433 | ||
6298c512 AK |
1434 | *n = check_interval * HZ; |
1435 | if (!*n) | |
52d168e2 | 1436 | return; |
6298c512 | 1437 | t->expires = round_jiffies(jiffies + *n); |
5be6066a | 1438 | add_timer_on(t, smp_processor_id()); |
52d168e2 AK |
1439 | } |
1440 | ||
9eda8cb3 AK |
1441 | /* Handle unconfigured int18 (should never happen) */ |
1442 | static void unexpected_machine_check(struct pt_regs *regs, long error_code) | |
1443 | { | |
1444 | printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n", | |
1445 | smp_processor_id()); | |
1446 | } | |
1447 | ||
1448 | /* Call the installed machine check handler for this CPU setup. */ | |
1449 | void (*machine_check_vector)(struct pt_regs *, long error_code) = | |
1450 | unexpected_machine_check; | |
1451 | ||
d88203d1 | 1452 | /* |
1da177e4 | 1453 | * Called for each booted CPU to set up machine checks. |
e9eee03e | 1454 | * Must be called with preempt off: |
1da177e4 | 1455 | */ |
5e09954a | 1456 | void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c) |
1da177e4 | 1457 | { |
4efc0670 AK |
1458 | if (mce_disabled) |
1459 | return; | |
1460 | ||
3a97fc34 HS |
1461 | if (__mcheck_cpu_ancient_init(c)) |
1462 | return; | |
4efc0670 | 1463 | |
5b4408fd | 1464 | if (!mce_available(c)) |
1da177e4 LT |
1465 | return; |
1466 | ||
5e09954a | 1467 | if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) { |
04b2b1a4 | 1468 | mce_disabled = 1; |
0d7482e3 AK |
1469 | return; |
1470 | } | |
0d7482e3 | 1471 | |
5d727926 AK |
1472 | machine_check_vector = do_machine_check; |
1473 | ||
5e09954a BP |
1474 | __mcheck_cpu_init_generic(); |
1475 | __mcheck_cpu_init_vendor(c); | |
1476 | __mcheck_cpu_init_timer(); | |
9b1beaf2 | 1477 | INIT_WORK(&__get_cpu_var(mce_work), mce_process_work); |
b77e70bf | 1478 | init_irq_work(&__get_cpu_var(mce_irq_work), &mce_irq_work_cb); |
1da177e4 LT |
1479 | } |
1480 | ||
1481 | /* | |
93b62c3c | 1482 | * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log. |
1da177e4 LT |
1483 | */ |
1484 | ||
93b62c3c HS |
1485 | static DEFINE_SPINLOCK(mce_chrdev_state_lock); |
1486 | static int mce_chrdev_open_count; /* #times opened */ | |
1487 | static int mce_chrdev_open_exclu; /* already open exclusive? */ | |
f528e7ba | 1488 | |
93b62c3c | 1489 | static int mce_chrdev_open(struct inode *inode, struct file *file) |
f528e7ba | 1490 | { |
93b62c3c | 1491 | spin_lock(&mce_chrdev_state_lock); |
f528e7ba | 1492 | |
93b62c3c HS |
1493 | if (mce_chrdev_open_exclu || |
1494 | (mce_chrdev_open_count && (file->f_flags & O_EXCL))) { | |
1495 | spin_unlock(&mce_chrdev_state_lock); | |
e9eee03e | 1496 | |
f528e7ba TH |
1497 | return -EBUSY; |
1498 | } | |
1499 | ||
1500 | if (file->f_flags & O_EXCL) | |
93b62c3c HS |
1501 | mce_chrdev_open_exclu = 1; |
1502 | mce_chrdev_open_count++; | |
f528e7ba | 1503 | |
93b62c3c | 1504 | spin_unlock(&mce_chrdev_state_lock); |
f528e7ba | 1505 | |
bd78432c | 1506 | return nonseekable_open(inode, file); |
f528e7ba TH |
1507 | } |
1508 | ||
93b62c3c | 1509 | static int mce_chrdev_release(struct inode *inode, struct file *file) |
f528e7ba | 1510 | { |
93b62c3c | 1511 | spin_lock(&mce_chrdev_state_lock); |
f528e7ba | 1512 | |
93b62c3c HS |
1513 | mce_chrdev_open_count--; |
1514 | mce_chrdev_open_exclu = 0; | |
f528e7ba | 1515 | |
93b62c3c | 1516 | spin_unlock(&mce_chrdev_state_lock); |
f528e7ba TH |
1517 | |
1518 | return 0; | |
1519 | } | |
1520 | ||
d88203d1 TG |
1521 | static void collect_tscs(void *data) |
1522 | { | |
1da177e4 | 1523 | unsigned long *cpu_tsc = (unsigned long *)data; |
d88203d1 | 1524 | |
1da177e4 | 1525 | rdtscll(cpu_tsc[smp_processor_id()]); |
d88203d1 | 1526 | } |
1da177e4 | 1527 | |
482908b4 HY |
1528 | static int mce_apei_read_done; |
1529 | ||
1530 | /* Collect MCE record of previous boot in persistent storage via APEI ERST. */ | |
1531 | static int __mce_read_apei(char __user **ubuf, size_t usize) | |
1532 | { | |
1533 | int rc; | |
1534 | u64 record_id; | |
1535 | struct mce m; | |
1536 | ||
1537 | if (usize < sizeof(struct mce)) | |
1538 | return -EINVAL; | |
1539 | ||
1540 | rc = apei_read_mce(&m, &record_id); | |
1541 | /* Error or no more MCE record */ | |
1542 | if (rc <= 0) { | |
1543 | mce_apei_read_done = 1; | |
1544 | return rc; | |
1545 | } | |
1546 | rc = -EFAULT; | |
1547 | if (copy_to_user(*ubuf, &m, sizeof(struct mce))) | |
1548 | return rc; | |
1549 | /* | |
1550 | * In fact, we should have cleared the record after that has | |
1551 | * been flushed to the disk or sent to network in | |
1552 | * /sbin/mcelog, but we have no interface to support that now, | |
1553 | * so just clear it to avoid duplication. | |
1554 | */ | |
1555 | rc = apei_clear_mce(record_id); | |
1556 | if (rc) { | |
1557 | mce_apei_read_done = 1; | |
1558 | return rc; | |
1559 | } | |
1560 | *ubuf += sizeof(struct mce); | |
1561 | ||
1562 | return 0; | |
1563 | } | |
1564 | ||
93b62c3c HS |
1565 | static ssize_t mce_chrdev_read(struct file *filp, char __user *ubuf, |
1566 | size_t usize, loff_t *off) | |
1da177e4 | 1567 | { |
e9eee03e | 1568 | char __user *buf = ubuf; |
f0de53bb | 1569 | unsigned long *cpu_tsc; |
ef41df43 | 1570 | unsigned prev, next; |
1da177e4 LT |
1571 | int i, err; |
1572 | ||
6bca67f9 | 1573 | cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL); |
f0de53bb AK |
1574 | if (!cpu_tsc) |
1575 | return -ENOMEM; | |
1576 | ||
93b62c3c | 1577 | mutex_lock(&mce_chrdev_read_mutex); |
482908b4 HY |
1578 | |
1579 | if (!mce_apei_read_done) { | |
1580 | err = __mce_read_apei(&buf, usize); | |
1581 | if (err || buf != ubuf) | |
1582 | goto out; | |
1583 | } | |
1584 | ||
f56e8a07 | 1585 | next = rcu_dereference_check_mce(mcelog.next); |
1da177e4 LT |
1586 | |
1587 | /* Only supports full reads right now */ | |
482908b4 HY |
1588 | err = -EINVAL; |
1589 | if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) | |
1590 | goto out; | |
1da177e4 LT |
1591 | |
1592 | err = 0; | |
ef41df43 HY |
1593 | prev = 0; |
1594 | do { | |
1595 | for (i = prev; i < next; i++) { | |
1596 | unsigned long start = jiffies; | |
559faa6b | 1597 | struct mce *m = &mcelog.entry[i]; |
ef41df43 | 1598 | |
559faa6b | 1599 | while (!m->finished) { |
ef41df43 | 1600 | if (time_after_eq(jiffies, start + 2)) { |
559faa6b | 1601 | memset(m, 0, sizeof(*m)); |
ef41df43 HY |
1602 | goto timeout; |
1603 | } | |
1604 | cpu_relax(); | |
673242c1 | 1605 | } |
ef41df43 | 1606 | smp_rmb(); |
559faa6b HS |
1607 | err |= copy_to_user(buf, m, sizeof(*m)); |
1608 | buf += sizeof(*m); | |
ef41df43 HY |
1609 | timeout: |
1610 | ; | |
673242c1 | 1611 | } |
1da177e4 | 1612 | |
ef41df43 HY |
1613 | memset(mcelog.entry + prev, 0, |
1614 | (next - prev) * sizeof(struct mce)); | |
1615 | prev = next; | |
1616 | next = cmpxchg(&mcelog.next, prev, 0); | |
1617 | } while (next != prev); | |
1da177e4 | 1618 | |
b2b18660 | 1619 | synchronize_sched(); |
1da177e4 | 1620 | |
d88203d1 TG |
1621 | /* |
1622 | * Collect entries that were still getting written before the | |
1623 | * synchronize. | |
1624 | */ | |
15c8b6c1 | 1625 | on_each_cpu(collect_tscs, cpu_tsc, 1); |
e9eee03e | 1626 | |
d88203d1 | 1627 | for (i = next; i < MCE_LOG_LEN; i++) { |
559faa6b HS |
1628 | struct mce *m = &mcelog.entry[i]; |
1629 | ||
1630 | if (m->finished && m->tsc < cpu_tsc[m->cpu]) { | |
1631 | err |= copy_to_user(buf, m, sizeof(*m)); | |
1da177e4 | 1632 | smp_rmb(); |
559faa6b HS |
1633 | buf += sizeof(*m); |
1634 | memset(m, 0, sizeof(*m)); | |
1da177e4 | 1635 | } |
d88203d1 | 1636 | } |
482908b4 HY |
1637 | |
1638 | if (err) | |
1639 | err = -EFAULT; | |
1640 | ||
1641 | out: | |
93b62c3c | 1642 | mutex_unlock(&mce_chrdev_read_mutex); |
f0de53bb | 1643 | kfree(cpu_tsc); |
e9eee03e | 1644 | |
482908b4 | 1645 | return err ? err : buf - ubuf; |
1da177e4 LT |
1646 | } |
1647 | ||
93b62c3c | 1648 | static unsigned int mce_chrdev_poll(struct file *file, poll_table *wait) |
e02e68d3 | 1649 | { |
93b62c3c | 1650 | poll_wait(file, &mce_chrdev_wait, wait); |
a4dd9925 | 1651 | if (rcu_access_index(mcelog.next)) |
e02e68d3 | 1652 | return POLLIN | POLLRDNORM; |
482908b4 HY |
1653 | if (!mce_apei_read_done && apei_check_mce()) |
1654 | return POLLIN | POLLRDNORM; | |
e02e68d3 TH |
1655 | return 0; |
1656 | } | |
1657 | ||
93b62c3c HS |
1658 | static long mce_chrdev_ioctl(struct file *f, unsigned int cmd, |
1659 | unsigned long arg) | |
1da177e4 LT |
1660 | { |
1661 | int __user *p = (int __user *)arg; | |
d88203d1 | 1662 | |
1da177e4 | 1663 | if (!capable(CAP_SYS_ADMIN)) |
d88203d1 | 1664 | return -EPERM; |
e9eee03e | 1665 | |
1da177e4 | 1666 | switch (cmd) { |
d88203d1 | 1667 | case MCE_GET_RECORD_LEN: |
1da177e4 LT |
1668 | return put_user(sizeof(struct mce), p); |
1669 | case MCE_GET_LOG_LEN: | |
d88203d1 | 1670 | return put_user(MCE_LOG_LEN, p); |
1da177e4 LT |
1671 | case MCE_GETCLEAR_FLAGS: { |
1672 | unsigned flags; | |
d88203d1 TG |
1673 | |
1674 | do { | |
1da177e4 | 1675 | flags = mcelog.flags; |
d88203d1 | 1676 | } while (cmpxchg(&mcelog.flags, flags, 0) != flags); |
e9eee03e | 1677 | |
d88203d1 | 1678 | return put_user(flags, p); |
1da177e4 LT |
1679 | } |
1680 | default: | |
d88203d1 TG |
1681 | return -ENOTTY; |
1682 | } | |
1da177e4 LT |
1683 | } |
1684 | ||
66f5ddf3 LT |
1685 | static ssize_t (*mce_write)(struct file *filp, const char __user *ubuf, |
1686 | size_t usize, loff_t *off); | |
1687 | ||
1688 | void register_mce_write_callback(ssize_t (*fn)(struct file *filp, | |
1689 | const char __user *ubuf, | |
1690 | size_t usize, loff_t *off)) | |
1691 | { | |
1692 | mce_write = fn; | |
1693 | } | |
1694 | EXPORT_SYMBOL_GPL(register_mce_write_callback); | |
1695 | ||
1696 | ssize_t mce_chrdev_write(struct file *filp, const char __user *ubuf, | |
1697 | size_t usize, loff_t *off) | |
1698 | { | |
1699 | if (mce_write) | |
1700 | return mce_write(filp, ubuf, usize, off); | |
1701 | else | |
1702 | return -EINVAL; | |
1703 | } | |
1704 | ||
1705 | static const struct file_operations mce_chrdev_ops = { | |
93b62c3c HS |
1706 | .open = mce_chrdev_open, |
1707 | .release = mce_chrdev_release, | |
1708 | .read = mce_chrdev_read, | |
66f5ddf3 | 1709 | .write = mce_chrdev_write, |
93b62c3c HS |
1710 | .poll = mce_chrdev_poll, |
1711 | .unlocked_ioctl = mce_chrdev_ioctl, | |
1712 | .llseek = no_llseek, | |
1da177e4 LT |
1713 | }; |
1714 | ||
93b62c3c | 1715 | static struct miscdevice mce_chrdev_device = { |
1da177e4 LT |
1716 | MISC_MCELOG_MINOR, |
1717 | "mcelog", | |
1718 | &mce_chrdev_ops, | |
1719 | }; | |
1720 | ||
13503fa9 | 1721 | /* |
62fdac59 HS |
1722 | * mce=off Disables machine check |
1723 | * mce=no_cmci Disables CMCI | |
1724 | * mce=dont_log_ce Clears corrected events silently, no log created for CEs. | |
1725 | * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared. | |
3c079792 AK |
1726 | * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above) |
1727 | * monarchtimeout is how long to wait for other CPUs on machine | |
1728 | * check, or 0 to not wait | |
13503fa9 HS |
1729 | * mce=bootlog Log MCEs from before booting. Disabled by default on AMD. |
1730 | * mce=nobootlog Don't log MCEs from before booting. | |
1731 | */ | |
1da177e4 LT |
1732 | static int __init mcheck_enable(char *str) |
1733 | { | |
e3346fc4 | 1734 | if (*str == 0) { |
4efc0670 | 1735 | enable_p5_mce(); |
e3346fc4 BZ |
1736 | return 1; |
1737 | } | |
4efc0670 AK |
1738 | if (*str == '=') |
1739 | str++; | |
1da177e4 | 1740 | if (!strcmp(str, "off")) |
04b2b1a4 | 1741 | mce_disabled = 1; |
62fdac59 HS |
1742 | else if (!strcmp(str, "no_cmci")) |
1743 | mce_cmci_disabled = 1; | |
1744 | else if (!strcmp(str, "dont_log_ce")) | |
1745 | mce_dont_log_ce = 1; | |
1746 | else if (!strcmp(str, "ignore_ce")) | |
1747 | mce_ignore_ce = 1; | |
13503fa9 HS |
1748 | else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) |
1749 | mce_bootlog = (str[0] == 'b'); | |
3c079792 | 1750 | else if (isdigit(str[0])) { |
8c566ef5 | 1751 | get_option(&str, &tolerant); |
3c079792 AK |
1752 | if (*str == ',') { |
1753 | ++str; | |
1754 | get_option(&str, &monarch_timeout); | |
1755 | } | |
1756 | } else { | |
4efc0670 | 1757 | printk(KERN_INFO "mce argument %s ignored. Please use /sys\n", |
13503fa9 HS |
1758 | str); |
1759 | return 0; | |
1760 | } | |
9b41046c | 1761 | return 1; |
1da177e4 | 1762 | } |
4efc0670 | 1763 | __setup("mce", mcheck_enable); |
1da177e4 | 1764 | |
a2202aa2 | 1765 | int __init mcheck_init(void) |
b33a6363 | 1766 | { |
a2202aa2 YW |
1767 | mcheck_intel_therm_init(); |
1768 | ||
b33a6363 BP |
1769 | return 0; |
1770 | } | |
b33a6363 | 1771 | |
d88203d1 | 1772 | /* |
c7cece89 | 1773 | * mce_syscore: PM support |
d88203d1 | 1774 | */ |
1da177e4 | 1775 | |
973a2dd1 AK |
1776 | /* |
1777 | * Disable machine checks on suspend and shutdown. We can't really handle | |
1778 | * them later. | |
1779 | */ | |
5e09954a | 1780 | static int mce_disable_error_reporting(void) |
973a2dd1 AK |
1781 | { |
1782 | int i; | |
1783 | ||
06b7a7a5 | 1784 | for (i = 0; i < banks; i++) { |
cebe1820 | 1785 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1786 | |
cebe1820 | 1787 | if (b->init) |
a2d32bcb | 1788 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 1789 | } |
973a2dd1 AK |
1790 | return 0; |
1791 | } | |
1792 | ||
c7cece89 | 1793 | static int mce_syscore_suspend(void) |
973a2dd1 | 1794 | { |
5e09954a | 1795 | return mce_disable_error_reporting(); |
973a2dd1 AK |
1796 | } |
1797 | ||
c7cece89 | 1798 | static void mce_syscore_shutdown(void) |
973a2dd1 | 1799 | { |
f3c6ea1b | 1800 | mce_disable_error_reporting(); |
973a2dd1 AK |
1801 | } |
1802 | ||
e9eee03e IM |
1803 | /* |
1804 | * On resume clear all MCE state. Don't want to see leftovers from the BIOS. | |
1805 | * Only one CPU is active at this time, the others get re-added later using | |
1806 | * CPU hotplug: | |
1807 | */ | |
c7cece89 | 1808 | static void mce_syscore_resume(void) |
1da177e4 | 1809 | { |
5e09954a | 1810 | __mcheck_cpu_init_generic(); |
7b543a53 | 1811 | __mcheck_cpu_init_vendor(__this_cpu_ptr(&cpu_info)); |
1da177e4 LT |
1812 | } |
1813 | ||
f3c6ea1b | 1814 | static struct syscore_ops mce_syscore_ops = { |
c7cece89 HS |
1815 | .suspend = mce_syscore_suspend, |
1816 | .shutdown = mce_syscore_shutdown, | |
1817 | .resume = mce_syscore_resume, | |
f3c6ea1b RW |
1818 | }; |
1819 | ||
c7cece89 | 1820 | /* |
8a25a2fd | 1821 | * mce_device: Sysfs support |
c7cece89 HS |
1822 | */ |
1823 | ||
52d168e2 AK |
1824 | static void mce_cpu_restart(void *data) |
1825 | { | |
7b543a53 | 1826 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
33edbf02 | 1827 | return; |
5e09954a BP |
1828 | __mcheck_cpu_init_generic(); |
1829 | __mcheck_cpu_init_timer(); | |
52d168e2 AK |
1830 | } |
1831 | ||
1da177e4 | 1832 | /* Reinit MCEs after user configuration changes */ |
d88203d1 TG |
1833 | static void mce_restart(void) |
1834 | { | |
9aaef96f | 1835 | mce_timer_delete_all(); |
52d168e2 | 1836 | on_each_cpu(mce_cpu_restart, NULL, 1); |
1da177e4 LT |
1837 | } |
1838 | ||
9af43b54 | 1839 | /* Toggle features for corrected errors */ |
9aaef96f | 1840 | static void mce_disable_cmci(void *data) |
9af43b54 | 1841 | { |
7b543a53 | 1842 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
9af43b54 | 1843 | return; |
9af43b54 HS |
1844 | cmci_clear(); |
1845 | } | |
1846 | ||
1847 | static void mce_enable_ce(void *all) | |
1848 | { | |
7b543a53 | 1849 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
9af43b54 HS |
1850 | return; |
1851 | cmci_reenable(); | |
1852 | cmci_recheck(); | |
1853 | if (all) | |
5e09954a | 1854 | __mcheck_cpu_init_timer(); |
9af43b54 HS |
1855 | } |
1856 | ||
8a25a2fd | 1857 | static struct bus_type mce_subsys = { |
e9eee03e | 1858 | .name = "machinecheck", |
8a25a2fd | 1859 | .dev_name = "machinecheck", |
1da177e4 LT |
1860 | }; |
1861 | ||
8a25a2fd | 1862 | DEFINE_PER_CPU(struct device, mce_device); |
e9eee03e IM |
1863 | |
1864 | __cpuinitdata | |
1865 | void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); | |
1da177e4 | 1866 | |
8a25a2fd | 1867 | static inline struct mce_bank *attr_to_bank(struct device_attribute *attr) |
cebe1820 AK |
1868 | { |
1869 | return container_of(attr, struct mce_bank, attr); | |
1870 | } | |
0d7482e3 | 1871 | |
8a25a2fd | 1872 | static ssize_t show_bank(struct device *s, struct device_attribute *attr, |
0d7482e3 AK |
1873 | char *buf) |
1874 | { | |
cebe1820 | 1875 | return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl); |
0d7482e3 AK |
1876 | } |
1877 | ||
8a25a2fd | 1878 | static ssize_t set_bank(struct device *s, struct device_attribute *attr, |
9319cec8 | 1879 | const char *buf, size_t size) |
0d7482e3 | 1880 | { |
9319cec8 | 1881 | u64 new; |
e9eee03e | 1882 | |
9319cec8 | 1883 | if (strict_strtoull(buf, 0, &new) < 0) |
0d7482e3 | 1884 | return -EINVAL; |
e9eee03e | 1885 | |
cebe1820 | 1886 | attr_to_bank(attr)->ctl = new; |
0d7482e3 | 1887 | mce_restart(); |
e9eee03e | 1888 | |
9319cec8 | 1889 | return size; |
0d7482e3 | 1890 | } |
a98f0dd3 | 1891 | |
e9eee03e | 1892 | static ssize_t |
8a25a2fd | 1893 | show_trigger(struct device *s, struct device_attribute *attr, char *buf) |
a98f0dd3 | 1894 | { |
1020bcbc | 1895 | strcpy(buf, mce_helper); |
a98f0dd3 | 1896 | strcat(buf, "\n"); |
1020bcbc | 1897 | return strlen(mce_helper) + 1; |
a98f0dd3 AK |
1898 | } |
1899 | ||
8a25a2fd | 1900 | static ssize_t set_trigger(struct device *s, struct device_attribute *attr, |
e9eee03e | 1901 | const char *buf, size_t siz) |
a98f0dd3 AK |
1902 | { |
1903 | char *p; | |
e9eee03e | 1904 | |
1020bcbc HS |
1905 | strncpy(mce_helper, buf, sizeof(mce_helper)); |
1906 | mce_helper[sizeof(mce_helper)-1] = 0; | |
1020bcbc | 1907 | p = strchr(mce_helper, '\n'); |
e9eee03e | 1908 | |
e9084ec9 | 1909 | if (p) |
e9eee03e IM |
1910 | *p = 0; |
1911 | ||
e9084ec9 | 1912 | return strlen(mce_helper) + !!p; |
a98f0dd3 AK |
1913 | } |
1914 | ||
8a25a2fd KS |
1915 | static ssize_t set_ignore_ce(struct device *s, |
1916 | struct device_attribute *attr, | |
9af43b54 HS |
1917 | const char *buf, size_t size) |
1918 | { | |
1919 | u64 new; | |
1920 | ||
1921 | if (strict_strtoull(buf, 0, &new) < 0) | |
1922 | return -EINVAL; | |
1923 | ||
1924 | if (mce_ignore_ce ^ !!new) { | |
1925 | if (new) { | |
1926 | /* disable ce features */ | |
9aaef96f HS |
1927 | mce_timer_delete_all(); |
1928 | on_each_cpu(mce_disable_cmci, NULL, 1); | |
9af43b54 HS |
1929 | mce_ignore_ce = 1; |
1930 | } else { | |
1931 | /* enable ce features */ | |
1932 | mce_ignore_ce = 0; | |
1933 | on_each_cpu(mce_enable_ce, (void *)1, 1); | |
1934 | } | |
1935 | } | |
1936 | return size; | |
1937 | } | |
1938 | ||
8a25a2fd KS |
1939 | static ssize_t set_cmci_disabled(struct device *s, |
1940 | struct device_attribute *attr, | |
9af43b54 HS |
1941 | const char *buf, size_t size) |
1942 | { | |
1943 | u64 new; | |
1944 | ||
1945 | if (strict_strtoull(buf, 0, &new) < 0) | |
1946 | return -EINVAL; | |
1947 | ||
1948 | if (mce_cmci_disabled ^ !!new) { | |
1949 | if (new) { | |
1950 | /* disable cmci */ | |
9aaef96f | 1951 | on_each_cpu(mce_disable_cmci, NULL, 1); |
9af43b54 HS |
1952 | mce_cmci_disabled = 1; |
1953 | } else { | |
1954 | /* enable cmci */ | |
1955 | mce_cmci_disabled = 0; | |
1956 | on_each_cpu(mce_enable_ce, NULL, 1); | |
1957 | } | |
1958 | } | |
1959 | return size; | |
1960 | } | |
1961 | ||
8a25a2fd KS |
1962 | static ssize_t store_int_with_restart(struct device *s, |
1963 | struct device_attribute *attr, | |
b56f642d AK |
1964 | const char *buf, size_t size) |
1965 | { | |
8a25a2fd | 1966 | ssize_t ret = device_store_int(s, attr, buf, size); |
b56f642d AK |
1967 | mce_restart(); |
1968 | return ret; | |
1969 | } | |
1970 | ||
8a25a2fd KS |
1971 | static DEVICE_ATTR(trigger, 0644, show_trigger, set_trigger); |
1972 | static DEVICE_INT_ATTR(tolerant, 0644, tolerant); | |
1973 | static DEVICE_INT_ATTR(monarch_timeout, 0644, monarch_timeout); | |
1974 | static DEVICE_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce); | |
e9eee03e | 1975 | |
8a25a2fd KS |
1976 | static struct dev_ext_attribute dev_attr_check_interval = { |
1977 | __ATTR(check_interval, 0644, device_show_int, store_int_with_restart), | |
b56f642d AK |
1978 | &check_interval |
1979 | }; | |
e9eee03e | 1980 | |
8a25a2fd KS |
1981 | static struct dev_ext_attribute dev_attr_ignore_ce = { |
1982 | __ATTR(ignore_ce, 0644, device_show_int, set_ignore_ce), | |
9af43b54 HS |
1983 | &mce_ignore_ce |
1984 | }; | |
1985 | ||
8a25a2fd KS |
1986 | static struct dev_ext_attribute dev_attr_cmci_disabled = { |
1987 | __ATTR(cmci_disabled, 0644, device_show_int, set_cmci_disabled), | |
9af43b54 HS |
1988 | &mce_cmci_disabled |
1989 | }; | |
1990 | ||
8a25a2fd KS |
1991 | static struct device_attribute *mce_device_attrs[] = { |
1992 | &dev_attr_tolerant.attr, | |
1993 | &dev_attr_check_interval.attr, | |
1994 | &dev_attr_trigger, | |
1995 | &dev_attr_monarch_timeout.attr, | |
1996 | &dev_attr_dont_log_ce.attr, | |
1997 | &dev_attr_ignore_ce.attr, | |
1998 | &dev_attr_cmci_disabled.attr, | |
a98f0dd3 AK |
1999 | NULL |
2000 | }; | |
1da177e4 | 2001 | |
8a25a2fd | 2002 | static cpumask_var_t mce_device_initialized; |
bae19fe0 | 2003 | |
8a25a2fd KS |
2004 | /* Per cpu device init. All of the cpus still share the same ctrl bank: */ |
2005 | static __cpuinit int mce_device_create(unsigned int cpu) | |
1da177e4 | 2006 | { |
8a25a2fd | 2007 | struct device *dev = &per_cpu(mce_device, cpu); |
1da177e4 | 2008 | int err; |
b1f49f95 | 2009 | int i, j; |
92cb7612 | 2010 | |
90367556 | 2011 | if (!mce_available(&boot_cpu_data)) |
91c6d400 AK |
2012 | return -EIO; |
2013 | ||
a3301b75 | 2014 | memset(dev, 0, sizeof(struct device)); |
8a25a2fd KS |
2015 | dev->id = cpu; |
2016 | dev->bus = &mce_subsys; | |
91c6d400 | 2017 | |
8a25a2fd | 2018 | err = device_register(dev); |
d435d862 AM |
2019 | if (err) |
2020 | return err; | |
2021 | ||
8a25a2fd KS |
2022 | for (i = 0; mce_device_attrs[i]; i++) { |
2023 | err = device_create_file(dev, mce_device_attrs[i]); | |
d435d862 AM |
2024 | if (err) |
2025 | goto error; | |
2026 | } | |
b1f49f95 | 2027 | for (j = 0; j < banks; j++) { |
8a25a2fd | 2028 | err = device_create_file(dev, &mce_banks[j].attr); |
0d7482e3 AK |
2029 | if (err) |
2030 | goto error2; | |
2031 | } | |
8a25a2fd | 2032 | cpumask_set_cpu(cpu, mce_device_initialized); |
91c6d400 | 2033 | |
d435d862 | 2034 | return 0; |
0d7482e3 | 2035 | error2: |
b1f49f95 | 2036 | while (--j >= 0) |
8a25a2fd | 2037 | device_remove_file(dev, &mce_banks[j].attr); |
d435d862 | 2038 | error: |
cb491fca | 2039 | while (--i >= 0) |
8a25a2fd | 2040 | device_remove_file(dev, mce_device_attrs[i]); |
cb491fca | 2041 | |
8a25a2fd | 2042 | device_unregister(dev); |
d435d862 | 2043 | |
91c6d400 AK |
2044 | return err; |
2045 | } | |
2046 | ||
8a25a2fd | 2047 | static __cpuinit void mce_device_remove(unsigned int cpu) |
91c6d400 | 2048 | { |
8a25a2fd | 2049 | struct device *dev = &per_cpu(mce_device, cpu); |
73ca5358 SL |
2050 | int i; |
2051 | ||
8a25a2fd | 2052 | if (!cpumask_test_cpu(cpu, mce_device_initialized)) |
bae19fe0 AH |
2053 | return; |
2054 | ||
8a25a2fd KS |
2055 | for (i = 0; mce_device_attrs[i]; i++) |
2056 | device_remove_file(dev, mce_device_attrs[i]); | |
cb491fca | 2057 | |
0d7482e3 | 2058 | for (i = 0; i < banks; i++) |
8a25a2fd | 2059 | device_remove_file(dev, &mce_banks[i].attr); |
cb491fca | 2060 | |
8a25a2fd KS |
2061 | device_unregister(dev); |
2062 | cpumask_clear_cpu(cpu, mce_device_initialized); | |
91c6d400 | 2063 | } |
91c6d400 | 2064 | |
d6b75584 | 2065 | /* Make sure there are no machine checks on offlined CPUs. */ |
767df1bd | 2066 | static void __cpuinit mce_disable_cpu(void *h) |
d6b75584 | 2067 | { |
88ccbedd | 2068 | unsigned long action = *(unsigned long *)h; |
cb491fca | 2069 | int i; |
d6b75584 | 2070 | |
7b543a53 | 2071 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
d6b75584 | 2072 | return; |
767df1bd | 2073 | |
88ccbedd AK |
2074 | if (!(action & CPU_TASKS_FROZEN)) |
2075 | cmci_clear(); | |
06b7a7a5 | 2076 | for (i = 0; i < banks; i++) { |
cebe1820 | 2077 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2078 | |
cebe1820 | 2079 | if (b->init) |
a2d32bcb | 2080 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 2081 | } |
d6b75584 AK |
2082 | } |
2083 | ||
767df1bd | 2084 | static void __cpuinit mce_reenable_cpu(void *h) |
d6b75584 | 2085 | { |
88ccbedd | 2086 | unsigned long action = *(unsigned long *)h; |
e9eee03e | 2087 | int i; |
d6b75584 | 2088 | |
7b543a53 | 2089 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
d6b75584 | 2090 | return; |
e9eee03e | 2091 | |
88ccbedd AK |
2092 | if (!(action & CPU_TASKS_FROZEN)) |
2093 | cmci_reenable(); | |
06b7a7a5 | 2094 | for (i = 0; i < banks; i++) { |
cebe1820 | 2095 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2096 | |
cebe1820 | 2097 | if (b->init) |
a2d32bcb | 2098 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
06b7a7a5 | 2099 | } |
d6b75584 AK |
2100 | } |
2101 | ||
91c6d400 | 2102 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ |
e9eee03e IM |
2103 | static int __cpuinit |
2104 | mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) | |
91c6d400 AK |
2105 | { |
2106 | unsigned int cpu = (unsigned long)hcpu; | |
52d168e2 | 2107 | struct timer_list *t = &per_cpu(mce_timer, cpu); |
91c6d400 AK |
2108 | |
2109 | switch (action) { | |
bae19fe0 AH |
2110 | case CPU_ONLINE: |
2111 | case CPU_ONLINE_FROZEN: | |
8a25a2fd | 2112 | mce_device_create(cpu); |
8735728e RW |
2113 | if (threshold_cpu_callback) |
2114 | threshold_cpu_callback(action, cpu); | |
91c6d400 | 2115 | break; |
91c6d400 | 2116 | case CPU_DEAD: |
8bb78442 | 2117 | case CPU_DEAD_FROZEN: |
8735728e RW |
2118 | if (threshold_cpu_callback) |
2119 | threshold_cpu_callback(action, cpu); | |
8a25a2fd | 2120 | mce_device_remove(cpu); |
91c6d400 | 2121 | break; |
52d168e2 AK |
2122 | case CPU_DOWN_PREPARE: |
2123 | case CPU_DOWN_PREPARE_FROZEN: | |
2124 | del_timer_sync(t); | |
88ccbedd | 2125 | smp_call_function_single(cpu, mce_disable_cpu, &action, 1); |
52d168e2 AK |
2126 | break; |
2127 | case CPU_DOWN_FAILED: | |
2128 | case CPU_DOWN_FAILED_FROZEN: | |
fe5ed91d HS |
2129 | if (!mce_ignore_ce && check_interval) { |
2130 | t->expires = round_jiffies(jiffies + | |
245b2e70 | 2131 | __get_cpu_var(mce_next_interval)); |
fe5ed91d HS |
2132 | add_timer_on(t, cpu); |
2133 | } | |
88ccbedd AK |
2134 | smp_call_function_single(cpu, mce_reenable_cpu, &action, 1); |
2135 | break; | |
2136 | case CPU_POST_DEAD: | |
2137 | /* intentionally ignoring frozen here */ | |
2138 | cmci_rediscover(cpu); | |
52d168e2 | 2139 | break; |
91c6d400 | 2140 | } |
bae19fe0 | 2141 | return NOTIFY_OK; |
91c6d400 AK |
2142 | } |
2143 | ||
1e35669d | 2144 | static struct notifier_block mce_cpu_notifier __cpuinitdata = { |
91c6d400 AK |
2145 | .notifier_call = mce_cpu_callback, |
2146 | }; | |
2147 | ||
cebe1820 | 2148 | static __init void mce_init_banks(void) |
0d7482e3 AK |
2149 | { |
2150 | int i; | |
2151 | ||
0d7482e3 | 2152 | for (i = 0; i < banks; i++) { |
cebe1820 | 2153 | struct mce_bank *b = &mce_banks[i]; |
8a25a2fd | 2154 | struct device_attribute *a = &b->attr; |
e9eee03e | 2155 | |
a07e4156 | 2156 | sysfs_attr_init(&a->attr); |
cebe1820 AK |
2157 | a->attr.name = b->attrname; |
2158 | snprintf(b->attrname, ATTR_LEN, "bank%d", i); | |
e9eee03e IM |
2159 | |
2160 | a->attr.mode = 0644; | |
2161 | a->show = show_bank; | |
2162 | a->store = set_bank; | |
0d7482e3 | 2163 | } |
0d7482e3 AK |
2164 | } |
2165 | ||
5e09954a | 2166 | static __init int mcheck_init_device(void) |
91c6d400 AK |
2167 | { |
2168 | int err; | |
2169 | int i = 0; | |
2170 | ||
1da177e4 LT |
2171 | if (!mce_available(&boot_cpu_data)) |
2172 | return -EIO; | |
0d7482e3 | 2173 | |
8a25a2fd | 2174 | zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL); |
996867d0 | 2175 | |
cebe1820 | 2176 | mce_init_banks(); |
0d7482e3 | 2177 | |
8a25a2fd | 2178 | err = subsys_system_register(&mce_subsys, NULL); |
d435d862 AM |
2179 | if (err) |
2180 | return err; | |
91c6d400 AK |
2181 | |
2182 | for_each_online_cpu(i) { | |
8a25a2fd | 2183 | err = mce_device_create(i); |
d435d862 AM |
2184 | if (err) |
2185 | return err; | |
91c6d400 AK |
2186 | } |
2187 | ||
f3c6ea1b | 2188 | register_syscore_ops(&mce_syscore_ops); |
be6b5a35 | 2189 | register_hotcpu_notifier(&mce_cpu_notifier); |
93b62c3c HS |
2190 | |
2191 | /* register character device /dev/mcelog */ | |
2192 | misc_register(&mce_chrdev_device); | |
e9eee03e | 2193 | |
1da177e4 | 2194 | return err; |
1da177e4 | 2195 | } |
5e09954a | 2196 | device_initcall(mcheck_init_device); |
a988d334 | 2197 | |
d7c3c9a6 AK |
2198 | /* |
2199 | * Old style boot options parsing. Only for compatibility. | |
2200 | */ | |
2201 | static int __init mcheck_disable(char *str) | |
2202 | { | |
2203 | mce_disabled = 1; | |
2204 | return 1; | |
2205 | } | |
2206 | __setup("nomce", mcheck_disable); | |
a988d334 | 2207 | |
5be9ed25 HY |
2208 | #ifdef CONFIG_DEBUG_FS |
2209 | struct dentry *mce_get_debugfs_dir(void) | |
a988d334 | 2210 | { |
5be9ed25 | 2211 | static struct dentry *dmce; |
a988d334 | 2212 | |
5be9ed25 HY |
2213 | if (!dmce) |
2214 | dmce = debugfs_create_dir("mce", NULL); | |
a988d334 | 2215 | |
5be9ed25 HY |
2216 | return dmce; |
2217 | } | |
a988d334 | 2218 | |
bf783f9f HY |
2219 | static void mce_reset(void) |
2220 | { | |
2221 | cpu_missing = 0; | |
2222 | atomic_set(&mce_fake_paniced, 0); | |
2223 | atomic_set(&mce_executing, 0); | |
2224 | atomic_set(&mce_callin, 0); | |
2225 | atomic_set(&global_nwo, 0); | |
2226 | } | |
a988d334 | 2227 | |
bf783f9f HY |
2228 | static int fake_panic_get(void *data, u64 *val) |
2229 | { | |
2230 | *val = fake_panic; | |
2231 | return 0; | |
a988d334 IM |
2232 | } |
2233 | ||
bf783f9f | 2234 | static int fake_panic_set(void *data, u64 val) |
a988d334 | 2235 | { |
bf783f9f HY |
2236 | mce_reset(); |
2237 | fake_panic = val; | |
2238 | return 0; | |
a988d334 | 2239 | } |
a988d334 | 2240 | |
bf783f9f HY |
2241 | DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get, |
2242 | fake_panic_set, "%llu\n"); | |
d7c3c9a6 | 2243 | |
5e09954a | 2244 | static int __init mcheck_debugfs_init(void) |
d7c3c9a6 | 2245 | { |
bf783f9f HY |
2246 | struct dentry *dmce, *ffake_panic; |
2247 | ||
2248 | dmce = mce_get_debugfs_dir(); | |
2249 | if (!dmce) | |
2250 | return -ENOMEM; | |
2251 | ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL, | |
2252 | &fake_panic_fops); | |
2253 | if (!ffake_panic) | |
2254 | return -ENOMEM; | |
2255 | ||
2256 | return 0; | |
d7c3c9a6 | 2257 | } |
5e09954a | 2258 | late_initcall(mcheck_debugfs_init); |
5be9ed25 | 2259 | #endif |