Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Machine check handler. | |
e9eee03e | 3 | * |
1da177e4 | 4 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. |
d88203d1 TG |
5 | * Rest from unknown author(s). |
6 | * 2004 Andi Kleen. Rewrote most of it. | |
b79109c3 AK |
7 | * Copyright 2008 Intel Corporation |
8 | * Author: Andi Kleen | |
1da177e4 | 9 | */ |
c767a54b JP |
10 | |
11 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
12 | ||
e9eee03e IM |
13 | #include <linux/thread_info.h> |
14 | #include <linux/capability.h> | |
15 | #include <linux/miscdevice.h> | |
16 | #include <linux/ratelimit.h> | |
17 | #include <linux/kallsyms.h> | |
18 | #include <linux/rcupdate.h> | |
e9eee03e | 19 | #include <linux/kobject.h> |
14a02530 | 20 | #include <linux/uaccess.h> |
e9eee03e IM |
21 | #include <linux/kdebug.h> |
22 | #include <linux/kernel.h> | |
23 | #include <linux/percpu.h> | |
1da177e4 | 24 | #include <linux/string.h> |
8a25a2fd | 25 | #include <linux/device.h> |
f3c6ea1b | 26 | #include <linux/syscore_ops.h> |
3c079792 | 27 | #include <linux/delay.h> |
8c566ef5 | 28 | #include <linux/ctype.h> |
e9eee03e | 29 | #include <linux/sched.h> |
0d7482e3 | 30 | #include <linux/sysfs.h> |
e9eee03e | 31 | #include <linux/types.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
e9eee03e IM |
33 | #include <linux/init.h> |
34 | #include <linux/kmod.h> | |
35 | #include <linux/poll.h> | |
3c079792 | 36 | #include <linux/nmi.h> |
e9eee03e | 37 | #include <linux/cpu.h> |
14a02530 | 38 | #include <linux/smp.h> |
e9eee03e | 39 | #include <linux/fs.h> |
9b1beaf2 | 40 | #include <linux/mm.h> |
5be9ed25 | 41 | #include <linux/debugfs.h> |
b77e70bf | 42 | #include <linux/irq_work.h> |
69c60c88 | 43 | #include <linux/export.h> |
e9eee03e | 44 | |
d88203d1 | 45 | #include <asm/processor.h> |
95927475 | 46 | #include <asm/traps.h> |
375074cc | 47 | #include <asm/tlbflush.h> |
e9eee03e IM |
48 | #include <asm/mce.h> |
49 | #include <asm/msr.h> | |
1da177e4 | 50 | |
bd19a5e6 | 51 | #include "mce-internal.h" |
711c2e48 | 52 | |
93b62c3c | 53 | static DEFINE_MUTEX(mce_chrdev_read_mutex); |
2aa2b50d | 54 | |
f56e8a07 | 55 | #define rcu_dereference_check_mce(p) \ |
ec8c27e0 | 56 | rcu_dereference_index_check((p), \ |
f56e8a07 | 57 | rcu_read_lock_sched_held() || \ |
93b62c3c | 58 | lockdep_is_held(&mce_chrdev_read_mutex)) |
f56e8a07 | 59 | |
8968f9d3 HS |
60 | #define CREATE_TRACE_POINTS |
61 | #include <trace/events/mce.h> | |
62 | ||
3f2f0680 | 63 | #define SPINUNIT 100 /* 100ns */ |
3c079792 | 64 | |
01ca79f1 AK |
65 | DEFINE_PER_CPU(unsigned, mce_exception_count); |
66 | ||
1462594b | 67 | struct mce_bank *mce_banks __read_mostly; |
bf80bbd7 | 68 | struct mce_vendor_flags mce_flags __read_mostly; |
cebe1820 | 69 | |
d203f0b8 | 70 | struct mca_config mca_cfg __read_mostly = { |
84c2559d | 71 | .bootlog = -1, |
d203f0b8 BP |
72 | /* |
73 | * Tolerant levels: | |
74 | * 0: always panic on uncorrected errors, log corrected errors | |
75 | * 1: panic or SIGBUS on uncorrected errors, log corrected errors | |
76 | * 2: SIGBUS or log uncorrected errors (if possible), log corr. errors | |
77 | * 3: never panic or SIGBUS, log all errors (for testing only) | |
78 | */ | |
84c2559d BP |
79 | .tolerant = 1, |
80 | .monarch_timeout = -1 | |
d203f0b8 BP |
81 | }; |
82 | ||
1020bcbc HS |
83 | /* User mode helper program triggered by machine check event */ |
84 | static unsigned long mce_need_notify; | |
85 | static char mce_helper[128]; | |
86 | static char *mce_helper_argv[2] = { mce_helper, NULL }; | |
1da177e4 | 87 | |
93b62c3c HS |
88 | static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait); |
89 | ||
3c079792 AK |
90 | static DEFINE_PER_CPU(struct mce, mces_seen); |
91 | static int cpu_missing; | |
92 | ||
0644414e NR |
93 | /* |
94 | * MCA banks polled by the period polling timer for corrected events. | |
95 | * With Intel CMCI, this only has MCA banks which do not support CMCI (if any). | |
96 | */ | |
ee031c31 AK |
97 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { |
98 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL | |
99 | }; | |
100 | ||
c3d1fb56 NR |
101 | /* |
102 | * MCA banks controlled through firmware first for corrected errors. | |
103 | * This is a global list of banks for which we won't enable CMCI and we | |
104 | * won't poll. Firmware controls these banks and is responsible for | |
105 | * reporting corrected errors through GHES. Uncorrected/recoverable | |
106 | * errors are still notified through a machine check. | |
107 | */ | |
108 | mce_banks_t mce_banks_ce_disabled; | |
109 | ||
9b1beaf2 AK |
110 | static DEFINE_PER_CPU(struct work_struct, mce_work); |
111 | ||
61b0fccd TL |
112 | static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs); |
113 | ||
3653ada5 BP |
114 | /* |
115 | * CPU/chipset specific EDAC code can register a notifier call here to print | |
116 | * MCE errors in a human-readable form. | |
117 | */ | |
83737691 | 118 | static ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain); |
3653ada5 | 119 | |
b5f2fa4e AK |
120 | /* Do initial initialization of a struct mce */ |
121 | void mce_setup(struct mce *m) | |
122 | { | |
123 | memset(m, 0, sizeof(struct mce)); | |
d620c67f | 124 | m->cpu = m->extcpu = smp_processor_id(); |
b5f2fa4e | 125 | rdtscll(m->tsc); |
8ee08347 AK |
126 | /* We hope get_seconds stays lockless */ |
127 | m->time = get_seconds(); | |
128 | m->cpuvendor = boot_cpu_data.x86_vendor; | |
129 | m->cpuid = cpuid_eax(1); | |
8ee08347 | 130 | m->socketid = cpu_data(m->extcpu).phys_proc_id; |
8ee08347 AK |
131 | m->apicid = cpu_data(m->extcpu).initial_apicid; |
132 | rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap); | |
b5f2fa4e AK |
133 | } |
134 | ||
ea149b36 AK |
135 | DEFINE_PER_CPU(struct mce, injectm); |
136 | EXPORT_PER_CPU_SYMBOL_GPL(injectm); | |
137 | ||
1da177e4 LT |
138 | /* |
139 | * Lockless MCE logging infrastructure. | |
140 | * This avoids deadlocks on printk locks without having to break locks. Also | |
141 | * separate MCEs from kernel messages to avoid bogus bug reports. | |
142 | */ | |
143 | ||
231fd906 | 144 | static struct mce_log mcelog = { |
f6fb0ac0 AK |
145 | .signature = MCE_LOG_SIGNATURE, |
146 | .len = MCE_LOG_LEN, | |
147 | .recordlen = sizeof(struct mce), | |
d88203d1 | 148 | }; |
1da177e4 LT |
149 | |
150 | void mce_log(struct mce *mce) | |
151 | { | |
152 | unsigned next, entry; | |
e9eee03e | 153 | |
8968f9d3 HS |
154 | /* Emit the trace record: */ |
155 | trace_mce_record(mce); | |
156 | ||
a2413d8b | 157 | atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, mce); |
f0cb5452 | 158 | |
1da177e4 | 159 | mce->finished = 0; |
7644143c | 160 | wmb(); |
1da177e4 | 161 | for (;;) { |
f56e8a07 | 162 | entry = rcu_dereference_check_mce(mcelog.next); |
673242c1 | 163 | for (;;) { |
696e409d | 164 | |
e9eee03e IM |
165 | /* |
166 | * When the buffer fills up discard new entries. | |
167 | * Assume that the earlier errors are the more | |
168 | * interesting ones: | |
169 | */ | |
673242c1 | 170 | if (entry >= MCE_LOG_LEN) { |
14a02530 HS |
171 | set_bit(MCE_OVERFLOW, |
172 | (unsigned long *)&mcelog.flags); | |
673242c1 AK |
173 | return; |
174 | } | |
e9eee03e | 175 | /* Old left over entry. Skip: */ |
673242c1 AK |
176 | if (mcelog.entry[entry].finished) { |
177 | entry++; | |
178 | continue; | |
179 | } | |
7644143c | 180 | break; |
1da177e4 | 181 | } |
1da177e4 LT |
182 | smp_rmb(); |
183 | next = entry + 1; | |
184 | if (cmpxchg(&mcelog.next, entry, next) == entry) | |
185 | break; | |
186 | } | |
187 | memcpy(mcelog.entry + entry, mce, sizeof(struct mce)); | |
7644143c | 188 | wmb(); |
1da177e4 | 189 | mcelog.entry[entry].finished = 1; |
7644143c | 190 | wmb(); |
1da177e4 | 191 | |
a0189c70 | 192 | mce->finished = 1; |
1020bcbc | 193 | set_bit(0, &mce_need_notify); |
1da177e4 LT |
194 | } |
195 | ||
09371957 BP |
196 | static void drain_mcelog_buffer(void) |
197 | { | |
198 | unsigned int next, i, prev = 0; | |
199 | ||
b11e3d78 | 200 | next = ACCESS_ONCE(mcelog.next); |
09371957 BP |
201 | |
202 | do { | |
203 | struct mce *m; | |
204 | ||
205 | /* drain what was logged during boot */ | |
206 | for (i = prev; i < next; i++) { | |
207 | unsigned long start = jiffies; | |
208 | unsigned retries = 1; | |
209 | ||
210 | m = &mcelog.entry[i]; | |
211 | ||
212 | while (!m->finished) { | |
213 | if (time_after_eq(jiffies, start + 2*retries)) | |
214 | retries++; | |
215 | ||
216 | cpu_relax(); | |
217 | ||
218 | if (!m->finished && retries >= 4) { | |
c767a54b | 219 | pr_err("skipping error being logged currently!\n"); |
09371957 BP |
220 | break; |
221 | } | |
222 | } | |
223 | smp_rmb(); | |
224 | atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m); | |
225 | } | |
226 | ||
227 | memset(mcelog.entry + prev, 0, (next - prev) * sizeof(*m)); | |
228 | prev = next; | |
229 | next = cmpxchg(&mcelog.next, prev, 0); | |
230 | } while (next != prev); | |
231 | } | |
232 | ||
233 | ||
3653ada5 BP |
234 | void mce_register_decode_chain(struct notifier_block *nb) |
235 | { | |
236 | atomic_notifier_chain_register(&x86_mce_decoder_chain, nb); | |
09371957 | 237 | drain_mcelog_buffer(); |
3653ada5 BP |
238 | } |
239 | EXPORT_SYMBOL_GPL(mce_register_decode_chain); | |
240 | ||
241 | void mce_unregister_decode_chain(struct notifier_block *nb) | |
242 | { | |
243 | atomic_notifier_chain_unregister(&x86_mce_decoder_chain, nb); | |
244 | } | |
245 | EXPORT_SYMBOL_GPL(mce_unregister_decode_chain); | |
246 | ||
77e26cca | 247 | static void print_mce(struct mce *m) |
1da177e4 | 248 | { |
dffa4b2f BP |
249 | int ret = 0; |
250 | ||
a2d7b0d4 | 251 | pr_emerg(HW_ERR "CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n", |
d620c67f | 252 | m->extcpu, m->mcgstatus, m->bank, m->status); |
f436f8bb | 253 | |
65ea5b03 | 254 | if (m->ip) { |
a2d7b0d4 | 255 | pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ", |
f436f8bb IM |
256 | !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", |
257 | m->cs, m->ip); | |
258 | ||
1da177e4 | 259 | if (m->cs == __KERNEL_CS) |
65ea5b03 | 260 | print_symbol("{%s}", m->ip); |
f436f8bb | 261 | pr_cont("\n"); |
1da177e4 | 262 | } |
f436f8bb | 263 | |
a2d7b0d4 | 264 | pr_emerg(HW_ERR "TSC %llx ", m->tsc); |
1da177e4 | 265 | if (m->addr) |
f436f8bb | 266 | pr_cont("ADDR %llx ", m->addr); |
1da177e4 | 267 | if (m->misc) |
f436f8bb | 268 | pr_cont("MISC %llx ", m->misc); |
549d042d | 269 | |
f436f8bb | 270 | pr_cont("\n"); |
506ed6b5 AK |
271 | /* |
272 | * Note this output is parsed by external tools and old fields | |
273 | * should not be changed. | |
274 | */ | |
881e23e5 | 275 | pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n", |
506ed6b5 AK |
276 | m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid, |
277 | cpu_data(m->extcpu).microcode); | |
f436f8bb IM |
278 | |
279 | /* | |
280 | * Print out human-readable details about the MCE error, | |
fb253195 | 281 | * (if the CPU has an implementation for that) |
f436f8bb | 282 | */ |
dffa4b2f BP |
283 | ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m); |
284 | if (ret == NOTIFY_STOP) | |
285 | return; | |
286 | ||
287 | pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n"); | |
86503560 AK |
288 | } |
289 | ||
f94b61c2 AK |
290 | #define PANIC_TIMEOUT 5 /* 5 seconds */ |
291 | ||
c7c9b392 | 292 | static atomic_t mce_panicked; |
f94b61c2 | 293 | |
bf783f9f | 294 | static int fake_panic; |
c7c9b392 | 295 | static atomic_t mce_fake_panicked; |
bf783f9f | 296 | |
f94b61c2 AK |
297 | /* Panic in progress. Enable interrupts and wait for final IPI */ |
298 | static void wait_for_panic(void) | |
299 | { | |
300 | long timeout = PANIC_TIMEOUT*USEC_PER_SEC; | |
f436f8bb | 301 | |
f94b61c2 AK |
302 | preempt_disable(); |
303 | local_irq_enable(); | |
304 | while (timeout-- > 0) | |
305 | udelay(1); | |
29b0f591 | 306 | if (panic_timeout == 0) |
7af19e4a | 307 | panic_timeout = mca_cfg.panic_timeout; |
f94b61c2 AK |
308 | panic("Panicing machine check CPU died"); |
309 | } | |
310 | ||
6c80f87e | 311 | static void mce_panic(const char *msg, struct mce *final, char *exp) |
d88203d1 | 312 | { |
482908b4 | 313 | int i, apei_err = 0; |
e02e68d3 | 314 | |
bf783f9f HY |
315 | if (!fake_panic) { |
316 | /* | |
317 | * Make sure only one CPU runs in machine check panic | |
318 | */ | |
c7c9b392 | 319 | if (atomic_inc_return(&mce_panicked) > 1) |
bf783f9f HY |
320 | wait_for_panic(); |
321 | barrier(); | |
f94b61c2 | 322 | |
bf783f9f HY |
323 | bust_spinlocks(1); |
324 | console_verbose(); | |
325 | } else { | |
326 | /* Don't log too much for fake panic */ | |
c7c9b392 | 327 | if (atomic_inc_return(&mce_fake_panicked) > 1) |
bf783f9f HY |
328 | return; |
329 | } | |
a0189c70 | 330 | /* First print corrected ones that are still unlogged */ |
1da177e4 | 331 | for (i = 0; i < MCE_LOG_LEN; i++) { |
a0189c70 | 332 | struct mce *m = &mcelog.entry[i]; |
77e26cca HS |
333 | if (!(m->status & MCI_STATUS_VAL)) |
334 | continue; | |
482908b4 | 335 | if (!(m->status & MCI_STATUS_UC)) { |
77e26cca | 336 | print_mce(m); |
482908b4 HY |
337 | if (!apei_err) |
338 | apei_err = apei_write_mce(m); | |
339 | } | |
a0189c70 AK |
340 | } |
341 | /* Now print uncorrected but with the final one last */ | |
342 | for (i = 0; i < MCE_LOG_LEN; i++) { | |
343 | struct mce *m = &mcelog.entry[i]; | |
344 | if (!(m->status & MCI_STATUS_VAL)) | |
1da177e4 | 345 | continue; |
77e26cca HS |
346 | if (!(m->status & MCI_STATUS_UC)) |
347 | continue; | |
482908b4 | 348 | if (!final || memcmp(m, final, sizeof(struct mce))) { |
77e26cca | 349 | print_mce(m); |
482908b4 HY |
350 | if (!apei_err) |
351 | apei_err = apei_write_mce(m); | |
352 | } | |
1da177e4 | 353 | } |
482908b4 | 354 | if (final) { |
77e26cca | 355 | print_mce(final); |
482908b4 HY |
356 | if (!apei_err) |
357 | apei_err = apei_write_mce(final); | |
358 | } | |
3c079792 | 359 | if (cpu_missing) |
a2d7b0d4 | 360 | pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n"); |
bd19a5e6 | 361 | if (exp) |
a2d7b0d4 | 362 | pr_emerg(HW_ERR "Machine check: %s\n", exp); |
bf783f9f HY |
363 | if (!fake_panic) { |
364 | if (panic_timeout == 0) | |
7af19e4a | 365 | panic_timeout = mca_cfg.panic_timeout; |
bf783f9f HY |
366 | panic(msg); |
367 | } else | |
a2d7b0d4 | 368 | pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg); |
d88203d1 | 369 | } |
1da177e4 | 370 | |
ea149b36 AK |
371 | /* Support code for software error injection */ |
372 | ||
373 | static int msr_to_offset(u32 msr) | |
374 | { | |
0a3aee0d | 375 | unsigned bank = __this_cpu_read(injectm.bank); |
f436f8bb | 376 | |
84c2559d | 377 | if (msr == mca_cfg.rip_msr) |
ea149b36 | 378 | return offsetof(struct mce, ip); |
a2d32bcb | 379 | if (msr == MSR_IA32_MCx_STATUS(bank)) |
ea149b36 | 380 | return offsetof(struct mce, status); |
a2d32bcb | 381 | if (msr == MSR_IA32_MCx_ADDR(bank)) |
ea149b36 | 382 | return offsetof(struct mce, addr); |
a2d32bcb | 383 | if (msr == MSR_IA32_MCx_MISC(bank)) |
ea149b36 AK |
384 | return offsetof(struct mce, misc); |
385 | if (msr == MSR_IA32_MCG_STATUS) | |
386 | return offsetof(struct mce, mcgstatus); | |
387 | return -1; | |
388 | } | |
389 | ||
5f8c1a54 AK |
390 | /* MSR access wrappers used for error injection */ |
391 | static u64 mce_rdmsrl(u32 msr) | |
392 | { | |
393 | u64 v; | |
11868a2d | 394 | |
0a3aee0d | 395 | if (__this_cpu_read(injectm.finished)) { |
ea149b36 | 396 | int offset = msr_to_offset(msr); |
11868a2d | 397 | |
ea149b36 AK |
398 | if (offset < 0) |
399 | return 0; | |
89cbc767 | 400 | return *(u64 *)((char *)this_cpu_ptr(&injectm) + offset); |
ea149b36 | 401 | } |
11868a2d IM |
402 | |
403 | if (rdmsrl_safe(msr, &v)) { | |
404 | WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr); | |
405 | /* | |
406 | * Return zero in case the access faulted. This should | |
407 | * not happen normally but can happen if the CPU does | |
408 | * something weird, or if the code is buggy. | |
409 | */ | |
410 | v = 0; | |
411 | } | |
412 | ||
5f8c1a54 AK |
413 | return v; |
414 | } | |
415 | ||
416 | static void mce_wrmsrl(u32 msr, u64 v) | |
417 | { | |
0a3aee0d | 418 | if (__this_cpu_read(injectm.finished)) { |
ea149b36 | 419 | int offset = msr_to_offset(msr); |
11868a2d | 420 | |
ea149b36 | 421 | if (offset >= 0) |
89cbc767 | 422 | *(u64 *)((char *)this_cpu_ptr(&injectm) + offset) = v; |
ea149b36 AK |
423 | return; |
424 | } | |
5f8c1a54 AK |
425 | wrmsrl(msr, v); |
426 | } | |
427 | ||
b8325c5b HS |
428 | /* |
429 | * Collect all global (w.r.t. this processor) status about this machine | |
430 | * check into our "mce" struct so that we can use it later to assess | |
431 | * the severity of the problem as we read per-bank specific details. | |
432 | */ | |
433 | static inline void mce_gather_info(struct mce *m, struct pt_regs *regs) | |
434 | { | |
435 | mce_setup(m); | |
436 | ||
437 | m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); | |
438 | if (regs) { | |
439 | /* | |
440 | * Get the address of the instruction at the time of | |
441 | * the machine check error. | |
442 | */ | |
443 | if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) { | |
444 | m->ip = regs->ip; | |
445 | m->cs = regs->cs; | |
a129a7c8 AK |
446 | |
447 | /* | |
448 | * When in VM86 mode make the cs look like ring 3 | |
449 | * always. This is a lie, but it's better than passing | |
450 | * the additional vm86 bit around everywhere. | |
451 | */ | |
452 | if (v8086_mode(regs)) | |
453 | m->cs |= 3; | |
b8325c5b HS |
454 | } |
455 | /* Use accurate RIP reporting if available. */ | |
84c2559d BP |
456 | if (mca_cfg.rip_msr) |
457 | m->ip = mce_rdmsrl(mca_cfg.rip_msr); | |
b8325c5b HS |
458 | } |
459 | } | |
460 | ||
9b1beaf2 AK |
461 | /* |
462 | * Simple lockless ring to communicate PFNs from the exception handler with the | |
463 | * process context work function. This is vastly simplified because there's | |
464 | * only a single reader and a single writer. | |
465 | */ | |
466 | #define MCE_RING_SIZE 16 /* we use one entry less */ | |
467 | ||
468 | struct mce_ring { | |
469 | unsigned short start; | |
470 | unsigned short end; | |
471 | unsigned long ring[MCE_RING_SIZE]; | |
472 | }; | |
473 | static DEFINE_PER_CPU(struct mce_ring, mce_ring); | |
474 | ||
475 | /* Runs with CPU affinity in workqueue */ | |
476 | static int mce_ring_empty(void) | |
477 | { | |
89cbc767 | 478 | struct mce_ring *r = this_cpu_ptr(&mce_ring); |
9b1beaf2 AK |
479 | |
480 | return r->start == r->end; | |
481 | } | |
482 | ||
483 | static int mce_ring_get(unsigned long *pfn) | |
484 | { | |
485 | struct mce_ring *r; | |
486 | int ret = 0; | |
487 | ||
488 | *pfn = 0; | |
489 | get_cpu(); | |
89cbc767 | 490 | r = this_cpu_ptr(&mce_ring); |
9b1beaf2 AK |
491 | if (r->start == r->end) |
492 | goto out; | |
493 | *pfn = r->ring[r->start]; | |
494 | r->start = (r->start + 1) % MCE_RING_SIZE; | |
495 | ret = 1; | |
496 | out: | |
497 | put_cpu(); | |
498 | return ret; | |
499 | } | |
500 | ||
501 | /* Always runs in MCE context with preempt off */ | |
502 | static int mce_ring_add(unsigned long pfn) | |
503 | { | |
89cbc767 | 504 | struct mce_ring *r = this_cpu_ptr(&mce_ring); |
9b1beaf2 AK |
505 | unsigned next; |
506 | ||
507 | next = (r->end + 1) % MCE_RING_SIZE; | |
508 | if (next == r->start) | |
509 | return -1; | |
510 | r->ring[r->end] = pfn; | |
511 | wmb(); | |
512 | r->end = next; | |
513 | return 0; | |
514 | } | |
515 | ||
88ccbedd | 516 | int mce_available(struct cpuinfo_x86 *c) |
1da177e4 | 517 | { |
1462594b | 518 | if (mca_cfg.disabled) |
5b4408fd | 519 | return 0; |
3d1712c9 | 520 | return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); |
1da177e4 LT |
521 | } |
522 | ||
9b1beaf2 AK |
523 | static void mce_schedule_work(void) |
524 | { | |
4d899be5 | 525 | if (!mce_ring_empty()) |
89cbc767 | 526 | schedule_work(this_cpu_ptr(&mce_work)); |
9b1beaf2 AK |
527 | } |
528 | ||
83737691 | 529 | static DEFINE_PER_CPU(struct irq_work, mce_irq_work); |
b77e70bf HS |
530 | |
531 | static void mce_irq_work_cb(struct irq_work *entry) | |
ccc3c319 | 532 | { |
9ff36ee9 | 533 | mce_notify_irq(); |
9b1beaf2 | 534 | mce_schedule_work(); |
ccc3c319 | 535 | } |
ccc3c319 AK |
536 | |
537 | static void mce_report_event(struct pt_regs *regs) | |
538 | { | |
539 | if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) { | |
9ff36ee9 | 540 | mce_notify_irq(); |
9b1beaf2 AK |
541 | /* |
542 | * Triggering the work queue here is just an insurance | |
543 | * policy in case the syscall exit notify handler | |
544 | * doesn't run soon enough or ends up running on the | |
545 | * wrong CPU (can happen when audit sleeps) | |
546 | */ | |
547 | mce_schedule_work(); | |
ccc3c319 AK |
548 | return; |
549 | } | |
550 | ||
89cbc767 | 551 | irq_work_queue(this_cpu_ptr(&mce_irq_work)); |
ccc3c319 AK |
552 | } |
553 | ||
85f92694 TL |
554 | /* |
555 | * Read ADDR and MISC registers. | |
556 | */ | |
557 | static void mce_read_aux(struct mce *m, int i) | |
558 | { | |
559 | if (m->status & MCI_STATUS_MISCV) | |
560 | m->misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i)); | |
561 | if (m->status & MCI_STATUS_ADDRV) { | |
562 | m->addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i)); | |
563 | ||
564 | /* | |
565 | * Mask the reported address by the reported granularity. | |
566 | */ | |
1462594b | 567 | if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) { |
85f92694 TL |
568 | u8 shift = MCI_MISC_ADDR_LSB(m->misc); |
569 | m->addr >>= shift; | |
570 | m->addr <<= shift; | |
571 | } | |
572 | } | |
573 | } | |
574 | ||
fa92c586 CY |
575 | static bool memory_error(struct mce *m) |
576 | { | |
577 | struct cpuinfo_x86 *c = &boot_cpu_data; | |
578 | ||
579 | if (c->x86_vendor == X86_VENDOR_AMD) { | |
580 | /* | |
581 | * coming soon | |
582 | */ | |
583 | return false; | |
584 | } else if (c->x86_vendor == X86_VENDOR_INTEL) { | |
585 | /* | |
586 | * Intel SDM Volume 3B - 15.9.2 Compound Error Codes | |
587 | * | |
588 | * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for | |
589 | * indicating a memory error. Bit 8 is used for indicating a | |
590 | * cache hierarchy error. The combination of bit 2 and bit 3 | |
591 | * is used for indicating a `generic' cache hierarchy error | |
592 | * But we can't just blindly check the above bits, because if | |
593 | * bit 11 is set, then it is a bus/interconnect error - and | |
594 | * either way the above bits just gives more detail on what | |
595 | * bus/interconnect error happened. Note that bit 12 can be | |
596 | * ignored, as it's the "filter" bit. | |
597 | */ | |
598 | return (m->status & 0xef80) == BIT(7) || | |
599 | (m->status & 0xef00) == BIT(8) || | |
600 | (m->status & 0xeffc) == 0xc; | |
601 | } | |
602 | ||
603 | return false; | |
604 | } | |
605 | ||
ca84f696 AK |
606 | DEFINE_PER_CPU(unsigned, mce_poll_count); |
607 | ||
d88203d1 | 608 | /* |
b79109c3 AK |
609 | * Poll for corrected events or events that happened before reset. |
610 | * Those are just logged through /dev/mcelog. | |
611 | * | |
612 | * This is executed in standard interrupt context. | |
ed7290d0 AK |
613 | * |
614 | * Note: spec recommends to panic for fatal unsignalled | |
615 | * errors here. However this would be quite problematic -- | |
616 | * we would need to reimplement the Monarch handling and | |
617 | * it would mess up the exclusion between exception handler | |
618 | * and poll hander -- * so we skip this for now. | |
619 | * These cases should not happen anyways, or only when the CPU | |
620 | * is already totally * confused. In this case it's likely it will | |
621 | * not fully execute the machine check handler either. | |
b79109c3 | 622 | */ |
3f2f0680 | 623 | bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b) |
b79109c3 | 624 | { |
3f2f0680 | 625 | bool error_logged = false; |
b79109c3 | 626 | struct mce m; |
fa92c586 | 627 | int severity; |
b79109c3 AK |
628 | int i; |
629 | ||
c6ae41e7 | 630 | this_cpu_inc(mce_poll_count); |
ca84f696 | 631 | |
b8325c5b | 632 | mce_gather_info(&m, NULL); |
b79109c3 | 633 | |
d203f0b8 | 634 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 635 | if (!mce_banks[i].ctl || !test_bit(i, *b)) |
b79109c3 AK |
636 | continue; |
637 | ||
638 | m.misc = 0; | |
639 | m.addr = 0; | |
640 | m.bank = i; | |
641 | m.tsc = 0; | |
642 | ||
643 | barrier(); | |
a2d32bcb | 644 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
b79109c3 AK |
645 | if (!(m.status & MCI_STATUS_VAL)) |
646 | continue; | |
647 | ||
3f2f0680 | 648 | |
b79109c3 | 649 | /* |
ed7290d0 AK |
650 | * Uncorrected or signalled events are handled by the exception |
651 | * handler when it is enabled, so don't process those here. | |
b79109c3 AK |
652 | * |
653 | * TBD do the same check for MCI_STATUS_EN here? | |
654 | */ | |
ed7290d0 | 655 | if (!(flags & MCP_UC) && |
1462594b | 656 | (m.status & (mca_cfg.ser ? MCI_STATUS_S : MCI_STATUS_UC))) |
b79109c3 AK |
657 | continue; |
658 | ||
85f92694 | 659 | mce_read_aux(&m, i); |
b79109c3 AK |
660 | |
661 | if (!(flags & MCP_TIMESTAMP)) | |
662 | m.tsc = 0; | |
fa92c586 CY |
663 | |
664 | severity = mce_severity(&m, mca_cfg.tolerant, NULL, false); | |
665 | ||
666 | /* | |
667 | * In the cases where we don't have a valid address after all, | |
668 | * do not add it into the ring buffer. | |
669 | */ | |
670 | if (severity == MCE_DEFERRED_SEVERITY && memory_error(&m)) { | |
671 | if (m.status & MCI_STATUS_ADDRV) { | |
672 | mce_ring_add(m.addr >> PAGE_SHIFT); | |
673 | mce_schedule_work(); | |
674 | } | |
675 | } | |
676 | ||
b79109c3 AK |
677 | /* |
678 | * Don't get the IP here because it's unlikely to | |
679 | * have anything to do with the actual error location. | |
680 | */ | |
3f2f0680 BP |
681 | if (!(flags & MCP_DONTLOG) && !mca_cfg.dont_log_ce) { |
682 | error_logged = true; | |
5679af4c | 683 | mce_log(&m); |
3f2f0680 | 684 | } |
b79109c3 AK |
685 | |
686 | /* | |
687 | * Clear state for this bank. | |
688 | */ | |
a2d32bcb | 689 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
b79109c3 AK |
690 | } |
691 | ||
692 | /* | |
693 | * Don't clear MCG_STATUS here because it's only defined for | |
694 | * exceptions. | |
695 | */ | |
88921be3 AK |
696 | |
697 | sync_core(); | |
3f2f0680 BP |
698 | |
699 | return error_logged; | |
b79109c3 | 700 | } |
ea149b36 | 701 | EXPORT_SYMBOL_GPL(machine_check_poll); |
b79109c3 | 702 | |
bd19a5e6 AK |
703 | /* |
704 | * Do a quick check if any of the events requires a panic. | |
705 | * This decides if we keep the events around or clear them. | |
706 | */ | |
61b0fccd TL |
707 | static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp, |
708 | struct pt_regs *regs) | |
bd19a5e6 | 709 | { |
95022b8c | 710 | int i, ret = 0; |
bd19a5e6 | 711 | |
d203f0b8 | 712 | for (i = 0; i < mca_cfg.banks; i++) { |
a2d32bcb | 713 | m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
61b0fccd | 714 | if (m->status & MCI_STATUS_VAL) { |
95022b8c | 715 | __set_bit(i, validp); |
61b0fccd TL |
716 | if (quirk_no_way_out) |
717 | quirk_no_way_out(i, m, regs); | |
718 | } | |
e3480271 CY |
719 | if (mce_severity(m, mca_cfg.tolerant, msg, true) >= |
720 | MCE_PANIC_SEVERITY) | |
95022b8c | 721 | ret = 1; |
bd19a5e6 | 722 | } |
95022b8c | 723 | return ret; |
bd19a5e6 AK |
724 | } |
725 | ||
3c079792 AK |
726 | /* |
727 | * Variable to establish order between CPUs while scanning. | |
728 | * Each CPU spins initially until executing is equal its number. | |
729 | */ | |
730 | static atomic_t mce_executing; | |
731 | ||
732 | /* | |
733 | * Defines order of CPUs on entry. First CPU becomes Monarch. | |
734 | */ | |
735 | static atomic_t mce_callin; | |
736 | ||
737 | /* | |
738 | * Check if a timeout waiting for other CPUs happened. | |
739 | */ | |
6c80f87e | 740 | static int mce_timed_out(u64 *t, const char *msg) |
3c079792 AK |
741 | { |
742 | /* | |
743 | * The others already did panic for some reason. | |
744 | * Bail out like in a timeout. | |
745 | * rmb() to tell the compiler that system_state | |
746 | * might have been modified by someone else. | |
747 | */ | |
748 | rmb(); | |
c7c9b392 | 749 | if (atomic_read(&mce_panicked)) |
3c079792 | 750 | wait_for_panic(); |
84c2559d | 751 | if (!mca_cfg.monarch_timeout) |
3c079792 AK |
752 | goto out; |
753 | if ((s64)*t < SPINUNIT) { | |
716079f6 | 754 | if (mca_cfg.tolerant <= 1) |
6c80f87e | 755 | mce_panic(msg, NULL, NULL); |
3c079792 AK |
756 | cpu_missing = 1; |
757 | return 1; | |
758 | } | |
759 | *t -= SPINUNIT; | |
760 | out: | |
761 | touch_nmi_watchdog(); | |
762 | return 0; | |
763 | } | |
764 | ||
765 | /* | |
766 | * The Monarch's reign. The Monarch is the CPU who entered | |
767 | * the machine check handler first. It waits for the others to | |
768 | * raise the exception too and then grades them. When any | |
769 | * error is fatal panic. Only then let the others continue. | |
770 | * | |
771 | * The other CPUs entering the MCE handler will be controlled by the | |
772 | * Monarch. They are called Subjects. | |
773 | * | |
774 | * This way we prevent any potential data corruption in a unrecoverable case | |
775 | * and also makes sure always all CPU's errors are examined. | |
776 | * | |
680b6cfd | 777 | * Also this detects the case of a machine check event coming from outer |
3c079792 AK |
778 | * space (not detected by any CPUs) In this case some external agent wants |
779 | * us to shut down, so panic too. | |
780 | * | |
781 | * The other CPUs might still decide to panic if the handler happens | |
782 | * in a unrecoverable place, but in this case the system is in a semi-stable | |
783 | * state and won't corrupt anything by itself. It's ok to let the others | |
784 | * continue for a bit first. | |
785 | * | |
786 | * All the spin loops have timeouts; when a timeout happens a CPU | |
787 | * typically elects itself to be Monarch. | |
788 | */ | |
789 | static void mce_reign(void) | |
790 | { | |
791 | int cpu; | |
792 | struct mce *m = NULL; | |
793 | int global_worst = 0; | |
794 | char *msg = NULL; | |
795 | char *nmsg = NULL; | |
796 | ||
797 | /* | |
798 | * This CPU is the Monarch and the other CPUs have run | |
799 | * through their handlers. | |
800 | * Grade the severity of the errors of all the CPUs. | |
801 | */ | |
802 | for_each_possible_cpu(cpu) { | |
d203f0b8 BP |
803 | int severity = mce_severity(&per_cpu(mces_seen, cpu), |
804 | mca_cfg.tolerant, | |
e3480271 | 805 | &nmsg, true); |
3c079792 AK |
806 | if (severity > global_worst) { |
807 | msg = nmsg; | |
808 | global_worst = severity; | |
809 | m = &per_cpu(mces_seen, cpu); | |
810 | } | |
811 | } | |
812 | ||
813 | /* | |
814 | * Cannot recover? Panic here then. | |
815 | * This dumps all the mces in the log buffer and stops the | |
816 | * other CPUs. | |
817 | */ | |
d203f0b8 | 818 | if (m && global_worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) |
8af7043a | 819 | mce_panic("Fatal machine check", m, msg); |
3c079792 AK |
820 | |
821 | /* | |
822 | * For UC somewhere we let the CPU who detects it handle it. | |
823 | * Also must let continue the others, otherwise the handling | |
824 | * CPU could deadlock on a lock. | |
825 | */ | |
826 | ||
827 | /* | |
828 | * No machine check event found. Must be some external | |
829 | * source or one CPU is hung. Panic. | |
830 | */ | |
d203f0b8 | 831 | if (global_worst <= MCE_KEEP_SEVERITY && mca_cfg.tolerant < 3) |
8af7043a | 832 | mce_panic("Fatal machine check from unknown source", NULL, NULL); |
3c079792 AK |
833 | |
834 | /* | |
835 | * Now clear all the mces_seen so that they don't reappear on | |
836 | * the next mce. | |
837 | */ | |
838 | for_each_possible_cpu(cpu) | |
839 | memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce)); | |
840 | } | |
841 | ||
842 | static atomic_t global_nwo; | |
843 | ||
844 | /* | |
845 | * Start of Monarch synchronization. This waits until all CPUs have | |
846 | * entered the exception handler and then determines if any of them | |
847 | * saw a fatal event that requires panic. Then it executes them | |
848 | * in the entry order. | |
849 | * TBD double check parallel CPU hotunplug | |
850 | */ | |
7fb06fc9 | 851 | static int mce_start(int *no_way_out) |
3c079792 | 852 | { |
7fb06fc9 | 853 | int order; |
3c079792 | 854 | int cpus = num_online_cpus(); |
84c2559d | 855 | u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; |
3c079792 | 856 | |
7fb06fc9 HS |
857 | if (!timeout) |
858 | return -1; | |
3c079792 | 859 | |
7fb06fc9 | 860 | atomic_add(*no_way_out, &global_nwo); |
184e1fdf HY |
861 | /* |
862 | * global_nwo should be updated before mce_callin | |
863 | */ | |
864 | smp_wmb(); | |
a95436e4 | 865 | order = atomic_inc_return(&mce_callin); |
3c079792 AK |
866 | |
867 | /* | |
868 | * Wait for everyone. | |
869 | */ | |
870 | while (atomic_read(&mce_callin) != cpus) { | |
6c80f87e AL |
871 | if (mce_timed_out(&timeout, |
872 | "Timeout: Not all CPUs entered broadcast exception handler")) { | |
3c079792 | 873 | atomic_set(&global_nwo, 0); |
7fb06fc9 | 874 | return -1; |
3c079792 AK |
875 | } |
876 | ndelay(SPINUNIT); | |
877 | } | |
878 | ||
184e1fdf HY |
879 | /* |
880 | * mce_callin should be read before global_nwo | |
881 | */ | |
882 | smp_rmb(); | |
3c079792 | 883 | |
7fb06fc9 HS |
884 | if (order == 1) { |
885 | /* | |
886 | * Monarch: Starts executing now, the others wait. | |
887 | */ | |
3c079792 | 888 | atomic_set(&mce_executing, 1); |
7fb06fc9 HS |
889 | } else { |
890 | /* | |
891 | * Subject: Now start the scanning loop one by one in | |
892 | * the original callin order. | |
893 | * This way when there are any shared banks it will be | |
894 | * only seen by one CPU before cleared, avoiding duplicates. | |
895 | */ | |
896 | while (atomic_read(&mce_executing) < order) { | |
6c80f87e AL |
897 | if (mce_timed_out(&timeout, |
898 | "Timeout: Subject CPUs unable to finish machine check processing")) { | |
7fb06fc9 HS |
899 | atomic_set(&global_nwo, 0); |
900 | return -1; | |
901 | } | |
902 | ndelay(SPINUNIT); | |
903 | } | |
3c079792 AK |
904 | } |
905 | ||
906 | /* | |
7fb06fc9 | 907 | * Cache the global no_way_out state. |
3c079792 | 908 | */ |
7fb06fc9 HS |
909 | *no_way_out = atomic_read(&global_nwo); |
910 | ||
911 | return order; | |
3c079792 AK |
912 | } |
913 | ||
914 | /* | |
915 | * Synchronize between CPUs after main scanning loop. | |
916 | * This invokes the bulk of the Monarch processing. | |
917 | */ | |
918 | static int mce_end(int order) | |
919 | { | |
920 | int ret = -1; | |
84c2559d | 921 | u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; |
3c079792 AK |
922 | |
923 | if (!timeout) | |
924 | goto reset; | |
925 | if (order < 0) | |
926 | goto reset; | |
927 | ||
928 | /* | |
929 | * Allow others to run. | |
930 | */ | |
931 | atomic_inc(&mce_executing); | |
932 | ||
933 | if (order == 1) { | |
934 | /* CHECKME: Can this race with a parallel hotplug? */ | |
935 | int cpus = num_online_cpus(); | |
936 | ||
937 | /* | |
938 | * Monarch: Wait for everyone to go through their scanning | |
939 | * loops. | |
940 | */ | |
941 | while (atomic_read(&mce_executing) <= cpus) { | |
6c80f87e AL |
942 | if (mce_timed_out(&timeout, |
943 | "Timeout: Monarch CPU unable to finish machine check processing")) | |
3c079792 AK |
944 | goto reset; |
945 | ndelay(SPINUNIT); | |
946 | } | |
947 | ||
948 | mce_reign(); | |
949 | barrier(); | |
950 | ret = 0; | |
951 | } else { | |
952 | /* | |
953 | * Subject: Wait for Monarch to finish. | |
954 | */ | |
955 | while (atomic_read(&mce_executing) != 0) { | |
6c80f87e AL |
956 | if (mce_timed_out(&timeout, |
957 | "Timeout: Monarch CPU did not finish machine check processing")) | |
3c079792 AK |
958 | goto reset; |
959 | ndelay(SPINUNIT); | |
960 | } | |
961 | ||
962 | /* | |
963 | * Don't reset anything. That's done by the Monarch. | |
964 | */ | |
965 | return 0; | |
966 | } | |
967 | ||
968 | /* | |
969 | * Reset all global state. | |
970 | */ | |
971 | reset: | |
972 | atomic_set(&global_nwo, 0); | |
973 | atomic_set(&mce_callin, 0); | |
974 | barrier(); | |
975 | ||
976 | /* | |
977 | * Let others run again. | |
978 | */ | |
979 | atomic_set(&mce_executing, 0); | |
980 | return ret; | |
981 | } | |
982 | ||
9b1beaf2 AK |
983 | /* |
984 | * Check if the address reported by the CPU is in a format we can parse. | |
985 | * It would be possible to add code for most other cases, but all would | |
986 | * be somewhat complicated (e.g. segment offset would require an instruction | |
0d2eb44f | 987 | * parser). So only support physical addresses up to page granuality for now. |
9b1beaf2 AK |
988 | */ |
989 | static int mce_usable_address(struct mce *m) | |
990 | { | |
991 | if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV)) | |
992 | return 0; | |
2b90e77e | 993 | if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT) |
9b1beaf2 | 994 | return 0; |
2b90e77e | 995 | if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS) |
9b1beaf2 AK |
996 | return 0; |
997 | return 1; | |
998 | } | |
999 | ||
3c079792 AK |
1000 | static void mce_clear_state(unsigned long *toclear) |
1001 | { | |
1002 | int i; | |
1003 | ||
d203f0b8 | 1004 | for (i = 0; i < mca_cfg.banks; i++) { |
3c079792 | 1005 | if (test_bit(i, toclear)) |
a2d32bcb | 1006 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
3c079792 AK |
1007 | } |
1008 | } | |
1009 | ||
b79109c3 AK |
1010 | /* |
1011 | * The actual machine check handler. This only handles real | |
1012 | * exceptions when something got corrupted coming in through int 18. | |
1013 | * | |
1014 | * This is executed in NMI context not subject to normal locking rules. This | |
1015 | * implies that most kernel services cannot be safely used. Don't even | |
1016 | * think about putting a printk in there! | |
3c079792 AK |
1017 | * |
1018 | * On Intel systems this is entered on all CPUs in parallel through | |
1019 | * MCE broadcast. However some CPUs might be broken beyond repair, | |
1020 | * so be always careful when synchronizing with others. | |
1da177e4 | 1021 | */ |
e9eee03e | 1022 | void do_machine_check(struct pt_regs *regs, long error_code) |
1da177e4 | 1023 | { |
1462594b | 1024 | struct mca_config *cfg = &mca_cfg; |
3c079792 | 1025 | struct mce m, *final; |
95927475 | 1026 | enum ctx_state prev_state; |
1da177e4 | 1027 | int i; |
3c079792 AK |
1028 | int worst = 0; |
1029 | int severity; | |
1030 | /* | |
1031 | * Establish sequential order between the CPUs entering the machine | |
1032 | * check handler. | |
1033 | */ | |
7fb06fc9 | 1034 | int order; |
bd78432c TH |
1035 | /* |
1036 | * If no_way_out gets set, there is no safe way to recover from this | |
d203f0b8 | 1037 | * MCE. If mca_cfg.tolerant is cranked up, we'll try anyway. |
bd78432c TH |
1038 | */ |
1039 | int no_way_out = 0; | |
1040 | /* | |
1041 | * If kill_it gets set, there might be a way to recover from this | |
1042 | * error. | |
1043 | */ | |
1044 | int kill_it = 0; | |
b79109c3 | 1045 | DECLARE_BITMAP(toclear, MAX_NR_BANKS); |
95022b8c | 1046 | DECLARE_BITMAP(valid_banks, MAX_NR_BANKS); |
bd19a5e6 | 1047 | char *msg = "Unknown"; |
d4812e16 LT |
1048 | u64 recover_paddr = ~0ull; |
1049 | int flags = MF_ACTION_REQUIRED; | |
1da177e4 | 1050 | |
95927475 AL |
1051 | prev_state = ist_enter(regs); |
1052 | ||
c6ae41e7 | 1053 | this_cpu_inc(mce_exception_count); |
01ca79f1 | 1054 | |
1462594b | 1055 | if (!cfg->banks) |
32561696 | 1056 | goto out; |
1da177e4 | 1057 | |
b8325c5b | 1058 | mce_gather_info(&m, regs); |
b5f2fa4e | 1059 | |
89cbc767 | 1060 | final = this_cpu_ptr(&mces_seen); |
3c079792 AK |
1061 | *final = m; |
1062 | ||
95022b8c | 1063 | memset(valid_banks, 0, sizeof(valid_banks)); |
61b0fccd | 1064 | no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs); |
680b6cfd | 1065 | |
1da177e4 LT |
1066 | barrier(); |
1067 | ||
ed7290d0 | 1068 | /* |
a8c321fb TL |
1069 | * When no restart IP might need to kill or panic. |
1070 | * Assume the worst for now, but if we find the | |
1071 | * severity is MCE_AR_SEVERITY we have other options. | |
ed7290d0 AK |
1072 | */ |
1073 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) | |
1074 | kill_it = 1; | |
1075 | ||
3c079792 AK |
1076 | /* |
1077 | * Go through all the banks in exclusion of the other CPUs. | |
1078 | * This way we don't report duplicated events on shared banks | |
1079 | * because the first one to see it will clear it. | |
1080 | */ | |
7fb06fc9 | 1081 | order = mce_start(&no_way_out); |
1462594b | 1082 | for (i = 0; i < cfg->banks; i++) { |
b79109c3 | 1083 | __clear_bit(i, toclear); |
95022b8c TL |
1084 | if (!test_bit(i, valid_banks)) |
1085 | continue; | |
cebe1820 | 1086 | if (!mce_banks[i].ctl) |
1da177e4 | 1087 | continue; |
d88203d1 TG |
1088 | |
1089 | m.misc = 0; | |
1da177e4 LT |
1090 | m.addr = 0; |
1091 | m.bank = i; | |
1da177e4 | 1092 | |
a2d32bcb | 1093 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
1da177e4 LT |
1094 | if ((m.status & MCI_STATUS_VAL) == 0) |
1095 | continue; | |
1096 | ||
b79109c3 | 1097 | /* |
ed7290d0 AK |
1098 | * Non uncorrected or non signaled errors are handled by |
1099 | * machine_check_poll. Leave them alone, unless this panics. | |
b79109c3 | 1100 | */ |
1462594b | 1101 | if (!(m.status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) && |
ed7290d0 | 1102 | !no_way_out) |
b79109c3 AK |
1103 | continue; |
1104 | ||
1105 | /* | |
1106 | * Set taint even when machine check was not enabled. | |
1107 | */ | |
373d4d09 | 1108 | add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); |
b79109c3 | 1109 | |
e3480271 | 1110 | severity = mce_severity(&m, cfg->tolerant, NULL, true); |
b79109c3 | 1111 | |
ed7290d0 | 1112 | /* |
e3480271 CY |
1113 | * When machine check was for corrected/deferred handler don't |
1114 | * touch, unless we're panicing. | |
ed7290d0 | 1115 | */ |
e3480271 CY |
1116 | if ((severity == MCE_KEEP_SEVERITY || |
1117 | severity == MCE_UCNA_SEVERITY) && !no_way_out) | |
ed7290d0 AK |
1118 | continue; |
1119 | __set_bit(i, toclear); | |
1120 | if (severity == MCE_NO_SEVERITY) { | |
b79109c3 AK |
1121 | /* |
1122 | * Machine check event was not enabled. Clear, but | |
1123 | * ignore. | |
1124 | */ | |
1125 | continue; | |
1da177e4 LT |
1126 | } |
1127 | ||
85f92694 | 1128 | mce_read_aux(&m, i); |
1da177e4 | 1129 | |
9b1beaf2 AK |
1130 | /* |
1131 | * Action optional error. Queue address for later processing. | |
1132 | * When the ring overflows we just ignore the AO error. | |
1133 | * RED-PEN add some logging mechanism when | |
1134 | * usable_address or mce_add_ring fails. | |
d203f0b8 | 1135 | * RED-PEN don't ignore overflow for mca_cfg.tolerant == 0 |
9b1beaf2 AK |
1136 | */ |
1137 | if (severity == MCE_AO_SEVERITY && mce_usable_address(&m)) | |
1138 | mce_ring_add(m.addr >> PAGE_SHIFT); | |
1139 | ||
b79109c3 | 1140 | mce_log(&m); |
1da177e4 | 1141 | |
3c079792 AK |
1142 | if (severity > worst) { |
1143 | *final = m; | |
1144 | worst = severity; | |
1da177e4 | 1145 | } |
1da177e4 LT |
1146 | } |
1147 | ||
a8c321fb TL |
1148 | /* mce_clear_state will clear *final, save locally for use later */ |
1149 | m = *final; | |
1150 | ||
3c079792 AK |
1151 | if (!no_way_out) |
1152 | mce_clear_state(toclear); | |
1153 | ||
e9eee03e | 1154 | /* |
3c079792 AK |
1155 | * Do most of the synchronization with other CPUs. |
1156 | * When there's any problem use only local no_way_out state. | |
e9eee03e | 1157 | */ |
3c079792 AK |
1158 | if (mce_end(order) < 0) |
1159 | no_way_out = worst >= MCE_PANIC_SEVERITY; | |
bd78432c TH |
1160 | |
1161 | /* | |
a8c321fb TL |
1162 | * At insane "tolerant" levels we take no action. Otherwise |
1163 | * we only die if we have no other choice. For less serious | |
1164 | * issues we try to recover, or limit damage to the current | |
1165 | * process. | |
bd78432c | 1166 | */ |
1462594b | 1167 | if (cfg->tolerant < 3) { |
a8c321fb TL |
1168 | if (no_way_out) |
1169 | mce_panic("Fatal machine check on current CPU", &m, msg); | |
1170 | if (worst == MCE_AR_SEVERITY) { | |
d4812e16 LT |
1171 | recover_paddr = m.addr; |
1172 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) | |
1173 | flags |= MF_MUST_KILL; | |
a8c321fb TL |
1174 | } else if (kill_it) { |
1175 | force_sig(SIGBUS, current); | |
1176 | } | |
1177 | } | |
e02e68d3 | 1178 | |
3c079792 AK |
1179 | if (worst > 0) |
1180 | mce_report_event(regs); | |
5f8c1a54 | 1181 | mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); |
32561696 | 1182 | out: |
88921be3 | 1183 | sync_core(); |
d4812e16 LT |
1184 | |
1185 | if (recover_paddr == ~0ull) | |
1186 | goto done; | |
1187 | ||
1188 | pr_err("Uncorrected hardware memory error in user-access at %llx", | |
1189 | recover_paddr); | |
1190 | /* | |
1191 | * We must call memory_failure() here even if the current process is | |
1192 | * doomed. We still need to mark the page as poisoned and alert any | |
1193 | * other users of the page. | |
1194 | */ | |
1195 | ist_begin_non_atomic(regs); | |
1196 | local_irq_enable(); | |
1197 | if (memory_failure(recover_paddr >> PAGE_SHIFT, MCE_VECTOR, flags) < 0) { | |
1198 | pr_err("Memory error not recovered"); | |
1199 | force_sig(SIGBUS, current); | |
1200 | } | |
1201 | local_irq_disable(); | |
1202 | ist_end_non_atomic(); | |
1203 | done: | |
95927475 | 1204 | ist_exit(regs, prev_state); |
1da177e4 | 1205 | } |
ea149b36 | 1206 | EXPORT_SYMBOL_GPL(do_machine_check); |
1da177e4 | 1207 | |
cd42f4a3 TL |
1208 | #ifndef CONFIG_MEMORY_FAILURE |
1209 | int memory_failure(unsigned long pfn, int vector, int flags) | |
9b1beaf2 | 1210 | { |
a8c321fb TL |
1211 | /* mce_severity() should not hand us an ACTION_REQUIRED error */ |
1212 | BUG_ON(flags & MF_ACTION_REQUIRED); | |
c767a54b JP |
1213 | pr_err("Uncorrected memory error in page 0x%lx ignored\n" |
1214 | "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n", | |
1215 | pfn); | |
cd42f4a3 TL |
1216 | |
1217 | return 0; | |
9b1beaf2 | 1218 | } |
cd42f4a3 | 1219 | #endif |
9b1beaf2 | 1220 | |
a8c321fb TL |
1221 | /* |
1222 | * Action optional processing happens here (picking up | |
1223 | * from the list of faulting pages that do_machine_check() | |
1224 | * placed into the "ring"). | |
1225 | */ | |
9b1beaf2 AK |
1226 | static void mce_process_work(struct work_struct *dummy) |
1227 | { | |
a8c321fb TL |
1228 | unsigned long pfn; |
1229 | ||
1230 | while (mce_ring_get(&pfn)) | |
1231 | memory_failure(pfn, MCE_VECTOR, 0); | |
9b1beaf2 AK |
1232 | } |
1233 | ||
15d5f839 DZ |
1234 | #ifdef CONFIG_X86_MCE_INTEL |
1235 | /*** | |
1236 | * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog | |
676b1855 | 1237 | * @cpu: The CPU on which the event occurred. |
15d5f839 DZ |
1238 | * @status: Event status information |
1239 | * | |
1240 | * This function should be called by the thermal interrupt after the | |
1241 | * event has been processed and the decision was made to log the event | |
1242 | * further. | |
1243 | * | |
1244 | * The status parameter will be saved to the 'status' field of 'struct mce' | |
1245 | * and historically has been the register value of the | |
1246 | * MSR_IA32_THERMAL_STATUS (Intel) msr. | |
1247 | */ | |
b5f2fa4e | 1248 | void mce_log_therm_throt_event(__u64 status) |
15d5f839 DZ |
1249 | { |
1250 | struct mce m; | |
1251 | ||
b5f2fa4e | 1252 | mce_setup(&m); |
15d5f839 DZ |
1253 | m.bank = MCE_THERMAL_BANK; |
1254 | m.status = status; | |
15d5f839 DZ |
1255 | mce_log(&m); |
1256 | } | |
1257 | #endif /* CONFIG_X86_MCE_INTEL */ | |
1258 | ||
1da177e4 | 1259 | /* |
8a336b0a TH |
1260 | * Periodic polling timer for "silent" machine check errors. If the |
1261 | * poller finds an MCE, poll 2x faster. When the poller finds no more | |
1262 | * errors, poll 2x slower (up to check_interval seconds). | |
1da177e4 | 1263 | */ |
3f2f0680 | 1264 | static unsigned long check_interval = INITIAL_CHECK_INTERVAL; |
e9eee03e | 1265 | |
82f7af09 | 1266 | static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */ |
52d168e2 | 1267 | static DEFINE_PER_CPU(struct timer_list, mce_timer); |
1da177e4 | 1268 | |
55babd8f CG |
1269 | static unsigned long mce_adjust_timer_default(unsigned long interval) |
1270 | { | |
1271 | return interval; | |
1272 | } | |
1273 | ||
3f2f0680 | 1274 | static unsigned long (*mce_adjust_timer)(unsigned long interval) = mce_adjust_timer_default; |
55babd8f | 1275 | |
3f2f0680 | 1276 | static void __restart_timer(struct timer_list *t, unsigned long interval) |
27f6c573 | 1277 | { |
3f2f0680 BP |
1278 | unsigned long when = jiffies + interval; |
1279 | unsigned long flags; | |
27f6c573 | 1280 | |
3f2f0680 | 1281 | local_irq_save(flags); |
27f6c573 | 1282 | |
3f2f0680 BP |
1283 | if (timer_pending(t)) { |
1284 | if (time_before(when, t->expires)) | |
1285 | mod_timer_pinned(t, when); | |
1286 | } else { | |
1287 | t->expires = round_jiffies(when); | |
1288 | add_timer_on(t, smp_processor_id()); | |
1289 | } | |
1290 | ||
1291 | local_irq_restore(flags); | |
27f6c573 CG |
1292 | } |
1293 | ||
82f7af09 | 1294 | static void mce_timer_fn(unsigned long data) |
1da177e4 | 1295 | { |
89cbc767 | 1296 | struct timer_list *t = this_cpu_ptr(&mce_timer); |
3f2f0680 | 1297 | int cpu = smp_processor_id(); |
82f7af09 | 1298 | unsigned long iv; |
52d168e2 | 1299 | |
3f2f0680 BP |
1300 | WARN_ON(cpu != data); |
1301 | ||
1302 | iv = __this_cpu_read(mce_next_interval); | |
52d168e2 | 1303 | |
89cbc767 | 1304 | if (mce_available(this_cpu_ptr(&cpu_info))) { |
3f2f0680 BP |
1305 | machine_check_poll(MCP_TIMESTAMP, this_cpu_ptr(&mce_poll_banks)); |
1306 | ||
1307 | if (mce_intel_cmci_poll()) { | |
1308 | iv = mce_adjust_timer(iv); | |
1309 | goto done; | |
1310 | } | |
e9eee03e | 1311 | } |
1da177e4 LT |
1312 | |
1313 | /* | |
3f2f0680 BP |
1314 | * Alert userspace if needed. If we logged an MCE, reduce the polling |
1315 | * interval, otherwise increase the polling interval. | |
1da177e4 | 1316 | */ |
3f2f0680 | 1317 | if (mce_notify_irq()) |
958fb3c5 | 1318 | iv = max(iv / 2, (unsigned long) HZ/100); |
3f2f0680 | 1319 | else |
82f7af09 | 1320 | iv = min(iv * 2, round_jiffies_relative(check_interval * HZ)); |
3f2f0680 BP |
1321 | |
1322 | done: | |
82f7af09 | 1323 | __this_cpu_write(mce_next_interval, iv); |
3f2f0680 | 1324 | __restart_timer(t, iv); |
55babd8f | 1325 | } |
e02e68d3 | 1326 | |
55babd8f CG |
1327 | /* |
1328 | * Ensure that the timer is firing in @interval from now. | |
1329 | */ | |
1330 | void mce_timer_kick(unsigned long interval) | |
1331 | { | |
89cbc767 | 1332 | struct timer_list *t = this_cpu_ptr(&mce_timer); |
55babd8f CG |
1333 | unsigned long iv = __this_cpu_read(mce_next_interval); |
1334 | ||
3f2f0680 BP |
1335 | __restart_timer(t, interval); |
1336 | ||
55babd8f CG |
1337 | if (interval < iv) |
1338 | __this_cpu_write(mce_next_interval, interval); | |
e02e68d3 TH |
1339 | } |
1340 | ||
9aaef96f HS |
1341 | /* Must not be called in IRQ context where del_timer_sync() can deadlock */ |
1342 | static void mce_timer_delete_all(void) | |
1343 | { | |
1344 | int cpu; | |
1345 | ||
1346 | for_each_online_cpu(cpu) | |
1347 | del_timer_sync(&per_cpu(mce_timer, cpu)); | |
1348 | } | |
1349 | ||
9bd98405 AK |
1350 | static void mce_do_trigger(struct work_struct *work) |
1351 | { | |
1020bcbc | 1352 | call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT); |
9bd98405 AK |
1353 | } |
1354 | ||
1355 | static DECLARE_WORK(mce_trigger_work, mce_do_trigger); | |
1356 | ||
e02e68d3 | 1357 | /* |
9bd98405 AK |
1358 | * Notify the user(s) about new machine check events. |
1359 | * Can be called from interrupt context, but not from machine check/NMI | |
1360 | * context. | |
e02e68d3 | 1361 | */ |
9ff36ee9 | 1362 | int mce_notify_irq(void) |
e02e68d3 | 1363 | { |
8457c84d AK |
1364 | /* Not more than two messages every minute */ |
1365 | static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); | |
1366 | ||
1020bcbc | 1367 | if (test_and_clear_bit(0, &mce_need_notify)) { |
93b62c3c HS |
1368 | /* wake processes polling /dev/mcelog */ |
1369 | wake_up_interruptible(&mce_chrdev_wait); | |
9bd98405 | 1370 | |
4d899be5 | 1371 | if (mce_helper[0]) |
9bd98405 | 1372 | schedule_work(&mce_trigger_work); |
e02e68d3 | 1373 | |
8457c84d | 1374 | if (__ratelimit(&ratelimit)) |
a2d7b0d4 | 1375 | pr_info(HW_ERR "Machine check events logged\n"); |
e02e68d3 TH |
1376 | |
1377 | return 1; | |
1da177e4 | 1378 | } |
e02e68d3 TH |
1379 | return 0; |
1380 | } | |
9ff36ee9 | 1381 | EXPORT_SYMBOL_GPL(mce_notify_irq); |
8a336b0a | 1382 | |
148f9bb8 | 1383 | static int __mcheck_cpu_mce_banks_init(void) |
cebe1820 AK |
1384 | { |
1385 | int i; | |
d203f0b8 | 1386 | u8 num_banks = mca_cfg.banks; |
cebe1820 | 1387 | |
d203f0b8 | 1388 | mce_banks = kzalloc(num_banks * sizeof(struct mce_bank), GFP_KERNEL); |
cebe1820 AK |
1389 | if (!mce_banks) |
1390 | return -ENOMEM; | |
d203f0b8 BP |
1391 | |
1392 | for (i = 0; i < num_banks; i++) { | |
cebe1820 | 1393 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1394 | |
cebe1820 AK |
1395 | b->ctl = -1ULL; |
1396 | b->init = 1; | |
1397 | } | |
1398 | return 0; | |
1399 | } | |
1400 | ||
d88203d1 | 1401 | /* |
1da177e4 LT |
1402 | * Initialize Machine Checks for a CPU. |
1403 | */ | |
148f9bb8 | 1404 | static int __mcheck_cpu_cap_init(void) |
1da177e4 | 1405 | { |
0d7482e3 | 1406 | unsigned b; |
e9eee03e | 1407 | u64 cap; |
1da177e4 LT |
1408 | |
1409 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
01c6680a TG |
1410 | |
1411 | b = cap & MCG_BANKCNT_MASK; | |
d203f0b8 | 1412 | if (!mca_cfg.banks) |
c767a54b | 1413 | pr_info("CPU supports %d MCE banks\n", b); |
b659294b | 1414 | |
0d7482e3 | 1415 | if (b > MAX_NR_BANKS) { |
c767a54b | 1416 | pr_warn("Using only %u machine check banks out of %u\n", |
0d7482e3 AK |
1417 | MAX_NR_BANKS, b); |
1418 | b = MAX_NR_BANKS; | |
1419 | } | |
1420 | ||
1421 | /* Don't support asymmetric configurations today */ | |
d203f0b8 BP |
1422 | WARN_ON(mca_cfg.banks != 0 && b != mca_cfg.banks); |
1423 | mca_cfg.banks = b; | |
1424 | ||
cebe1820 | 1425 | if (!mce_banks) { |
cffd377e | 1426 | int err = __mcheck_cpu_mce_banks_init(); |
11868a2d | 1427 | |
cebe1820 AK |
1428 | if (err) |
1429 | return err; | |
1da177e4 | 1430 | } |
0d7482e3 | 1431 | |
94ad8474 | 1432 | /* Use accurate RIP reporting if available. */ |
01c6680a | 1433 | if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) |
84c2559d | 1434 | mca_cfg.rip_msr = MSR_IA32_MCG_EIP; |
1da177e4 | 1435 | |
ed7290d0 | 1436 | if (cap & MCG_SER_P) |
1462594b | 1437 | mca_cfg.ser = true; |
ed7290d0 | 1438 | |
0d7482e3 AK |
1439 | return 0; |
1440 | } | |
1441 | ||
5e09954a | 1442 | static void __mcheck_cpu_init_generic(void) |
0d7482e3 | 1443 | { |
84c2559d | 1444 | enum mcp_flags m_fl = 0; |
e9eee03e | 1445 | mce_banks_t all_banks; |
0d7482e3 AK |
1446 | u64 cap; |
1447 | int i; | |
1448 | ||
84c2559d BP |
1449 | if (!mca_cfg.bootlog) |
1450 | m_fl = MCP_DONTLOG; | |
1451 | ||
b79109c3 AK |
1452 | /* |
1453 | * Log the machine checks left over from the previous reset. | |
1454 | */ | |
ee031c31 | 1455 | bitmap_fill(all_banks, MAX_NR_BANKS); |
84c2559d | 1456 | machine_check_poll(MCP_UC | m_fl, &all_banks); |
1da177e4 | 1457 | |
375074cc | 1458 | cr4_set_bits(X86_CR4_MCE); |
1da177e4 | 1459 | |
0d7482e3 | 1460 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
1da177e4 LT |
1461 | if (cap & MCG_CTL_P) |
1462 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); | |
1463 | ||
d203f0b8 | 1464 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 1465 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1466 | |
cebe1820 | 1467 | if (!b->init) |
06b7a7a5 | 1468 | continue; |
a2d32bcb AK |
1469 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
1470 | wrmsrl(MSR_IA32_MCx_STATUS(i), 0); | |
d88203d1 | 1471 | } |
1da177e4 LT |
1472 | } |
1473 | ||
61b0fccd TL |
1474 | /* |
1475 | * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and | |
1476 | * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM | |
1477 | * Vol 3B Table 15-20). But this confuses both the code that determines | |
1478 | * whether the machine check occurred in kernel or user mode, and also | |
1479 | * the severity assessment code. Pretend that EIPV was set, and take the | |
1480 | * ip/cs values from the pt_regs that mce_gather_info() ignored earlier. | |
1481 | */ | |
1482 | static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs) | |
1483 | { | |
1484 | if (bank != 0) | |
1485 | return; | |
1486 | if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0) | |
1487 | return; | |
1488 | if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC| | |
1489 | MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV| | |
1490 | MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR| | |
1491 | MCACOD)) != | |
1492 | (MCI_STATUS_UC|MCI_STATUS_EN| | |
1493 | MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S| | |
1494 | MCI_STATUS_AR|MCACOD_INSTR)) | |
1495 | return; | |
1496 | ||
1497 | m->mcgstatus |= MCG_STATUS_EIPV; | |
1498 | m->ip = regs->ip; | |
1499 | m->cs = regs->cs; | |
1500 | } | |
1501 | ||
1da177e4 | 1502 | /* Add per CPU specific workarounds here */ |
148f9bb8 | 1503 | static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) |
d88203d1 | 1504 | { |
d203f0b8 BP |
1505 | struct mca_config *cfg = &mca_cfg; |
1506 | ||
e412cd25 | 1507 | if (c->x86_vendor == X86_VENDOR_UNKNOWN) { |
c767a54b | 1508 | pr_info("unknown CPU type - not enabling MCE support\n"); |
e412cd25 IM |
1509 | return -EOPNOTSUPP; |
1510 | } | |
1511 | ||
1da177e4 | 1512 | /* This should be disabled by the BIOS, but isn't always */ |
911f6a7b | 1513 | if (c->x86_vendor == X86_VENDOR_AMD) { |
d203f0b8 | 1514 | if (c->x86 == 15 && cfg->banks > 4) { |
e9eee03e IM |
1515 | /* |
1516 | * disable GART TBL walk error reporting, which | |
1517 | * trips off incorrectly with the IOMMU & 3ware | |
1518 | * & Cerberus: | |
1519 | */ | |
cebe1820 | 1520 | clear_bit(10, (unsigned long *)&mce_banks[4].ctl); |
e9eee03e | 1521 | } |
84c2559d | 1522 | if (c->x86 <= 17 && cfg->bootlog < 0) { |
e9eee03e IM |
1523 | /* |
1524 | * Lots of broken BIOS around that don't clear them | |
1525 | * by default and leave crap in there. Don't log: | |
1526 | */ | |
84c2559d | 1527 | cfg->bootlog = 0; |
e9eee03e | 1528 | } |
2e6f694f AK |
1529 | /* |
1530 | * Various K7s with broken bank 0 around. Always disable | |
1531 | * by default. | |
1532 | */ | |
c9ce8712 | 1533 | if (c->x86 == 6 && cfg->banks > 0) |
cebe1820 | 1534 | mce_banks[0].ctl = 0; |
575203b4 | 1535 | |
bf80bbd7 AG |
1536 | /* |
1537 | * overflow_recov is supported for F15h Models 00h-0fh | |
1538 | * even though we don't have a CPUID bit for it. | |
1539 | */ | |
1540 | if (c->x86 == 0x15 && c->x86_model <= 0xf) | |
1541 | mce_flags.overflow_recov = 1; | |
1542 | ||
c9ce8712 BP |
1543 | /* |
1544 | * Turn off MC4_MISC thresholding banks on those models since | |
1545 | * they're not supported there. | |
1546 | */ | |
1547 | if (c->x86 == 0x15 && | |
1548 | (c->x86_model >= 0x10 && c->x86_model <= 0x1f)) { | |
1549 | int i; | |
1550 | u64 hwcr; | |
1551 | bool need_toggle; | |
1552 | u32 msrs[] = { | |
575203b4 BP |
1553 | 0x00000413, /* MC4_MISC0 */ |
1554 | 0xc0000408, /* MC4_MISC1 */ | |
c9ce8712 | 1555 | }; |
575203b4 | 1556 | |
c9ce8712 | 1557 | rdmsrl(MSR_K7_HWCR, hwcr); |
575203b4 | 1558 | |
c9ce8712 BP |
1559 | /* McStatusWrEn has to be set */ |
1560 | need_toggle = !(hwcr & BIT(18)); | |
575203b4 | 1561 | |
c9ce8712 BP |
1562 | if (need_toggle) |
1563 | wrmsrl(MSR_K7_HWCR, hwcr | BIT(18)); | |
575203b4 | 1564 | |
c9ce8712 BP |
1565 | /* Clear CntP bit safely */ |
1566 | for (i = 0; i < ARRAY_SIZE(msrs); i++) | |
1567 | msr_clear_bit(msrs[i], 62); | |
575203b4 | 1568 | |
c9ce8712 BP |
1569 | /* restore old settings */ |
1570 | if (need_toggle) | |
1571 | wrmsrl(MSR_K7_HWCR, hwcr); | |
1572 | } | |
1da177e4 | 1573 | } |
e583538f | 1574 | |
06b7a7a5 AK |
1575 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
1576 | /* | |
1577 | * SDM documents that on family 6 bank 0 should not be written | |
1578 | * because it aliases to another special BIOS controlled | |
1579 | * register. | |
1580 | * But it's not aliased anymore on model 0x1a+ | |
1581 | * Don't ignore bank 0 completely because there could be a | |
1582 | * valid event later, merely don't write CTL0. | |
1583 | */ | |
1584 | ||
d203f0b8 | 1585 | if (c->x86 == 6 && c->x86_model < 0x1A && cfg->banks > 0) |
cebe1820 | 1586 | mce_banks[0].init = 0; |
3c079792 AK |
1587 | |
1588 | /* | |
1589 | * All newer Intel systems support MCE broadcasting. Enable | |
1590 | * synchronization with a one second timeout. | |
1591 | */ | |
1592 | if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && | |
84c2559d BP |
1593 | cfg->monarch_timeout < 0) |
1594 | cfg->monarch_timeout = USEC_PER_SEC; | |
c7f6fa44 | 1595 | |
e412cd25 IM |
1596 | /* |
1597 | * There are also broken BIOSes on some Pentium M and | |
1598 | * earlier systems: | |
1599 | */ | |
84c2559d BP |
1600 | if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0) |
1601 | cfg->bootlog = 0; | |
61b0fccd TL |
1602 | |
1603 | if (c->x86 == 6 && c->x86_model == 45) | |
1604 | quirk_no_way_out = quirk_sandybridge_ifu; | |
06b7a7a5 | 1605 | } |
84c2559d BP |
1606 | if (cfg->monarch_timeout < 0) |
1607 | cfg->monarch_timeout = 0; | |
1608 | if (cfg->bootlog != 0) | |
7af19e4a | 1609 | cfg->panic_timeout = 30; |
e412cd25 IM |
1610 | |
1611 | return 0; | |
d88203d1 | 1612 | } |
1da177e4 | 1613 | |
148f9bb8 | 1614 | static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) |
4efc0670 AK |
1615 | { |
1616 | if (c->x86 != 5) | |
3a97fc34 HS |
1617 | return 0; |
1618 | ||
4efc0670 AK |
1619 | switch (c->x86_vendor) { |
1620 | case X86_VENDOR_INTEL: | |
c6978369 | 1621 | intel_p5_mcheck_init(c); |
3a97fc34 | 1622 | return 1; |
4efc0670 AK |
1623 | break; |
1624 | case X86_VENDOR_CENTAUR: | |
1625 | winchip_mcheck_init(c); | |
3a97fc34 | 1626 | return 1; |
4efc0670 AK |
1627 | break; |
1628 | } | |
3a97fc34 HS |
1629 | |
1630 | return 0; | |
4efc0670 AK |
1631 | } |
1632 | ||
5e09954a | 1633 | static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
1634 | { |
1635 | switch (c->x86_vendor) { | |
1636 | case X86_VENDOR_INTEL: | |
1637 | mce_intel_feature_init(c); | |
3f2f0680 | 1638 | mce_adjust_timer = cmci_intel_adjust_timer; |
1da177e4 | 1639 | break; |
89b831ef JS |
1640 | case X86_VENDOR_AMD: |
1641 | mce_amd_feature_init(c); | |
bf80bbd7 | 1642 | mce_flags.overflow_recov = cpuid_ebx(0x80000007) & 0x1; |
89b831ef | 1643 | break; |
1da177e4 LT |
1644 | default: |
1645 | break; | |
1646 | } | |
1647 | } | |
1648 | ||
26c3c283 | 1649 | static void mce_start_timer(unsigned int cpu, struct timer_list *t) |
52d168e2 | 1650 | { |
4f75d841 | 1651 | unsigned long iv = check_interval * HZ; |
bc09effa | 1652 | |
7af19e4a | 1653 | if (mca_cfg.ignore_ce || !iv) |
62fdac59 HS |
1654 | return; |
1655 | ||
4f75d841 BP |
1656 | per_cpu(mce_next_interval, cpu) = iv; |
1657 | ||
82f7af09 | 1658 | t->expires = round_jiffies(jiffies + iv); |
4f75d841 | 1659 | add_timer_on(t, cpu); |
52d168e2 AK |
1660 | } |
1661 | ||
26c3c283 TG |
1662 | static void __mcheck_cpu_init_timer(void) |
1663 | { | |
89cbc767 | 1664 | struct timer_list *t = this_cpu_ptr(&mce_timer); |
26c3c283 TG |
1665 | unsigned int cpu = smp_processor_id(); |
1666 | ||
1667 | setup_timer(t, mce_timer_fn, cpu); | |
1668 | mce_start_timer(cpu, t); | |
1669 | } | |
1670 | ||
9eda8cb3 AK |
1671 | /* Handle unconfigured int18 (should never happen) */ |
1672 | static void unexpected_machine_check(struct pt_regs *regs, long error_code) | |
1673 | { | |
c767a54b | 1674 | pr_err("CPU#%d: Unexpected int18 (Machine Check)\n", |
9eda8cb3 AK |
1675 | smp_processor_id()); |
1676 | } | |
1677 | ||
1678 | /* Call the installed machine check handler for this CPU setup. */ | |
1679 | void (*machine_check_vector)(struct pt_regs *, long error_code) = | |
1680 | unexpected_machine_check; | |
1681 | ||
d88203d1 | 1682 | /* |
1da177e4 | 1683 | * Called for each booted CPU to set up machine checks. |
e9eee03e | 1684 | * Must be called with preempt off: |
1da177e4 | 1685 | */ |
148f9bb8 | 1686 | void mcheck_cpu_init(struct cpuinfo_x86 *c) |
1da177e4 | 1687 | { |
1462594b | 1688 | if (mca_cfg.disabled) |
4efc0670 AK |
1689 | return; |
1690 | ||
3a97fc34 HS |
1691 | if (__mcheck_cpu_ancient_init(c)) |
1692 | return; | |
4efc0670 | 1693 | |
5b4408fd | 1694 | if (!mce_available(c)) |
1da177e4 LT |
1695 | return; |
1696 | ||
5e09954a | 1697 | if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) { |
1462594b | 1698 | mca_cfg.disabled = true; |
0d7482e3 AK |
1699 | return; |
1700 | } | |
0d7482e3 | 1701 | |
5d727926 AK |
1702 | machine_check_vector = do_machine_check; |
1703 | ||
5e09954a BP |
1704 | __mcheck_cpu_init_generic(); |
1705 | __mcheck_cpu_init_vendor(c); | |
1706 | __mcheck_cpu_init_timer(); | |
89cbc767 CL |
1707 | INIT_WORK(this_cpu_ptr(&mce_work), mce_process_work); |
1708 | init_irq_work(this_cpu_ptr(&mce_irq_work), &mce_irq_work_cb); | |
1da177e4 LT |
1709 | } |
1710 | ||
1711 | /* | |
93b62c3c | 1712 | * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log. |
1da177e4 LT |
1713 | */ |
1714 | ||
93b62c3c HS |
1715 | static DEFINE_SPINLOCK(mce_chrdev_state_lock); |
1716 | static int mce_chrdev_open_count; /* #times opened */ | |
1717 | static int mce_chrdev_open_exclu; /* already open exclusive? */ | |
f528e7ba | 1718 | |
93b62c3c | 1719 | static int mce_chrdev_open(struct inode *inode, struct file *file) |
f528e7ba | 1720 | { |
93b62c3c | 1721 | spin_lock(&mce_chrdev_state_lock); |
f528e7ba | 1722 | |
93b62c3c HS |
1723 | if (mce_chrdev_open_exclu || |
1724 | (mce_chrdev_open_count && (file->f_flags & O_EXCL))) { | |
1725 | spin_unlock(&mce_chrdev_state_lock); | |
e9eee03e | 1726 | |
f528e7ba TH |
1727 | return -EBUSY; |
1728 | } | |
1729 | ||
1730 | if (file->f_flags & O_EXCL) | |
93b62c3c HS |
1731 | mce_chrdev_open_exclu = 1; |
1732 | mce_chrdev_open_count++; | |
f528e7ba | 1733 | |
93b62c3c | 1734 | spin_unlock(&mce_chrdev_state_lock); |
f528e7ba | 1735 | |
bd78432c | 1736 | return nonseekable_open(inode, file); |
f528e7ba TH |
1737 | } |
1738 | ||
93b62c3c | 1739 | static int mce_chrdev_release(struct inode *inode, struct file *file) |
f528e7ba | 1740 | { |
93b62c3c | 1741 | spin_lock(&mce_chrdev_state_lock); |
f528e7ba | 1742 | |
93b62c3c HS |
1743 | mce_chrdev_open_count--; |
1744 | mce_chrdev_open_exclu = 0; | |
f528e7ba | 1745 | |
93b62c3c | 1746 | spin_unlock(&mce_chrdev_state_lock); |
f528e7ba TH |
1747 | |
1748 | return 0; | |
1749 | } | |
1750 | ||
d88203d1 TG |
1751 | static void collect_tscs(void *data) |
1752 | { | |
1da177e4 | 1753 | unsigned long *cpu_tsc = (unsigned long *)data; |
d88203d1 | 1754 | |
1da177e4 | 1755 | rdtscll(cpu_tsc[smp_processor_id()]); |
d88203d1 | 1756 | } |
1da177e4 | 1757 | |
482908b4 HY |
1758 | static int mce_apei_read_done; |
1759 | ||
1760 | /* Collect MCE record of previous boot in persistent storage via APEI ERST. */ | |
1761 | static int __mce_read_apei(char __user **ubuf, size_t usize) | |
1762 | { | |
1763 | int rc; | |
1764 | u64 record_id; | |
1765 | struct mce m; | |
1766 | ||
1767 | if (usize < sizeof(struct mce)) | |
1768 | return -EINVAL; | |
1769 | ||
1770 | rc = apei_read_mce(&m, &record_id); | |
1771 | /* Error or no more MCE record */ | |
1772 | if (rc <= 0) { | |
1773 | mce_apei_read_done = 1; | |
fadd85f1 NH |
1774 | /* |
1775 | * When ERST is disabled, mce_chrdev_read() should return | |
1776 | * "no record" instead of "no device." | |
1777 | */ | |
1778 | if (rc == -ENODEV) | |
1779 | return 0; | |
482908b4 HY |
1780 | return rc; |
1781 | } | |
1782 | rc = -EFAULT; | |
1783 | if (copy_to_user(*ubuf, &m, sizeof(struct mce))) | |
1784 | return rc; | |
1785 | /* | |
1786 | * In fact, we should have cleared the record after that has | |
1787 | * been flushed to the disk or sent to network in | |
1788 | * /sbin/mcelog, but we have no interface to support that now, | |
1789 | * so just clear it to avoid duplication. | |
1790 | */ | |
1791 | rc = apei_clear_mce(record_id); | |
1792 | if (rc) { | |
1793 | mce_apei_read_done = 1; | |
1794 | return rc; | |
1795 | } | |
1796 | *ubuf += sizeof(struct mce); | |
1797 | ||
1798 | return 0; | |
1799 | } | |
1800 | ||
93b62c3c HS |
1801 | static ssize_t mce_chrdev_read(struct file *filp, char __user *ubuf, |
1802 | size_t usize, loff_t *off) | |
1da177e4 | 1803 | { |
e9eee03e | 1804 | char __user *buf = ubuf; |
f0de53bb | 1805 | unsigned long *cpu_tsc; |
ef41df43 | 1806 | unsigned prev, next; |
1da177e4 LT |
1807 | int i, err; |
1808 | ||
6bca67f9 | 1809 | cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL); |
f0de53bb AK |
1810 | if (!cpu_tsc) |
1811 | return -ENOMEM; | |
1812 | ||
93b62c3c | 1813 | mutex_lock(&mce_chrdev_read_mutex); |
482908b4 HY |
1814 | |
1815 | if (!mce_apei_read_done) { | |
1816 | err = __mce_read_apei(&buf, usize); | |
1817 | if (err || buf != ubuf) | |
1818 | goto out; | |
1819 | } | |
1820 | ||
f56e8a07 | 1821 | next = rcu_dereference_check_mce(mcelog.next); |
1da177e4 LT |
1822 | |
1823 | /* Only supports full reads right now */ | |
482908b4 HY |
1824 | err = -EINVAL; |
1825 | if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) | |
1826 | goto out; | |
1da177e4 LT |
1827 | |
1828 | err = 0; | |
ef41df43 HY |
1829 | prev = 0; |
1830 | do { | |
1831 | for (i = prev; i < next; i++) { | |
1832 | unsigned long start = jiffies; | |
559faa6b | 1833 | struct mce *m = &mcelog.entry[i]; |
ef41df43 | 1834 | |
559faa6b | 1835 | while (!m->finished) { |
ef41df43 | 1836 | if (time_after_eq(jiffies, start + 2)) { |
559faa6b | 1837 | memset(m, 0, sizeof(*m)); |
ef41df43 HY |
1838 | goto timeout; |
1839 | } | |
1840 | cpu_relax(); | |
673242c1 | 1841 | } |
ef41df43 | 1842 | smp_rmb(); |
559faa6b HS |
1843 | err |= copy_to_user(buf, m, sizeof(*m)); |
1844 | buf += sizeof(*m); | |
ef41df43 HY |
1845 | timeout: |
1846 | ; | |
673242c1 | 1847 | } |
1da177e4 | 1848 | |
ef41df43 HY |
1849 | memset(mcelog.entry + prev, 0, |
1850 | (next - prev) * sizeof(struct mce)); | |
1851 | prev = next; | |
1852 | next = cmpxchg(&mcelog.next, prev, 0); | |
1853 | } while (next != prev); | |
1da177e4 | 1854 | |
b2b18660 | 1855 | synchronize_sched(); |
1da177e4 | 1856 | |
d88203d1 TG |
1857 | /* |
1858 | * Collect entries that were still getting written before the | |
1859 | * synchronize. | |
1860 | */ | |
15c8b6c1 | 1861 | on_each_cpu(collect_tscs, cpu_tsc, 1); |
e9eee03e | 1862 | |
d88203d1 | 1863 | for (i = next; i < MCE_LOG_LEN; i++) { |
559faa6b HS |
1864 | struct mce *m = &mcelog.entry[i]; |
1865 | ||
1866 | if (m->finished && m->tsc < cpu_tsc[m->cpu]) { | |
1867 | err |= copy_to_user(buf, m, sizeof(*m)); | |
1da177e4 | 1868 | smp_rmb(); |
559faa6b HS |
1869 | buf += sizeof(*m); |
1870 | memset(m, 0, sizeof(*m)); | |
1da177e4 | 1871 | } |
d88203d1 | 1872 | } |
482908b4 HY |
1873 | |
1874 | if (err) | |
1875 | err = -EFAULT; | |
1876 | ||
1877 | out: | |
93b62c3c | 1878 | mutex_unlock(&mce_chrdev_read_mutex); |
f0de53bb | 1879 | kfree(cpu_tsc); |
e9eee03e | 1880 | |
482908b4 | 1881 | return err ? err : buf - ubuf; |
1da177e4 LT |
1882 | } |
1883 | ||
93b62c3c | 1884 | static unsigned int mce_chrdev_poll(struct file *file, poll_table *wait) |
e02e68d3 | 1885 | { |
93b62c3c | 1886 | poll_wait(file, &mce_chrdev_wait, wait); |
a4dd9925 | 1887 | if (rcu_access_index(mcelog.next)) |
e02e68d3 | 1888 | return POLLIN | POLLRDNORM; |
482908b4 HY |
1889 | if (!mce_apei_read_done && apei_check_mce()) |
1890 | return POLLIN | POLLRDNORM; | |
e02e68d3 TH |
1891 | return 0; |
1892 | } | |
1893 | ||
93b62c3c HS |
1894 | static long mce_chrdev_ioctl(struct file *f, unsigned int cmd, |
1895 | unsigned long arg) | |
1da177e4 LT |
1896 | { |
1897 | int __user *p = (int __user *)arg; | |
d88203d1 | 1898 | |
1da177e4 | 1899 | if (!capable(CAP_SYS_ADMIN)) |
d88203d1 | 1900 | return -EPERM; |
e9eee03e | 1901 | |
1da177e4 | 1902 | switch (cmd) { |
d88203d1 | 1903 | case MCE_GET_RECORD_LEN: |
1da177e4 LT |
1904 | return put_user(sizeof(struct mce), p); |
1905 | case MCE_GET_LOG_LEN: | |
d88203d1 | 1906 | return put_user(MCE_LOG_LEN, p); |
1da177e4 LT |
1907 | case MCE_GETCLEAR_FLAGS: { |
1908 | unsigned flags; | |
d88203d1 TG |
1909 | |
1910 | do { | |
1da177e4 | 1911 | flags = mcelog.flags; |
d88203d1 | 1912 | } while (cmpxchg(&mcelog.flags, flags, 0) != flags); |
e9eee03e | 1913 | |
d88203d1 | 1914 | return put_user(flags, p); |
1da177e4 LT |
1915 | } |
1916 | default: | |
d88203d1 TG |
1917 | return -ENOTTY; |
1918 | } | |
1da177e4 LT |
1919 | } |
1920 | ||
66f5ddf3 LT |
1921 | static ssize_t (*mce_write)(struct file *filp, const char __user *ubuf, |
1922 | size_t usize, loff_t *off); | |
1923 | ||
1924 | void register_mce_write_callback(ssize_t (*fn)(struct file *filp, | |
1925 | const char __user *ubuf, | |
1926 | size_t usize, loff_t *off)) | |
1927 | { | |
1928 | mce_write = fn; | |
1929 | } | |
1930 | EXPORT_SYMBOL_GPL(register_mce_write_callback); | |
1931 | ||
1932 | ssize_t mce_chrdev_write(struct file *filp, const char __user *ubuf, | |
1933 | size_t usize, loff_t *off) | |
1934 | { | |
1935 | if (mce_write) | |
1936 | return mce_write(filp, ubuf, usize, off); | |
1937 | else | |
1938 | return -EINVAL; | |
1939 | } | |
1940 | ||
1941 | static const struct file_operations mce_chrdev_ops = { | |
93b62c3c HS |
1942 | .open = mce_chrdev_open, |
1943 | .release = mce_chrdev_release, | |
1944 | .read = mce_chrdev_read, | |
66f5ddf3 | 1945 | .write = mce_chrdev_write, |
93b62c3c HS |
1946 | .poll = mce_chrdev_poll, |
1947 | .unlocked_ioctl = mce_chrdev_ioctl, | |
1948 | .llseek = no_llseek, | |
1da177e4 LT |
1949 | }; |
1950 | ||
93b62c3c | 1951 | static struct miscdevice mce_chrdev_device = { |
1da177e4 LT |
1952 | MISC_MCELOG_MINOR, |
1953 | "mcelog", | |
1954 | &mce_chrdev_ops, | |
1955 | }; | |
1956 | ||
c3d1fb56 NR |
1957 | static void __mce_disable_bank(void *arg) |
1958 | { | |
1959 | int bank = *((int *)arg); | |
89cbc767 | 1960 | __clear_bit(bank, this_cpu_ptr(mce_poll_banks)); |
c3d1fb56 NR |
1961 | cmci_disable_bank(bank); |
1962 | } | |
1963 | ||
1964 | void mce_disable_bank(int bank) | |
1965 | { | |
1966 | if (bank >= mca_cfg.banks) { | |
1967 | pr_warn(FW_BUG | |
1968 | "Ignoring request to disable invalid MCA bank %d.\n", | |
1969 | bank); | |
1970 | return; | |
1971 | } | |
1972 | set_bit(bank, mce_banks_ce_disabled); | |
1973 | on_each_cpu(__mce_disable_bank, &bank, 1); | |
1974 | } | |
1975 | ||
13503fa9 | 1976 | /* |
62fdac59 HS |
1977 | * mce=off Disables machine check |
1978 | * mce=no_cmci Disables CMCI | |
1979 | * mce=dont_log_ce Clears corrected events silently, no log created for CEs. | |
1980 | * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared. | |
3c079792 AK |
1981 | * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above) |
1982 | * monarchtimeout is how long to wait for other CPUs on machine | |
1983 | * check, or 0 to not wait | |
13503fa9 HS |
1984 | * mce=bootlog Log MCEs from before booting. Disabled by default on AMD. |
1985 | * mce=nobootlog Don't log MCEs from before booting. | |
450cc201 | 1986 | * mce=bios_cmci_threshold Don't program the CMCI threshold |
13503fa9 | 1987 | */ |
1da177e4 LT |
1988 | static int __init mcheck_enable(char *str) |
1989 | { | |
d203f0b8 BP |
1990 | struct mca_config *cfg = &mca_cfg; |
1991 | ||
e3346fc4 | 1992 | if (*str == 0) { |
4efc0670 | 1993 | enable_p5_mce(); |
e3346fc4 BZ |
1994 | return 1; |
1995 | } | |
4efc0670 AK |
1996 | if (*str == '=') |
1997 | str++; | |
1da177e4 | 1998 | if (!strcmp(str, "off")) |
1462594b | 1999 | cfg->disabled = true; |
62fdac59 | 2000 | else if (!strcmp(str, "no_cmci")) |
7af19e4a | 2001 | cfg->cmci_disabled = true; |
62fdac59 | 2002 | else if (!strcmp(str, "dont_log_ce")) |
d203f0b8 | 2003 | cfg->dont_log_ce = true; |
62fdac59 | 2004 | else if (!strcmp(str, "ignore_ce")) |
7af19e4a | 2005 | cfg->ignore_ce = true; |
13503fa9 | 2006 | else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) |
84c2559d | 2007 | cfg->bootlog = (str[0] == 'b'); |
450cc201 | 2008 | else if (!strcmp(str, "bios_cmci_threshold")) |
1462594b | 2009 | cfg->bios_cmci_threshold = true; |
3c079792 | 2010 | else if (isdigit(str[0])) { |
d203f0b8 | 2011 | get_option(&str, &(cfg->tolerant)); |
3c079792 AK |
2012 | if (*str == ',') { |
2013 | ++str; | |
84c2559d | 2014 | get_option(&str, &(cfg->monarch_timeout)); |
3c079792 AK |
2015 | } |
2016 | } else { | |
c767a54b | 2017 | pr_info("mce argument %s ignored. Please use /sys\n", str); |
13503fa9 HS |
2018 | return 0; |
2019 | } | |
9b41046c | 2020 | return 1; |
1da177e4 | 2021 | } |
4efc0670 | 2022 | __setup("mce", mcheck_enable); |
1da177e4 | 2023 | |
a2202aa2 | 2024 | int __init mcheck_init(void) |
b33a6363 | 2025 | { |
a2202aa2 | 2026 | mcheck_intel_therm_init(); |
43eaa2a1 | 2027 | mcheck_vendor_init_severity(); |
a2202aa2 | 2028 | |
b33a6363 BP |
2029 | return 0; |
2030 | } | |
b33a6363 | 2031 | |
d88203d1 | 2032 | /* |
c7cece89 | 2033 | * mce_syscore: PM support |
d88203d1 | 2034 | */ |
1da177e4 | 2035 | |
973a2dd1 AK |
2036 | /* |
2037 | * Disable machine checks on suspend and shutdown. We can't really handle | |
2038 | * them later. | |
2039 | */ | |
5e09954a | 2040 | static int mce_disable_error_reporting(void) |
973a2dd1 AK |
2041 | { |
2042 | int i; | |
2043 | ||
d203f0b8 | 2044 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2045 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2046 | |
cebe1820 | 2047 | if (b->init) |
a2d32bcb | 2048 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 2049 | } |
973a2dd1 AK |
2050 | return 0; |
2051 | } | |
2052 | ||
c7cece89 | 2053 | static int mce_syscore_suspend(void) |
973a2dd1 | 2054 | { |
5e09954a | 2055 | return mce_disable_error_reporting(); |
973a2dd1 AK |
2056 | } |
2057 | ||
c7cece89 | 2058 | static void mce_syscore_shutdown(void) |
973a2dd1 | 2059 | { |
f3c6ea1b | 2060 | mce_disable_error_reporting(); |
973a2dd1 AK |
2061 | } |
2062 | ||
e9eee03e IM |
2063 | /* |
2064 | * On resume clear all MCE state. Don't want to see leftovers from the BIOS. | |
2065 | * Only one CPU is active at this time, the others get re-added later using | |
2066 | * CPU hotplug: | |
2067 | */ | |
c7cece89 | 2068 | static void mce_syscore_resume(void) |
1da177e4 | 2069 | { |
5e09954a | 2070 | __mcheck_cpu_init_generic(); |
89cbc767 | 2071 | __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info)); |
1da177e4 LT |
2072 | } |
2073 | ||
f3c6ea1b | 2074 | static struct syscore_ops mce_syscore_ops = { |
c7cece89 HS |
2075 | .suspend = mce_syscore_suspend, |
2076 | .shutdown = mce_syscore_shutdown, | |
2077 | .resume = mce_syscore_resume, | |
f3c6ea1b RW |
2078 | }; |
2079 | ||
c7cece89 | 2080 | /* |
8a25a2fd | 2081 | * mce_device: Sysfs support |
c7cece89 HS |
2082 | */ |
2083 | ||
52d168e2 AK |
2084 | static void mce_cpu_restart(void *data) |
2085 | { | |
89cbc767 | 2086 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
33edbf02 | 2087 | return; |
5e09954a BP |
2088 | __mcheck_cpu_init_generic(); |
2089 | __mcheck_cpu_init_timer(); | |
52d168e2 AK |
2090 | } |
2091 | ||
1da177e4 | 2092 | /* Reinit MCEs after user configuration changes */ |
d88203d1 TG |
2093 | static void mce_restart(void) |
2094 | { | |
9aaef96f | 2095 | mce_timer_delete_all(); |
52d168e2 | 2096 | on_each_cpu(mce_cpu_restart, NULL, 1); |
1da177e4 LT |
2097 | } |
2098 | ||
9af43b54 | 2099 | /* Toggle features for corrected errors */ |
9aaef96f | 2100 | static void mce_disable_cmci(void *data) |
9af43b54 | 2101 | { |
89cbc767 | 2102 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
9af43b54 | 2103 | return; |
9af43b54 HS |
2104 | cmci_clear(); |
2105 | } | |
2106 | ||
2107 | static void mce_enable_ce(void *all) | |
2108 | { | |
89cbc767 | 2109 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
9af43b54 HS |
2110 | return; |
2111 | cmci_reenable(); | |
2112 | cmci_recheck(); | |
2113 | if (all) | |
5e09954a | 2114 | __mcheck_cpu_init_timer(); |
9af43b54 HS |
2115 | } |
2116 | ||
8a25a2fd | 2117 | static struct bus_type mce_subsys = { |
e9eee03e | 2118 | .name = "machinecheck", |
8a25a2fd | 2119 | .dev_name = "machinecheck", |
1da177e4 LT |
2120 | }; |
2121 | ||
d6126ef5 | 2122 | DEFINE_PER_CPU(struct device *, mce_device); |
e9eee03e | 2123 | |
e9eee03e | 2124 | void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); |
1da177e4 | 2125 | |
8a25a2fd | 2126 | static inline struct mce_bank *attr_to_bank(struct device_attribute *attr) |
cebe1820 AK |
2127 | { |
2128 | return container_of(attr, struct mce_bank, attr); | |
2129 | } | |
0d7482e3 | 2130 | |
8a25a2fd | 2131 | static ssize_t show_bank(struct device *s, struct device_attribute *attr, |
0d7482e3 AK |
2132 | char *buf) |
2133 | { | |
cebe1820 | 2134 | return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl); |
0d7482e3 AK |
2135 | } |
2136 | ||
8a25a2fd | 2137 | static ssize_t set_bank(struct device *s, struct device_attribute *attr, |
9319cec8 | 2138 | const char *buf, size_t size) |
0d7482e3 | 2139 | { |
9319cec8 | 2140 | u64 new; |
e9eee03e | 2141 | |
164109e3 | 2142 | if (kstrtou64(buf, 0, &new) < 0) |
0d7482e3 | 2143 | return -EINVAL; |
e9eee03e | 2144 | |
cebe1820 | 2145 | attr_to_bank(attr)->ctl = new; |
0d7482e3 | 2146 | mce_restart(); |
e9eee03e | 2147 | |
9319cec8 | 2148 | return size; |
0d7482e3 | 2149 | } |
a98f0dd3 | 2150 | |
e9eee03e | 2151 | static ssize_t |
8a25a2fd | 2152 | show_trigger(struct device *s, struct device_attribute *attr, char *buf) |
a98f0dd3 | 2153 | { |
1020bcbc | 2154 | strcpy(buf, mce_helper); |
a98f0dd3 | 2155 | strcat(buf, "\n"); |
1020bcbc | 2156 | return strlen(mce_helper) + 1; |
a98f0dd3 AK |
2157 | } |
2158 | ||
8a25a2fd | 2159 | static ssize_t set_trigger(struct device *s, struct device_attribute *attr, |
e9eee03e | 2160 | const char *buf, size_t siz) |
a98f0dd3 AK |
2161 | { |
2162 | char *p; | |
e9eee03e | 2163 | |
1020bcbc HS |
2164 | strncpy(mce_helper, buf, sizeof(mce_helper)); |
2165 | mce_helper[sizeof(mce_helper)-1] = 0; | |
1020bcbc | 2166 | p = strchr(mce_helper, '\n'); |
e9eee03e | 2167 | |
e9084ec9 | 2168 | if (p) |
e9eee03e IM |
2169 | *p = 0; |
2170 | ||
e9084ec9 | 2171 | return strlen(mce_helper) + !!p; |
a98f0dd3 AK |
2172 | } |
2173 | ||
8a25a2fd KS |
2174 | static ssize_t set_ignore_ce(struct device *s, |
2175 | struct device_attribute *attr, | |
9af43b54 HS |
2176 | const char *buf, size_t size) |
2177 | { | |
2178 | u64 new; | |
2179 | ||
164109e3 | 2180 | if (kstrtou64(buf, 0, &new) < 0) |
9af43b54 HS |
2181 | return -EINVAL; |
2182 | ||
7af19e4a | 2183 | if (mca_cfg.ignore_ce ^ !!new) { |
9af43b54 HS |
2184 | if (new) { |
2185 | /* disable ce features */ | |
9aaef96f HS |
2186 | mce_timer_delete_all(); |
2187 | on_each_cpu(mce_disable_cmci, NULL, 1); | |
7af19e4a | 2188 | mca_cfg.ignore_ce = true; |
9af43b54 HS |
2189 | } else { |
2190 | /* enable ce features */ | |
7af19e4a | 2191 | mca_cfg.ignore_ce = false; |
9af43b54 HS |
2192 | on_each_cpu(mce_enable_ce, (void *)1, 1); |
2193 | } | |
2194 | } | |
2195 | return size; | |
2196 | } | |
2197 | ||
8a25a2fd KS |
2198 | static ssize_t set_cmci_disabled(struct device *s, |
2199 | struct device_attribute *attr, | |
9af43b54 HS |
2200 | const char *buf, size_t size) |
2201 | { | |
2202 | u64 new; | |
2203 | ||
164109e3 | 2204 | if (kstrtou64(buf, 0, &new) < 0) |
9af43b54 HS |
2205 | return -EINVAL; |
2206 | ||
7af19e4a | 2207 | if (mca_cfg.cmci_disabled ^ !!new) { |
9af43b54 HS |
2208 | if (new) { |
2209 | /* disable cmci */ | |
9aaef96f | 2210 | on_each_cpu(mce_disable_cmci, NULL, 1); |
7af19e4a | 2211 | mca_cfg.cmci_disabled = true; |
9af43b54 HS |
2212 | } else { |
2213 | /* enable cmci */ | |
7af19e4a | 2214 | mca_cfg.cmci_disabled = false; |
9af43b54 HS |
2215 | on_each_cpu(mce_enable_ce, NULL, 1); |
2216 | } | |
2217 | } | |
2218 | return size; | |
2219 | } | |
2220 | ||
8a25a2fd KS |
2221 | static ssize_t store_int_with_restart(struct device *s, |
2222 | struct device_attribute *attr, | |
b56f642d AK |
2223 | const char *buf, size_t size) |
2224 | { | |
8a25a2fd | 2225 | ssize_t ret = device_store_int(s, attr, buf, size); |
b56f642d AK |
2226 | mce_restart(); |
2227 | return ret; | |
2228 | } | |
2229 | ||
8a25a2fd | 2230 | static DEVICE_ATTR(trigger, 0644, show_trigger, set_trigger); |
d203f0b8 | 2231 | static DEVICE_INT_ATTR(tolerant, 0644, mca_cfg.tolerant); |
84c2559d | 2232 | static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout); |
d203f0b8 | 2233 | static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce); |
e9eee03e | 2234 | |
8a25a2fd KS |
2235 | static struct dev_ext_attribute dev_attr_check_interval = { |
2236 | __ATTR(check_interval, 0644, device_show_int, store_int_with_restart), | |
b56f642d AK |
2237 | &check_interval |
2238 | }; | |
e9eee03e | 2239 | |
8a25a2fd | 2240 | static struct dev_ext_attribute dev_attr_ignore_ce = { |
7af19e4a BP |
2241 | __ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce), |
2242 | &mca_cfg.ignore_ce | |
9af43b54 HS |
2243 | }; |
2244 | ||
8a25a2fd | 2245 | static struct dev_ext_attribute dev_attr_cmci_disabled = { |
7af19e4a BP |
2246 | __ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled), |
2247 | &mca_cfg.cmci_disabled | |
9af43b54 HS |
2248 | }; |
2249 | ||
8a25a2fd KS |
2250 | static struct device_attribute *mce_device_attrs[] = { |
2251 | &dev_attr_tolerant.attr, | |
2252 | &dev_attr_check_interval.attr, | |
2253 | &dev_attr_trigger, | |
2254 | &dev_attr_monarch_timeout.attr, | |
2255 | &dev_attr_dont_log_ce.attr, | |
2256 | &dev_attr_ignore_ce.attr, | |
2257 | &dev_attr_cmci_disabled.attr, | |
a98f0dd3 AK |
2258 | NULL |
2259 | }; | |
1da177e4 | 2260 | |
8a25a2fd | 2261 | static cpumask_var_t mce_device_initialized; |
bae19fe0 | 2262 | |
e032d807 GKH |
2263 | static void mce_device_release(struct device *dev) |
2264 | { | |
2265 | kfree(dev); | |
2266 | } | |
2267 | ||
8a25a2fd | 2268 | /* Per cpu device init. All of the cpus still share the same ctrl bank: */ |
148f9bb8 | 2269 | static int mce_device_create(unsigned int cpu) |
1da177e4 | 2270 | { |
e032d807 | 2271 | struct device *dev; |
1da177e4 | 2272 | int err; |
b1f49f95 | 2273 | int i, j; |
92cb7612 | 2274 | |
90367556 | 2275 | if (!mce_available(&boot_cpu_data)) |
91c6d400 AK |
2276 | return -EIO; |
2277 | ||
e032d807 GKH |
2278 | dev = kzalloc(sizeof *dev, GFP_KERNEL); |
2279 | if (!dev) | |
2280 | return -ENOMEM; | |
8a25a2fd KS |
2281 | dev->id = cpu; |
2282 | dev->bus = &mce_subsys; | |
e032d807 | 2283 | dev->release = &mce_device_release; |
91c6d400 | 2284 | |
8a25a2fd | 2285 | err = device_register(dev); |
853d9b18 LK |
2286 | if (err) { |
2287 | put_device(dev); | |
d435d862 | 2288 | return err; |
853d9b18 | 2289 | } |
d435d862 | 2290 | |
8a25a2fd KS |
2291 | for (i = 0; mce_device_attrs[i]; i++) { |
2292 | err = device_create_file(dev, mce_device_attrs[i]); | |
d435d862 AM |
2293 | if (err) |
2294 | goto error; | |
2295 | } | |
d203f0b8 | 2296 | for (j = 0; j < mca_cfg.banks; j++) { |
8a25a2fd | 2297 | err = device_create_file(dev, &mce_banks[j].attr); |
0d7482e3 AK |
2298 | if (err) |
2299 | goto error2; | |
2300 | } | |
8a25a2fd | 2301 | cpumask_set_cpu(cpu, mce_device_initialized); |
d6126ef5 | 2302 | per_cpu(mce_device, cpu) = dev; |
91c6d400 | 2303 | |
d435d862 | 2304 | return 0; |
0d7482e3 | 2305 | error2: |
b1f49f95 | 2306 | while (--j >= 0) |
8a25a2fd | 2307 | device_remove_file(dev, &mce_banks[j].attr); |
d435d862 | 2308 | error: |
cb491fca | 2309 | while (--i >= 0) |
8a25a2fd | 2310 | device_remove_file(dev, mce_device_attrs[i]); |
cb491fca | 2311 | |
8a25a2fd | 2312 | device_unregister(dev); |
d435d862 | 2313 | |
91c6d400 AK |
2314 | return err; |
2315 | } | |
2316 | ||
148f9bb8 | 2317 | static void mce_device_remove(unsigned int cpu) |
91c6d400 | 2318 | { |
d6126ef5 | 2319 | struct device *dev = per_cpu(mce_device, cpu); |
73ca5358 SL |
2320 | int i; |
2321 | ||
8a25a2fd | 2322 | if (!cpumask_test_cpu(cpu, mce_device_initialized)) |
bae19fe0 AH |
2323 | return; |
2324 | ||
8a25a2fd KS |
2325 | for (i = 0; mce_device_attrs[i]; i++) |
2326 | device_remove_file(dev, mce_device_attrs[i]); | |
cb491fca | 2327 | |
d203f0b8 | 2328 | for (i = 0; i < mca_cfg.banks; i++) |
8a25a2fd | 2329 | device_remove_file(dev, &mce_banks[i].attr); |
cb491fca | 2330 | |
8a25a2fd KS |
2331 | device_unregister(dev); |
2332 | cpumask_clear_cpu(cpu, mce_device_initialized); | |
d6126ef5 | 2333 | per_cpu(mce_device, cpu) = NULL; |
91c6d400 | 2334 | } |
91c6d400 | 2335 | |
d6b75584 | 2336 | /* Make sure there are no machine checks on offlined CPUs. */ |
148f9bb8 | 2337 | static void mce_disable_cpu(void *h) |
d6b75584 | 2338 | { |
88ccbedd | 2339 | unsigned long action = *(unsigned long *)h; |
cb491fca | 2340 | int i; |
d6b75584 | 2341 | |
89cbc767 | 2342 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
d6b75584 | 2343 | return; |
767df1bd | 2344 | |
88ccbedd AK |
2345 | if (!(action & CPU_TASKS_FROZEN)) |
2346 | cmci_clear(); | |
d203f0b8 | 2347 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2348 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2349 | |
cebe1820 | 2350 | if (b->init) |
a2d32bcb | 2351 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 2352 | } |
d6b75584 AK |
2353 | } |
2354 | ||
148f9bb8 | 2355 | static void mce_reenable_cpu(void *h) |
d6b75584 | 2356 | { |
88ccbedd | 2357 | unsigned long action = *(unsigned long *)h; |
e9eee03e | 2358 | int i; |
d6b75584 | 2359 | |
89cbc767 | 2360 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
d6b75584 | 2361 | return; |
e9eee03e | 2362 | |
88ccbedd AK |
2363 | if (!(action & CPU_TASKS_FROZEN)) |
2364 | cmci_reenable(); | |
d203f0b8 | 2365 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2366 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2367 | |
cebe1820 | 2368 | if (b->init) |
a2d32bcb | 2369 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
06b7a7a5 | 2370 | } |
d6b75584 AK |
2371 | } |
2372 | ||
91c6d400 | 2373 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ |
148f9bb8 | 2374 | static int |
e9eee03e | 2375 | mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) |
91c6d400 AK |
2376 | { |
2377 | unsigned int cpu = (unsigned long)hcpu; | |
52d168e2 | 2378 | struct timer_list *t = &per_cpu(mce_timer, cpu); |
91c6d400 | 2379 | |
1a65f970 | 2380 | switch (action & ~CPU_TASKS_FROZEN) { |
bae19fe0 | 2381 | case CPU_ONLINE: |
8a25a2fd | 2382 | mce_device_create(cpu); |
8735728e RW |
2383 | if (threshold_cpu_callback) |
2384 | threshold_cpu_callback(action, cpu); | |
91c6d400 | 2385 | break; |
91c6d400 | 2386 | case CPU_DEAD: |
8735728e RW |
2387 | if (threshold_cpu_callback) |
2388 | threshold_cpu_callback(action, cpu); | |
8a25a2fd | 2389 | mce_device_remove(cpu); |
55babd8f | 2390 | mce_intel_hcpu_update(cpu); |
38356c1f BP |
2391 | |
2392 | /* intentionally ignoring frozen here */ | |
2393 | if (!(action & CPU_TASKS_FROZEN)) | |
2394 | cmci_rediscover(); | |
91c6d400 | 2395 | break; |
52d168e2 | 2396 | case CPU_DOWN_PREPARE: |
88ccbedd | 2397 | smp_call_function_single(cpu, mce_disable_cpu, &action, 1); |
55babd8f | 2398 | del_timer_sync(t); |
52d168e2 AK |
2399 | break; |
2400 | case CPU_DOWN_FAILED: | |
88ccbedd | 2401 | smp_call_function_single(cpu, mce_reenable_cpu, &action, 1); |
26c3c283 | 2402 | mce_start_timer(cpu, t); |
88ccbedd | 2403 | break; |
1a65f970 TG |
2404 | } |
2405 | ||
bae19fe0 | 2406 | return NOTIFY_OK; |
91c6d400 AK |
2407 | } |
2408 | ||
148f9bb8 | 2409 | static struct notifier_block mce_cpu_notifier = { |
91c6d400 AK |
2410 | .notifier_call = mce_cpu_callback, |
2411 | }; | |
2412 | ||
cebe1820 | 2413 | static __init void mce_init_banks(void) |
0d7482e3 AK |
2414 | { |
2415 | int i; | |
2416 | ||
d203f0b8 | 2417 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2418 | struct mce_bank *b = &mce_banks[i]; |
8a25a2fd | 2419 | struct device_attribute *a = &b->attr; |
e9eee03e | 2420 | |
a07e4156 | 2421 | sysfs_attr_init(&a->attr); |
cebe1820 AK |
2422 | a->attr.name = b->attrname; |
2423 | snprintf(b->attrname, ATTR_LEN, "bank%d", i); | |
e9eee03e IM |
2424 | |
2425 | a->attr.mode = 0644; | |
2426 | a->show = show_bank; | |
2427 | a->store = set_bank; | |
0d7482e3 | 2428 | } |
0d7482e3 AK |
2429 | } |
2430 | ||
5e09954a | 2431 | static __init int mcheck_init_device(void) |
91c6d400 AK |
2432 | { |
2433 | int err; | |
2434 | int i = 0; | |
2435 | ||
9c15a24b MS |
2436 | if (!mce_available(&boot_cpu_data)) { |
2437 | err = -EIO; | |
2438 | goto err_out; | |
2439 | } | |
0d7482e3 | 2440 | |
9c15a24b MS |
2441 | if (!zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL)) { |
2442 | err = -ENOMEM; | |
2443 | goto err_out; | |
2444 | } | |
996867d0 | 2445 | |
cebe1820 | 2446 | mce_init_banks(); |
0d7482e3 | 2447 | |
8a25a2fd | 2448 | err = subsys_system_register(&mce_subsys, NULL); |
d435d862 | 2449 | if (err) |
9c15a24b | 2450 | goto err_out_mem; |
91c6d400 | 2451 | |
82a8f131 | 2452 | cpu_notifier_register_begin(); |
91c6d400 | 2453 | for_each_online_cpu(i) { |
8a25a2fd | 2454 | err = mce_device_create(i); |
82a8f131 | 2455 | if (err) { |
27c93415 BP |
2456 | /* |
2457 | * Register notifier anyway (and do not unreg it) so | |
2458 | * that we don't leave undeleted timers, see notifier | |
2459 | * callback above. | |
2460 | */ | |
2461 | __register_hotcpu_notifier(&mce_cpu_notifier); | |
82a8f131 | 2462 | cpu_notifier_register_done(); |
9c15a24b | 2463 | goto err_device_create; |
82a8f131 | 2464 | } |
91c6d400 AK |
2465 | } |
2466 | ||
82a8f131 SB |
2467 | __register_hotcpu_notifier(&mce_cpu_notifier); |
2468 | cpu_notifier_register_done(); | |
93b62c3c | 2469 | |
9c15a24b MS |
2470 | register_syscore_ops(&mce_syscore_ops); |
2471 | ||
93b62c3c | 2472 | /* register character device /dev/mcelog */ |
9c15a24b MS |
2473 | err = misc_register(&mce_chrdev_device); |
2474 | if (err) | |
2475 | goto err_register; | |
2476 | ||
2477 | return 0; | |
2478 | ||
2479 | err_register: | |
2480 | unregister_syscore_ops(&mce_syscore_ops); | |
2481 | ||
9c15a24b MS |
2482 | err_device_create: |
2483 | /* | |
2484 | * We didn't keep track of which devices were created above, but | |
2485 | * even if we had, the set of online cpus might have changed. | |
2486 | * Play safe and remove for every possible cpu, since | |
2487 | * mce_device_remove() will do the right thing. | |
2488 | */ | |
2489 | for_each_possible_cpu(i) | |
2490 | mce_device_remove(i); | |
2491 | ||
2492 | err_out_mem: | |
2493 | free_cpumask_var(mce_device_initialized); | |
2494 | ||
2495 | err_out: | |
2496 | pr_err("Unable to init device /dev/mcelog (rc: %d)\n", err); | |
e9eee03e | 2497 | |
1da177e4 | 2498 | return err; |
1da177e4 | 2499 | } |
cef12ee5 | 2500 | device_initcall_sync(mcheck_init_device); |
a988d334 | 2501 | |
d7c3c9a6 AK |
2502 | /* |
2503 | * Old style boot options parsing. Only for compatibility. | |
2504 | */ | |
2505 | static int __init mcheck_disable(char *str) | |
2506 | { | |
1462594b | 2507 | mca_cfg.disabled = true; |
d7c3c9a6 AK |
2508 | return 1; |
2509 | } | |
2510 | __setup("nomce", mcheck_disable); | |
a988d334 | 2511 | |
5be9ed25 HY |
2512 | #ifdef CONFIG_DEBUG_FS |
2513 | struct dentry *mce_get_debugfs_dir(void) | |
a988d334 | 2514 | { |
5be9ed25 | 2515 | static struct dentry *dmce; |
a988d334 | 2516 | |
5be9ed25 HY |
2517 | if (!dmce) |
2518 | dmce = debugfs_create_dir("mce", NULL); | |
a988d334 | 2519 | |
5be9ed25 HY |
2520 | return dmce; |
2521 | } | |
a988d334 | 2522 | |
bf783f9f HY |
2523 | static void mce_reset(void) |
2524 | { | |
2525 | cpu_missing = 0; | |
c7c9b392 | 2526 | atomic_set(&mce_fake_panicked, 0); |
bf783f9f HY |
2527 | atomic_set(&mce_executing, 0); |
2528 | atomic_set(&mce_callin, 0); | |
2529 | atomic_set(&global_nwo, 0); | |
2530 | } | |
a988d334 | 2531 | |
bf783f9f HY |
2532 | static int fake_panic_get(void *data, u64 *val) |
2533 | { | |
2534 | *val = fake_panic; | |
2535 | return 0; | |
a988d334 IM |
2536 | } |
2537 | ||
bf783f9f | 2538 | static int fake_panic_set(void *data, u64 val) |
a988d334 | 2539 | { |
bf783f9f HY |
2540 | mce_reset(); |
2541 | fake_panic = val; | |
2542 | return 0; | |
a988d334 | 2543 | } |
a988d334 | 2544 | |
bf783f9f HY |
2545 | DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get, |
2546 | fake_panic_set, "%llu\n"); | |
d7c3c9a6 | 2547 | |
5e09954a | 2548 | static int __init mcheck_debugfs_init(void) |
d7c3c9a6 | 2549 | { |
bf783f9f HY |
2550 | struct dentry *dmce, *ffake_panic; |
2551 | ||
2552 | dmce = mce_get_debugfs_dir(); | |
2553 | if (!dmce) | |
2554 | return -ENOMEM; | |
2555 | ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL, | |
2556 | &fake_panic_fops); | |
2557 | if (!ffake_panic) | |
2558 | return -ENOMEM; | |
2559 | ||
2560 | return 0; | |
d7c3c9a6 | 2561 | } |
5e09954a | 2562 | late_initcall(mcheck_debugfs_init); |
5be9ed25 | 2563 | #endif |