Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Machine check handler. | |
e9eee03e | 3 | * |
1da177e4 | 4 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. |
d88203d1 TG |
5 | * Rest from unknown author(s). |
6 | * 2004 Andi Kleen. Rewrote most of it. | |
b79109c3 AK |
7 | * Copyright 2008 Intel Corporation |
8 | * Author: Andi Kleen | |
1da177e4 | 9 | */ |
e9eee03e IM |
10 | #include <linux/thread_info.h> |
11 | #include <linux/capability.h> | |
12 | #include <linux/miscdevice.h> | |
13 | #include <linux/ratelimit.h> | |
14 | #include <linux/kallsyms.h> | |
15 | #include <linux/rcupdate.h> | |
e9eee03e | 16 | #include <linux/kobject.h> |
14a02530 | 17 | #include <linux/uaccess.h> |
e9eee03e IM |
18 | #include <linux/kdebug.h> |
19 | #include <linux/kernel.h> | |
20 | #include <linux/percpu.h> | |
1da177e4 | 21 | #include <linux/string.h> |
1da177e4 | 22 | #include <linux/sysdev.h> |
8c566ef5 | 23 | #include <linux/ctype.h> |
e9eee03e | 24 | #include <linux/sched.h> |
0d7482e3 | 25 | #include <linux/sysfs.h> |
e9eee03e IM |
26 | #include <linux/types.h> |
27 | #include <linux/init.h> | |
28 | #include <linux/kmod.h> | |
29 | #include <linux/poll.h> | |
30 | #include <linux/cpu.h> | |
14a02530 | 31 | #include <linux/smp.h> |
e9eee03e IM |
32 | #include <linux/fs.h> |
33 | ||
d88203d1 | 34 | #include <asm/processor.h> |
e02e68d3 | 35 | #include <asm/idle.h> |
e9eee03e IM |
36 | #include <asm/mce.h> |
37 | #include <asm/msr.h> | |
1da177e4 | 38 | |
711c2e48 IM |
39 | #include "mce.h" |
40 | ||
5d727926 AK |
41 | /* Handle unconfigured int18 (should never happen) */ |
42 | static void unexpected_machine_check(struct pt_regs *regs, long error_code) | |
43 | { | |
44 | printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n", | |
45 | smp_processor_id()); | |
46 | } | |
47 | ||
48 | /* Call the installed machine check handler for this CPU setup. */ | |
49 | void (*machine_check_vector)(struct pt_regs *, long error_code) = | |
50 | unexpected_machine_check; | |
04b2b1a4 AK |
51 | |
52 | int mce_disabled; | |
53 | ||
4efc0670 | 54 | #ifdef CONFIG_X86_NEW_MCE |
711c2e48 | 55 | |
e9eee03e | 56 | #define MISC_MCELOG_MINOR 227 |
0d7482e3 | 57 | |
553f265f AK |
58 | atomic_t mce_entry; |
59 | ||
01ca79f1 AK |
60 | DEFINE_PER_CPU(unsigned, mce_exception_count); |
61 | ||
bd78432c TH |
62 | /* |
63 | * Tolerant levels: | |
64 | * 0: always panic on uncorrected errors, log corrected errors | |
65 | * 1: panic or SIGBUS on uncorrected errors, log corrected errors | |
66 | * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors | |
67 | * 3: never panic or SIGBUS, log all errors (for testing only) | |
68 | */ | |
e9eee03e IM |
69 | static int tolerant = 1; |
70 | static int banks; | |
71 | static u64 *bank; | |
72 | static unsigned long notify_user; | |
73 | static int rip_msr; | |
74 | static int mce_bootlog = -1; | |
a98f0dd3 | 75 | |
e9eee03e IM |
76 | static char trigger[128]; |
77 | static char *trigger_argv[2] = { trigger, NULL }; | |
1da177e4 | 78 | |
06b7a7a5 AK |
79 | static unsigned long dont_init_banks; |
80 | ||
e02e68d3 TH |
81 | static DECLARE_WAIT_QUEUE_HEAD(mce_wait); |
82 | ||
ee031c31 AK |
83 | /* MCA banks polled by the period polling timer for corrected events */ |
84 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { | |
85 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL | |
86 | }; | |
87 | ||
06b7a7a5 AK |
88 | static inline int skip_bank_init(int i) |
89 | { | |
90 | return i < BITS_PER_LONG && test_bit(i, &dont_init_banks); | |
91 | } | |
92 | ||
b5f2fa4e AK |
93 | /* Do initial initialization of a struct mce */ |
94 | void mce_setup(struct mce *m) | |
95 | { | |
96 | memset(m, 0, sizeof(struct mce)); | |
d620c67f | 97 | m->cpu = m->extcpu = smp_processor_id(); |
b5f2fa4e | 98 | rdtscll(m->tsc); |
8ee08347 AK |
99 | /* We hope get_seconds stays lockless */ |
100 | m->time = get_seconds(); | |
101 | m->cpuvendor = boot_cpu_data.x86_vendor; | |
102 | m->cpuid = cpuid_eax(1); | |
103 | #ifdef CONFIG_SMP | |
104 | m->socketid = cpu_data(m->extcpu).phys_proc_id; | |
105 | #endif | |
106 | m->apicid = cpu_data(m->extcpu).initial_apicid; | |
107 | rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap); | |
b5f2fa4e AK |
108 | } |
109 | ||
ea149b36 AK |
110 | DEFINE_PER_CPU(struct mce, injectm); |
111 | EXPORT_PER_CPU_SYMBOL_GPL(injectm); | |
112 | ||
1da177e4 LT |
113 | /* |
114 | * Lockless MCE logging infrastructure. | |
115 | * This avoids deadlocks on printk locks without having to break locks. Also | |
116 | * separate MCEs from kernel messages to avoid bogus bug reports. | |
117 | */ | |
118 | ||
231fd906 | 119 | static struct mce_log mcelog = { |
f6fb0ac0 AK |
120 | .signature = MCE_LOG_SIGNATURE, |
121 | .len = MCE_LOG_LEN, | |
122 | .recordlen = sizeof(struct mce), | |
d88203d1 | 123 | }; |
1da177e4 LT |
124 | |
125 | void mce_log(struct mce *mce) | |
126 | { | |
127 | unsigned next, entry; | |
e9eee03e | 128 | |
1da177e4 | 129 | mce->finished = 0; |
7644143c | 130 | wmb(); |
1da177e4 LT |
131 | for (;;) { |
132 | entry = rcu_dereference(mcelog.next); | |
673242c1 | 133 | for (;;) { |
e9eee03e IM |
134 | /* |
135 | * When the buffer fills up discard new entries. | |
136 | * Assume that the earlier errors are the more | |
137 | * interesting ones: | |
138 | */ | |
673242c1 | 139 | if (entry >= MCE_LOG_LEN) { |
14a02530 HS |
140 | set_bit(MCE_OVERFLOW, |
141 | (unsigned long *)&mcelog.flags); | |
673242c1 AK |
142 | return; |
143 | } | |
e9eee03e | 144 | /* Old left over entry. Skip: */ |
673242c1 AK |
145 | if (mcelog.entry[entry].finished) { |
146 | entry++; | |
147 | continue; | |
148 | } | |
7644143c | 149 | break; |
1da177e4 | 150 | } |
1da177e4 LT |
151 | smp_rmb(); |
152 | next = entry + 1; | |
153 | if (cmpxchg(&mcelog.next, entry, next) == entry) | |
154 | break; | |
155 | } | |
156 | memcpy(mcelog.entry + entry, mce, sizeof(struct mce)); | |
7644143c | 157 | wmb(); |
1da177e4 | 158 | mcelog.entry[entry].finished = 1; |
7644143c | 159 | wmb(); |
1da177e4 | 160 | |
a0189c70 | 161 | mce->finished = 1; |
e02e68d3 | 162 | set_bit(0, ¬ify_user); |
1da177e4 LT |
163 | } |
164 | ||
165 | static void print_mce(struct mce *m) | |
166 | { | |
167 | printk(KERN_EMERG "\n" | |
4855170f | 168 | KERN_EMERG "HARDWARE ERROR\n" |
1da177e4 LT |
169 | KERN_EMERG |
170 | "CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n", | |
d620c67f | 171 | m->extcpu, m->mcgstatus, m->bank, m->status); |
65ea5b03 | 172 | if (m->ip) { |
d88203d1 | 173 | printk(KERN_EMERG "RIP%s %02x:<%016Lx> ", |
1da177e4 | 174 | !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", |
65ea5b03 | 175 | m->cs, m->ip); |
1da177e4 | 176 | if (m->cs == __KERNEL_CS) |
65ea5b03 | 177 | print_symbol("{%s}", m->ip); |
1da177e4 LT |
178 | printk("\n"); |
179 | } | |
f6d1826d | 180 | printk(KERN_EMERG "TSC %llx ", m->tsc); |
1da177e4 | 181 | if (m->addr) |
f6d1826d | 182 | printk("ADDR %llx ", m->addr); |
1da177e4 | 183 | if (m->misc) |
f6d1826d | 184 | printk("MISC %llx ", m->misc); |
1da177e4 | 185 | printk("\n"); |
8ee08347 AK |
186 | printk(KERN_EMERG "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n", |
187 | m->cpuvendor, m->cpuid, m->time, m->socketid, | |
188 | m->apicid); | |
4855170f | 189 | printk(KERN_EMERG "This is not a software problem!\n"); |
d88203d1 TG |
190 | printk(KERN_EMERG "Run through mcelog --ascii to decode " |
191 | "and contact your hardware vendor\n"); | |
1da177e4 LT |
192 | } |
193 | ||
a0189c70 | 194 | static void mce_panic(char *msg, struct mce *final) |
d88203d1 | 195 | { |
1da177e4 | 196 | int i; |
e02e68d3 | 197 | |
d896a940 AK |
198 | bust_spinlocks(1); |
199 | console_verbose(); | |
a0189c70 | 200 | /* First print corrected ones that are still unlogged */ |
1da177e4 | 201 | for (i = 0; i < MCE_LOG_LEN; i++) { |
a0189c70 AK |
202 | struct mce *m = &mcelog.entry[i]; |
203 | if ((m->status & MCI_STATUS_VAL) && | |
204 | !(m->status & MCI_STATUS_UC)) | |
205 | print_mce(m); | |
206 | } | |
207 | /* Now print uncorrected but with the final one last */ | |
208 | for (i = 0; i < MCE_LOG_LEN; i++) { | |
209 | struct mce *m = &mcelog.entry[i]; | |
210 | if (!(m->status & MCI_STATUS_VAL)) | |
1da177e4 | 211 | continue; |
a0189c70 AK |
212 | if (!final || memcmp(m, final, sizeof(struct mce))) |
213 | print_mce(m); | |
1da177e4 | 214 | } |
a0189c70 AK |
215 | if (final) |
216 | print_mce(final); | |
e02e68d3 | 217 | panic(msg); |
d88203d1 | 218 | } |
1da177e4 | 219 | |
ea149b36 AK |
220 | /* Support code for software error injection */ |
221 | ||
222 | static int msr_to_offset(u32 msr) | |
223 | { | |
224 | unsigned bank = __get_cpu_var(injectm.bank); | |
225 | if (msr == rip_msr) | |
226 | return offsetof(struct mce, ip); | |
227 | if (msr == MSR_IA32_MC0_STATUS + bank*4) | |
228 | return offsetof(struct mce, status); | |
229 | if (msr == MSR_IA32_MC0_ADDR + bank*4) | |
230 | return offsetof(struct mce, addr); | |
231 | if (msr == MSR_IA32_MC0_MISC + bank*4) | |
232 | return offsetof(struct mce, misc); | |
233 | if (msr == MSR_IA32_MCG_STATUS) | |
234 | return offsetof(struct mce, mcgstatus); | |
235 | return -1; | |
236 | } | |
237 | ||
5f8c1a54 AK |
238 | /* MSR access wrappers used for error injection */ |
239 | static u64 mce_rdmsrl(u32 msr) | |
240 | { | |
241 | u64 v; | |
ea149b36 AK |
242 | if (__get_cpu_var(injectm).finished) { |
243 | int offset = msr_to_offset(msr); | |
244 | if (offset < 0) | |
245 | return 0; | |
246 | return *(u64 *)((char *)&__get_cpu_var(injectm) + offset); | |
247 | } | |
5f8c1a54 AK |
248 | rdmsrl(msr, v); |
249 | return v; | |
250 | } | |
251 | ||
252 | static void mce_wrmsrl(u32 msr, u64 v) | |
253 | { | |
ea149b36 AK |
254 | if (__get_cpu_var(injectm).finished) { |
255 | int offset = msr_to_offset(msr); | |
256 | if (offset >= 0) | |
257 | *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v; | |
258 | return; | |
259 | } | |
5f8c1a54 AK |
260 | wrmsrl(msr, v); |
261 | } | |
262 | ||
88ccbedd | 263 | int mce_available(struct cpuinfo_x86 *c) |
1da177e4 | 264 | { |
04b2b1a4 | 265 | if (mce_disabled) |
5b4408fd | 266 | return 0; |
3d1712c9 | 267 | return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); |
1da177e4 LT |
268 | } |
269 | ||
94ad8474 AK |
270 | static inline void mce_get_rip(struct mce *m, struct pt_regs *regs) |
271 | { | |
272 | if (regs && (m->mcgstatus & MCG_STATUS_RIPV)) { | |
65ea5b03 | 273 | m->ip = regs->ip; |
94ad8474 AK |
274 | m->cs = regs->cs; |
275 | } else { | |
65ea5b03 | 276 | m->ip = 0; |
94ad8474 AK |
277 | m->cs = 0; |
278 | } | |
279 | if (rip_msr) { | |
280 | /* Assume the RIP in the MSR is exact. Is this true? */ | |
281 | m->mcgstatus |= MCG_STATUS_EIPV; | |
5f8c1a54 | 282 | m->ip = mce_rdmsrl(rip_msr); |
94ad8474 AK |
283 | m->cs = 0; |
284 | } | |
285 | } | |
286 | ||
ca84f696 AK |
287 | DEFINE_PER_CPU(unsigned, mce_poll_count); |
288 | ||
d88203d1 | 289 | /* |
b79109c3 AK |
290 | * Poll for corrected events or events that happened before reset. |
291 | * Those are just logged through /dev/mcelog. | |
292 | * | |
293 | * This is executed in standard interrupt context. | |
294 | */ | |
ee031c31 | 295 | void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) |
b79109c3 AK |
296 | { |
297 | struct mce m; | |
298 | int i; | |
299 | ||
ca84f696 AK |
300 | __get_cpu_var(mce_poll_count)++; |
301 | ||
b79109c3 AK |
302 | mce_setup(&m); |
303 | ||
5f8c1a54 | 304 | m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); |
b79109c3 | 305 | for (i = 0; i < banks; i++) { |
ee031c31 | 306 | if (!bank[i] || !test_bit(i, *b)) |
b79109c3 AK |
307 | continue; |
308 | ||
309 | m.misc = 0; | |
310 | m.addr = 0; | |
311 | m.bank = i; | |
312 | m.tsc = 0; | |
313 | ||
314 | barrier(); | |
5f8c1a54 | 315 | m.status = mce_rdmsrl(MSR_IA32_MC0_STATUS + i*4); |
b79109c3 AK |
316 | if (!(m.status & MCI_STATUS_VAL)) |
317 | continue; | |
318 | ||
319 | /* | |
320 | * Uncorrected events are handled by the exception handler | |
321 | * when it is enabled. But when the exception is disabled log | |
322 | * everything. | |
323 | * | |
324 | * TBD do the same check for MCI_STATUS_EN here? | |
325 | */ | |
326 | if ((m.status & MCI_STATUS_UC) && !(flags & MCP_UC)) | |
327 | continue; | |
328 | ||
329 | if (m.status & MCI_STATUS_MISCV) | |
5f8c1a54 | 330 | m.misc = mce_rdmsrl(MSR_IA32_MC0_MISC + i*4); |
b79109c3 | 331 | if (m.status & MCI_STATUS_ADDRV) |
5f8c1a54 | 332 | m.addr = mce_rdmsrl(MSR_IA32_MC0_ADDR + i*4); |
b79109c3 AK |
333 | |
334 | if (!(flags & MCP_TIMESTAMP)) | |
335 | m.tsc = 0; | |
336 | /* | |
337 | * Don't get the IP here because it's unlikely to | |
338 | * have anything to do with the actual error location. | |
339 | */ | |
5679af4c AK |
340 | if (!(flags & MCP_DONTLOG)) { |
341 | mce_log(&m); | |
342 | add_taint(TAINT_MACHINE_CHECK); | |
343 | } | |
b79109c3 AK |
344 | |
345 | /* | |
346 | * Clear state for this bank. | |
347 | */ | |
5f8c1a54 | 348 | mce_wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); |
b79109c3 AK |
349 | } |
350 | ||
351 | /* | |
352 | * Don't clear MCG_STATUS here because it's only defined for | |
353 | * exceptions. | |
354 | */ | |
88921be3 AK |
355 | |
356 | sync_core(); | |
b79109c3 | 357 | } |
ea149b36 | 358 | EXPORT_SYMBOL_GPL(machine_check_poll); |
b79109c3 AK |
359 | |
360 | /* | |
361 | * The actual machine check handler. This only handles real | |
362 | * exceptions when something got corrupted coming in through int 18. | |
363 | * | |
364 | * This is executed in NMI context not subject to normal locking rules. This | |
365 | * implies that most kernel services cannot be safely used. Don't even | |
366 | * think about putting a printk in there! | |
1da177e4 | 367 | */ |
e9eee03e | 368 | void do_machine_check(struct pt_regs *regs, long error_code) |
1da177e4 LT |
369 | { |
370 | struct mce m, panicm; | |
e9eee03e | 371 | int panicm_found = 0; |
1da177e4 | 372 | int i; |
bd78432c TH |
373 | /* |
374 | * If no_way_out gets set, there is no safe way to recover from this | |
375 | * MCE. If tolerant is cranked up, we'll try anyway. | |
376 | */ | |
377 | int no_way_out = 0; | |
378 | /* | |
379 | * If kill_it gets set, there might be a way to recover from this | |
380 | * error. | |
381 | */ | |
382 | int kill_it = 0; | |
b79109c3 | 383 | DECLARE_BITMAP(toclear, MAX_NR_BANKS); |
1da177e4 | 384 | |
553f265f AK |
385 | atomic_inc(&mce_entry); |
386 | ||
01ca79f1 AK |
387 | __get_cpu_var(mce_exception_count)++; |
388 | ||
b79109c3 | 389 | if (notify_die(DIE_NMI, "machine check", regs, error_code, |
22f5991c | 390 | 18, SIGKILL) == NOTIFY_STOP) |
32561696 | 391 | goto out; |
b79109c3 | 392 | if (!banks) |
32561696 | 393 | goto out; |
1da177e4 | 394 | |
b5f2fa4e AK |
395 | mce_setup(&m); |
396 | ||
5f8c1a54 | 397 | m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); |
e9eee03e | 398 | |
bd78432c | 399 | /* if the restart IP is not valid, we're done for */ |
1da177e4 | 400 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) |
bd78432c | 401 | no_way_out = 1; |
d88203d1 | 402 | |
1da177e4 LT |
403 | barrier(); |
404 | ||
405 | for (i = 0; i < banks; i++) { | |
b79109c3 | 406 | __clear_bit(i, toclear); |
0d7482e3 | 407 | if (!bank[i]) |
1da177e4 | 408 | continue; |
d88203d1 TG |
409 | |
410 | m.misc = 0; | |
1da177e4 LT |
411 | m.addr = 0; |
412 | m.bank = i; | |
1da177e4 | 413 | |
5f8c1a54 | 414 | m.status = mce_rdmsrl(MSR_IA32_MC0_STATUS + i*4); |
1da177e4 LT |
415 | if ((m.status & MCI_STATUS_VAL) == 0) |
416 | continue; | |
417 | ||
b79109c3 AK |
418 | /* |
419 | * Non uncorrected errors are handled by machine_check_poll | |
de8a84d8 | 420 | * Leave them alone, unless this panics. |
b79109c3 | 421 | */ |
de8a84d8 | 422 | if ((m.status & MCI_STATUS_UC) == 0 && !no_way_out) |
b79109c3 AK |
423 | continue; |
424 | ||
425 | /* | |
426 | * Set taint even when machine check was not enabled. | |
427 | */ | |
428 | add_taint(TAINT_MACHINE_CHECK); | |
429 | ||
430 | __set_bit(i, toclear); | |
431 | ||
1da177e4 | 432 | if (m.status & MCI_STATUS_EN) { |
bd78432c TH |
433 | /* if PCC was set, there's no way out */ |
434 | no_way_out |= !!(m.status & MCI_STATUS_PCC); | |
435 | /* | |
436 | * If this error was uncorrectable and there was | |
437 | * an overflow, we're in trouble. If no overflow, | |
438 | * we might get away with just killing a task. | |
439 | */ | |
440 | if (m.status & MCI_STATUS_UC) { | |
441 | if (tolerant < 1 || m.status & MCI_STATUS_OVER) | |
442 | no_way_out = 1; | |
443 | kill_it = 1; | |
444 | } | |
b79109c3 AK |
445 | } else { |
446 | /* | |
447 | * Machine check event was not enabled. Clear, but | |
448 | * ignore. | |
449 | */ | |
450 | continue; | |
1da177e4 LT |
451 | } |
452 | ||
453 | if (m.status & MCI_STATUS_MISCV) | |
5f8c1a54 | 454 | m.misc = mce_rdmsrl(MSR_IA32_MC0_MISC + i*4); |
1da177e4 | 455 | if (m.status & MCI_STATUS_ADDRV) |
5f8c1a54 | 456 | m.addr = mce_rdmsrl(MSR_IA32_MC0_ADDR + i*4); |
1da177e4 | 457 | |
94ad8474 | 458 | mce_get_rip(&m, regs); |
b79109c3 | 459 | mce_log(&m); |
1da177e4 | 460 | |
e9eee03e IM |
461 | /* |
462 | * Did this bank cause the exception? | |
463 | * | |
464 | * Assume that the bank with uncorrectable errors did it, | |
465 | * and that there is only a single one: | |
466 | */ | |
467 | if ((m.status & MCI_STATUS_UC) && | |
468 | (m.status & MCI_STATUS_EN)) { | |
1da177e4 LT |
469 | panicm = m; |
470 | panicm_found = 1; | |
471 | } | |
1da177e4 LT |
472 | } |
473 | ||
e9eee03e IM |
474 | /* |
475 | * If we didn't find an uncorrectable error, pick | |
476 | * the last one (shouldn't happen, just being safe). | |
477 | */ | |
1da177e4 LT |
478 | if (!panicm_found) |
479 | panicm = m; | |
bd78432c TH |
480 | |
481 | /* | |
482 | * If we have decided that we just CAN'T continue, and the user | |
e9eee03e | 483 | * has not set tolerant to an insane level, give up and die. |
bd78432c TH |
484 | */ |
485 | if (no_way_out && tolerant < 3) | |
a0189c70 | 486 | mce_panic("Machine check", &panicm); |
bd78432c TH |
487 | |
488 | /* | |
489 | * If the error seems to be unrecoverable, something should be | |
490 | * done. Try to kill as little as possible. If we can kill just | |
491 | * one task, do that. If the user has set the tolerance very | |
492 | * high, don't try to do anything at all. | |
493 | */ | |
494 | if (kill_it && tolerant < 3) { | |
1da177e4 LT |
495 | int user_space = 0; |
496 | ||
bd78432c TH |
497 | /* |
498 | * If the EIPV bit is set, it means the saved IP is the | |
499 | * instruction which caused the MCE. | |
500 | */ | |
501 | if (m.mcgstatus & MCG_STATUS_EIPV) | |
65ea5b03 | 502 | user_space = panicm.ip && (panicm.cs & 3); |
bd78432c TH |
503 | |
504 | /* | |
505 | * If we know that the error was in user space, send a | |
506 | * SIGBUS. Otherwise, panic if tolerance is low. | |
507 | * | |
380851bc | 508 | * force_sig() takes an awful lot of locks and has a slight |
bd78432c TH |
509 | * risk of deadlocking. |
510 | */ | |
511 | if (user_space) { | |
380851bc | 512 | force_sig(SIGBUS, current); |
bd78432c | 513 | } else if (panic_on_oops || tolerant < 2) { |
a0189c70 | 514 | mce_panic("Uncorrected machine check", &panicm); |
bd78432c | 515 | } |
1da177e4 LT |
516 | } |
517 | ||
e02e68d3 TH |
518 | /* notify userspace ASAP */ |
519 | set_thread_flag(TIF_MCE_NOTIFY); | |
520 | ||
bd78432c | 521 | /* the last thing we do is clear state */ |
b79109c3 AK |
522 | for (i = 0; i < banks; i++) { |
523 | if (test_bit(i, toclear)) | |
5f8c1a54 | 524 | mce_wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); |
b79109c3 | 525 | } |
5f8c1a54 | 526 | mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); |
32561696 | 527 | out: |
553f265f | 528 | atomic_dec(&mce_entry); |
88921be3 | 529 | sync_core(); |
1da177e4 | 530 | } |
ea149b36 | 531 | EXPORT_SYMBOL_GPL(do_machine_check); |
1da177e4 | 532 | |
15d5f839 DZ |
533 | #ifdef CONFIG_X86_MCE_INTEL |
534 | /*** | |
535 | * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog | |
676b1855 | 536 | * @cpu: The CPU on which the event occurred. |
15d5f839 DZ |
537 | * @status: Event status information |
538 | * | |
539 | * This function should be called by the thermal interrupt after the | |
540 | * event has been processed and the decision was made to log the event | |
541 | * further. | |
542 | * | |
543 | * The status parameter will be saved to the 'status' field of 'struct mce' | |
544 | * and historically has been the register value of the | |
545 | * MSR_IA32_THERMAL_STATUS (Intel) msr. | |
546 | */ | |
b5f2fa4e | 547 | void mce_log_therm_throt_event(__u64 status) |
15d5f839 DZ |
548 | { |
549 | struct mce m; | |
550 | ||
b5f2fa4e | 551 | mce_setup(&m); |
15d5f839 DZ |
552 | m.bank = MCE_THERMAL_BANK; |
553 | m.status = status; | |
15d5f839 DZ |
554 | mce_log(&m); |
555 | } | |
556 | #endif /* CONFIG_X86_MCE_INTEL */ | |
557 | ||
1da177e4 | 558 | /* |
8a336b0a TH |
559 | * Periodic polling timer for "silent" machine check errors. If the |
560 | * poller finds an MCE, poll 2x faster. When the poller finds no more | |
561 | * errors, poll 2x slower (up to check_interval seconds). | |
1da177e4 | 562 | */ |
1da177e4 | 563 | static int check_interval = 5 * 60; /* 5 minutes */ |
e9eee03e | 564 | |
6298c512 | 565 | static DEFINE_PER_CPU(int, next_interval); /* in jiffies */ |
52d168e2 | 566 | static DEFINE_PER_CPU(struct timer_list, mce_timer); |
1da177e4 | 567 | |
52d168e2 | 568 | static void mcheck_timer(unsigned long data) |
1da177e4 | 569 | { |
52d168e2 | 570 | struct timer_list *t = &per_cpu(mce_timer, data); |
6298c512 | 571 | int *n; |
52d168e2 AK |
572 | |
573 | WARN_ON(smp_processor_id() != data); | |
574 | ||
e9eee03e | 575 | if (mce_available(¤t_cpu_data)) { |
ee031c31 AK |
576 | machine_check_poll(MCP_TIMESTAMP, |
577 | &__get_cpu_var(mce_poll_banks)); | |
e9eee03e | 578 | } |
1da177e4 LT |
579 | |
580 | /* | |
e02e68d3 TH |
581 | * Alert userspace if needed. If we logged an MCE, reduce the |
582 | * polling interval, otherwise increase the polling interval. | |
1da177e4 | 583 | */ |
6298c512 | 584 | n = &__get_cpu_var(next_interval); |
14a02530 | 585 | if (mce_notify_user()) |
6298c512 | 586 | *n = max(*n/2, HZ/100); |
14a02530 | 587 | else |
6298c512 | 588 | *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ)); |
e02e68d3 | 589 | |
6298c512 | 590 | t->expires = jiffies + *n; |
52d168e2 | 591 | add_timer(t); |
e02e68d3 TH |
592 | } |
593 | ||
9bd98405 AK |
594 | static void mce_do_trigger(struct work_struct *work) |
595 | { | |
596 | call_usermodehelper(trigger, trigger_argv, NULL, UMH_NO_WAIT); | |
597 | } | |
598 | ||
599 | static DECLARE_WORK(mce_trigger_work, mce_do_trigger); | |
600 | ||
e02e68d3 | 601 | /* |
9bd98405 AK |
602 | * Notify the user(s) about new machine check events. |
603 | * Can be called from interrupt context, but not from machine check/NMI | |
604 | * context. | |
e02e68d3 TH |
605 | */ |
606 | int mce_notify_user(void) | |
607 | { | |
8457c84d AK |
608 | /* Not more than two messages every minute */ |
609 | static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); | |
610 | ||
e02e68d3 | 611 | clear_thread_flag(TIF_MCE_NOTIFY); |
e9eee03e | 612 | |
e02e68d3 | 613 | if (test_and_clear_bit(0, ¬ify_user)) { |
e02e68d3 | 614 | wake_up_interruptible(&mce_wait); |
9bd98405 AK |
615 | |
616 | /* | |
617 | * There is no risk of missing notifications because | |
618 | * work_pending is always cleared before the function is | |
619 | * executed. | |
620 | */ | |
621 | if (trigger[0] && !work_pending(&mce_trigger_work)) | |
622 | schedule_work(&mce_trigger_work); | |
e02e68d3 | 623 | |
8457c84d | 624 | if (__ratelimit(&ratelimit)) |
8a336b0a | 625 | printk(KERN_INFO "Machine check events logged\n"); |
e02e68d3 TH |
626 | |
627 | return 1; | |
1da177e4 | 628 | } |
e02e68d3 TH |
629 | return 0; |
630 | } | |
ea149b36 | 631 | EXPORT_SYMBOL_GPL(mce_notify_user); |
8a336b0a | 632 | |
d88203d1 | 633 | /* |
1da177e4 LT |
634 | * Initialize Machine Checks for a CPU. |
635 | */ | |
0d7482e3 | 636 | static int mce_cap_init(void) |
1da177e4 | 637 | { |
0d7482e3 | 638 | unsigned b; |
e9eee03e | 639 | u64 cap; |
1da177e4 LT |
640 | |
641 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
01c6680a TG |
642 | |
643 | b = cap & MCG_BANKCNT_MASK; | |
b659294b IM |
644 | printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b); |
645 | ||
0d7482e3 AK |
646 | if (b > MAX_NR_BANKS) { |
647 | printk(KERN_WARNING | |
648 | "MCE: Using only %u machine check banks out of %u\n", | |
649 | MAX_NR_BANKS, b); | |
650 | b = MAX_NR_BANKS; | |
651 | } | |
652 | ||
653 | /* Don't support asymmetric configurations today */ | |
654 | WARN_ON(banks != 0 && b != banks); | |
655 | banks = b; | |
656 | if (!bank) { | |
657 | bank = kmalloc(banks * sizeof(u64), GFP_KERNEL); | |
658 | if (!bank) | |
659 | return -ENOMEM; | |
660 | memset(bank, 0xff, banks * sizeof(u64)); | |
1da177e4 | 661 | } |
0d7482e3 | 662 | |
94ad8474 | 663 | /* Use accurate RIP reporting if available. */ |
01c6680a | 664 | if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) |
94ad8474 | 665 | rip_msr = MSR_IA32_MCG_EIP; |
1da177e4 | 666 | |
0d7482e3 AK |
667 | return 0; |
668 | } | |
669 | ||
8be91105 | 670 | static void mce_init(void) |
0d7482e3 | 671 | { |
e9eee03e | 672 | mce_banks_t all_banks; |
0d7482e3 AK |
673 | u64 cap; |
674 | int i; | |
675 | ||
b79109c3 AK |
676 | /* |
677 | * Log the machine checks left over from the previous reset. | |
678 | */ | |
ee031c31 | 679 | bitmap_fill(all_banks, MAX_NR_BANKS); |
5679af4c | 680 | machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks); |
1da177e4 LT |
681 | |
682 | set_in_cr4(X86_CR4_MCE); | |
683 | ||
0d7482e3 | 684 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
1da177e4 LT |
685 | if (cap & MCG_CTL_P) |
686 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); | |
687 | ||
688 | for (i = 0; i < banks; i++) { | |
06b7a7a5 AK |
689 | if (skip_bank_init(i)) |
690 | continue; | |
0d7482e3 | 691 | wrmsrl(MSR_IA32_MC0_CTL+4*i, bank[i]); |
1da177e4 | 692 | wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); |
d88203d1 | 693 | } |
1da177e4 LT |
694 | } |
695 | ||
696 | /* Add per CPU specific workarounds here */ | |
ec5b3d32 | 697 | static void mce_cpu_quirks(struct cpuinfo_x86 *c) |
d88203d1 | 698 | { |
1da177e4 | 699 | /* This should be disabled by the BIOS, but isn't always */ |
911f6a7b | 700 | if (c->x86_vendor == X86_VENDOR_AMD) { |
e9eee03e IM |
701 | if (c->x86 == 15 && banks > 4) { |
702 | /* | |
703 | * disable GART TBL walk error reporting, which | |
704 | * trips off incorrectly with the IOMMU & 3ware | |
705 | * & Cerberus: | |
706 | */ | |
0d7482e3 | 707 | clear_bit(10, (unsigned long *)&bank[4]); |
e9eee03e IM |
708 | } |
709 | if (c->x86 <= 17 && mce_bootlog < 0) { | |
710 | /* | |
711 | * Lots of broken BIOS around that don't clear them | |
712 | * by default and leave crap in there. Don't log: | |
713 | */ | |
911f6a7b | 714 | mce_bootlog = 0; |
e9eee03e | 715 | } |
2e6f694f AK |
716 | /* |
717 | * Various K7s with broken bank 0 around. Always disable | |
718 | * by default. | |
719 | */ | |
720 | if (c->x86 == 6) | |
721 | bank[0] = 0; | |
1da177e4 | 722 | } |
e583538f | 723 | |
06b7a7a5 AK |
724 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
725 | /* | |
726 | * SDM documents that on family 6 bank 0 should not be written | |
727 | * because it aliases to another special BIOS controlled | |
728 | * register. | |
729 | * But it's not aliased anymore on model 0x1a+ | |
730 | * Don't ignore bank 0 completely because there could be a | |
731 | * valid event later, merely don't write CTL0. | |
732 | */ | |
733 | ||
734 | if (c->x86 == 6 && c->x86_model < 0x1A) | |
735 | __set_bit(0, &dont_init_banks); | |
736 | } | |
d88203d1 | 737 | } |
1da177e4 | 738 | |
4efc0670 AK |
739 | static void __cpuinit mce_ancient_init(struct cpuinfo_x86 *c) |
740 | { | |
741 | if (c->x86 != 5) | |
742 | return; | |
743 | switch (c->x86_vendor) { | |
744 | case X86_VENDOR_INTEL: | |
745 | if (mce_p5_enabled()) | |
746 | intel_p5_mcheck_init(c); | |
747 | break; | |
748 | case X86_VENDOR_CENTAUR: | |
749 | winchip_mcheck_init(c); | |
750 | break; | |
751 | } | |
752 | } | |
753 | ||
cc3ca220 | 754 | static void mce_cpu_features(struct cpuinfo_x86 *c) |
1da177e4 LT |
755 | { |
756 | switch (c->x86_vendor) { | |
757 | case X86_VENDOR_INTEL: | |
758 | mce_intel_feature_init(c); | |
759 | break; | |
89b831ef JS |
760 | case X86_VENDOR_AMD: |
761 | mce_amd_feature_init(c); | |
762 | break; | |
1da177e4 LT |
763 | default: |
764 | break; | |
765 | } | |
766 | } | |
767 | ||
52d168e2 AK |
768 | static void mce_init_timer(void) |
769 | { | |
770 | struct timer_list *t = &__get_cpu_var(mce_timer); | |
6298c512 | 771 | int *n = &__get_cpu_var(next_interval); |
52d168e2 | 772 | |
6298c512 AK |
773 | *n = check_interval * HZ; |
774 | if (!*n) | |
52d168e2 AK |
775 | return; |
776 | setup_timer(t, mcheck_timer, smp_processor_id()); | |
6298c512 | 777 | t->expires = round_jiffies(jiffies + *n); |
52d168e2 AK |
778 | add_timer(t); |
779 | } | |
780 | ||
d88203d1 | 781 | /* |
1da177e4 | 782 | * Called for each booted CPU to set up machine checks. |
e9eee03e | 783 | * Must be called with preempt off: |
1da177e4 | 784 | */ |
e6982c67 | 785 | void __cpuinit mcheck_init(struct cpuinfo_x86 *c) |
1da177e4 | 786 | { |
4efc0670 AK |
787 | if (mce_disabled) |
788 | return; | |
789 | ||
790 | mce_ancient_init(c); | |
791 | ||
5b4408fd | 792 | if (!mce_available(c)) |
1da177e4 LT |
793 | return; |
794 | ||
0d7482e3 | 795 | if (mce_cap_init() < 0) { |
04b2b1a4 | 796 | mce_disabled = 1; |
0d7482e3 AK |
797 | return; |
798 | } | |
799 | mce_cpu_quirks(c); | |
800 | ||
5d727926 AK |
801 | machine_check_vector = do_machine_check; |
802 | ||
8be91105 | 803 | mce_init(); |
1da177e4 | 804 | mce_cpu_features(c); |
52d168e2 | 805 | mce_init_timer(); |
1da177e4 LT |
806 | } |
807 | ||
808 | /* | |
809 | * Character device to read and clear the MCE log. | |
810 | */ | |
811 | ||
f528e7ba | 812 | static DEFINE_SPINLOCK(mce_state_lock); |
e9eee03e IM |
813 | static int open_count; /* #times opened */ |
814 | static int open_exclu; /* already open exclusive? */ | |
f528e7ba TH |
815 | |
816 | static int mce_open(struct inode *inode, struct file *file) | |
817 | { | |
818 | spin_lock(&mce_state_lock); | |
819 | ||
820 | if (open_exclu || (open_count && (file->f_flags & O_EXCL))) { | |
821 | spin_unlock(&mce_state_lock); | |
e9eee03e | 822 | |
f528e7ba TH |
823 | return -EBUSY; |
824 | } | |
825 | ||
826 | if (file->f_flags & O_EXCL) | |
827 | open_exclu = 1; | |
828 | open_count++; | |
829 | ||
830 | spin_unlock(&mce_state_lock); | |
831 | ||
bd78432c | 832 | return nonseekable_open(inode, file); |
f528e7ba TH |
833 | } |
834 | ||
835 | static int mce_release(struct inode *inode, struct file *file) | |
836 | { | |
837 | spin_lock(&mce_state_lock); | |
838 | ||
839 | open_count--; | |
840 | open_exclu = 0; | |
841 | ||
842 | spin_unlock(&mce_state_lock); | |
843 | ||
844 | return 0; | |
845 | } | |
846 | ||
d88203d1 TG |
847 | static void collect_tscs(void *data) |
848 | { | |
1da177e4 | 849 | unsigned long *cpu_tsc = (unsigned long *)data; |
d88203d1 | 850 | |
1da177e4 | 851 | rdtscll(cpu_tsc[smp_processor_id()]); |
d88203d1 | 852 | } |
1da177e4 | 853 | |
e9eee03e IM |
854 | static DEFINE_MUTEX(mce_read_mutex); |
855 | ||
d88203d1 TG |
856 | static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize, |
857 | loff_t *off) | |
1da177e4 | 858 | { |
e9eee03e | 859 | char __user *buf = ubuf; |
f0de53bb | 860 | unsigned long *cpu_tsc; |
ef41df43 | 861 | unsigned prev, next; |
1da177e4 LT |
862 | int i, err; |
863 | ||
6bca67f9 | 864 | cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL); |
f0de53bb AK |
865 | if (!cpu_tsc) |
866 | return -ENOMEM; | |
867 | ||
8c8b8859 | 868 | mutex_lock(&mce_read_mutex); |
1da177e4 LT |
869 | next = rcu_dereference(mcelog.next); |
870 | ||
871 | /* Only supports full reads right now */ | |
d88203d1 | 872 | if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) { |
8c8b8859 | 873 | mutex_unlock(&mce_read_mutex); |
f0de53bb | 874 | kfree(cpu_tsc); |
e9eee03e | 875 | |
1da177e4 LT |
876 | return -EINVAL; |
877 | } | |
878 | ||
879 | err = 0; | |
ef41df43 HY |
880 | prev = 0; |
881 | do { | |
882 | for (i = prev; i < next; i++) { | |
883 | unsigned long start = jiffies; | |
884 | ||
885 | while (!mcelog.entry[i].finished) { | |
886 | if (time_after_eq(jiffies, start + 2)) { | |
887 | memset(mcelog.entry + i, 0, | |
888 | sizeof(struct mce)); | |
889 | goto timeout; | |
890 | } | |
891 | cpu_relax(); | |
673242c1 | 892 | } |
ef41df43 HY |
893 | smp_rmb(); |
894 | err |= copy_to_user(buf, mcelog.entry + i, | |
895 | sizeof(struct mce)); | |
896 | buf += sizeof(struct mce); | |
897 | timeout: | |
898 | ; | |
673242c1 | 899 | } |
1da177e4 | 900 | |
ef41df43 HY |
901 | memset(mcelog.entry + prev, 0, |
902 | (next - prev) * sizeof(struct mce)); | |
903 | prev = next; | |
904 | next = cmpxchg(&mcelog.next, prev, 0); | |
905 | } while (next != prev); | |
1da177e4 | 906 | |
b2b18660 | 907 | synchronize_sched(); |
1da177e4 | 908 | |
d88203d1 TG |
909 | /* |
910 | * Collect entries that were still getting written before the | |
911 | * synchronize. | |
912 | */ | |
15c8b6c1 | 913 | on_each_cpu(collect_tscs, cpu_tsc, 1); |
e9eee03e | 914 | |
d88203d1 TG |
915 | for (i = next; i < MCE_LOG_LEN; i++) { |
916 | if (mcelog.entry[i].finished && | |
917 | mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) { | |
918 | err |= copy_to_user(buf, mcelog.entry+i, | |
919 | sizeof(struct mce)); | |
1da177e4 LT |
920 | smp_rmb(); |
921 | buf += sizeof(struct mce); | |
922 | memset(&mcelog.entry[i], 0, sizeof(struct mce)); | |
923 | } | |
d88203d1 | 924 | } |
8c8b8859 | 925 | mutex_unlock(&mce_read_mutex); |
f0de53bb | 926 | kfree(cpu_tsc); |
e9eee03e | 927 | |
d88203d1 | 928 | return err ? -EFAULT : buf - ubuf; |
1da177e4 LT |
929 | } |
930 | ||
e02e68d3 TH |
931 | static unsigned int mce_poll(struct file *file, poll_table *wait) |
932 | { | |
933 | poll_wait(file, &mce_wait, wait); | |
934 | if (rcu_dereference(mcelog.next)) | |
935 | return POLLIN | POLLRDNORM; | |
936 | return 0; | |
937 | } | |
938 | ||
c68461b6 | 939 | static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg) |
1da177e4 LT |
940 | { |
941 | int __user *p = (int __user *)arg; | |
d88203d1 | 942 | |
1da177e4 | 943 | if (!capable(CAP_SYS_ADMIN)) |
d88203d1 | 944 | return -EPERM; |
e9eee03e | 945 | |
1da177e4 | 946 | switch (cmd) { |
d88203d1 | 947 | case MCE_GET_RECORD_LEN: |
1da177e4 LT |
948 | return put_user(sizeof(struct mce), p); |
949 | case MCE_GET_LOG_LEN: | |
d88203d1 | 950 | return put_user(MCE_LOG_LEN, p); |
1da177e4 LT |
951 | case MCE_GETCLEAR_FLAGS: { |
952 | unsigned flags; | |
d88203d1 TG |
953 | |
954 | do { | |
1da177e4 | 955 | flags = mcelog.flags; |
d88203d1 | 956 | } while (cmpxchg(&mcelog.flags, flags, 0) != flags); |
e9eee03e | 957 | |
d88203d1 | 958 | return put_user(flags, p); |
1da177e4 LT |
959 | } |
960 | default: | |
d88203d1 TG |
961 | return -ENOTTY; |
962 | } | |
1da177e4 LT |
963 | } |
964 | ||
a1ff41bf | 965 | /* Modified in mce-inject.c, so not static or const */ |
ea149b36 | 966 | struct file_operations mce_chrdev_ops = { |
e9eee03e IM |
967 | .open = mce_open, |
968 | .release = mce_release, | |
969 | .read = mce_read, | |
970 | .poll = mce_poll, | |
971 | .unlocked_ioctl = mce_ioctl, | |
1da177e4 | 972 | }; |
ea149b36 | 973 | EXPORT_SYMBOL_GPL(mce_chrdev_ops); |
1da177e4 LT |
974 | |
975 | static struct miscdevice mce_log_device = { | |
976 | MISC_MCELOG_MINOR, | |
977 | "mcelog", | |
978 | &mce_chrdev_ops, | |
979 | }; | |
980 | ||
13503fa9 HS |
981 | /* |
982 | * mce=off disables machine check | |
983 | * mce=TOLERANCELEVEL (number, see above) | |
984 | * mce=bootlog Log MCEs from before booting. Disabled by default on AMD. | |
985 | * mce=nobootlog Don't log MCEs from before booting. | |
986 | */ | |
1da177e4 LT |
987 | static int __init mcheck_enable(char *str) |
988 | { | |
4efc0670 AK |
989 | if (*str == 0) |
990 | enable_p5_mce(); | |
991 | if (*str == '=') | |
992 | str++; | |
1da177e4 | 993 | if (!strcmp(str, "off")) |
04b2b1a4 | 994 | mce_disabled = 1; |
13503fa9 HS |
995 | else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) |
996 | mce_bootlog = (str[0] == 'b'); | |
8c566ef5 AK |
997 | else if (isdigit(str[0])) |
998 | get_option(&str, &tolerant); | |
13503fa9 | 999 | else { |
4efc0670 | 1000 | printk(KERN_INFO "mce argument %s ignored. Please use /sys\n", |
13503fa9 HS |
1001 | str); |
1002 | return 0; | |
1003 | } | |
9b41046c | 1004 | return 1; |
1da177e4 | 1005 | } |
4efc0670 | 1006 | __setup("mce", mcheck_enable); |
1da177e4 | 1007 | |
d88203d1 | 1008 | /* |
1da177e4 | 1009 | * Sysfs support |
d88203d1 | 1010 | */ |
1da177e4 | 1011 | |
973a2dd1 AK |
1012 | /* |
1013 | * Disable machine checks on suspend and shutdown. We can't really handle | |
1014 | * them later. | |
1015 | */ | |
1016 | static int mce_disable(void) | |
1017 | { | |
1018 | int i; | |
1019 | ||
06b7a7a5 AK |
1020 | for (i = 0; i < banks; i++) { |
1021 | if (!skip_bank_init(i)) | |
1022 | wrmsrl(MSR_IA32_MC0_CTL + i*4, 0); | |
1023 | } | |
973a2dd1 AK |
1024 | return 0; |
1025 | } | |
1026 | ||
1027 | static int mce_suspend(struct sys_device *dev, pm_message_t state) | |
1028 | { | |
1029 | return mce_disable(); | |
1030 | } | |
1031 | ||
1032 | static int mce_shutdown(struct sys_device *dev) | |
1033 | { | |
1034 | return mce_disable(); | |
1035 | } | |
1036 | ||
e9eee03e IM |
1037 | /* |
1038 | * On resume clear all MCE state. Don't want to see leftovers from the BIOS. | |
1039 | * Only one CPU is active at this time, the others get re-added later using | |
1040 | * CPU hotplug: | |
1041 | */ | |
1da177e4 LT |
1042 | static int mce_resume(struct sys_device *dev) |
1043 | { | |
8be91105 | 1044 | mce_init(); |
6ec68bff | 1045 | mce_cpu_features(¤t_cpu_data); |
e9eee03e | 1046 | |
1da177e4 LT |
1047 | return 0; |
1048 | } | |
1049 | ||
52d168e2 AK |
1050 | static void mce_cpu_restart(void *data) |
1051 | { | |
1052 | del_timer_sync(&__get_cpu_var(mce_timer)); | |
1053 | if (mce_available(¤t_cpu_data)) | |
8be91105 | 1054 | mce_init(); |
52d168e2 AK |
1055 | mce_init_timer(); |
1056 | } | |
1057 | ||
1da177e4 | 1058 | /* Reinit MCEs after user configuration changes */ |
d88203d1 TG |
1059 | static void mce_restart(void) |
1060 | { | |
52d168e2 | 1061 | on_each_cpu(mce_cpu_restart, NULL, 1); |
1da177e4 LT |
1062 | } |
1063 | ||
1064 | static struct sysdev_class mce_sysclass = { | |
e9eee03e IM |
1065 | .suspend = mce_suspend, |
1066 | .shutdown = mce_shutdown, | |
1067 | .resume = mce_resume, | |
1068 | .name = "machinecheck", | |
1da177e4 LT |
1069 | }; |
1070 | ||
cb491fca | 1071 | DEFINE_PER_CPU(struct sys_device, mce_dev); |
e9eee03e IM |
1072 | |
1073 | __cpuinitdata | |
1074 | void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); | |
1da177e4 | 1075 | |
0d7482e3 AK |
1076 | static struct sysdev_attribute *bank_attrs; |
1077 | ||
1078 | static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
1079 | char *buf) | |
1080 | { | |
1081 | u64 b = bank[attr - bank_attrs]; | |
e9eee03e | 1082 | |
f6d1826d | 1083 | return sprintf(buf, "%llx\n", b); |
0d7482e3 AK |
1084 | } |
1085 | ||
1086 | static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
9319cec8 | 1087 | const char *buf, size_t size) |
0d7482e3 | 1088 | { |
9319cec8 | 1089 | u64 new; |
e9eee03e | 1090 | |
9319cec8 | 1091 | if (strict_strtoull(buf, 0, &new) < 0) |
0d7482e3 | 1092 | return -EINVAL; |
e9eee03e | 1093 | |
0d7482e3 AK |
1094 | bank[attr - bank_attrs] = new; |
1095 | mce_restart(); | |
e9eee03e | 1096 | |
9319cec8 | 1097 | return size; |
0d7482e3 | 1098 | } |
a98f0dd3 | 1099 | |
e9eee03e IM |
1100 | static ssize_t |
1101 | show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf) | |
a98f0dd3 AK |
1102 | { |
1103 | strcpy(buf, trigger); | |
1104 | strcat(buf, "\n"); | |
1105 | return strlen(trigger) + 1; | |
1106 | } | |
1107 | ||
4a0b2b4d | 1108 | static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr, |
e9eee03e | 1109 | const char *buf, size_t siz) |
a98f0dd3 AK |
1110 | { |
1111 | char *p; | |
1112 | int len; | |
e9eee03e | 1113 | |
a98f0dd3 AK |
1114 | strncpy(trigger, buf, sizeof(trigger)); |
1115 | trigger[sizeof(trigger)-1] = 0; | |
1116 | len = strlen(trigger); | |
1117 | p = strchr(trigger, '\n'); | |
e9eee03e IM |
1118 | |
1119 | if (*p) | |
1120 | *p = 0; | |
1121 | ||
a98f0dd3 AK |
1122 | return len; |
1123 | } | |
1124 | ||
b56f642d AK |
1125 | static ssize_t store_int_with_restart(struct sys_device *s, |
1126 | struct sysdev_attribute *attr, | |
1127 | const char *buf, size_t size) | |
1128 | { | |
1129 | ssize_t ret = sysdev_store_int(s, attr, buf, size); | |
1130 | mce_restart(); | |
1131 | return ret; | |
1132 | } | |
1133 | ||
a98f0dd3 | 1134 | static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger); |
d95d62c0 | 1135 | static SYSDEV_INT_ATTR(tolerant, 0644, tolerant); |
e9eee03e | 1136 | |
b56f642d AK |
1137 | static struct sysdev_ext_attribute attr_check_interval = { |
1138 | _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int, | |
1139 | store_int_with_restart), | |
1140 | &check_interval | |
1141 | }; | |
e9eee03e | 1142 | |
cb491fca | 1143 | static struct sysdev_attribute *mce_attrs[] = { |
b56f642d | 1144 | &attr_tolerant.attr, &attr_check_interval.attr, &attr_trigger, |
a98f0dd3 AK |
1145 | NULL |
1146 | }; | |
1da177e4 | 1147 | |
cb491fca | 1148 | static cpumask_var_t mce_dev_initialized; |
bae19fe0 | 1149 | |
e9eee03e | 1150 | /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */ |
91c6d400 | 1151 | static __cpuinit int mce_create_device(unsigned int cpu) |
1da177e4 LT |
1152 | { |
1153 | int err; | |
73ca5358 | 1154 | int i; |
92cb7612 | 1155 | |
90367556 | 1156 | if (!mce_available(&boot_cpu_data)) |
91c6d400 AK |
1157 | return -EIO; |
1158 | ||
cb491fca IM |
1159 | memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject)); |
1160 | per_cpu(mce_dev, cpu).id = cpu; | |
1161 | per_cpu(mce_dev, cpu).cls = &mce_sysclass; | |
91c6d400 | 1162 | |
cb491fca | 1163 | err = sysdev_register(&per_cpu(mce_dev, cpu)); |
d435d862 AM |
1164 | if (err) |
1165 | return err; | |
1166 | ||
cb491fca IM |
1167 | for (i = 0; mce_attrs[i]; i++) { |
1168 | err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
d435d862 AM |
1169 | if (err) |
1170 | goto error; | |
1171 | } | |
0d7482e3 | 1172 | for (i = 0; i < banks; i++) { |
cb491fca | 1173 | err = sysdev_create_file(&per_cpu(mce_dev, cpu), |
0d7482e3 AK |
1174 | &bank_attrs[i]); |
1175 | if (err) | |
1176 | goto error2; | |
1177 | } | |
cb491fca | 1178 | cpumask_set_cpu(cpu, mce_dev_initialized); |
91c6d400 | 1179 | |
d435d862 | 1180 | return 0; |
0d7482e3 | 1181 | error2: |
cb491fca IM |
1182 | while (--i >= 0) |
1183 | sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[i]); | |
d435d862 | 1184 | error: |
cb491fca IM |
1185 | while (--i >= 0) |
1186 | sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
1187 | ||
1188 | sysdev_unregister(&per_cpu(mce_dev, cpu)); | |
d435d862 | 1189 | |
91c6d400 AK |
1190 | return err; |
1191 | } | |
1192 | ||
2d9cd6c2 | 1193 | static __cpuinit void mce_remove_device(unsigned int cpu) |
91c6d400 | 1194 | { |
73ca5358 SL |
1195 | int i; |
1196 | ||
cb491fca | 1197 | if (!cpumask_test_cpu(cpu, mce_dev_initialized)) |
bae19fe0 AH |
1198 | return; |
1199 | ||
cb491fca IM |
1200 | for (i = 0; mce_attrs[i]; i++) |
1201 | sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
1202 | ||
0d7482e3 | 1203 | for (i = 0; i < banks; i++) |
cb491fca IM |
1204 | sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[i]); |
1205 | ||
1206 | sysdev_unregister(&per_cpu(mce_dev, cpu)); | |
1207 | cpumask_clear_cpu(cpu, mce_dev_initialized); | |
91c6d400 | 1208 | } |
91c6d400 | 1209 | |
d6b75584 | 1210 | /* Make sure there are no machine checks on offlined CPUs. */ |
ec5b3d32 | 1211 | static void mce_disable_cpu(void *h) |
d6b75584 | 1212 | { |
88ccbedd | 1213 | unsigned long action = *(unsigned long *)h; |
cb491fca | 1214 | int i; |
d6b75584 AK |
1215 | |
1216 | if (!mce_available(¤t_cpu_data)) | |
1217 | return; | |
88ccbedd AK |
1218 | if (!(action & CPU_TASKS_FROZEN)) |
1219 | cmci_clear(); | |
06b7a7a5 AK |
1220 | for (i = 0; i < banks; i++) { |
1221 | if (!skip_bank_init(i)) | |
1222 | wrmsrl(MSR_IA32_MC0_CTL + i*4, 0); | |
1223 | } | |
d6b75584 AK |
1224 | } |
1225 | ||
ec5b3d32 | 1226 | static void mce_reenable_cpu(void *h) |
d6b75584 | 1227 | { |
88ccbedd | 1228 | unsigned long action = *(unsigned long *)h; |
e9eee03e | 1229 | int i; |
d6b75584 AK |
1230 | |
1231 | if (!mce_available(¤t_cpu_data)) | |
1232 | return; | |
e9eee03e | 1233 | |
88ccbedd AK |
1234 | if (!(action & CPU_TASKS_FROZEN)) |
1235 | cmci_reenable(); | |
06b7a7a5 AK |
1236 | for (i = 0; i < banks; i++) { |
1237 | if (!skip_bank_init(i)) | |
1238 | wrmsrl(MSR_IA32_MC0_CTL + i*4, bank[i]); | |
1239 | } | |
d6b75584 AK |
1240 | } |
1241 | ||
91c6d400 | 1242 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ |
e9eee03e IM |
1243 | static int __cpuinit |
1244 | mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) | |
91c6d400 AK |
1245 | { |
1246 | unsigned int cpu = (unsigned long)hcpu; | |
52d168e2 | 1247 | struct timer_list *t = &per_cpu(mce_timer, cpu); |
91c6d400 AK |
1248 | |
1249 | switch (action) { | |
bae19fe0 AH |
1250 | case CPU_ONLINE: |
1251 | case CPU_ONLINE_FROZEN: | |
1252 | mce_create_device(cpu); | |
8735728e RW |
1253 | if (threshold_cpu_callback) |
1254 | threshold_cpu_callback(action, cpu); | |
91c6d400 | 1255 | break; |
91c6d400 | 1256 | case CPU_DEAD: |
8bb78442 | 1257 | case CPU_DEAD_FROZEN: |
8735728e RW |
1258 | if (threshold_cpu_callback) |
1259 | threshold_cpu_callback(action, cpu); | |
91c6d400 AK |
1260 | mce_remove_device(cpu); |
1261 | break; | |
52d168e2 AK |
1262 | case CPU_DOWN_PREPARE: |
1263 | case CPU_DOWN_PREPARE_FROZEN: | |
1264 | del_timer_sync(t); | |
88ccbedd | 1265 | smp_call_function_single(cpu, mce_disable_cpu, &action, 1); |
52d168e2 AK |
1266 | break; |
1267 | case CPU_DOWN_FAILED: | |
1268 | case CPU_DOWN_FAILED_FROZEN: | |
6298c512 AK |
1269 | t->expires = round_jiffies(jiffies + |
1270 | __get_cpu_var(next_interval)); | |
52d168e2 | 1271 | add_timer_on(t, cpu); |
88ccbedd AK |
1272 | smp_call_function_single(cpu, mce_reenable_cpu, &action, 1); |
1273 | break; | |
1274 | case CPU_POST_DEAD: | |
1275 | /* intentionally ignoring frozen here */ | |
1276 | cmci_rediscover(cpu); | |
52d168e2 | 1277 | break; |
91c6d400 | 1278 | } |
bae19fe0 | 1279 | return NOTIFY_OK; |
91c6d400 AK |
1280 | } |
1281 | ||
1e35669d | 1282 | static struct notifier_block mce_cpu_notifier __cpuinitdata = { |
91c6d400 AK |
1283 | .notifier_call = mce_cpu_callback, |
1284 | }; | |
1285 | ||
0d7482e3 AK |
1286 | static __init int mce_init_banks(void) |
1287 | { | |
1288 | int i; | |
1289 | ||
1290 | bank_attrs = kzalloc(sizeof(struct sysdev_attribute) * banks, | |
1291 | GFP_KERNEL); | |
1292 | if (!bank_attrs) | |
1293 | return -ENOMEM; | |
1294 | ||
1295 | for (i = 0; i < banks; i++) { | |
1296 | struct sysdev_attribute *a = &bank_attrs[i]; | |
e9eee03e IM |
1297 | |
1298 | a->attr.name = kasprintf(GFP_KERNEL, "bank%d", i); | |
0d7482e3 AK |
1299 | if (!a->attr.name) |
1300 | goto nomem; | |
e9eee03e IM |
1301 | |
1302 | a->attr.mode = 0644; | |
1303 | a->show = show_bank; | |
1304 | a->store = set_bank; | |
0d7482e3 AK |
1305 | } |
1306 | return 0; | |
1307 | ||
1308 | nomem: | |
1309 | while (--i >= 0) | |
1310 | kfree(bank_attrs[i].attr.name); | |
1311 | kfree(bank_attrs); | |
1312 | bank_attrs = NULL; | |
e9eee03e | 1313 | |
0d7482e3 AK |
1314 | return -ENOMEM; |
1315 | } | |
1316 | ||
91c6d400 AK |
1317 | static __init int mce_init_device(void) |
1318 | { | |
1319 | int err; | |
1320 | int i = 0; | |
1321 | ||
1da177e4 LT |
1322 | if (!mce_available(&boot_cpu_data)) |
1323 | return -EIO; | |
0d7482e3 | 1324 | |
cb491fca | 1325 | alloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL); |
996867d0 | 1326 | |
0d7482e3 AK |
1327 | err = mce_init_banks(); |
1328 | if (err) | |
1329 | return err; | |
1330 | ||
1da177e4 | 1331 | err = sysdev_class_register(&mce_sysclass); |
d435d862 AM |
1332 | if (err) |
1333 | return err; | |
91c6d400 AK |
1334 | |
1335 | for_each_online_cpu(i) { | |
d435d862 AM |
1336 | err = mce_create_device(i); |
1337 | if (err) | |
1338 | return err; | |
91c6d400 AK |
1339 | } |
1340 | ||
be6b5a35 | 1341 | register_hotcpu_notifier(&mce_cpu_notifier); |
1da177e4 | 1342 | misc_register(&mce_log_device); |
e9eee03e | 1343 | |
1da177e4 | 1344 | return err; |
1da177e4 | 1345 | } |
91c6d400 | 1346 | |
1da177e4 | 1347 | device_initcall(mce_init_device); |
a988d334 | 1348 | |
4efc0670 | 1349 | #else /* CONFIG_X86_OLD_MCE: */ |
a988d334 | 1350 | |
a988d334 IM |
1351 | int nr_mce_banks; |
1352 | EXPORT_SYMBOL_GPL(nr_mce_banks); /* non-fatal.o */ | |
1353 | ||
a988d334 IM |
1354 | /* This has to be run for each processor */ |
1355 | void mcheck_init(struct cpuinfo_x86 *c) | |
1356 | { | |
1357 | if (mce_disabled == 1) | |
1358 | return; | |
1359 | ||
1360 | switch (c->x86_vendor) { | |
1361 | case X86_VENDOR_AMD: | |
1362 | amd_mcheck_init(c); | |
1363 | break; | |
1364 | ||
1365 | case X86_VENDOR_INTEL: | |
1366 | if (c->x86 == 5) | |
1367 | intel_p5_mcheck_init(c); | |
1368 | if (c->x86 == 6) | |
1369 | intel_p6_mcheck_init(c); | |
1370 | if (c->x86 == 15) | |
1371 | intel_p4_mcheck_init(c); | |
1372 | break; | |
1373 | ||
1374 | case X86_VENDOR_CENTAUR: | |
1375 | if (c->x86 == 5) | |
1376 | winchip_mcheck_init(c); | |
1377 | break; | |
1378 | ||
1379 | default: | |
1380 | break; | |
1381 | } | |
b659294b | 1382 | printk(KERN_INFO "mce: CPU supports %d MCE banks\n", nr_mce_banks); |
a988d334 IM |
1383 | } |
1384 | ||
a988d334 IM |
1385 | static int __init mcheck_enable(char *str) |
1386 | { | |
1387 | mce_disabled = -1; | |
1388 | return 1; | |
1389 | } | |
1390 | ||
a988d334 IM |
1391 | __setup("mce", mcheck_enable); |
1392 | ||
d7c3c9a6 AK |
1393 | #endif /* CONFIG_X86_OLD_MCE */ |
1394 | ||
1395 | /* | |
1396 | * Old style boot options parsing. Only for compatibility. | |
1397 | */ | |
1398 | static int __init mcheck_disable(char *str) | |
1399 | { | |
1400 | mce_disabled = 1; | |
1401 | return 1; | |
1402 | } | |
1403 | __setup("nomce", mcheck_disable); |