Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Machine check handler. | |
e9eee03e | 3 | * |
1da177e4 | 4 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. |
d88203d1 TG |
5 | * Rest from unknown author(s). |
6 | * 2004 Andi Kleen. Rewrote most of it. | |
b79109c3 AK |
7 | * Copyright 2008 Intel Corporation |
8 | * Author: Andi Kleen | |
1da177e4 | 9 | */ |
e9eee03e IM |
10 | #include <linux/thread_info.h> |
11 | #include <linux/capability.h> | |
12 | #include <linux/miscdevice.h> | |
13 | #include <linux/ratelimit.h> | |
14 | #include <linux/kallsyms.h> | |
15 | #include <linux/rcupdate.h> | |
e9eee03e | 16 | #include <linux/kobject.h> |
14a02530 | 17 | #include <linux/uaccess.h> |
e9eee03e IM |
18 | #include <linux/kdebug.h> |
19 | #include <linux/kernel.h> | |
20 | #include <linux/percpu.h> | |
1da177e4 | 21 | #include <linux/string.h> |
1da177e4 | 22 | #include <linux/sysdev.h> |
8c566ef5 | 23 | #include <linux/ctype.h> |
e9eee03e | 24 | #include <linux/sched.h> |
0d7482e3 | 25 | #include <linux/sysfs.h> |
e9eee03e IM |
26 | #include <linux/types.h> |
27 | #include <linux/init.h> | |
28 | #include <linux/kmod.h> | |
29 | #include <linux/poll.h> | |
30 | #include <linux/cpu.h> | |
14a02530 | 31 | #include <linux/smp.h> |
e9eee03e IM |
32 | #include <linux/fs.h> |
33 | ||
d88203d1 | 34 | #include <asm/processor.h> |
e02e68d3 | 35 | #include <asm/idle.h> |
e9eee03e IM |
36 | #include <asm/mce.h> |
37 | #include <asm/msr.h> | |
1da177e4 | 38 | |
bd19a5e6 | 39 | #include "mce-internal.h" |
711c2e48 IM |
40 | #include "mce.h" |
41 | ||
5d727926 AK |
42 | /* Handle unconfigured int18 (should never happen) */ |
43 | static void unexpected_machine_check(struct pt_regs *regs, long error_code) | |
44 | { | |
45 | printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n", | |
46 | smp_processor_id()); | |
47 | } | |
48 | ||
49 | /* Call the installed machine check handler for this CPU setup. */ | |
50 | void (*machine_check_vector)(struct pt_regs *, long error_code) = | |
51 | unexpected_machine_check; | |
04b2b1a4 AK |
52 | |
53 | int mce_disabled; | |
54 | ||
4efc0670 | 55 | #ifdef CONFIG_X86_NEW_MCE |
711c2e48 | 56 | |
e9eee03e | 57 | #define MISC_MCELOG_MINOR 227 |
0d7482e3 | 58 | |
553f265f AK |
59 | atomic_t mce_entry; |
60 | ||
01ca79f1 AK |
61 | DEFINE_PER_CPU(unsigned, mce_exception_count); |
62 | ||
bd78432c TH |
63 | /* |
64 | * Tolerant levels: | |
65 | * 0: always panic on uncorrected errors, log corrected errors | |
66 | * 1: panic or SIGBUS on uncorrected errors, log corrected errors | |
67 | * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors | |
68 | * 3: never panic or SIGBUS, log all errors (for testing only) | |
69 | */ | |
e9eee03e IM |
70 | static int tolerant = 1; |
71 | static int banks; | |
72 | static u64 *bank; | |
73 | static unsigned long notify_user; | |
74 | static int rip_msr; | |
75 | static int mce_bootlog = -1; | |
a98f0dd3 | 76 | |
e9eee03e IM |
77 | static char trigger[128]; |
78 | static char *trigger_argv[2] = { trigger, NULL }; | |
1da177e4 | 79 | |
06b7a7a5 AK |
80 | static unsigned long dont_init_banks; |
81 | ||
e02e68d3 TH |
82 | static DECLARE_WAIT_QUEUE_HEAD(mce_wait); |
83 | ||
ee031c31 AK |
84 | /* MCA banks polled by the period polling timer for corrected events */ |
85 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { | |
86 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL | |
87 | }; | |
88 | ||
06b7a7a5 AK |
89 | static inline int skip_bank_init(int i) |
90 | { | |
91 | return i < BITS_PER_LONG && test_bit(i, &dont_init_banks); | |
92 | } | |
93 | ||
b5f2fa4e AK |
94 | /* Do initial initialization of a struct mce */ |
95 | void mce_setup(struct mce *m) | |
96 | { | |
97 | memset(m, 0, sizeof(struct mce)); | |
d620c67f | 98 | m->cpu = m->extcpu = smp_processor_id(); |
b5f2fa4e | 99 | rdtscll(m->tsc); |
8ee08347 AK |
100 | /* We hope get_seconds stays lockless */ |
101 | m->time = get_seconds(); | |
102 | m->cpuvendor = boot_cpu_data.x86_vendor; | |
103 | m->cpuid = cpuid_eax(1); | |
104 | #ifdef CONFIG_SMP | |
105 | m->socketid = cpu_data(m->extcpu).phys_proc_id; | |
106 | #endif | |
107 | m->apicid = cpu_data(m->extcpu).initial_apicid; | |
108 | rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap); | |
b5f2fa4e AK |
109 | } |
110 | ||
ea149b36 AK |
111 | DEFINE_PER_CPU(struct mce, injectm); |
112 | EXPORT_PER_CPU_SYMBOL_GPL(injectm); | |
113 | ||
1da177e4 LT |
114 | /* |
115 | * Lockless MCE logging infrastructure. | |
116 | * This avoids deadlocks on printk locks without having to break locks. Also | |
117 | * separate MCEs from kernel messages to avoid bogus bug reports. | |
118 | */ | |
119 | ||
231fd906 | 120 | static struct mce_log mcelog = { |
f6fb0ac0 AK |
121 | .signature = MCE_LOG_SIGNATURE, |
122 | .len = MCE_LOG_LEN, | |
123 | .recordlen = sizeof(struct mce), | |
d88203d1 | 124 | }; |
1da177e4 LT |
125 | |
126 | void mce_log(struct mce *mce) | |
127 | { | |
128 | unsigned next, entry; | |
e9eee03e | 129 | |
1da177e4 | 130 | mce->finished = 0; |
7644143c | 131 | wmb(); |
1da177e4 LT |
132 | for (;;) { |
133 | entry = rcu_dereference(mcelog.next); | |
673242c1 | 134 | for (;;) { |
e9eee03e IM |
135 | /* |
136 | * When the buffer fills up discard new entries. | |
137 | * Assume that the earlier errors are the more | |
138 | * interesting ones: | |
139 | */ | |
673242c1 | 140 | if (entry >= MCE_LOG_LEN) { |
14a02530 HS |
141 | set_bit(MCE_OVERFLOW, |
142 | (unsigned long *)&mcelog.flags); | |
673242c1 AK |
143 | return; |
144 | } | |
e9eee03e | 145 | /* Old left over entry. Skip: */ |
673242c1 AK |
146 | if (mcelog.entry[entry].finished) { |
147 | entry++; | |
148 | continue; | |
149 | } | |
7644143c | 150 | break; |
1da177e4 | 151 | } |
1da177e4 LT |
152 | smp_rmb(); |
153 | next = entry + 1; | |
154 | if (cmpxchg(&mcelog.next, entry, next) == entry) | |
155 | break; | |
156 | } | |
157 | memcpy(mcelog.entry + entry, mce, sizeof(struct mce)); | |
7644143c | 158 | wmb(); |
1da177e4 | 159 | mcelog.entry[entry].finished = 1; |
7644143c | 160 | wmb(); |
1da177e4 | 161 | |
a0189c70 | 162 | mce->finished = 1; |
e02e68d3 | 163 | set_bit(0, ¬ify_user); |
1da177e4 LT |
164 | } |
165 | ||
166 | static void print_mce(struct mce *m) | |
167 | { | |
168 | printk(KERN_EMERG "\n" | |
4855170f | 169 | KERN_EMERG "HARDWARE ERROR\n" |
1da177e4 LT |
170 | KERN_EMERG |
171 | "CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n", | |
d620c67f | 172 | m->extcpu, m->mcgstatus, m->bank, m->status); |
65ea5b03 | 173 | if (m->ip) { |
d88203d1 | 174 | printk(KERN_EMERG "RIP%s %02x:<%016Lx> ", |
1da177e4 | 175 | !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", |
65ea5b03 | 176 | m->cs, m->ip); |
1da177e4 | 177 | if (m->cs == __KERNEL_CS) |
65ea5b03 | 178 | print_symbol("{%s}", m->ip); |
1da177e4 LT |
179 | printk("\n"); |
180 | } | |
f6d1826d | 181 | printk(KERN_EMERG "TSC %llx ", m->tsc); |
1da177e4 | 182 | if (m->addr) |
f6d1826d | 183 | printk("ADDR %llx ", m->addr); |
1da177e4 | 184 | if (m->misc) |
f6d1826d | 185 | printk("MISC %llx ", m->misc); |
1da177e4 | 186 | printk("\n"); |
8ee08347 AK |
187 | printk(KERN_EMERG "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n", |
188 | m->cpuvendor, m->cpuid, m->time, m->socketid, | |
189 | m->apicid); | |
4855170f | 190 | printk(KERN_EMERG "This is not a software problem!\n"); |
d88203d1 TG |
191 | printk(KERN_EMERG "Run through mcelog --ascii to decode " |
192 | "and contact your hardware vendor\n"); | |
1da177e4 LT |
193 | } |
194 | ||
bd19a5e6 | 195 | static void mce_panic(char *msg, struct mce *final, char *exp) |
d88203d1 | 196 | { |
1da177e4 | 197 | int i; |
e02e68d3 | 198 | |
d896a940 AK |
199 | bust_spinlocks(1); |
200 | console_verbose(); | |
a0189c70 | 201 | /* First print corrected ones that are still unlogged */ |
1da177e4 | 202 | for (i = 0; i < MCE_LOG_LEN; i++) { |
a0189c70 AK |
203 | struct mce *m = &mcelog.entry[i]; |
204 | if ((m->status & MCI_STATUS_VAL) && | |
205 | !(m->status & MCI_STATUS_UC)) | |
206 | print_mce(m); | |
207 | } | |
208 | /* Now print uncorrected but with the final one last */ | |
209 | for (i = 0; i < MCE_LOG_LEN; i++) { | |
210 | struct mce *m = &mcelog.entry[i]; | |
211 | if (!(m->status & MCI_STATUS_VAL)) | |
1da177e4 | 212 | continue; |
a0189c70 AK |
213 | if (!final || memcmp(m, final, sizeof(struct mce))) |
214 | print_mce(m); | |
1da177e4 | 215 | } |
a0189c70 AK |
216 | if (final) |
217 | print_mce(final); | |
bd19a5e6 AK |
218 | if (exp) |
219 | printk(KERN_EMERG "Machine check: %s\n", exp); | |
e02e68d3 | 220 | panic(msg); |
d88203d1 | 221 | } |
1da177e4 | 222 | |
ea149b36 AK |
223 | /* Support code for software error injection */ |
224 | ||
225 | static int msr_to_offset(u32 msr) | |
226 | { | |
227 | unsigned bank = __get_cpu_var(injectm.bank); | |
228 | if (msr == rip_msr) | |
229 | return offsetof(struct mce, ip); | |
230 | if (msr == MSR_IA32_MC0_STATUS + bank*4) | |
231 | return offsetof(struct mce, status); | |
232 | if (msr == MSR_IA32_MC0_ADDR + bank*4) | |
233 | return offsetof(struct mce, addr); | |
234 | if (msr == MSR_IA32_MC0_MISC + bank*4) | |
235 | return offsetof(struct mce, misc); | |
236 | if (msr == MSR_IA32_MCG_STATUS) | |
237 | return offsetof(struct mce, mcgstatus); | |
238 | return -1; | |
239 | } | |
240 | ||
5f8c1a54 AK |
241 | /* MSR access wrappers used for error injection */ |
242 | static u64 mce_rdmsrl(u32 msr) | |
243 | { | |
244 | u64 v; | |
ea149b36 AK |
245 | if (__get_cpu_var(injectm).finished) { |
246 | int offset = msr_to_offset(msr); | |
247 | if (offset < 0) | |
248 | return 0; | |
249 | return *(u64 *)((char *)&__get_cpu_var(injectm) + offset); | |
250 | } | |
5f8c1a54 AK |
251 | rdmsrl(msr, v); |
252 | return v; | |
253 | } | |
254 | ||
255 | static void mce_wrmsrl(u32 msr, u64 v) | |
256 | { | |
ea149b36 AK |
257 | if (__get_cpu_var(injectm).finished) { |
258 | int offset = msr_to_offset(msr); | |
259 | if (offset >= 0) | |
260 | *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v; | |
261 | return; | |
262 | } | |
5f8c1a54 AK |
263 | wrmsrl(msr, v); |
264 | } | |
265 | ||
88ccbedd | 266 | int mce_available(struct cpuinfo_x86 *c) |
1da177e4 | 267 | { |
04b2b1a4 | 268 | if (mce_disabled) |
5b4408fd | 269 | return 0; |
3d1712c9 | 270 | return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); |
1da177e4 LT |
271 | } |
272 | ||
94ad8474 AK |
273 | static inline void mce_get_rip(struct mce *m, struct pt_regs *regs) |
274 | { | |
275 | if (regs && (m->mcgstatus & MCG_STATUS_RIPV)) { | |
65ea5b03 | 276 | m->ip = regs->ip; |
94ad8474 AK |
277 | m->cs = regs->cs; |
278 | } else { | |
65ea5b03 | 279 | m->ip = 0; |
94ad8474 AK |
280 | m->cs = 0; |
281 | } | |
282 | if (rip_msr) { | |
283 | /* Assume the RIP in the MSR is exact. Is this true? */ | |
284 | m->mcgstatus |= MCG_STATUS_EIPV; | |
5f8c1a54 | 285 | m->ip = mce_rdmsrl(rip_msr); |
94ad8474 AK |
286 | m->cs = 0; |
287 | } | |
288 | } | |
289 | ||
ca84f696 AK |
290 | DEFINE_PER_CPU(unsigned, mce_poll_count); |
291 | ||
d88203d1 | 292 | /* |
b79109c3 AK |
293 | * Poll for corrected events or events that happened before reset. |
294 | * Those are just logged through /dev/mcelog. | |
295 | * | |
296 | * This is executed in standard interrupt context. | |
297 | */ | |
ee031c31 | 298 | void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) |
b79109c3 AK |
299 | { |
300 | struct mce m; | |
301 | int i; | |
302 | ||
ca84f696 AK |
303 | __get_cpu_var(mce_poll_count)++; |
304 | ||
b79109c3 AK |
305 | mce_setup(&m); |
306 | ||
5f8c1a54 | 307 | m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); |
b79109c3 | 308 | for (i = 0; i < banks; i++) { |
ee031c31 | 309 | if (!bank[i] || !test_bit(i, *b)) |
b79109c3 AK |
310 | continue; |
311 | ||
312 | m.misc = 0; | |
313 | m.addr = 0; | |
314 | m.bank = i; | |
315 | m.tsc = 0; | |
316 | ||
317 | barrier(); | |
5f8c1a54 | 318 | m.status = mce_rdmsrl(MSR_IA32_MC0_STATUS + i*4); |
b79109c3 AK |
319 | if (!(m.status & MCI_STATUS_VAL)) |
320 | continue; | |
321 | ||
322 | /* | |
323 | * Uncorrected events are handled by the exception handler | |
324 | * when it is enabled. But when the exception is disabled log | |
325 | * everything. | |
326 | * | |
327 | * TBD do the same check for MCI_STATUS_EN here? | |
328 | */ | |
329 | if ((m.status & MCI_STATUS_UC) && !(flags & MCP_UC)) | |
330 | continue; | |
331 | ||
332 | if (m.status & MCI_STATUS_MISCV) | |
5f8c1a54 | 333 | m.misc = mce_rdmsrl(MSR_IA32_MC0_MISC + i*4); |
b79109c3 | 334 | if (m.status & MCI_STATUS_ADDRV) |
5f8c1a54 | 335 | m.addr = mce_rdmsrl(MSR_IA32_MC0_ADDR + i*4); |
b79109c3 AK |
336 | |
337 | if (!(flags & MCP_TIMESTAMP)) | |
338 | m.tsc = 0; | |
339 | /* | |
340 | * Don't get the IP here because it's unlikely to | |
341 | * have anything to do with the actual error location. | |
342 | */ | |
5679af4c AK |
343 | if (!(flags & MCP_DONTLOG)) { |
344 | mce_log(&m); | |
345 | add_taint(TAINT_MACHINE_CHECK); | |
346 | } | |
b79109c3 AK |
347 | |
348 | /* | |
349 | * Clear state for this bank. | |
350 | */ | |
5f8c1a54 | 351 | mce_wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); |
b79109c3 AK |
352 | } |
353 | ||
354 | /* | |
355 | * Don't clear MCG_STATUS here because it's only defined for | |
356 | * exceptions. | |
357 | */ | |
88921be3 AK |
358 | |
359 | sync_core(); | |
b79109c3 | 360 | } |
ea149b36 | 361 | EXPORT_SYMBOL_GPL(machine_check_poll); |
b79109c3 | 362 | |
bd19a5e6 AK |
363 | /* |
364 | * Do a quick check if any of the events requires a panic. | |
365 | * This decides if we keep the events around or clear them. | |
366 | */ | |
367 | static int mce_no_way_out(struct mce *m, char **msg) | |
368 | { | |
369 | int i; | |
370 | ||
371 | for (i = 0; i < banks; i++) { | |
372 | m->status = mce_rdmsrl(MSR_IA32_MC0_STATUS + i*4); | |
373 | if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY) | |
374 | return 1; | |
375 | } | |
376 | return 0; | |
377 | } | |
378 | ||
b79109c3 AK |
379 | /* |
380 | * The actual machine check handler. This only handles real | |
381 | * exceptions when something got corrupted coming in through int 18. | |
382 | * | |
383 | * This is executed in NMI context not subject to normal locking rules. This | |
384 | * implies that most kernel services cannot be safely used. Don't even | |
385 | * think about putting a printk in there! | |
1da177e4 | 386 | */ |
e9eee03e | 387 | void do_machine_check(struct pt_regs *regs, long error_code) |
1da177e4 LT |
388 | { |
389 | struct mce m, panicm; | |
e9eee03e | 390 | int panicm_found = 0; |
1da177e4 | 391 | int i; |
bd78432c TH |
392 | /* |
393 | * If no_way_out gets set, there is no safe way to recover from this | |
394 | * MCE. If tolerant is cranked up, we'll try anyway. | |
395 | */ | |
396 | int no_way_out = 0; | |
397 | /* | |
398 | * If kill_it gets set, there might be a way to recover from this | |
399 | * error. | |
400 | */ | |
401 | int kill_it = 0; | |
b79109c3 | 402 | DECLARE_BITMAP(toclear, MAX_NR_BANKS); |
bd19a5e6 | 403 | char *msg = "Unknown"; |
1da177e4 | 404 | |
553f265f AK |
405 | atomic_inc(&mce_entry); |
406 | ||
01ca79f1 AK |
407 | __get_cpu_var(mce_exception_count)++; |
408 | ||
b79109c3 | 409 | if (notify_die(DIE_NMI, "machine check", regs, error_code, |
22f5991c | 410 | 18, SIGKILL) == NOTIFY_STOP) |
32561696 | 411 | goto out; |
b79109c3 | 412 | if (!banks) |
32561696 | 413 | goto out; |
1da177e4 | 414 | |
b5f2fa4e AK |
415 | mce_setup(&m); |
416 | ||
5f8c1a54 | 417 | m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); |
bd19a5e6 | 418 | no_way_out = mce_no_way_out(&m, &msg); |
d88203d1 | 419 | |
1da177e4 LT |
420 | barrier(); |
421 | ||
422 | for (i = 0; i < banks; i++) { | |
b79109c3 | 423 | __clear_bit(i, toclear); |
0d7482e3 | 424 | if (!bank[i]) |
1da177e4 | 425 | continue; |
d88203d1 TG |
426 | |
427 | m.misc = 0; | |
1da177e4 LT |
428 | m.addr = 0; |
429 | m.bank = i; | |
1da177e4 | 430 | |
5f8c1a54 | 431 | m.status = mce_rdmsrl(MSR_IA32_MC0_STATUS + i*4); |
1da177e4 LT |
432 | if ((m.status & MCI_STATUS_VAL) == 0) |
433 | continue; | |
434 | ||
b79109c3 AK |
435 | /* |
436 | * Non uncorrected errors are handled by machine_check_poll | |
de8a84d8 | 437 | * Leave them alone, unless this panics. |
b79109c3 | 438 | */ |
de8a84d8 | 439 | if ((m.status & MCI_STATUS_UC) == 0 && !no_way_out) |
b79109c3 AK |
440 | continue; |
441 | ||
442 | /* | |
443 | * Set taint even when machine check was not enabled. | |
444 | */ | |
445 | add_taint(TAINT_MACHINE_CHECK); | |
446 | ||
447 | __set_bit(i, toclear); | |
448 | ||
1da177e4 | 449 | if (m.status & MCI_STATUS_EN) { |
bd78432c TH |
450 | /* |
451 | * If this error was uncorrectable and there was | |
452 | * an overflow, we're in trouble. If no overflow, | |
453 | * we might get away with just killing a task. | |
454 | */ | |
bd19a5e6 | 455 | if (m.status & MCI_STATUS_UC) |
bd78432c | 456 | kill_it = 1; |
b79109c3 AK |
457 | } else { |
458 | /* | |
459 | * Machine check event was not enabled. Clear, but | |
460 | * ignore. | |
461 | */ | |
462 | continue; | |
1da177e4 LT |
463 | } |
464 | ||
465 | if (m.status & MCI_STATUS_MISCV) | |
5f8c1a54 | 466 | m.misc = mce_rdmsrl(MSR_IA32_MC0_MISC + i*4); |
1da177e4 | 467 | if (m.status & MCI_STATUS_ADDRV) |
5f8c1a54 | 468 | m.addr = mce_rdmsrl(MSR_IA32_MC0_ADDR + i*4); |
1da177e4 | 469 | |
94ad8474 | 470 | mce_get_rip(&m, regs); |
b79109c3 | 471 | mce_log(&m); |
1da177e4 | 472 | |
e9eee03e IM |
473 | /* |
474 | * Did this bank cause the exception? | |
475 | * | |
476 | * Assume that the bank with uncorrectable errors did it, | |
477 | * and that there is only a single one: | |
478 | */ | |
479 | if ((m.status & MCI_STATUS_UC) && | |
480 | (m.status & MCI_STATUS_EN)) { | |
1da177e4 LT |
481 | panicm = m; |
482 | panicm_found = 1; | |
483 | } | |
1da177e4 LT |
484 | } |
485 | ||
e9eee03e IM |
486 | /* |
487 | * If we didn't find an uncorrectable error, pick | |
488 | * the last one (shouldn't happen, just being safe). | |
489 | */ | |
1da177e4 LT |
490 | if (!panicm_found) |
491 | panicm = m; | |
bd78432c TH |
492 | |
493 | /* | |
494 | * If we have decided that we just CAN'T continue, and the user | |
e9eee03e | 495 | * has not set tolerant to an insane level, give up and die. |
bd78432c TH |
496 | */ |
497 | if (no_way_out && tolerant < 3) | |
bd19a5e6 | 498 | mce_panic("Machine check", &panicm, msg); |
bd78432c TH |
499 | |
500 | /* | |
501 | * If the error seems to be unrecoverable, something should be | |
502 | * done. Try to kill as little as possible. If we can kill just | |
503 | * one task, do that. If the user has set the tolerance very | |
504 | * high, don't try to do anything at all. | |
505 | */ | |
506 | if (kill_it && tolerant < 3) { | |
1da177e4 LT |
507 | int user_space = 0; |
508 | ||
bd78432c TH |
509 | /* |
510 | * If the EIPV bit is set, it means the saved IP is the | |
511 | * instruction which caused the MCE. | |
512 | */ | |
513 | if (m.mcgstatus & MCG_STATUS_EIPV) | |
65ea5b03 | 514 | user_space = panicm.ip && (panicm.cs & 3); |
bd78432c TH |
515 | |
516 | /* | |
517 | * If we know that the error was in user space, send a | |
518 | * SIGBUS. Otherwise, panic if tolerance is low. | |
519 | * | |
380851bc | 520 | * force_sig() takes an awful lot of locks and has a slight |
bd78432c TH |
521 | * risk of deadlocking. |
522 | */ | |
523 | if (user_space) { | |
380851bc | 524 | force_sig(SIGBUS, current); |
bd78432c | 525 | } else if (panic_on_oops || tolerant < 2) { |
bd19a5e6 | 526 | mce_panic("Uncorrected machine check", &panicm, msg); |
bd78432c | 527 | } |
1da177e4 LT |
528 | } |
529 | ||
e02e68d3 TH |
530 | /* notify userspace ASAP */ |
531 | set_thread_flag(TIF_MCE_NOTIFY); | |
532 | ||
bd78432c | 533 | /* the last thing we do is clear state */ |
b79109c3 AK |
534 | for (i = 0; i < banks; i++) { |
535 | if (test_bit(i, toclear)) | |
5f8c1a54 | 536 | mce_wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); |
b79109c3 | 537 | } |
5f8c1a54 | 538 | mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); |
32561696 | 539 | out: |
553f265f | 540 | atomic_dec(&mce_entry); |
88921be3 | 541 | sync_core(); |
1da177e4 | 542 | } |
ea149b36 | 543 | EXPORT_SYMBOL_GPL(do_machine_check); |
1da177e4 | 544 | |
15d5f839 DZ |
545 | #ifdef CONFIG_X86_MCE_INTEL |
546 | /*** | |
547 | * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog | |
676b1855 | 548 | * @cpu: The CPU on which the event occurred. |
15d5f839 DZ |
549 | * @status: Event status information |
550 | * | |
551 | * This function should be called by the thermal interrupt after the | |
552 | * event has been processed and the decision was made to log the event | |
553 | * further. | |
554 | * | |
555 | * The status parameter will be saved to the 'status' field of 'struct mce' | |
556 | * and historically has been the register value of the | |
557 | * MSR_IA32_THERMAL_STATUS (Intel) msr. | |
558 | */ | |
b5f2fa4e | 559 | void mce_log_therm_throt_event(__u64 status) |
15d5f839 DZ |
560 | { |
561 | struct mce m; | |
562 | ||
b5f2fa4e | 563 | mce_setup(&m); |
15d5f839 DZ |
564 | m.bank = MCE_THERMAL_BANK; |
565 | m.status = status; | |
15d5f839 DZ |
566 | mce_log(&m); |
567 | } | |
568 | #endif /* CONFIG_X86_MCE_INTEL */ | |
569 | ||
1da177e4 | 570 | /* |
8a336b0a TH |
571 | * Periodic polling timer for "silent" machine check errors. If the |
572 | * poller finds an MCE, poll 2x faster. When the poller finds no more | |
573 | * errors, poll 2x slower (up to check_interval seconds). | |
1da177e4 | 574 | */ |
1da177e4 | 575 | static int check_interval = 5 * 60; /* 5 minutes */ |
e9eee03e | 576 | |
6298c512 | 577 | static DEFINE_PER_CPU(int, next_interval); /* in jiffies */ |
52d168e2 | 578 | static DEFINE_PER_CPU(struct timer_list, mce_timer); |
1da177e4 | 579 | |
52d168e2 | 580 | static void mcheck_timer(unsigned long data) |
1da177e4 | 581 | { |
52d168e2 | 582 | struct timer_list *t = &per_cpu(mce_timer, data); |
6298c512 | 583 | int *n; |
52d168e2 AK |
584 | |
585 | WARN_ON(smp_processor_id() != data); | |
586 | ||
e9eee03e | 587 | if (mce_available(¤t_cpu_data)) { |
ee031c31 AK |
588 | machine_check_poll(MCP_TIMESTAMP, |
589 | &__get_cpu_var(mce_poll_banks)); | |
e9eee03e | 590 | } |
1da177e4 LT |
591 | |
592 | /* | |
e02e68d3 TH |
593 | * Alert userspace if needed. If we logged an MCE, reduce the |
594 | * polling interval, otherwise increase the polling interval. | |
1da177e4 | 595 | */ |
6298c512 | 596 | n = &__get_cpu_var(next_interval); |
14a02530 | 597 | if (mce_notify_user()) |
6298c512 | 598 | *n = max(*n/2, HZ/100); |
14a02530 | 599 | else |
6298c512 | 600 | *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ)); |
e02e68d3 | 601 | |
6298c512 | 602 | t->expires = jiffies + *n; |
52d168e2 | 603 | add_timer(t); |
e02e68d3 TH |
604 | } |
605 | ||
9bd98405 AK |
606 | static void mce_do_trigger(struct work_struct *work) |
607 | { | |
608 | call_usermodehelper(trigger, trigger_argv, NULL, UMH_NO_WAIT); | |
609 | } | |
610 | ||
611 | static DECLARE_WORK(mce_trigger_work, mce_do_trigger); | |
612 | ||
e02e68d3 | 613 | /* |
9bd98405 AK |
614 | * Notify the user(s) about new machine check events. |
615 | * Can be called from interrupt context, but not from machine check/NMI | |
616 | * context. | |
e02e68d3 TH |
617 | */ |
618 | int mce_notify_user(void) | |
619 | { | |
8457c84d AK |
620 | /* Not more than two messages every minute */ |
621 | static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); | |
622 | ||
e02e68d3 | 623 | clear_thread_flag(TIF_MCE_NOTIFY); |
e9eee03e | 624 | |
e02e68d3 | 625 | if (test_and_clear_bit(0, ¬ify_user)) { |
e02e68d3 | 626 | wake_up_interruptible(&mce_wait); |
9bd98405 AK |
627 | |
628 | /* | |
629 | * There is no risk of missing notifications because | |
630 | * work_pending is always cleared before the function is | |
631 | * executed. | |
632 | */ | |
633 | if (trigger[0] && !work_pending(&mce_trigger_work)) | |
634 | schedule_work(&mce_trigger_work); | |
e02e68d3 | 635 | |
8457c84d | 636 | if (__ratelimit(&ratelimit)) |
8a336b0a | 637 | printk(KERN_INFO "Machine check events logged\n"); |
e02e68d3 TH |
638 | |
639 | return 1; | |
1da177e4 | 640 | } |
e02e68d3 TH |
641 | return 0; |
642 | } | |
ea149b36 | 643 | EXPORT_SYMBOL_GPL(mce_notify_user); |
8a336b0a | 644 | |
d88203d1 | 645 | /* |
1da177e4 LT |
646 | * Initialize Machine Checks for a CPU. |
647 | */ | |
0d7482e3 | 648 | static int mce_cap_init(void) |
1da177e4 | 649 | { |
0d7482e3 | 650 | unsigned b; |
e9eee03e | 651 | u64 cap; |
1da177e4 LT |
652 | |
653 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
01c6680a TG |
654 | |
655 | b = cap & MCG_BANKCNT_MASK; | |
b659294b IM |
656 | printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b); |
657 | ||
0d7482e3 AK |
658 | if (b > MAX_NR_BANKS) { |
659 | printk(KERN_WARNING | |
660 | "MCE: Using only %u machine check banks out of %u\n", | |
661 | MAX_NR_BANKS, b); | |
662 | b = MAX_NR_BANKS; | |
663 | } | |
664 | ||
665 | /* Don't support asymmetric configurations today */ | |
666 | WARN_ON(banks != 0 && b != banks); | |
667 | banks = b; | |
668 | if (!bank) { | |
669 | bank = kmalloc(banks * sizeof(u64), GFP_KERNEL); | |
670 | if (!bank) | |
671 | return -ENOMEM; | |
672 | memset(bank, 0xff, banks * sizeof(u64)); | |
1da177e4 | 673 | } |
0d7482e3 | 674 | |
94ad8474 | 675 | /* Use accurate RIP reporting if available. */ |
01c6680a | 676 | if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) |
94ad8474 | 677 | rip_msr = MSR_IA32_MCG_EIP; |
1da177e4 | 678 | |
0d7482e3 AK |
679 | return 0; |
680 | } | |
681 | ||
8be91105 | 682 | static void mce_init(void) |
0d7482e3 | 683 | { |
e9eee03e | 684 | mce_banks_t all_banks; |
0d7482e3 AK |
685 | u64 cap; |
686 | int i; | |
687 | ||
b79109c3 AK |
688 | /* |
689 | * Log the machine checks left over from the previous reset. | |
690 | */ | |
ee031c31 | 691 | bitmap_fill(all_banks, MAX_NR_BANKS); |
5679af4c | 692 | machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks); |
1da177e4 LT |
693 | |
694 | set_in_cr4(X86_CR4_MCE); | |
695 | ||
0d7482e3 | 696 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
1da177e4 LT |
697 | if (cap & MCG_CTL_P) |
698 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); | |
699 | ||
700 | for (i = 0; i < banks; i++) { | |
06b7a7a5 AK |
701 | if (skip_bank_init(i)) |
702 | continue; | |
0d7482e3 | 703 | wrmsrl(MSR_IA32_MC0_CTL+4*i, bank[i]); |
1da177e4 | 704 | wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); |
d88203d1 | 705 | } |
1da177e4 LT |
706 | } |
707 | ||
708 | /* Add per CPU specific workarounds here */ | |
ec5b3d32 | 709 | static void mce_cpu_quirks(struct cpuinfo_x86 *c) |
d88203d1 | 710 | { |
1da177e4 | 711 | /* This should be disabled by the BIOS, but isn't always */ |
911f6a7b | 712 | if (c->x86_vendor == X86_VENDOR_AMD) { |
e9eee03e IM |
713 | if (c->x86 == 15 && banks > 4) { |
714 | /* | |
715 | * disable GART TBL walk error reporting, which | |
716 | * trips off incorrectly with the IOMMU & 3ware | |
717 | * & Cerberus: | |
718 | */ | |
0d7482e3 | 719 | clear_bit(10, (unsigned long *)&bank[4]); |
e9eee03e IM |
720 | } |
721 | if (c->x86 <= 17 && mce_bootlog < 0) { | |
722 | /* | |
723 | * Lots of broken BIOS around that don't clear them | |
724 | * by default and leave crap in there. Don't log: | |
725 | */ | |
911f6a7b | 726 | mce_bootlog = 0; |
e9eee03e | 727 | } |
2e6f694f AK |
728 | /* |
729 | * Various K7s with broken bank 0 around. Always disable | |
730 | * by default. | |
731 | */ | |
732 | if (c->x86 == 6) | |
733 | bank[0] = 0; | |
1da177e4 | 734 | } |
e583538f | 735 | |
06b7a7a5 AK |
736 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
737 | /* | |
738 | * SDM documents that on family 6 bank 0 should not be written | |
739 | * because it aliases to another special BIOS controlled | |
740 | * register. | |
741 | * But it's not aliased anymore on model 0x1a+ | |
742 | * Don't ignore bank 0 completely because there could be a | |
743 | * valid event later, merely don't write CTL0. | |
744 | */ | |
745 | ||
746 | if (c->x86 == 6 && c->x86_model < 0x1A) | |
747 | __set_bit(0, &dont_init_banks); | |
748 | } | |
d88203d1 | 749 | } |
1da177e4 | 750 | |
4efc0670 AK |
751 | static void __cpuinit mce_ancient_init(struct cpuinfo_x86 *c) |
752 | { | |
753 | if (c->x86 != 5) | |
754 | return; | |
755 | switch (c->x86_vendor) { | |
756 | case X86_VENDOR_INTEL: | |
757 | if (mce_p5_enabled()) | |
758 | intel_p5_mcheck_init(c); | |
759 | break; | |
760 | case X86_VENDOR_CENTAUR: | |
761 | winchip_mcheck_init(c); | |
762 | break; | |
763 | } | |
764 | } | |
765 | ||
cc3ca220 | 766 | static void mce_cpu_features(struct cpuinfo_x86 *c) |
1da177e4 LT |
767 | { |
768 | switch (c->x86_vendor) { | |
769 | case X86_VENDOR_INTEL: | |
770 | mce_intel_feature_init(c); | |
771 | break; | |
89b831ef JS |
772 | case X86_VENDOR_AMD: |
773 | mce_amd_feature_init(c); | |
774 | break; | |
1da177e4 LT |
775 | default: |
776 | break; | |
777 | } | |
778 | } | |
779 | ||
52d168e2 AK |
780 | static void mce_init_timer(void) |
781 | { | |
782 | struct timer_list *t = &__get_cpu_var(mce_timer); | |
6298c512 | 783 | int *n = &__get_cpu_var(next_interval); |
52d168e2 | 784 | |
6298c512 AK |
785 | *n = check_interval * HZ; |
786 | if (!*n) | |
52d168e2 AK |
787 | return; |
788 | setup_timer(t, mcheck_timer, smp_processor_id()); | |
6298c512 | 789 | t->expires = round_jiffies(jiffies + *n); |
52d168e2 AK |
790 | add_timer(t); |
791 | } | |
792 | ||
d88203d1 | 793 | /* |
1da177e4 | 794 | * Called for each booted CPU to set up machine checks. |
e9eee03e | 795 | * Must be called with preempt off: |
1da177e4 | 796 | */ |
e6982c67 | 797 | void __cpuinit mcheck_init(struct cpuinfo_x86 *c) |
1da177e4 | 798 | { |
4efc0670 AK |
799 | if (mce_disabled) |
800 | return; | |
801 | ||
802 | mce_ancient_init(c); | |
803 | ||
5b4408fd | 804 | if (!mce_available(c)) |
1da177e4 LT |
805 | return; |
806 | ||
0d7482e3 | 807 | if (mce_cap_init() < 0) { |
04b2b1a4 | 808 | mce_disabled = 1; |
0d7482e3 AK |
809 | return; |
810 | } | |
811 | mce_cpu_quirks(c); | |
812 | ||
5d727926 AK |
813 | machine_check_vector = do_machine_check; |
814 | ||
8be91105 | 815 | mce_init(); |
1da177e4 | 816 | mce_cpu_features(c); |
52d168e2 | 817 | mce_init_timer(); |
1da177e4 LT |
818 | } |
819 | ||
820 | /* | |
821 | * Character device to read and clear the MCE log. | |
822 | */ | |
823 | ||
f528e7ba | 824 | static DEFINE_SPINLOCK(mce_state_lock); |
e9eee03e IM |
825 | static int open_count; /* #times opened */ |
826 | static int open_exclu; /* already open exclusive? */ | |
f528e7ba TH |
827 | |
828 | static int mce_open(struct inode *inode, struct file *file) | |
829 | { | |
830 | spin_lock(&mce_state_lock); | |
831 | ||
832 | if (open_exclu || (open_count && (file->f_flags & O_EXCL))) { | |
833 | spin_unlock(&mce_state_lock); | |
e9eee03e | 834 | |
f528e7ba TH |
835 | return -EBUSY; |
836 | } | |
837 | ||
838 | if (file->f_flags & O_EXCL) | |
839 | open_exclu = 1; | |
840 | open_count++; | |
841 | ||
842 | spin_unlock(&mce_state_lock); | |
843 | ||
bd78432c | 844 | return nonseekable_open(inode, file); |
f528e7ba TH |
845 | } |
846 | ||
847 | static int mce_release(struct inode *inode, struct file *file) | |
848 | { | |
849 | spin_lock(&mce_state_lock); | |
850 | ||
851 | open_count--; | |
852 | open_exclu = 0; | |
853 | ||
854 | spin_unlock(&mce_state_lock); | |
855 | ||
856 | return 0; | |
857 | } | |
858 | ||
d88203d1 TG |
859 | static void collect_tscs(void *data) |
860 | { | |
1da177e4 | 861 | unsigned long *cpu_tsc = (unsigned long *)data; |
d88203d1 | 862 | |
1da177e4 | 863 | rdtscll(cpu_tsc[smp_processor_id()]); |
d88203d1 | 864 | } |
1da177e4 | 865 | |
e9eee03e IM |
866 | static DEFINE_MUTEX(mce_read_mutex); |
867 | ||
d88203d1 TG |
868 | static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize, |
869 | loff_t *off) | |
1da177e4 | 870 | { |
e9eee03e | 871 | char __user *buf = ubuf; |
f0de53bb | 872 | unsigned long *cpu_tsc; |
ef41df43 | 873 | unsigned prev, next; |
1da177e4 LT |
874 | int i, err; |
875 | ||
6bca67f9 | 876 | cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL); |
f0de53bb AK |
877 | if (!cpu_tsc) |
878 | return -ENOMEM; | |
879 | ||
8c8b8859 | 880 | mutex_lock(&mce_read_mutex); |
1da177e4 LT |
881 | next = rcu_dereference(mcelog.next); |
882 | ||
883 | /* Only supports full reads right now */ | |
d88203d1 | 884 | if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) { |
8c8b8859 | 885 | mutex_unlock(&mce_read_mutex); |
f0de53bb | 886 | kfree(cpu_tsc); |
e9eee03e | 887 | |
1da177e4 LT |
888 | return -EINVAL; |
889 | } | |
890 | ||
891 | err = 0; | |
ef41df43 HY |
892 | prev = 0; |
893 | do { | |
894 | for (i = prev; i < next; i++) { | |
895 | unsigned long start = jiffies; | |
896 | ||
897 | while (!mcelog.entry[i].finished) { | |
898 | if (time_after_eq(jiffies, start + 2)) { | |
899 | memset(mcelog.entry + i, 0, | |
900 | sizeof(struct mce)); | |
901 | goto timeout; | |
902 | } | |
903 | cpu_relax(); | |
673242c1 | 904 | } |
ef41df43 HY |
905 | smp_rmb(); |
906 | err |= copy_to_user(buf, mcelog.entry + i, | |
907 | sizeof(struct mce)); | |
908 | buf += sizeof(struct mce); | |
909 | timeout: | |
910 | ; | |
673242c1 | 911 | } |
1da177e4 | 912 | |
ef41df43 HY |
913 | memset(mcelog.entry + prev, 0, |
914 | (next - prev) * sizeof(struct mce)); | |
915 | prev = next; | |
916 | next = cmpxchg(&mcelog.next, prev, 0); | |
917 | } while (next != prev); | |
1da177e4 | 918 | |
b2b18660 | 919 | synchronize_sched(); |
1da177e4 | 920 | |
d88203d1 TG |
921 | /* |
922 | * Collect entries that were still getting written before the | |
923 | * synchronize. | |
924 | */ | |
15c8b6c1 | 925 | on_each_cpu(collect_tscs, cpu_tsc, 1); |
e9eee03e | 926 | |
d88203d1 TG |
927 | for (i = next; i < MCE_LOG_LEN; i++) { |
928 | if (mcelog.entry[i].finished && | |
929 | mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) { | |
930 | err |= copy_to_user(buf, mcelog.entry+i, | |
931 | sizeof(struct mce)); | |
1da177e4 LT |
932 | smp_rmb(); |
933 | buf += sizeof(struct mce); | |
934 | memset(&mcelog.entry[i], 0, sizeof(struct mce)); | |
935 | } | |
d88203d1 | 936 | } |
8c8b8859 | 937 | mutex_unlock(&mce_read_mutex); |
f0de53bb | 938 | kfree(cpu_tsc); |
e9eee03e | 939 | |
d88203d1 | 940 | return err ? -EFAULT : buf - ubuf; |
1da177e4 LT |
941 | } |
942 | ||
e02e68d3 TH |
943 | static unsigned int mce_poll(struct file *file, poll_table *wait) |
944 | { | |
945 | poll_wait(file, &mce_wait, wait); | |
946 | if (rcu_dereference(mcelog.next)) | |
947 | return POLLIN | POLLRDNORM; | |
948 | return 0; | |
949 | } | |
950 | ||
c68461b6 | 951 | static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg) |
1da177e4 LT |
952 | { |
953 | int __user *p = (int __user *)arg; | |
d88203d1 | 954 | |
1da177e4 | 955 | if (!capable(CAP_SYS_ADMIN)) |
d88203d1 | 956 | return -EPERM; |
e9eee03e | 957 | |
1da177e4 | 958 | switch (cmd) { |
d88203d1 | 959 | case MCE_GET_RECORD_LEN: |
1da177e4 LT |
960 | return put_user(sizeof(struct mce), p); |
961 | case MCE_GET_LOG_LEN: | |
d88203d1 | 962 | return put_user(MCE_LOG_LEN, p); |
1da177e4 LT |
963 | case MCE_GETCLEAR_FLAGS: { |
964 | unsigned flags; | |
d88203d1 TG |
965 | |
966 | do { | |
1da177e4 | 967 | flags = mcelog.flags; |
d88203d1 | 968 | } while (cmpxchg(&mcelog.flags, flags, 0) != flags); |
e9eee03e | 969 | |
d88203d1 | 970 | return put_user(flags, p); |
1da177e4 LT |
971 | } |
972 | default: | |
d88203d1 TG |
973 | return -ENOTTY; |
974 | } | |
1da177e4 LT |
975 | } |
976 | ||
a1ff41bf | 977 | /* Modified in mce-inject.c, so not static or const */ |
ea149b36 | 978 | struct file_operations mce_chrdev_ops = { |
e9eee03e IM |
979 | .open = mce_open, |
980 | .release = mce_release, | |
981 | .read = mce_read, | |
982 | .poll = mce_poll, | |
983 | .unlocked_ioctl = mce_ioctl, | |
1da177e4 | 984 | }; |
ea149b36 | 985 | EXPORT_SYMBOL_GPL(mce_chrdev_ops); |
1da177e4 LT |
986 | |
987 | static struct miscdevice mce_log_device = { | |
988 | MISC_MCELOG_MINOR, | |
989 | "mcelog", | |
990 | &mce_chrdev_ops, | |
991 | }; | |
992 | ||
13503fa9 HS |
993 | /* |
994 | * mce=off disables machine check | |
995 | * mce=TOLERANCELEVEL (number, see above) | |
996 | * mce=bootlog Log MCEs from before booting. Disabled by default on AMD. | |
997 | * mce=nobootlog Don't log MCEs from before booting. | |
998 | */ | |
1da177e4 LT |
999 | static int __init mcheck_enable(char *str) |
1000 | { | |
4efc0670 AK |
1001 | if (*str == 0) |
1002 | enable_p5_mce(); | |
1003 | if (*str == '=') | |
1004 | str++; | |
1da177e4 | 1005 | if (!strcmp(str, "off")) |
04b2b1a4 | 1006 | mce_disabled = 1; |
13503fa9 HS |
1007 | else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) |
1008 | mce_bootlog = (str[0] == 'b'); | |
8c566ef5 AK |
1009 | else if (isdigit(str[0])) |
1010 | get_option(&str, &tolerant); | |
13503fa9 | 1011 | else { |
4efc0670 | 1012 | printk(KERN_INFO "mce argument %s ignored. Please use /sys\n", |
13503fa9 HS |
1013 | str); |
1014 | return 0; | |
1015 | } | |
9b41046c | 1016 | return 1; |
1da177e4 | 1017 | } |
4efc0670 | 1018 | __setup("mce", mcheck_enable); |
1da177e4 | 1019 | |
d88203d1 | 1020 | /* |
1da177e4 | 1021 | * Sysfs support |
d88203d1 | 1022 | */ |
1da177e4 | 1023 | |
973a2dd1 AK |
1024 | /* |
1025 | * Disable machine checks on suspend and shutdown. We can't really handle | |
1026 | * them later. | |
1027 | */ | |
1028 | static int mce_disable(void) | |
1029 | { | |
1030 | int i; | |
1031 | ||
06b7a7a5 AK |
1032 | for (i = 0; i < banks; i++) { |
1033 | if (!skip_bank_init(i)) | |
1034 | wrmsrl(MSR_IA32_MC0_CTL + i*4, 0); | |
1035 | } | |
973a2dd1 AK |
1036 | return 0; |
1037 | } | |
1038 | ||
1039 | static int mce_suspend(struct sys_device *dev, pm_message_t state) | |
1040 | { | |
1041 | return mce_disable(); | |
1042 | } | |
1043 | ||
1044 | static int mce_shutdown(struct sys_device *dev) | |
1045 | { | |
1046 | return mce_disable(); | |
1047 | } | |
1048 | ||
e9eee03e IM |
1049 | /* |
1050 | * On resume clear all MCE state. Don't want to see leftovers from the BIOS. | |
1051 | * Only one CPU is active at this time, the others get re-added later using | |
1052 | * CPU hotplug: | |
1053 | */ | |
1da177e4 LT |
1054 | static int mce_resume(struct sys_device *dev) |
1055 | { | |
8be91105 | 1056 | mce_init(); |
6ec68bff | 1057 | mce_cpu_features(¤t_cpu_data); |
e9eee03e | 1058 | |
1da177e4 LT |
1059 | return 0; |
1060 | } | |
1061 | ||
52d168e2 AK |
1062 | static void mce_cpu_restart(void *data) |
1063 | { | |
1064 | del_timer_sync(&__get_cpu_var(mce_timer)); | |
1065 | if (mce_available(¤t_cpu_data)) | |
8be91105 | 1066 | mce_init(); |
52d168e2 AK |
1067 | mce_init_timer(); |
1068 | } | |
1069 | ||
1da177e4 | 1070 | /* Reinit MCEs after user configuration changes */ |
d88203d1 TG |
1071 | static void mce_restart(void) |
1072 | { | |
52d168e2 | 1073 | on_each_cpu(mce_cpu_restart, NULL, 1); |
1da177e4 LT |
1074 | } |
1075 | ||
1076 | static struct sysdev_class mce_sysclass = { | |
e9eee03e IM |
1077 | .suspend = mce_suspend, |
1078 | .shutdown = mce_shutdown, | |
1079 | .resume = mce_resume, | |
1080 | .name = "machinecheck", | |
1da177e4 LT |
1081 | }; |
1082 | ||
cb491fca | 1083 | DEFINE_PER_CPU(struct sys_device, mce_dev); |
e9eee03e IM |
1084 | |
1085 | __cpuinitdata | |
1086 | void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); | |
1da177e4 | 1087 | |
0d7482e3 AK |
1088 | static struct sysdev_attribute *bank_attrs; |
1089 | ||
1090 | static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
1091 | char *buf) | |
1092 | { | |
1093 | u64 b = bank[attr - bank_attrs]; | |
e9eee03e | 1094 | |
f6d1826d | 1095 | return sprintf(buf, "%llx\n", b); |
0d7482e3 AK |
1096 | } |
1097 | ||
1098 | static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
9319cec8 | 1099 | const char *buf, size_t size) |
0d7482e3 | 1100 | { |
9319cec8 | 1101 | u64 new; |
e9eee03e | 1102 | |
9319cec8 | 1103 | if (strict_strtoull(buf, 0, &new) < 0) |
0d7482e3 | 1104 | return -EINVAL; |
e9eee03e | 1105 | |
0d7482e3 AK |
1106 | bank[attr - bank_attrs] = new; |
1107 | mce_restart(); | |
e9eee03e | 1108 | |
9319cec8 | 1109 | return size; |
0d7482e3 | 1110 | } |
a98f0dd3 | 1111 | |
e9eee03e IM |
1112 | static ssize_t |
1113 | show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf) | |
a98f0dd3 AK |
1114 | { |
1115 | strcpy(buf, trigger); | |
1116 | strcat(buf, "\n"); | |
1117 | return strlen(trigger) + 1; | |
1118 | } | |
1119 | ||
4a0b2b4d | 1120 | static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr, |
e9eee03e | 1121 | const char *buf, size_t siz) |
a98f0dd3 AK |
1122 | { |
1123 | char *p; | |
1124 | int len; | |
e9eee03e | 1125 | |
a98f0dd3 AK |
1126 | strncpy(trigger, buf, sizeof(trigger)); |
1127 | trigger[sizeof(trigger)-1] = 0; | |
1128 | len = strlen(trigger); | |
1129 | p = strchr(trigger, '\n'); | |
e9eee03e IM |
1130 | |
1131 | if (*p) | |
1132 | *p = 0; | |
1133 | ||
a98f0dd3 AK |
1134 | return len; |
1135 | } | |
1136 | ||
b56f642d AK |
1137 | static ssize_t store_int_with_restart(struct sys_device *s, |
1138 | struct sysdev_attribute *attr, | |
1139 | const char *buf, size_t size) | |
1140 | { | |
1141 | ssize_t ret = sysdev_store_int(s, attr, buf, size); | |
1142 | mce_restart(); | |
1143 | return ret; | |
1144 | } | |
1145 | ||
a98f0dd3 | 1146 | static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger); |
d95d62c0 | 1147 | static SYSDEV_INT_ATTR(tolerant, 0644, tolerant); |
e9eee03e | 1148 | |
b56f642d AK |
1149 | static struct sysdev_ext_attribute attr_check_interval = { |
1150 | _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int, | |
1151 | store_int_with_restart), | |
1152 | &check_interval | |
1153 | }; | |
e9eee03e | 1154 | |
cb491fca | 1155 | static struct sysdev_attribute *mce_attrs[] = { |
b56f642d | 1156 | &attr_tolerant.attr, &attr_check_interval.attr, &attr_trigger, |
a98f0dd3 AK |
1157 | NULL |
1158 | }; | |
1da177e4 | 1159 | |
cb491fca | 1160 | static cpumask_var_t mce_dev_initialized; |
bae19fe0 | 1161 | |
e9eee03e | 1162 | /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */ |
91c6d400 | 1163 | static __cpuinit int mce_create_device(unsigned int cpu) |
1da177e4 LT |
1164 | { |
1165 | int err; | |
73ca5358 | 1166 | int i; |
92cb7612 | 1167 | |
90367556 | 1168 | if (!mce_available(&boot_cpu_data)) |
91c6d400 AK |
1169 | return -EIO; |
1170 | ||
cb491fca IM |
1171 | memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject)); |
1172 | per_cpu(mce_dev, cpu).id = cpu; | |
1173 | per_cpu(mce_dev, cpu).cls = &mce_sysclass; | |
91c6d400 | 1174 | |
cb491fca | 1175 | err = sysdev_register(&per_cpu(mce_dev, cpu)); |
d435d862 AM |
1176 | if (err) |
1177 | return err; | |
1178 | ||
cb491fca IM |
1179 | for (i = 0; mce_attrs[i]; i++) { |
1180 | err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
d435d862 AM |
1181 | if (err) |
1182 | goto error; | |
1183 | } | |
0d7482e3 | 1184 | for (i = 0; i < banks; i++) { |
cb491fca | 1185 | err = sysdev_create_file(&per_cpu(mce_dev, cpu), |
0d7482e3 AK |
1186 | &bank_attrs[i]); |
1187 | if (err) | |
1188 | goto error2; | |
1189 | } | |
cb491fca | 1190 | cpumask_set_cpu(cpu, mce_dev_initialized); |
91c6d400 | 1191 | |
d435d862 | 1192 | return 0; |
0d7482e3 | 1193 | error2: |
cb491fca IM |
1194 | while (--i >= 0) |
1195 | sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[i]); | |
d435d862 | 1196 | error: |
cb491fca IM |
1197 | while (--i >= 0) |
1198 | sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
1199 | ||
1200 | sysdev_unregister(&per_cpu(mce_dev, cpu)); | |
d435d862 | 1201 | |
91c6d400 AK |
1202 | return err; |
1203 | } | |
1204 | ||
2d9cd6c2 | 1205 | static __cpuinit void mce_remove_device(unsigned int cpu) |
91c6d400 | 1206 | { |
73ca5358 SL |
1207 | int i; |
1208 | ||
cb491fca | 1209 | if (!cpumask_test_cpu(cpu, mce_dev_initialized)) |
bae19fe0 AH |
1210 | return; |
1211 | ||
cb491fca IM |
1212 | for (i = 0; mce_attrs[i]; i++) |
1213 | sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
1214 | ||
0d7482e3 | 1215 | for (i = 0; i < banks; i++) |
cb491fca IM |
1216 | sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[i]); |
1217 | ||
1218 | sysdev_unregister(&per_cpu(mce_dev, cpu)); | |
1219 | cpumask_clear_cpu(cpu, mce_dev_initialized); | |
91c6d400 | 1220 | } |
91c6d400 | 1221 | |
d6b75584 | 1222 | /* Make sure there are no machine checks on offlined CPUs. */ |
ec5b3d32 | 1223 | static void mce_disable_cpu(void *h) |
d6b75584 | 1224 | { |
88ccbedd | 1225 | unsigned long action = *(unsigned long *)h; |
cb491fca | 1226 | int i; |
d6b75584 AK |
1227 | |
1228 | if (!mce_available(¤t_cpu_data)) | |
1229 | return; | |
88ccbedd AK |
1230 | if (!(action & CPU_TASKS_FROZEN)) |
1231 | cmci_clear(); | |
06b7a7a5 AK |
1232 | for (i = 0; i < banks; i++) { |
1233 | if (!skip_bank_init(i)) | |
1234 | wrmsrl(MSR_IA32_MC0_CTL + i*4, 0); | |
1235 | } | |
d6b75584 AK |
1236 | } |
1237 | ||
ec5b3d32 | 1238 | static void mce_reenable_cpu(void *h) |
d6b75584 | 1239 | { |
88ccbedd | 1240 | unsigned long action = *(unsigned long *)h; |
e9eee03e | 1241 | int i; |
d6b75584 AK |
1242 | |
1243 | if (!mce_available(¤t_cpu_data)) | |
1244 | return; | |
e9eee03e | 1245 | |
88ccbedd AK |
1246 | if (!(action & CPU_TASKS_FROZEN)) |
1247 | cmci_reenable(); | |
06b7a7a5 AK |
1248 | for (i = 0; i < banks; i++) { |
1249 | if (!skip_bank_init(i)) | |
1250 | wrmsrl(MSR_IA32_MC0_CTL + i*4, bank[i]); | |
1251 | } | |
d6b75584 AK |
1252 | } |
1253 | ||
91c6d400 | 1254 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ |
e9eee03e IM |
1255 | static int __cpuinit |
1256 | mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) | |
91c6d400 AK |
1257 | { |
1258 | unsigned int cpu = (unsigned long)hcpu; | |
52d168e2 | 1259 | struct timer_list *t = &per_cpu(mce_timer, cpu); |
91c6d400 AK |
1260 | |
1261 | switch (action) { | |
bae19fe0 AH |
1262 | case CPU_ONLINE: |
1263 | case CPU_ONLINE_FROZEN: | |
1264 | mce_create_device(cpu); | |
8735728e RW |
1265 | if (threshold_cpu_callback) |
1266 | threshold_cpu_callback(action, cpu); | |
91c6d400 | 1267 | break; |
91c6d400 | 1268 | case CPU_DEAD: |
8bb78442 | 1269 | case CPU_DEAD_FROZEN: |
8735728e RW |
1270 | if (threshold_cpu_callback) |
1271 | threshold_cpu_callback(action, cpu); | |
91c6d400 AK |
1272 | mce_remove_device(cpu); |
1273 | break; | |
52d168e2 AK |
1274 | case CPU_DOWN_PREPARE: |
1275 | case CPU_DOWN_PREPARE_FROZEN: | |
1276 | del_timer_sync(t); | |
88ccbedd | 1277 | smp_call_function_single(cpu, mce_disable_cpu, &action, 1); |
52d168e2 AK |
1278 | break; |
1279 | case CPU_DOWN_FAILED: | |
1280 | case CPU_DOWN_FAILED_FROZEN: | |
6298c512 AK |
1281 | t->expires = round_jiffies(jiffies + |
1282 | __get_cpu_var(next_interval)); | |
52d168e2 | 1283 | add_timer_on(t, cpu); |
88ccbedd AK |
1284 | smp_call_function_single(cpu, mce_reenable_cpu, &action, 1); |
1285 | break; | |
1286 | case CPU_POST_DEAD: | |
1287 | /* intentionally ignoring frozen here */ | |
1288 | cmci_rediscover(cpu); | |
52d168e2 | 1289 | break; |
91c6d400 | 1290 | } |
bae19fe0 | 1291 | return NOTIFY_OK; |
91c6d400 AK |
1292 | } |
1293 | ||
1e35669d | 1294 | static struct notifier_block mce_cpu_notifier __cpuinitdata = { |
91c6d400 AK |
1295 | .notifier_call = mce_cpu_callback, |
1296 | }; | |
1297 | ||
0d7482e3 AK |
1298 | static __init int mce_init_banks(void) |
1299 | { | |
1300 | int i; | |
1301 | ||
1302 | bank_attrs = kzalloc(sizeof(struct sysdev_attribute) * banks, | |
1303 | GFP_KERNEL); | |
1304 | if (!bank_attrs) | |
1305 | return -ENOMEM; | |
1306 | ||
1307 | for (i = 0; i < banks; i++) { | |
1308 | struct sysdev_attribute *a = &bank_attrs[i]; | |
e9eee03e IM |
1309 | |
1310 | a->attr.name = kasprintf(GFP_KERNEL, "bank%d", i); | |
0d7482e3 AK |
1311 | if (!a->attr.name) |
1312 | goto nomem; | |
e9eee03e IM |
1313 | |
1314 | a->attr.mode = 0644; | |
1315 | a->show = show_bank; | |
1316 | a->store = set_bank; | |
0d7482e3 AK |
1317 | } |
1318 | return 0; | |
1319 | ||
1320 | nomem: | |
1321 | while (--i >= 0) | |
1322 | kfree(bank_attrs[i].attr.name); | |
1323 | kfree(bank_attrs); | |
1324 | bank_attrs = NULL; | |
e9eee03e | 1325 | |
0d7482e3 AK |
1326 | return -ENOMEM; |
1327 | } | |
1328 | ||
91c6d400 AK |
1329 | static __init int mce_init_device(void) |
1330 | { | |
1331 | int err; | |
1332 | int i = 0; | |
1333 | ||
1da177e4 LT |
1334 | if (!mce_available(&boot_cpu_data)) |
1335 | return -EIO; | |
0d7482e3 | 1336 | |
cb491fca | 1337 | alloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL); |
996867d0 | 1338 | |
0d7482e3 AK |
1339 | err = mce_init_banks(); |
1340 | if (err) | |
1341 | return err; | |
1342 | ||
1da177e4 | 1343 | err = sysdev_class_register(&mce_sysclass); |
d435d862 AM |
1344 | if (err) |
1345 | return err; | |
91c6d400 AK |
1346 | |
1347 | for_each_online_cpu(i) { | |
d435d862 AM |
1348 | err = mce_create_device(i); |
1349 | if (err) | |
1350 | return err; | |
91c6d400 AK |
1351 | } |
1352 | ||
be6b5a35 | 1353 | register_hotcpu_notifier(&mce_cpu_notifier); |
1da177e4 | 1354 | misc_register(&mce_log_device); |
e9eee03e | 1355 | |
1da177e4 | 1356 | return err; |
1da177e4 | 1357 | } |
91c6d400 | 1358 | |
1da177e4 | 1359 | device_initcall(mce_init_device); |
a988d334 | 1360 | |
4efc0670 | 1361 | #else /* CONFIG_X86_OLD_MCE: */ |
a988d334 | 1362 | |
a988d334 IM |
1363 | int nr_mce_banks; |
1364 | EXPORT_SYMBOL_GPL(nr_mce_banks); /* non-fatal.o */ | |
1365 | ||
a988d334 IM |
1366 | /* This has to be run for each processor */ |
1367 | void mcheck_init(struct cpuinfo_x86 *c) | |
1368 | { | |
1369 | if (mce_disabled == 1) | |
1370 | return; | |
1371 | ||
1372 | switch (c->x86_vendor) { | |
1373 | case X86_VENDOR_AMD: | |
1374 | amd_mcheck_init(c); | |
1375 | break; | |
1376 | ||
1377 | case X86_VENDOR_INTEL: | |
1378 | if (c->x86 == 5) | |
1379 | intel_p5_mcheck_init(c); | |
1380 | if (c->x86 == 6) | |
1381 | intel_p6_mcheck_init(c); | |
1382 | if (c->x86 == 15) | |
1383 | intel_p4_mcheck_init(c); | |
1384 | break; | |
1385 | ||
1386 | case X86_VENDOR_CENTAUR: | |
1387 | if (c->x86 == 5) | |
1388 | winchip_mcheck_init(c); | |
1389 | break; | |
1390 | ||
1391 | default: | |
1392 | break; | |
1393 | } | |
b659294b | 1394 | printk(KERN_INFO "mce: CPU supports %d MCE banks\n", nr_mce_banks); |
a988d334 IM |
1395 | } |
1396 | ||
a988d334 IM |
1397 | static int __init mcheck_enable(char *str) |
1398 | { | |
1399 | mce_disabled = -1; | |
1400 | return 1; | |
1401 | } | |
1402 | ||
a988d334 IM |
1403 | __setup("mce", mcheck_enable); |
1404 | ||
d7c3c9a6 AK |
1405 | #endif /* CONFIG_X86_OLD_MCE */ |
1406 | ||
1407 | /* | |
1408 | * Old style boot options parsing. Only for compatibility. | |
1409 | */ | |
1410 | static int __init mcheck_disable(char *str) | |
1411 | { | |
1412 | mce_disabled = 1; | |
1413 | return 1; | |
1414 | } | |
1415 | __setup("nomce", mcheck_disable); |