Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Machine check handler. | |
e9eee03e | 3 | * |
1da177e4 | 4 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. |
d88203d1 TG |
5 | * Rest from unknown author(s). |
6 | * 2004 Andi Kleen. Rewrote most of it. | |
b79109c3 AK |
7 | * Copyright 2008 Intel Corporation |
8 | * Author: Andi Kleen | |
1da177e4 | 9 | */ |
e9eee03e IM |
10 | #include <linux/thread_info.h> |
11 | #include <linux/capability.h> | |
12 | #include <linux/miscdevice.h> | |
ccc3c319 | 13 | #include <linux/interrupt.h> |
e9eee03e IM |
14 | #include <linux/ratelimit.h> |
15 | #include <linux/kallsyms.h> | |
16 | #include <linux/rcupdate.h> | |
e9eee03e | 17 | #include <linux/kobject.h> |
14a02530 | 18 | #include <linux/uaccess.h> |
e9eee03e IM |
19 | #include <linux/kdebug.h> |
20 | #include <linux/kernel.h> | |
21 | #include <linux/percpu.h> | |
1da177e4 | 22 | #include <linux/string.h> |
1da177e4 | 23 | #include <linux/sysdev.h> |
3c079792 | 24 | #include <linux/delay.h> |
8c566ef5 | 25 | #include <linux/ctype.h> |
e9eee03e | 26 | #include <linux/sched.h> |
0d7482e3 | 27 | #include <linux/sysfs.h> |
e9eee03e | 28 | #include <linux/types.h> |
5a0e3ad6 | 29 | #include <linux/slab.h> |
e9eee03e IM |
30 | #include <linux/init.h> |
31 | #include <linux/kmod.h> | |
32 | #include <linux/poll.h> | |
3c079792 | 33 | #include <linux/nmi.h> |
e9eee03e | 34 | #include <linux/cpu.h> |
14a02530 | 35 | #include <linux/smp.h> |
e9eee03e | 36 | #include <linux/fs.h> |
9b1beaf2 | 37 | #include <linux/mm.h> |
5be9ed25 | 38 | #include <linux/debugfs.h> |
696e409d | 39 | #include <linux/edac_mce.h> |
e9eee03e | 40 | |
d88203d1 | 41 | #include <asm/processor.h> |
ccc3c319 AK |
42 | #include <asm/hw_irq.h> |
43 | #include <asm/apic.h> | |
e02e68d3 | 44 | #include <asm/idle.h> |
ccc3c319 | 45 | #include <asm/ipi.h> |
e9eee03e IM |
46 | #include <asm/mce.h> |
47 | #include <asm/msr.h> | |
1da177e4 | 48 | |
bd19a5e6 | 49 | #include "mce-internal.h" |
711c2e48 | 50 | |
2aa2b50d IM |
51 | static DEFINE_MUTEX(mce_read_mutex); |
52 | ||
f56e8a07 PM |
53 | #define rcu_dereference_check_mce(p) \ |
54 | rcu_dereference_check((p), \ | |
55 | rcu_read_lock_sched_held() || \ | |
56 | lockdep_is_held(&mce_read_mutex)) | |
57 | ||
8968f9d3 HS |
58 | #define CREATE_TRACE_POINTS |
59 | #include <trace/events/mce.h> | |
60 | ||
4e5b3e69 | 61 | int mce_disabled __read_mostly; |
04b2b1a4 | 62 | |
e9eee03e | 63 | #define MISC_MCELOG_MINOR 227 |
0d7482e3 | 64 | |
3c079792 AK |
65 | #define SPINUNIT 100 /* 100ns */ |
66 | ||
553f265f AK |
67 | atomic_t mce_entry; |
68 | ||
01ca79f1 AK |
69 | DEFINE_PER_CPU(unsigned, mce_exception_count); |
70 | ||
bd78432c TH |
71 | /* |
72 | * Tolerant levels: | |
73 | * 0: always panic on uncorrected errors, log corrected errors | |
74 | * 1: panic or SIGBUS on uncorrected errors, log corrected errors | |
75 | * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors | |
76 | * 3: never panic or SIGBUS, log all errors (for testing only) | |
77 | */ | |
4e5b3e69 HS |
78 | static int tolerant __read_mostly = 1; |
79 | static int banks __read_mostly; | |
4e5b3e69 HS |
80 | static int rip_msr __read_mostly; |
81 | static int mce_bootlog __read_mostly = -1; | |
82 | static int monarch_timeout __read_mostly = -1; | |
83 | static int mce_panic_timeout __read_mostly; | |
84 | static int mce_dont_log_ce __read_mostly; | |
85 | int mce_cmci_disabled __read_mostly; | |
86 | int mce_ignore_ce __read_mostly; | |
87 | int mce_ser __read_mostly; | |
a98f0dd3 | 88 | |
cebe1820 AK |
89 | struct mce_bank *mce_banks __read_mostly; |
90 | ||
1020bcbc HS |
91 | /* User mode helper program triggered by machine check event */ |
92 | static unsigned long mce_need_notify; | |
93 | static char mce_helper[128]; | |
94 | static char *mce_helper_argv[2] = { mce_helper, NULL }; | |
1da177e4 | 95 | |
e02e68d3 | 96 | static DECLARE_WAIT_QUEUE_HEAD(mce_wait); |
3c079792 AK |
97 | static DEFINE_PER_CPU(struct mce, mces_seen); |
98 | static int cpu_missing; | |
99 | ||
fb253195 BP |
100 | /* |
101 | * CPU/chipset specific EDAC code can register a notifier call here to print | |
102 | * MCE errors in a human-readable form. | |
103 | */ | |
104 | ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain); | |
105 | EXPORT_SYMBOL_GPL(x86_mce_decoder_chain); | |
106 | ||
107 | static int default_decode_mce(struct notifier_block *nb, unsigned long val, | |
108 | void *data) | |
f436f8bb IM |
109 | { |
110 | pr_emerg("No human readable MCE decoding support on this CPU type.\n"); | |
111 | pr_emerg("Run the message through 'mcelog --ascii' to decode.\n"); | |
fb253195 BP |
112 | |
113 | return NOTIFY_STOP; | |
f436f8bb IM |
114 | } |
115 | ||
fb253195 BP |
116 | static struct notifier_block mce_dec_nb = { |
117 | .notifier_call = default_decode_mce, | |
118 | .priority = -1, | |
119 | }; | |
e02e68d3 | 120 | |
ee031c31 AK |
121 | /* MCA banks polled by the period polling timer for corrected events */ |
122 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { | |
123 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL | |
124 | }; | |
125 | ||
9b1beaf2 AK |
126 | static DEFINE_PER_CPU(struct work_struct, mce_work); |
127 | ||
b5f2fa4e AK |
128 | /* Do initial initialization of a struct mce */ |
129 | void mce_setup(struct mce *m) | |
130 | { | |
131 | memset(m, 0, sizeof(struct mce)); | |
d620c67f | 132 | m->cpu = m->extcpu = smp_processor_id(); |
b5f2fa4e | 133 | rdtscll(m->tsc); |
8ee08347 AK |
134 | /* We hope get_seconds stays lockless */ |
135 | m->time = get_seconds(); | |
136 | m->cpuvendor = boot_cpu_data.x86_vendor; | |
137 | m->cpuid = cpuid_eax(1); | |
138 | #ifdef CONFIG_SMP | |
139 | m->socketid = cpu_data(m->extcpu).phys_proc_id; | |
140 | #endif | |
141 | m->apicid = cpu_data(m->extcpu).initial_apicid; | |
142 | rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap); | |
b5f2fa4e AK |
143 | } |
144 | ||
ea149b36 AK |
145 | DEFINE_PER_CPU(struct mce, injectm); |
146 | EXPORT_PER_CPU_SYMBOL_GPL(injectm); | |
147 | ||
1da177e4 LT |
148 | /* |
149 | * Lockless MCE logging infrastructure. | |
150 | * This avoids deadlocks on printk locks without having to break locks. Also | |
151 | * separate MCEs from kernel messages to avoid bogus bug reports. | |
152 | */ | |
153 | ||
231fd906 | 154 | static struct mce_log mcelog = { |
f6fb0ac0 AK |
155 | .signature = MCE_LOG_SIGNATURE, |
156 | .len = MCE_LOG_LEN, | |
157 | .recordlen = sizeof(struct mce), | |
d88203d1 | 158 | }; |
1da177e4 LT |
159 | |
160 | void mce_log(struct mce *mce) | |
161 | { | |
162 | unsigned next, entry; | |
e9eee03e | 163 | |
8968f9d3 HS |
164 | /* Emit the trace record: */ |
165 | trace_mce_record(mce); | |
166 | ||
1da177e4 | 167 | mce->finished = 0; |
7644143c | 168 | wmb(); |
1da177e4 | 169 | for (;;) { |
f56e8a07 | 170 | entry = rcu_dereference_check_mce(mcelog.next); |
673242c1 | 171 | for (;;) { |
696e409d MCC |
172 | /* |
173 | * If edac_mce is enabled, it will check the error type | |
174 | * and will process it, if it is a known error. | |
175 | * Otherwise, the error will be sent through mcelog | |
176 | * interface | |
177 | */ | |
178 | if (edac_mce_parse(mce)) | |
179 | return; | |
180 | ||
e9eee03e IM |
181 | /* |
182 | * When the buffer fills up discard new entries. | |
183 | * Assume that the earlier errors are the more | |
184 | * interesting ones: | |
185 | */ | |
673242c1 | 186 | if (entry >= MCE_LOG_LEN) { |
14a02530 HS |
187 | set_bit(MCE_OVERFLOW, |
188 | (unsigned long *)&mcelog.flags); | |
673242c1 AK |
189 | return; |
190 | } | |
e9eee03e | 191 | /* Old left over entry. Skip: */ |
673242c1 AK |
192 | if (mcelog.entry[entry].finished) { |
193 | entry++; | |
194 | continue; | |
195 | } | |
7644143c | 196 | break; |
1da177e4 | 197 | } |
1da177e4 LT |
198 | smp_rmb(); |
199 | next = entry + 1; | |
200 | if (cmpxchg(&mcelog.next, entry, next) == entry) | |
201 | break; | |
202 | } | |
203 | memcpy(mcelog.entry + entry, mce, sizeof(struct mce)); | |
7644143c | 204 | wmb(); |
1da177e4 | 205 | mcelog.entry[entry].finished = 1; |
7644143c | 206 | wmb(); |
1da177e4 | 207 | |
a0189c70 | 208 | mce->finished = 1; |
1020bcbc | 209 | set_bit(0, &mce_need_notify); |
1da177e4 LT |
210 | } |
211 | ||
77e26cca | 212 | static void print_mce(struct mce *m) |
1da177e4 | 213 | { |
f436f8bb | 214 | pr_emerg("CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n", |
d620c67f | 215 | m->extcpu, m->mcgstatus, m->bank, m->status); |
f436f8bb | 216 | |
65ea5b03 | 217 | if (m->ip) { |
f436f8bb IM |
218 | pr_emerg("RIP%s %02x:<%016Lx> ", |
219 | !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", | |
220 | m->cs, m->ip); | |
221 | ||
1da177e4 | 222 | if (m->cs == __KERNEL_CS) |
65ea5b03 | 223 | print_symbol("{%s}", m->ip); |
f436f8bb | 224 | pr_cont("\n"); |
1da177e4 | 225 | } |
f436f8bb IM |
226 | |
227 | pr_emerg("TSC %llx ", m->tsc); | |
1da177e4 | 228 | if (m->addr) |
f436f8bb | 229 | pr_cont("ADDR %llx ", m->addr); |
1da177e4 | 230 | if (m->misc) |
f436f8bb | 231 | pr_cont("MISC %llx ", m->misc); |
549d042d | 232 | |
f436f8bb IM |
233 | pr_cont("\n"); |
234 | pr_emerg("PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n", | |
235 | m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid); | |
236 | ||
237 | /* | |
238 | * Print out human-readable details about the MCE error, | |
fb253195 | 239 | * (if the CPU has an implementation for that) |
f436f8bb | 240 | */ |
fb253195 | 241 | atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m); |
86503560 AK |
242 | } |
243 | ||
77e26cca HS |
244 | static void print_mce_head(void) |
245 | { | |
f436f8bb | 246 | pr_emerg("\nHARDWARE ERROR\n"); |
77e26cca HS |
247 | } |
248 | ||
86503560 AK |
249 | static void print_mce_tail(void) |
250 | { | |
f436f8bb | 251 | pr_emerg("This is not a software problem!\n"); |
1da177e4 LT |
252 | } |
253 | ||
f94b61c2 AK |
254 | #define PANIC_TIMEOUT 5 /* 5 seconds */ |
255 | ||
256 | static atomic_t mce_paniced; | |
257 | ||
bf783f9f HY |
258 | static int fake_panic; |
259 | static atomic_t mce_fake_paniced; | |
260 | ||
f94b61c2 AK |
261 | /* Panic in progress. Enable interrupts and wait for final IPI */ |
262 | static void wait_for_panic(void) | |
263 | { | |
264 | long timeout = PANIC_TIMEOUT*USEC_PER_SEC; | |
f436f8bb | 265 | |
f94b61c2 AK |
266 | preempt_disable(); |
267 | local_irq_enable(); | |
268 | while (timeout-- > 0) | |
269 | udelay(1); | |
29b0f591 AK |
270 | if (panic_timeout == 0) |
271 | panic_timeout = mce_panic_timeout; | |
f94b61c2 AK |
272 | panic("Panicing machine check CPU died"); |
273 | } | |
274 | ||
bd19a5e6 | 275 | static void mce_panic(char *msg, struct mce *final, char *exp) |
d88203d1 | 276 | { |
482908b4 | 277 | int i, apei_err = 0; |
e02e68d3 | 278 | |
bf783f9f HY |
279 | if (!fake_panic) { |
280 | /* | |
281 | * Make sure only one CPU runs in machine check panic | |
282 | */ | |
283 | if (atomic_inc_return(&mce_paniced) > 1) | |
284 | wait_for_panic(); | |
285 | barrier(); | |
f94b61c2 | 286 | |
bf783f9f HY |
287 | bust_spinlocks(1); |
288 | console_verbose(); | |
289 | } else { | |
290 | /* Don't log too much for fake panic */ | |
291 | if (atomic_inc_return(&mce_fake_paniced) > 1) | |
292 | return; | |
293 | } | |
77e26cca | 294 | print_mce_head(); |
a0189c70 | 295 | /* First print corrected ones that are still unlogged */ |
1da177e4 | 296 | for (i = 0; i < MCE_LOG_LEN; i++) { |
a0189c70 | 297 | struct mce *m = &mcelog.entry[i]; |
77e26cca HS |
298 | if (!(m->status & MCI_STATUS_VAL)) |
299 | continue; | |
482908b4 | 300 | if (!(m->status & MCI_STATUS_UC)) { |
77e26cca | 301 | print_mce(m); |
482908b4 HY |
302 | if (!apei_err) |
303 | apei_err = apei_write_mce(m); | |
304 | } | |
a0189c70 AK |
305 | } |
306 | /* Now print uncorrected but with the final one last */ | |
307 | for (i = 0; i < MCE_LOG_LEN; i++) { | |
308 | struct mce *m = &mcelog.entry[i]; | |
309 | if (!(m->status & MCI_STATUS_VAL)) | |
1da177e4 | 310 | continue; |
77e26cca HS |
311 | if (!(m->status & MCI_STATUS_UC)) |
312 | continue; | |
482908b4 | 313 | if (!final || memcmp(m, final, sizeof(struct mce))) { |
77e26cca | 314 | print_mce(m); |
482908b4 HY |
315 | if (!apei_err) |
316 | apei_err = apei_write_mce(m); | |
317 | } | |
1da177e4 | 318 | } |
482908b4 | 319 | if (final) { |
77e26cca | 320 | print_mce(final); |
482908b4 HY |
321 | if (!apei_err) |
322 | apei_err = apei_write_mce(final); | |
323 | } | |
3c079792 AK |
324 | if (cpu_missing) |
325 | printk(KERN_EMERG "Some CPUs didn't answer in synchronization\n"); | |
86503560 | 326 | print_mce_tail(); |
bd19a5e6 AK |
327 | if (exp) |
328 | printk(KERN_EMERG "Machine check: %s\n", exp); | |
bf783f9f HY |
329 | if (!fake_panic) { |
330 | if (panic_timeout == 0) | |
331 | panic_timeout = mce_panic_timeout; | |
332 | panic(msg); | |
333 | } else | |
334 | printk(KERN_EMERG "Fake kernel panic: %s\n", msg); | |
d88203d1 | 335 | } |
1da177e4 | 336 | |
ea149b36 AK |
337 | /* Support code for software error injection */ |
338 | ||
339 | static int msr_to_offset(u32 msr) | |
340 | { | |
341 | unsigned bank = __get_cpu_var(injectm.bank); | |
f436f8bb | 342 | |
ea149b36 AK |
343 | if (msr == rip_msr) |
344 | return offsetof(struct mce, ip); | |
a2d32bcb | 345 | if (msr == MSR_IA32_MCx_STATUS(bank)) |
ea149b36 | 346 | return offsetof(struct mce, status); |
a2d32bcb | 347 | if (msr == MSR_IA32_MCx_ADDR(bank)) |
ea149b36 | 348 | return offsetof(struct mce, addr); |
a2d32bcb | 349 | if (msr == MSR_IA32_MCx_MISC(bank)) |
ea149b36 AK |
350 | return offsetof(struct mce, misc); |
351 | if (msr == MSR_IA32_MCG_STATUS) | |
352 | return offsetof(struct mce, mcgstatus); | |
353 | return -1; | |
354 | } | |
355 | ||
5f8c1a54 AK |
356 | /* MSR access wrappers used for error injection */ |
357 | static u64 mce_rdmsrl(u32 msr) | |
358 | { | |
359 | u64 v; | |
11868a2d | 360 | |
ea149b36 AK |
361 | if (__get_cpu_var(injectm).finished) { |
362 | int offset = msr_to_offset(msr); | |
11868a2d | 363 | |
ea149b36 AK |
364 | if (offset < 0) |
365 | return 0; | |
366 | return *(u64 *)((char *)&__get_cpu_var(injectm) + offset); | |
367 | } | |
11868a2d IM |
368 | |
369 | if (rdmsrl_safe(msr, &v)) { | |
370 | WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr); | |
371 | /* | |
372 | * Return zero in case the access faulted. This should | |
373 | * not happen normally but can happen if the CPU does | |
374 | * something weird, or if the code is buggy. | |
375 | */ | |
376 | v = 0; | |
377 | } | |
378 | ||
5f8c1a54 AK |
379 | return v; |
380 | } | |
381 | ||
382 | static void mce_wrmsrl(u32 msr, u64 v) | |
383 | { | |
ea149b36 AK |
384 | if (__get_cpu_var(injectm).finished) { |
385 | int offset = msr_to_offset(msr); | |
11868a2d | 386 | |
ea149b36 AK |
387 | if (offset >= 0) |
388 | *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v; | |
389 | return; | |
390 | } | |
5f8c1a54 AK |
391 | wrmsrl(msr, v); |
392 | } | |
393 | ||
9b1beaf2 AK |
394 | /* |
395 | * Simple lockless ring to communicate PFNs from the exception handler with the | |
396 | * process context work function. This is vastly simplified because there's | |
397 | * only a single reader and a single writer. | |
398 | */ | |
399 | #define MCE_RING_SIZE 16 /* we use one entry less */ | |
400 | ||
401 | struct mce_ring { | |
402 | unsigned short start; | |
403 | unsigned short end; | |
404 | unsigned long ring[MCE_RING_SIZE]; | |
405 | }; | |
406 | static DEFINE_PER_CPU(struct mce_ring, mce_ring); | |
407 | ||
408 | /* Runs with CPU affinity in workqueue */ | |
409 | static int mce_ring_empty(void) | |
410 | { | |
411 | struct mce_ring *r = &__get_cpu_var(mce_ring); | |
412 | ||
413 | return r->start == r->end; | |
414 | } | |
415 | ||
416 | static int mce_ring_get(unsigned long *pfn) | |
417 | { | |
418 | struct mce_ring *r; | |
419 | int ret = 0; | |
420 | ||
421 | *pfn = 0; | |
422 | get_cpu(); | |
423 | r = &__get_cpu_var(mce_ring); | |
424 | if (r->start == r->end) | |
425 | goto out; | |
426 | *pfn = r->ring[r->start]; | |
427 | r->start = (r->start + 1) % MCE_RING_SIZE; | |
428 | ret = 1; | |
429 | out: | |
430 | put_cpu(); | |
431 | return ret; | |
432 | } | |
433 | ||
434 | /* Always runs in MCE context with preempt off */ | |
435 | static int mce_ring_add(unsigned long pfn) | |
436 | { | |
437 | struct mce_ring *r = &__get_cpu_var(mce_ring); | |
438 | unsigned next; | |
439 | ||
440 | next = (r->end + 1) % MCE_RING_SIZE; | |
441 | if (next == r->start) | |
442 | return -1; | |
443 | r->ring[r->end] = pfn; | |
444 | wmb(); | |
445 | r->end = next; | |
446 | return 0; | |
447 | } | |
448 | ||
88ccbedd | 449 | int mce_available(struct cpuinfo_x86 *c) |
1da177e4 | 450 | { |
04b2b1a4 | 451 | if (mce_disabled) |
5b4408fd | 452 | return 0; |
3d1712c9 | 453 | return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); |
1da177e4 LT |
454 | } |
455 | ||
9b1beaf2 AK |
456 | static void mce_schedule_work(void) |
457 | { | |
458 | if (!mce_ring_empty()) { | |
459 | struct work_struct *work = &__get_cpu_var(mce_work); | |
460 | if (!work_pending(work)) | |
461 | schedule_work(work); | |
462 | } | |
463 | } | |
464 | ||
1b2797dc HY |
465 | /* |
466 | * Get the address of the instruction at the time of the machine check | |
467 | * error. | |
468 | */ | |
94ad8474 AK |
469 | static inline void mce_get_rip(struct mce *m, struct pt_regs *regs) |
470 | { | |
1b2797dc HY |
471 | |
472 | if (regs && (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV))) { | |
65ea5b03 | 473 | m->ip = regs->ip; |
94ad8474 AK |
474 | m->cs = regs->cs; |
475 | } else { | |
65ea5b03 | 476 | m->ip = 0; |
94ad8474 AK |
477 | m->cs = 0; |
478 | } | |
1b2797dc | 479 | if (rip_msr) |
5f8c1a54 | 480 | m->ip = mce_rdmsrl(rip_msr); |
94ad8474 AK |
481 | } |
482 | ||
11868a2d | 483 | #ifdef CONFIG_X86_LOCAL_APIC |
ccc3c319 AK |
484 | /* |
485 | * Called after interrupts have been reenabled again | |
486 | * when a MCE happened during an interrupts off region | |
487 | * in the kernel. | |
488 | */ | |
489 | asmlinkage void smp_mce_self_interrupt(struct pt_regs *regs) | |
490 | { | |
491 | ack_APIC_irq(); | |
492 | exit_idle(); | |
493 | irq_enter(); | |
9ff36ee9 | 494 | mce_notify_irq(); |
9b1beaf2 | 495 | mce_schedule_work(); |
ccc3c319 AK |
496 | irq_exit(); |
497 | } | |
498 | #endif | |
499 | ||
500 | static void mce_report_event(struct pt_regs *regs) | |
501 | { | |
502 | if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) { | |
9ff36ee9 | 503 | mce_notify_irq(); |
9b1beaf2 AK |
504 | /* |
505 | * Triggering the work queue here is just an insurance | |
506 | * policy in case the syscall exit notify handler | |
507 | * doesn't run soon enough or ends up running on the | |
508 | * wrong CPU (can happen when audit sleeps) | |
509 | */ | |
510 | mce_schedule_work(); | |
ccc3c319 AK |
511 | return; |
512 | } | |
513 | ||
514 | #ifdef CONFIG_X86_LOCAL_APIC | |
515 | /* | |
516 | * Without APIC do not notify. The event will be picked | |
517 | * up eventually. | |
518 | */ | |
519 | if (!cpu_has_apic) | |
520 | return; | |
521 | ||
522 | /* | |
523 | * When interrupts are disabled we cannot use | |
524 | * kernel services safely. Trigger an self interrupt | |
525 | * through the APIC to instead do the notification | |
526 | * after interrupts are reenabled again. | |
527 | */ | |
528 | apic->send_IPI_self(MCE_SELF_VECTOR); | |
529 | ||
530 | /* | |
531 | * Wait for idle afterwards again so that we don't leave the | |
532 | * APIC in a non idle state because the normal APIC writes | |
533 | * cannot exclude us. | |
534 | */ | |
535 | apic_wait_icr_idle(); | |
536 | #endif | |
537 | } | |
538 | ||
ca84f696 AK |
539 | DEFINE_PER_CPU(unsigned, mce_poll_count); |
540 | ||
d88203d1 | 541 | /* |
b79109c3 AK |
542 | * Poll for corrected events or events that happened before reset. |
543 | * Those are just logged through /dev/mcelog. | |
544 | * | |
545 | * This is executed in standard interrupt context. | |
ed7290d0 AK |
546 | * |
547 | * Note: spec recommends to panic for fatal unsignalled | |
548 | * errors here. However this would be quite problematic -- | |
549 | * we would need to reimplement the Monarch handling and | |
550 | * it would mess up the exclusion between exception handler | |
551 | * and poll hander -- * so we skip this for now. | |
552 | * These cases should not happen anyways, or only when the CPU | |
553 | * is already totally * confused. In this case it's likely it will | |
554 | * not fully execute the machine check handler either. | |
b79109c3 | 555 | */ |
ee031c31 | 556 | void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) |
b79109c3 AK |
557 | { |
558 | struct mce m; | |
559 | int i; | |
560 | ||
402af0d7 | 561 | percpu_inc(mce_poll_count); |
ca84f696 | 562 | |
b79109c3 AK |
563 | mce_setup(&m); |
564 | ||
5f8c1a54 | 565 | m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); |
b79109c3 | 566 | for (i = 0; i < banks; i++) { |
cebe1820 | 567 | if (!mce_banks[i].ctl || !test_bit(i, *b)) |
b79109c3 AK |
568 | continue; |
569 | ||
570 | m.misc = 0; | |
571 | m.addr = 0; | |
572 | m.bank = i; | |
573 | m.tsc = 0; | |
574 | ||
575 | barrier(); | |
a2d32bcb | 576 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
b79109c3 AK |
577 | if (!(m.status & MCI_STATUS_VAL)) |
578 | continue; | |
579 | ||
580 | /* | |
ed7290d0 AK |
581 | * Uncorrected or signalled events are handled by the exception |
582 | * handler when it is enabled, so don't process those here. | |
b79109c3 AK |
583 | * |
584 | * TBD do the same check for MCI_STATUS_EN here? | |
585 | */ | |
ed7290d0 AK |
586 | if (!(flags & MCP_UC) && |
587 | (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC))) | |
b79109c3 AK |
588 | continue; |
589 | ||
590 | if (m.status & MCI_STATUS_MISCV) | |
a2d32bcb | 591 | m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i)); |
b79109c3 | 592 | if (m.status & MCI_STATUS_ADDRV) |
a2d32bcb | 593 | m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i)); |
b79109c3 AK |
594 | |
595 | if (!(flags & MCP_TIMESTAMP)) | |
596 | m.tsc = 0; | |
597 | /* | |
598 | * Don't get the IP here because it's unlikely to | |
599 | * have anything to do with the actual error location. | |
600 | */ | |
62fdac59 | 601 | if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) { |
5679af4c AK |
602 | mce_log(&m); |
603 | add_taint(TAINT_MACHINE_CHECK); | |
604 | } | |
b79109c3 AK |
605 | |
606 | /* | |
607 | * Clear state for this bank. | |
608 | */ | |
a2d32bcb | 609 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
b79109c3 AK |
610 | } |
611 | ||
612 | /* | |
613 | * Don't clear MCG_STATUS here because it's only defined for | |
614 | * exceptions. | |
615 | */ | |
88921be3 AK |
616 | |
617 | sync_core(); | |
b79109c3 | 618 | } |
ea149b36 | 619 | EXPORT_SYMBOL_GPL(machine_check_poll); |
b79109c3 | 620 | |
bd19a5e6 AK |
621 | /* |
622 | * Do a quick check if any of the events requires a panic. | |
623 | * This decides if we keep the events around or clear them. | |
624 | */ | |
625 | static int mce_no_way_out(struct mce *m, char **msg) | |
626 | { | |
627 | int i; | |
628 | ||
629 | for (i = 0; i < banks; i++) { | |
a2d32bcb | 630 | m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
bd19a5e6 AK |
631 | if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY) |
632 | return 1; | |
633 | } | |
634 | return 0; | |
635 | } | |
636 | ||
3c079792 AK |
637 | /* |
638 | * Variable to establish order between CPUs while scanning. | |
639 | * Each CPU spins initially until executing is equal its number. | |
640 | */ | |
641 | static atomic_t mce_executing; | |
642 | ||
643 | /* | |
644 | * Defines order of CPUs on entry. First CPU becomes Monarch. | |
645 | */ | |
646 | static atomic_t mce_callin; | |
647 | ||
648 | /* | |
649 | * Check if a timeout waiting for other CPUs happened. | |
650 | */ | |
651 | static int mce_timed_out(u64 *t) | |
652 | { | |
653 | /* | |
654 | * The others already did panic for some reason. | |
655 | * Bail out like in a timeout. | |
656 | * rmb() to tell the compiler that system_state | |
657 | * might have been modified by someone else. | |
658 | */ | |
659 | rmb(); | |
660 | if (atomic_read(&mce_paniced)) | |
661 | wait_for_panic(); | |
662 | if (!monarch_timeout) | |
663 | goto out; | |
664 | if ((s64)*t < SPINUNIT) { | |
665 | /* CHECKME: Make panic default for 1 too? */ | |
666 | if (tolerant < 1) | |
667 | mce_panic("Timeout synchronizing machine check over CPUs", | |
668 | NULL, NULL); | |
669 | cpu_missing = 1; | |
670 | return 1; | |
671 | } | |
672 | *t -= SPINUNIT; | |
673 | out: | |
674 | touch_nmi_watchdog(); | |
675 | return 0; | |
676 | } | |
677 | ||
678 | /* | |
679 | * The Monarch's reign. The Monarch is the CPU who entered | |
680 | * the machine check handler first. It waits for the others to | |
681 | * raise the exception too and then grades them. When any | |
682 | * error is fatal panic. Only then let the others continue. | |
683 | * | |
684 | * The other CPUs entering the MCE handler will be controlled by the | |
685 | * Monarch. They are called Subjects. | |
686 | * | |
687 | * This way we prevent any potential data corruption in a unrecoverable case | |
688 | * and also makes sure always all CPU's errors are examined. | |
689 | * | |
680b6cfd | 690 | * Also this detects the case of a machine check event coming from outer |
3c079792 AK |
691 | * space (not detected by any CPUs) In this case some external agent wants |
692 | * us to shut down, so panic too. | |
693 | * | |
694 | * The other CPUs might still decide to panic if the handler happens | |
695 | * in a unrecoverable place, but in this case the system is in a semi-stable | |
696 | * state and won't corrupt anything by itself. It's ok to let the others | |
697 | * continue for a bit first. | |
698 | * | |
699 | * All the spin loops have timeouts; when a timeout happens a CPU | |
700 | * typically elects itself to be Monarch. | |
701 | */ | |
702 | static void mce_reign(void) | |
703 | { | |
704 | int cpu; | |
705 | struct mce *m = NULL; | |
706 | int global_worst = 0; | |
707 | char *msg = NULL; | |
708 | char *nmsg = NULL; | |
709 | ||
710 | /* | |
711 | * This CPU is the Monarch and the other CPUs have run | |
712 | * through their handlers. | |
713 | * Grade the severity of the errors of all the CPUs. | |
714 | */ | |
715 | for_each_possible_cpu(cpu) { | |
716 | int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant, | |
717 | &nmsg); | |
718 | if (severity > global_worst) { | |
719 | msg = nmsg; | |
720 | global_worst = severity; | |
721 | m = &per_cpu(mces_seen, cpu); | |
722 | } | |
723 | } | |
724 | ||
725 | /* | |
726 | * Cannot recover? Panic here then. | |
727 | * This dumps all the mces in the log buffer and stops the | |
728 | * other CPUs. | |
729 | */ | |
730 | if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3) | |
ac960375 | 731 | mce_panic("Fatal Machine check", m, msg); |
3c079792 AK |
732 | |
733 | /* | |
734 | * For UC somewhere we let the CPU who detects it handle it. | |
735 | * Also must let continue the others, otherwise the handling | |
736 | * CPU could deadlock on a lock. | |
737 | */ | |
738 | ||
739 | /* | |
740 | * No machine check event found. Must be some external | |
741 | * source or one CPU is hung. Panic. | |
742 | */ | |
680b6cfd | 743 | if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3) |
3c079792 AK |
744 | mce_panic("Machine check from unknown source", NULL, NULL); |
745 | ||
746 | /* | |
747 | * Now clear all the mces_seen so that they don't reappear on | |
748 | * the next mce. | |
749 | */ | |
750 | for_each_possible_cpu(cpu) | |
751 | memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce)); | |
752 | } | |
753 | ||
754 | static atomic_t global_nwo; | |
755 | ||
756 | /* | |
757 | * Start of Monarch synchronization. This waits until all CPUs have | |
758 | * entered the exception handler and then determines if any of them | |
759 | * saw a fatal event that requires panic. Then it executes them | |
760 | * in the entry order. | |
761 | * TBD double check parallel CPU hotunplug | |
762 | */ | |
7fb06fc9 | 763 | static int mce_start(int *no_way_out) |
3c079792 | 764 | { |
7fb06fc9 | 765 | int order; |
3c079792 AK |
766 | int cpus = num_online_cpus(); |
767 | u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC; | |
768 | ||
7fb06fc9 HS |
769 | if (!timeout) |
770 | return -1; | |
3c079792 | 771 | |
7fb06fc9 | 772 | atomic_add(*no_way_out, &global_nwo); |
184e1fdf HY |
773 | /* |
774 | * global_nwo should be updated before mce_callin | |
775 | */ | |
776 | smp_wmb(); | |
a95436e4 | 777 | order = atomic_inc_return(&mce_callin); |
3c079792 AK |
778 | |
779 | /* | |
780 | * Wait for everyone. | |
781 | */ | |
782 | while (atomic_read(&mce_callin) != cpus) { | |
783 | if (mce_timed_out(&timeout)) { | |
784 | atomic_set(&global_nwo, 0); | |
7fb06fc9 | 785 | return -1; |
3c079792 AK |
786 | } |
787 | ndelay(SPINUNIT); | |
788 | } | |
789 | ||
184e1fdf HY |
790 | /* |
791 | * mce_callin should be read before global_nwo | |
792 | */ | |
793 | smp_rmb(); | |
3c079792 | 794 | |
7fb06fc9 HS |
795 | if (order == 1) { |
796 | /* | |
797 | * Monarch: Starts executing now, the others wait. | |
798 | */ | |
3c079792 | 799 | atomic_set(&mce_executing, 1); |
7fb06fc9 HS |
800 | } else { |
801 | /* | |
802 | * Subject: Now start the scanning loop one by one in | |
803 | * the original callin order. | |
804 | * This way when there are any shared banks it will be | |
805 | * only seen by one CPU before cleared, avoiding duplicates. | |
806 | */ | |
807 | while (atomic_read(&mce_executing) < order) { | |
808 | if (mce_timed_out(&timeout)) { | |
809 | atomic_set(&global_nwo, 0); | |
810 | return -1; | |
811 | } | |
812 | ndelay(SPINUNIT); | |
813 | } | |
3c079792 AK |
814 | } |
815 | ||
816 | /* | |
7fb06fc9 | 817 | * Cache the global no_way_out state. |
3c079792 | 818 | */ |
7fb06fc9 HS |
819 | *no_way_out = atomic_read(&global_nwo); |
820 | ||
821 | return order; | |
3c079792 AK |
822 | } |
823 | ||
824 | /* | |
825 | * Synchronize between CPUs after main scanning loop. | |
826 | * This invokes the bulk of the Monarch processing. | |
827 | */ | |
828 | static int mce_end(int order) | |
829 | { | |
830 | int ret = -1; | |
831 | u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC; | |
832 | ||
833 | if (!timeout) | |
834 | goto reset; | |
835 | if (order < 0) | |
836 | goto reset; | |
837 | ||
838 | /* | |
839 | * Allow others to run. | |
840 | */ | |
841 | atomic_inc(&mce_executing); | |
842 | ||
843 | if (order == 1) { | |
844 | /* CHECKME: Can this race with a parallel hotplug? */ | |
845 | int cpus = num_online_cpus(); | |
846 | ||
847 | /* | |
848 | * Monarch: Wait for everyone to go through their scanning | |
849 | * loops. | |
850 | */ | |
851 | while (atomic_read(&mce_executing) <= cpus) { | |
852 | if (mce_timed_out(&timeout)) | |
853 | goto reset; | |
854 | ndelay(SPINUNIT); | |
855 | } | |
856 | ||
857 | mce_reign(); | |
858 | barrier(); | |
859 | ret = 0; | |
860 | } else { | |
861 | /* | |
862 | * Subject: Wait for Monarch to finish. | |
863 | */ | |
864 | while (atomic_read(&mce_executing) != 0) { | |
865 | if (mce_timed_out(&timeout)) | |
866 | goto reset; | |
867 | ndelay(SPINUNIT); | |
868 | } | |
869 | ||
870 | /* | |
871 | * Don't reset anything. That's done by the Monarch. | |
872 | */ | |
873 | return 0; | |
874 | } | |
875 | ||
876 | /* | |
877 | * Reset all global state. | |
878 | */ | |
879 | reset: | |
880 | atomic_set(&global_nwo, 0); | |
881 | atomic_set(&mce_callin, 0); | |
882 | barrier(); | |
883 | ||
884 | /* | |
885 | * Let others run again. | |
886 | */ | |
887 | atomic_set(&mce_executing, 0); | |
888 | return ret; | |
889 | } | |
890 | ||
9b1beaf2 AK |
891 | /* |
892 | * Check if the address reported by the CPU is in a format we can parse. | |
893 | * It would be possible to add code for most other cases, but all would | |
894 | * be somewhat complicated (e.g. segment offset would require an instruction | |
895 | * parser). So only support physical addresses upto page granuality for now. | |
896 | */ | |
897 | static int mce_usable_address(struct mce *m) | |
898 | { | |
899 | if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV)) | |
900 | return 0; | |
901 | if ((m->misc & 0x3f) > PAGE_SHIFT) | |
902 | return 0; | |
903 | if (((m->misc >> 6) & 7) != MCM_ADDR_PHYS) | |
904 | return 0; | |
905 | return 1; | |
906 | } | |
907 | ||
3c079792 AK |
908 | static void mce_clear_state(unsigned long *toclear) |
909 | { | |
910 | int i; | |
911 | ||
912 | for (i = 0; i < banks; i++) { | |
913 | if (test_bit(i, toclear)) | |
a2d32bcb | 914 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
3c079792 AK |
915 | } |
916 | } | |
917 | ||
b79109c3 AK |
918 | /* |
919 | * The actual machine check handler. This only handles real | |
920 | * exceptions when something got corrupted coming in through int 18. | |
921 | * | |
922 | * This is executed in NMI context not subject to normal locking rules. This | |
923 | * implies that most kernel services cannot be safely used. Don't even | |
924 | * think about putting a printk in there! | |
3c079792 AK |
925 | * |
926 | * On Intel systems this is entered on all CPUs in parallel through | |
927 | * MCE broadcast. However some CPUs might be broken beyond repair, | |
928 | * so be always careful when synchronizing with others. | |
1da177e4 | 929 | */ |
e9eee03e | 930 | void do_machine_check(struct pt_regs *regs, long error_code) |
1da177e4 | 931 | { |
3c079792 | 932 | struct mce m, *final; |
1da177e4 | 933 | int i; |
3c079792 AK |
934 | int worst = 0; |
935 | int severity; | |
936 | /* | |
937 | * Establish sequential order between the CPUs entering the machine | |
938 | * check handler. | |
939 | */ | |
7fb06fc9 | 940 | int order; |
bd78432c TH |
941 | /* |
942 | * If no_way_out gets set, there is no safe way to recover from this | |
943 | * MCE. If tolerant is cranked up, we'll try anyway. | |
944 | */ | |
945 | int no_way_out = 0; | |
946 | /* | |
947 | * If kill_it gets set, there might be a way to recover from this | |
948 | * error. | |
949 | */ | |
950 | int kill_it = 0; | |
b79109c3 | 951 | DECLARE_BITMAP(toclear, MAX_NR_BANKS); |
bd19a5e6 | 952 | char *msg = "Unknown"; |
1da177e4 | 953 | |
553f265f AK |
954 | atomic_inc(&mce_entry); |
955 | ||
402af0d7 | 956 | percpu_inc(mce_exception_count); |
01ca79f1 | 957 | |
b79109c3 | 958 | if (notify_die(DIE_NMI, "machine check", regs, error_code, |
22f5991c | 959 | 18, SIGKILL) == NOTIFY_STOP) |
32561696 | 960 | goto out; |
b79109c3 | 961 | if (!banks) |
32561696 | 962 | goto out; |
1da177e4 | 963 | |
b5f2fa4e AK |
964 | mce_setup(&m); |
965 | ||
5f8c1a54 | 966 | m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); |
3c079792 AK |
967 | final = &__get_cpu_var(mces_seen); |
968 | *final = m; | |
969 | ||
680b6cfd HS |
970 | no_way_out = mce_no_way_out(&m, &msg); |
971 | ||
1da177e4 LT |
972 | barrier(); |
973 | ||
ed7290d0 AK |
974 | /* |
975 | * When no restart IP must always kill or panic. | |
976 | */ | |
977 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) | |
978 | kill_it = 1; | |
979 | ||
3c079792 AK |
980 | /* |
981 | * Go through all the banks in exclusion of the other CPUs. | |
982 | * This way we don't report duplicated events on shared banks | |
983 | * because the first one to see it will clear it. | |
984 | */ | |
7fb06fc9 | 985 | order = mce_start(&no_way_out); |
1da177e4 | 986 | for (i = 0; i < banks; i++) { |
b79109c3 | 987 | __clear_bit(i, toclear); |
cebe1820 | 988 | if (!mce_banks[i].ctl) |
1da177e4 | 989 | continue; |
d88203d1 TG |
990 | |
991 | m.misc = 0; | |
1da177e4 LT |
992 | m.addr = 0; |
993 | m.bank = i; | |
1da177e4 | 994 | |
a2d32bcb | 995 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
1da177e4 LT |
996 | if ((m.status & MCI_STATUS_VAL) == 0) |
997 | continue; | |
998 | ||
b79109c3 | 999 | /* |
ed7290d0 AK |
1000 | * Non uncorrected or non signaled errors are handled by |
1001 | * machine_check_poll. Leave them alone, unless this panics. | |
b79109c3 | 1002 | */ |
ed7290d0 AK |
1003 | if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) && |
1004 | !no_way_out) | |
b79109c3 AK |
1005 | continue; |
1006 | ||
1007 | /* | |
1008 | * Set taint even when machine check was not enabled. | |
1009 | */ | |
1010 | add_taint(TAINT_MACHINE_CHECK); | |
1011 | ||
ed7290d0 | 1012 | severity = mce_severity(&m, tolerant, NULL); |
b79109c3 | 1013 | |
ed7290d0 AK |
1014 | /* |
1015 | * When machine check was for corrected handler don't touch, | |
1016 | * unless we're panicing. | |
1017 | */ | |
1018 | if (severity == MCE_KEEP_SEVERITY && !no_way_out) | |
1019 | continue; | |
1020 | __set_bit(i, toclear); | |
1021 | if (severity == MCE_NO_SEVERITY) { | |
b79109c3 AK |
1022 | /* |
1023 | * Machine check event was not enabled. Clear, but | |
1024 | * ignore. | |
1025 | */ | |
1026 | continue; | |
1da177e4 LT |
1027 | } |
1028 | ||
ed7290d0 AK |
1029 | /* |
1030 | * Kill on action required. | |
1031 | */ | |
1032 | if (severity == MCE_AR_SEVERITY) | |
1033 | kill_it = 1; | |
1034 | ||
1da177e4 | 1035 | if (m.status & MCI_STATUS_MISCV) |
a2d32bcb | 1036 | m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i)); |
1da177e4 | 1037 | if (m.status & MCI_STATUS_ADDRV) |
a2d32bcb | 1038 | m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i)); |
1da177e4 | 1039 | |
9b1beaf2 AK |
1040 | /* |
1041 | * Action optional error. Queue address for later processing. | |
1042 | * When the ring overflows we just ignore the AO error. | |
1043 | * RED-PEN add some logging mechanism when | |
1044 | * usable_address or mce_add_ring fails. | |
1045 | * RED-PEN don't ignore overflow for tolerant == 0 | |
1046 | */ | |
1047 | if (severity == MCE_AO_SEVERITY && mce_usable_address(&m)) | |
1048 | mce_ring_add(m.addr >> PAGE_SHIFT); | |
1049 | ||
94ad8474 | 1050 | mce_get_rip(&m, regs); |
b79109c3 | 1051 | mce_log(&m); |
1da177e4 | 1052 | |
3c079792 AK |
1053 | if (severity > worst) { |
1054 | *final = m; | |
1055 | worst = severity; | |
1da177e4 | 1056 | } |
1da177e4 LT |
1057 | } |
1058 | ||
3c079792 AK |
1059 | if (!no_way_out) |
1060 | mce_clear_state(toclear); | |
1061 | ||
e9eee03e | 1062 | /* |
3c079792 AK |
1063 | * Do most of the synchronization with other CPUs. |
1064 | * When there's any problem use only local no_way_out state. | |
e9eee03e | 1065 | */ |
3c079792 AK |
1066 | if (mce_end(order) < 0) |
1067 | no_way_out = worst >= MCE_PANIC_SEVERITY; | |
bd78432c TH |
1068 | |
1069 | /* | |
1070 | * If we have decided that we just CAN'T continue, and the user | |
e9eee03e | 1071 | * has not set tolerant to an insane level, give up and die. |
3c079792 AK |
1072 | * |
1073 | * This is mainly used in the case when the system doesn't | |
1074 | * support MCE broadcasting or it has been disabled. | |
bd78432c TH |
1075 | */ |
1076 | if (no_way_out && tolerant < 3) | |
ac960375 | 1077 | mce_panic("Fatal machine check on current CPU", final, msg); |
bd78432c TH |
1078 | |
1079 | /* | |
1080 | * If the error seems to be unrecoverable, something should be | |
1081 | * done. Try to kill as little as possible. If we can kill just | |
1082 | * one task, do that. If the user has set the tolerance very | |
1083 | * high, don't try to do anything at all. | |
1084 | */ | |
bd78432c | 1085 | |
ed7290d0 AK |
1086 | if (kill_it && tolerant < 3) |
1087 | force_sig(SIGBUS, current); | |
1da177e4 | 1088 | |
e02e68d3 TH |
1089 | /* notify userspace ASAP */ |
1090 | set_thread_flag(TIF_MCE_NOTIFY); | |
1091 | ||
3c079792 AK |
1092 | if (worst > 0) |
1093 | mce_report_event(regs); | |
5f8c1a54 | 1094 | mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); |
32561696 | 1095 | out: |
553f265f | 1096 | atomic_dec(&mce_entry); |
88921be3 | 1097 | sync_core(); |
1da177e4 | 1098 | } |
ea149b36 | 1099 | EXPORT_SYMBOL_GPL(do_machine_check); |
1da177e4 | 1100 | |
9b1beaf2 AK |
1101 | /* dummy to break dependency. actual code is in mm/memory-failure.c */ |
1102 | void __attribute__((weak)) memory_failure(unsigned long pfn, int vector) | |
1103 | { | |
1104 | printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn); | |
1105 | } | |
1106 | ||
1107 | /* | |
1108 | * Called after mce notification in process context. This code | |
1109 | * is allowed to sleep. Call the high level VM handler to process | |
1110 | * any corrupted pages. | |
1111 | * Assume that the work queue code only calls this one at a time | |
1112 | * per CPU. | |
1113 | * Note we don't disable preemption, so this code might run on the wrong | |
1114 | * CPU. In this case the event is picked up by the scheduled work queue. | |
1115 | * This is merely a fast path to expedite processing in some common | |
1116 | * cases. | |
1117 | */ | |
1118 | void mce_notify_process(void) | |
1119 | { | |
1120 | unsigned long pfn; | |
1121 | mce_notify_irq(); | |
1122 | while (mce_ring_get(&pfn)) | |
1123 | memory_failure(pfn, MCE_VECTOR); | |
1124 | } | |
1125 | ||
1126 | static void mce_process_work(struct work_struct *dummy) | |
1127 | { | |
1128 | mce_notify_process(); | |
1129 | } | |
1130 | ||
15d5f839 DZ |
1131 | #ifdef CONFIG_X86_MCE_INTEL |
1132 | /*** | |
1133 | * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog | |
676b1855 | 1134 | * @cpu: The CPU on which the event occurred. |
15d5f839 DZ |
1135 | * @status: Event status information |
1136 | * | |
1137 | * This function should be called by the thermal interrupt after the | |
1138 | * event has been processed and the decision was made to log the event | |
1139 | * further. | |
1140 | * | |
1141 | * The status parameter will be saved to the 'status' field of 'struct mce' | |
1142 | * and historically has been the register value of the | |
1143 | * MSR_IA32_THERMAL_STATUS (Intel) msr. | |
1144 | */ | |
b5f2fa4e | 1145 | void mce_log_therm_throt_event(__u64 status) |
15d5f839 DZ |
1146 | { |
1147 | struct mce m; | |
1148 | ||
b5f2fa4e | 1149 | mce_setup(&m); |
15d5f839 DZ |
1150 | m.bank = MCE_THERMAL_BANK; |
1151 | m.status = status; | |
15d5f839 DZ |
1152 | mce_log(&m); |
1153 | } | |
1154 | #endif /* CONFIG_X86_MCE_INTEL */ | |
1155 | ||
1da177e4 | 1156 | /* |
8a336b0a TH |
1157 | * Periodic polling timer for "silent" machine check errors. If the |
1158 | * poller finds an MCE, poll 2x faster. When the poller finds no more | |
1159 | * errors, poll 2x slower (up to check_interval seconds). | |
1da177e4 | 1160 | */ |
1da177e4 | 1161 | static int check_interval = 5 * 60; /* 5 minutes */ |
e9eee03e | 1162 | |
245b2e70 | 1163 | static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */ |
52d168e2 | 1164 | static DEFINE_PER_CPU(struct timer_list, mce_timer); |
1da177e4 | 1165 | |
5e09954a | 1166 | static void mce_start_timer(unsigned long data) |
1da177e4 | 1167 | { |
52d168e2 | 1168 | struct timer_list *t = &per_cpu(mce_timer, data); |
6298c512 | 1169 | int *n; |
52d168e2 AK |
1170 | |
1171 | WARN_ON(smp_processor_id() != data); | |
1172 | ||
e9eee03e | 1173 | if (mce_available(¤t_cpu_data)) { |
ee031c31 AK |
1174 | machine_check_poll(MCP_TIMESTAMP, |
1175 | &__get_cpu_var(mce_poll_banks)); | |
e9eee03e | 1176 | } |
1da177e4 LT |
1177 | |
1178 | /* | |
e02e68d3 TH |
1179 | * Alert userspace if needed. If we logged an MCE, reduce the |
1180 | * polling interval, otherwise increase the polling interval. | |
1da177e4 | 1181 | */ |
245b2e70 | 1182 | n = &__get_cpu_var(mce_next_interval); |
9ff36ee9 | 1183 | if (mce_notify_irq()) |
6298c512 | 1184 | *n = max(*n/2, HZ/100); |
14a02530 | 1185 | else |
6298c512 | 1186 | *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ)); |
e02e68d3 | 1187 | |
6298c512 | 1188 | t->expires = jiffies + *n; |
5be6066a | 1189 | add_timer_on(t, smp_processor_id()); |
e02e68d3 TH |
1190 | } |
1191 | ||
9bd98405 AK |
1192 | static void mce_do_trigger(struct work_struct *work) |
1193 | { | |
1020bcbc | 1194 | call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT); |
9bd98405 AK |
1195 | } |
1196 | ||
1197 | static DECLARE_WORK(mce_trigger_work, mce_do_trigger); | |
1198 | ||
e02e68d3 | 1199 | /* |
9bd98405 AK |
1200 | * Notify the user(s) about new machine check events. |
1201 | * Can be called from interrupt context, but not from machine check/NMI | |
1202 | * context. | |
e02e68d3 | 1203 | */ |
9ff36ee9 | 1204 | int mce_notify_irq(void) |
e02e68d3 | 1205 | { |
8457c84d AK |
1206 | /* Not more than two messages every minute */ |
1207 | static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); | |
1208 | ||
e02e68d3 | 1209 | clear_thread_flag(TIF_MCE_NOTIFY); |
e9eee03e | 1210 | |
1020bcbc | 1211 | if (test_and_clear_bit(0, &mce_need_notify)) { |
e02e68d3 | 1212 | wake_up_interruptible(&mce_wait); |
9bd98405 AK |
1213 | |
1214 | /* | |
1215 | * There is no risk of missing notifications because | |
1216 | * work_pending is always cleared before the function is | |
1217 | * executed. | |
1218 | */ | |
1020bcbc | 1219 | if (mce_helper[0] && !work_pending(&mce_trigger_work)) |
9bd98405 | 1220 | schedule_work(&mce_trigger_work); |
e02e68d3 | 1221 | |
8457c84d | 1222 | if (__ratelimit(&ratelimit)) |
8a336b0a | 1223 | printk(KERN_INFO "Machine check events logged\n"); |
e02e68d3 TH |
1224 | |
1225 | return 1; | |
1da177e4 | 1226 | } |
e02e68d3 TH |
1227 | return 0; |
1228 | } | |
9ff36ee9 | 1229 | EXPORT_SYMBOL_GPL(mce_notify_irq); |
8a336b0a | 1230 | |
cffd377e | 1231 | static int __cpuinit __mcheck_cpu_mce_banks_init(void) |
cebe1820 AK |
1232 | { |
1233 | int i; | |
1234 | ||
1235 | mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL); | |
1236 | if (!mce_banks) | |
1237 | return -ENOMEM; | |
1238 | for (i = 0; i < banks; i++) { | |
1239 | struct mce_bank *b = &mce_banks[i]; | |
11868a2d | 1240 | |
cebe1820 AK |
1241 | b->ctl = -1ULL; |
1242 | b->init = 1; | |
1243 | } | |
1244 | return 0; | |
1245 | } | |
1246 | ||
d88203d1 | 1247 | /* |
1da177e4 LT |
1248 | * Initialize Machine Checks for a CPU. |
1249 | */ | |
5e09954a | 1250 | static int __cpuinit __mcheck_cpu_cap_init(void) |
1da177e4 | 1251 | { |
0d7482e3 | 1252 | unsigned b; |
e9eee03e | 1253 | u64 cap; |
1da177e4 LT |
1254 | |
1255 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
01c6680a TG |
1256 | |
1257 | b = cap & MCG_BANKCNT_MASK; | |
93ae5012 RD |
1258 | if (!banks) |
1259 | printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b); | |
b659294b | 1260 | |
0d7482e3 AK |
1261 | if (b > MAX_NR_BANKS) { |
1262 | printk(KERN_WARNING | |
1263 | "MCE: Using only %u machine check banks out of %u\n", | |
1264 | MAX_NR_BANKS, b); | |
1265 | b = MAX_NR_BANKS; | |
1266 | } | |
1267 | ||
1268 | /* Don't support asymmetric configurations today */ | |
1269 | WARN_ON(banks != 0 && b != banks); | |
1270 | banks = b; | |
cebe1820 | 1271 | if (!mce_banks) { |
cffd377e | 1272 | int err = __mcheck_cpu_mce_banks_init(); |
11868a2d | 1273 | |
cebe1820 AK |
1274 | if (err) |
1275 | return err; | |
1da177e4 | 1276 | } |
0d7482e3 | 1277 | |
94ad8474 | 1278 | /* Use accurate RIP reporting if available. */ |
01c6680a | 1279 | if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) |
94ad8474 | 1280 | rip_msr = MSR_IA32_MCG_EIP; |
1da177e4 | 1281 | |
ed7290d0 AK |
1282 | if (cap & MCG_SER_P) |
1283 | mce_ser = 1; | |
1284 | ||
0d7482e3 AK |
1285 | return 0; |
1286 | } | |
1287 | ||
5e09954a | 1288 | static void __mcheck_cpu_init_generic(void) |
0d7482e3 | 1289 | { |
e9eee03e | 1290 | mce_banks_t all_banks; |
0d7482e3 AK |
1291 | u64 cap; |
1292 | int i; | |
1293 | ||
b79109c3 AK |
1294 | /* |
1295 | * Log the machine checks left over from the previous reset. | |
1296 | */ | |
ee031c31 | 1297 | bitmap_fill(all_banks, MAX_NR_BANKS); |
5679af4c | 1298 | machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks); |
1da177e4 LT |
1299 | |
1300 | set_in_cr4(X86_CR4_MCE); | |
1301 | ||
0d7482e3 | 1302 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
1da177e4 LT |
1303 | if (cap & MCG_CTL_P) |
1304 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); | |
1305 | ||
1306 | for (i = 0; i < banks; i++) { | |
cebe1820 | 1307 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1308 | |
cebe1820 | 1309 | if (!b->init) |
06b7a7a5 | 1310 | continue; |
a2d32bcb AK |
1311 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
1312 | wrmsrl(MSR_IA32_MCx_STATUS(i), 0); | |
d88203d1 | 1313 | } |
1da177e4 LT |
1314 | } |
1315 | ||
1316 | /* Add per CPU specific workarounds here */ | |
5e09954a | 1317 | static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) |
d88203d1 | 1318 | { |
e412cd25 IM |
1319 | if (c->x86_vendor == X86_VENDOR_UNKNOWN) { |
1320 | pr_info("MCE: unknown CPU type - not enabling MCE support.\n"); | |
1321 | return -EOPNOTSUPP; | |
1322 | } | |
1323 | ||
1da177e4 | 1324 | /* This should be disabled by the BIOS, but isn't always */ |
911f6a7b | 1325 | if (c->x86_vendor == X86_VENDOR_AMD) { |
e9eee03e IM |
1326 | if (c->x86 == 15 && banks > 4) { |
1327 | /* | |
1328 | * disable GART TBL walk error reporting, which | |
1329 | * trips off incorrectly with the IOMMU & 3ware | |
1330 | * & Cerberus: | |
1331 | */ | |
cebe1820 | 1332 | clear_bit(10, (unsigned long *)&mce_banks[4].ctl); |
e9eee03e IM |
1333 | } |
1334 | if (c->x86 <= 17 && mce_bootlog < 0) { | |
1335 | /* | |
1336 | * Lots of broken BIOS around that don't clear them | |
1337 | * by default and leave crap in there. Don't log: | |
1338 | */ | |
911f6a7b | 1339 | mce_bootlog = 0; |
e9eee03e | 1340 | } |
2e6f694f AK |
1341 | /* |
1342 | * Various K7s with broken bank 0 around. Always disable | |
1343 | * by default. | |
1344 | */ | |
203abd67 | 1345 | if (c->x86 == 6 && banks > 0) |
cebe1820 | 1346 | mce_banks[0].ctl = 0; |
1da177e4 | 1347 | } |
e583538f | 1348 | |
06b7a7a5 AK |
1349 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
1350 | /* | |
1351 | * SDM documents that on family 6 bank 0 should not be written | |
1352 | * because it aliases to another special BIOS controlled | |
1353 | * register. | |
1354 | * But it's not aliased anymore on model 0x1a+ | |
1355 | * Don't ignore bank 0 completely because there could be a | |
1356 | * valid event later, merely don't write CTL0. | |
1357 | */ | |
1358 | ||
cebe1820 AK |
1359 | if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0) |
1360 | mce_banks[0].init = 0; | |
3c079792 AK |
1361 | |
1362 | /* | |
1363 | * All newer Intel systems support MCE broadcasting. Enable | |
1364 | * synchronization with a one second timeout. | |
1365 | */ | |
1366 | if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && | |
1367 | monarch_timeout < 0) | |
1368 | monarch_timeout = USEC_PER_SEC; | |
c7f6fa44 | 1369 | |
e412cd25 IM |
1370 | /* |
1371 | * There are also broken BIOSes on some Pentium M and | |
1372 | * earlier systems: | |
1373 | */ | |
1374 | if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0) | |
c7f6fa44 | 1375 | mce_bootlog = 0; |
06b7a7a5 | 1376 | } |
3c079792 AK |
1377 | if (monarch_timeout < 0) |
1378 | monarch_timeout = 0; | |
29b0f591 AK |
1379 | if (mce_bootlog != 0) |
1380 | mce_panic_timeout = 30; | |
e412cd25 IM |
1381 | |
1382 | return 0; | |
d88203d1 | 1383 | } |
1da177e4 | 1384 | |
5e09954a | 1385 | static void __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) |
4efc0670 AK |
1386 | { |
1387 | if (c->x86 != 5) | |
1388 | return; | |
1389 | switch (c->x86_vendor) { | |
1390 | case X86_VENDOR_INTEL: | |
c6978369 | 1391 | intel_p5_mcheck_init(c); |
4efc0670 AK |
1392 | break; |
1393 | case X86_VENDOR_CENTAUR: | |
1394 | winchip_mcheck_init(c); | |
1395 | break; | |
1396 | } | |
1397 | } | |
1398 | ||
5e09954a | 1399 | static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
1400 | { |
1401 | switch (c->x86_vendor) { | |
1402 | case X86_VENDOR_INTEL: | |
1403 | mce_intel_feature_init(c); | |
1404 | break; | |
89b831ef JS |
1405 | case X86_VENDOR_AMD: |
1406 | mce_amd_feature_init(c); | |
1407 | break; | |
1da177e4 LT |
1408 | default: |
1409 | break; | |
1410 | } | |
1411 | } | |
1412 | ||
5e09954a | 1413 | static void __mcheck_cpu_init_timer(void) |
52d168e2 AK |
1414 | { |
1415 | struct timer_list *t = &__get_cpu_var(mce_timer); | |
245b2e70 | 1416 | int *n = &__get_cpu_var(mce_next_interval); |
52d168e2 | 1417 | |
bc09effa JB |
1418 | setup_timer(t, mce_start_timer, smp_processor_id()); |
1419 | ||
62fdac59 HS |
1420 | if (mce_ignore_ce) |
1421 | return; | |
1422 | ||
6298c512 AK |
1423 | *n = check_interval * HZ; |
1424 | if (!*n) | |
52d168e2 | 1425 | return; |
6298c512 | 1426 | t->expires = round_jiffies(jiffies + *n); |
5be6066a | 1427 | add_timer_on(t, smp_processor_id()); |
52d168e2 AK |
1428 | } |
1429 | ||
9eda8cb3 AK |
1430 | /* Handle unconfigured int18 (should never happen) */ |
1431 | static void unexpected_machine_check(struct pt_regs *regs, long error_code) | |
1432 | { | |
1433 | printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n", | |
1434 | smp_processor_id()); | |
1435 | } | |
1436 | ||
1437 | /* Call the installed machine check handler for this CPU setup. */ | |
1438 | void (*machine_check_vector)(struct pt_regs *, long error_code) = | |
1439 | unexpected_machine_check; | |
1440 | ||
d88203d1 | 1441 | /* |
1da177e4 | 1442 | * Called for each booted CPU to set up machine checks. |
e9eee03e | 1443 | * Must be called with preempt off: |
1da177e4 | 1444 | */ |
5e09954a | 1445 | void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c) |
1da177e4 | 1446 | { |
4efc0670 AK |
1447 | if (mce_disabled) |
1448 | return; | |
1449 | ||
5e09954a | 1450 | __mcheck_cpu_ancient_init(c); |
4efc0670 | 1451 | |
5b4408fd | 1452 | if (!mce_available(c)) |
1da177e4 LT |
1453 | return; |
1454 | ||
5e09954a | 1455 | if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) { |
04b2b1a4 | 1456 | mce_disabled = 1; |
0d7482e3 AK |
1457 | return; |
1458 | } | |
0d7482e3 | 1459 | |
5d727926 AK |
1460 | machine_check_vector = do_machine_check; |
1461 | ||
5e09954a BP |
1462 | __mcheck_cpu_init_generic(); |
1463 | __mcheck_cpu_init_vendor(c); | |
1464 | __mcheck_cpu_init_timer(); | |
9b1beaf2 | 1465 | INIT_WORK(&__get_cpu_var(mce_work), mce_process_work); |
fb253195 | 1466 | |
1da177e4 LT |
1467 | } |
1468 | ||
1469 | /* | |
1470 | * Character device to read and clear the MCE log. | |
1471 | */ | |
1472 | ||
f528e7ba | 1473 | static DEFINE_SPINLOCK(mce_state_lock); |
e9eee03e IM |
1474 | static int open_count; /* #times opened */ |
1475 | static int open_exclu; /* already open exclusive? */ | |
f528e7ba TH |
1476 | |
1477 | static int mce_open(struct inode *inode, struct file *file) | |
1478 | { | |
1479 | spin_lock(&mce_state_lock); | |
1480 | ||
1481 | if (open_exclu || (open_count && (file->f_flags & O_EXCL))) { | |
1482 | spin_unlock(&mce_state_lock); | |
e9eee03e | 1483 | |
f528e7ba TH |
1484 | return -EBUSY; |
1485 | } | |
1486 | ||
1487 | if (file->f_flags & O_EXCL) | |
1488 | open_exclu = 1; | |
1489 | open_count++; | |
1490 | ||
1491 | spin_unlock(&mce_state_lock); | |
1492 | ||
bd78432c | 1493 | return nonseekable_open(inode, file); |
f528e7ba TH |
1494 | } |
1495 | ||
1496 | static int mce_release(struct inode *inode, struct file *file) | |
1497 | { | |
1498 | spin_lock(&mce_state_lock); | |
1499 | ||
1500 | open_count--; | |
1501 | open_exclu = 0; | |
1502 | ||
1503 | spin_unlock(&mce_state_lock); | |
1504 | ||
1505 | return 0; | |
1506 | } | |
1507 | ||
d88203d1 TG |
1508 | static void collect_tscs(void *data) |
1509 | { | |
1da177e4 | 1510 | unsigned long *cpu_tsc = (unsigned long *)data; |
d88203d1 | 1511 | |
1da177e4 | 1512 | rdtscll(cpu_tsc[smp_processor_id()]); |
d88203d1 | 1513 | } |
1da177e4 | 1514 | |
482908b4 HY |
1515 | static int mce_apei_read_done; |
1516 | ||
1517 | /* Collect MCE record of previous boot in persistent storage via APEI ERST. */ | |
1518 | static int __mce_read_apei(char __user **ubuf, size_t usize) | |
1519 | { | |
1520 | int rc; | |
1521 | u64 record_id; | |
1522 | struct mce m; | |
1523 | ||
1524 | if (usize < sizeof(struct mce)) | |
1525 | return -EINVAL; | |
1526 | ||
1527 | rc = apei_read_mce(&m, &record_id); | |
1528 | /* Error or no more MCE record */ | |
1529 | if (rc <= 0) { | |
1530 | mce_apei_read_done = 1; | |
1531 | return rc; | |
1532 | } | |
1533 | rc = -EFAULT; | |
1534 | if (copy_to_user(*ubuf, &m, sizeof(struct mce))) | |
1535 | return rc; | |
1536 | /* | |
1537 | * In fact, we should have cleared the record after that has | |
1538 | * been flushed to the disk or sent to network in | |
1539 | * /sbin/mcelog, but we have no interface to support that now, | |
1540 | * so just clear it to avoid duplication. | |
1541 | */ | |
1542 | rc = apei_clear_mce(record_id); | |
1543 | if (rc) { | |
1544 | mce_apei_read_done = 1; | |
1545 | return rc; | |
1546 | } | |
1547 | *ubuf += sizeof(struct mce); | |
1548 | ||
1549 | return 0; | |
1550 | } | |
1551 | ||
d88203d1 TG |
1552 | static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize, |
1553 | loff_t *off) | |
1da177e4 | 1554 | { |
e9eee03e | 1555 | char __user *buf = ubuf; |
f0de53bb | 1556 | unsigned long *cpu_tsc; |
ef41df43 | 1557 | unsigned prev, next; |
1da177e4 LT |
1558 | int i, err; |
1559 | ||
6bca67f9 | 1560 | cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL); |
f0de53bb AK |
1561 | if (!cpu_tsc) |
1562 | return -ENOMEM; | |
1563 | ||
8c8b8859 | 1564 | mutex_lock(&mce_read_mutex); |
482908b4 HY |
1565 | |
1566 | if (!mce_apei_read_done) { | |
1567 | err = __mce_read_apei(&buf, usize); | |
1568 | if (err || buf != ubuf) | |
1569 | goto out; | |
1570 | } | |
1571 | ||
f56e8a07 | 1572 | next = rcu_dereference_check_mce(mcelog.next); |
1da177e4 LT |
1573 | |
1574 | /* Only supports full reads right now */ | |
482908b4 HY |
1575 | err = -EINVAL; |
1576 | if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) | |
1577 | goto out; | |
1da177e4 LT |
1578 | |
1579 | err = 0; | |
ef41df43 HY |
1580 | prev = 0; |
1581 | do { | |
1582 | for (i = prev; i < next; i++) { | |
1583 | unsigned long start = jiffies; | |
1584 | ||
1585 | while (!mcelog.entry[i].finished) { | |
1586 | if (time_after_eq(jiffies, start + 2)) { | |
1587 | memset(mcelog.entry + i, 0, | |
1588 | sizeof(struct mce)); | |
1589 | goto timeout; | |
1590 | } | |
1591 | cpu_relax(); | |
673242c1 | 1592 | } |
ef41df43 HY |
1593 | smp_rmb(); |
1594 | err |= copy_to_user(buf, mcelog.entry + i, | |
1595 | sizeof(struct mce)); | |
1596 | buf += sizeof(struct mce); | |
1597 | timeout: | |
1598 | ; | |
673242c1 | 1599 | } |
1da177e4 | 1600 | |
ef41df43 HY |
1601 | memset(mcelog.entry + prev, 0, |
1602 | (next - prev) * sizeof(struct mce)); | |
1603 | prev = next; | |
1604 | next = cmpxchg(&mcelog.next, prev, 0); | |
1605 | } while (next != prev); | |
1da177e4 | 1606 | |
b2b18660 | 1607 | synchronize_sched(); |
1da177e4 | 1608 | |
d88203d1 TG |
1609 | /* |
1610 | * Collect entries that were still getting written before the | |
1611 | * synchronize. | |
1612 | */ | |
15c8b6c1 | 1613 | on_each_cpu(collect_tscs, cpu_tsc, 1); |
e9eee03e | 1614 | |
d88203d1 TG |
1615 | for (i = next; i < MCE_LOG_LEN; i++) { |
1616 | if (mcelog.entry[i].finished && | |
1617 | mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) { | |
1618 | err |= copy_to_user(buf, mcelog.entry+i, | |
1619 | sizeof(struct mce)); | |
1da177e4 LT |
1620 | smp_rmb(); |
1621 | buf += sizeof(struct mce); | |
1622 | memset(&mcelog.entry[i], 0, sizeof(struct mce)); | |
1623 | } | |
d88203d1 | 1624 | } |
482908b4 HY |
1625 | |
1626 | if (err) | |
1627 | err = -EFAULT; | |
1628 | ||
1629 | out: | |
8c8b8859 | 1630 | mutex_unlock(&mce_read_mutex); |
f0de53bb | 1631 | kfree(cpu_tsc); |
e9eee03e | 1632 | |
482908b4 | 1633 | return err ? err : buf - ubuf; |
1da177e4 LT |
1634 | } |
1635 | ||
e02e68d3 TH |
1636 | static unsigned int mce_poll(struct file *file, poll_table *wait) |
1637 | { | |
1638 | poll_wait(file, &mce_wait, wait); | |
f56e8a07 | 1639 | if (rcu_dereference_check_mce(mcelog.next)) |
e02e68d3 | 1640 | return POLLIN | POLLRDNORM; |
482908b4 HY |
1641 | if (!mce_apei_read_done && apei_check_mce()) |
1642 | return POLLIN | POLLRDNORM; | |
e02e68d3 TH |
1643 | return 0; |
1644 | } | |
1645 | ||
c68461b6 | 1646 | static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg) |
1da177e4 LT |
1647 | { |
1648 | int __user *p = (int __user *)arg; | |
d88203d1 | 1649 | |
1da177e4 | 1650 | if (!capable(CAP_SYS_ADMIN)) |
d88203d1 | 1651 | return -EPERM; |
e9eee03e | 1652 | |
1da177e4 | 1653 | switch (cmd) { |
d88203d1 | 1654 | case MCE_GET_RECORD_LEN: |
1da177e4 LT |
1655 | return put_user(sizeof(struct mce), p); |
1656 | case MCE_GET_LOG_LEN: | |
d88203d1 | 1657 | return put_user(MCE_LOG_LEN, p); |
1da177e4 LT |
1658 | case MCE_GETCLEAR_FLAGS: { |
1659 | unsigned flags; | |
d88203d1 TG |
1660 | |
1661 | do { | |
1da177e4 | 1662 | flags = mcelog.flags; |
d88203d1 | 1663 | } while (cmpxchg(&mcelog.flags, flags, 0) != flags); |
e9eee03e | 1664 | |
d88203d1 | 1665 | return put_user(flags, p); |
1da177e4 LT |
1666 | } |
1667 | default: | |
d88203d1 TG |
1668 | return -ENOTTY; |
1669 | } | |
1da177e4 LT |
1670 | } |
1671 | ||
a1ff41bf | 1672 | /* Modified in mce-inject.c, so not static or const */ |
ea149b36 | 1673 | struct file_operations mce_chrdev_ops = { |
e9eee03e IM |
1674 | .open = mce_open, |
1675 | .release = mce_release, | |
1676 | .read = mce_read, | |
1677 | .poll = mce_poll, | |
1678 | .unlocked_ioctl = mce_ioctl, | |
1da177e4 | 1679 | }; |
ea149b36 | 1680 | EXPORT_SYMBOL_GPL(mce_chrdev_ops); |
1da177e4 LT |
1681 | |
1682 | static struct miscdevice mce_log_device = { | |
1683 | MISC_MCELOG_MINOR, | |
1684 | "mcelog", | |
1685 | &mce_chrdev_ops, | |
1686 | }; | |
1687 | ||
13503fa9 | 1688 | /* |
62fdac59 HS |
1689 | * mce=off Disables machine check |
1690 | * mce=no_cmci Disables CMCI | |
1691 | * mce=dont_log_ce Clears corrected events silently, no log created for CEs. | |
1692 | * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared. | |
3c079792 AK |
1693 | * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above) |
1694 | * monarchtimeout is how long to wait for other CPUs on machine | |
1695 | * check, or 0 to not wait | |
13503fa9 HS |
1696 | * mce=bootlog Log MCEs from before booting. Disabled by default on AMD. |
1697 | * mce=nobootlog Don't log MCEs from before booting. | |
1698 | */ | |
1da177e4 LT |
1699 | static int __init mcheck_enable(char *str) |
1700 | { | |
e3346fc4 | 1701 | if (*str == 0) { |
4efc0670 | 1702 | enable_p5_mce(); |
e3346fc4 BZ |
1703 | return 1; |
1704 | } | |
4efc0670 AK |
1705 | if (*str == '=') |
1706 | str++; | |
1da177e4 | 1707 | if (!strcmp(str, "off")) |
04b2b1a4 | 1708 | mce_disabled = 1; |
62fdac59 HS |
1709 | else if (!strcmp(str, "no_cmci")) |
1710 | mce_cmci_disabled = 1; | |
1711 | else if (!strcmp(str, "dont_log_ce")) | |
1712 | mce_dont_log_ce = 1; | |
1713 | else if (!strcmp(str, "ignore_ce")) | |
1714 | mce_ignore_ce = 1; | |
13503fa9 HS |
1715 | else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) |
1716 | mce_bootlog = (str[0] == 'b'); | |
3c079792 | 1717 | else if (isdigit(str[0])) { |
8c566ef5 | 1718 | get_option(&str, &tolerant); |
3c079792 AK |
1719 | if (*str == ',') { |
1720 | ++str; | |
1721 | get_option(&str, &monarch_timeout); | |
1722 | } | |
1723 | } else { | |
4efc0670 | 1724 | printk(KERN_INFO "mce argument %s ignored. Please use /sys\n", |
13503fa9 HS |
1725 | str); |
1726 | return 0; | |
1727 | } | |
9b41046c | 1728 | return 1; |
1da177e4 | 1729 | } |
4efc0670 | 1730 | __setup("mce", mcheck_enable); |
1da177e4 | 1731 | |
a2202aa2 | 1732 | int __init mcheck_init(void) |
b33a6363 BP |
1733 | { |
1734 | atomic_notifier_chain_register(&x86_mce_decoder_chain, &mce_dec_nb); | |
1735 | ||
a2202aa2 YW |
1736 | mcheck_intel_therm_init(); |
1737 | ||
b33a6363 BP |
1738 | return 0; |
1739 | } | |
b33a6363 | 1740 | |
d88203d1 | 1741 | /* |
1da177e4 | 1742 | * Sysfs support |
d88203d1 | 1743 | */ |
1da177e4 | 1744 | |
973a2dd1 AK |
1745 | /* |
1746 | * Disable machine checks on suspend and shutdown. We can't really handle | |
1747 | * them later. | |
1748 | */ | |
5e09954a | 1749 | static int mce_disable_error_reporting(void) |
973a2dd1 AK |
1750 | { |
1751 | int i; | |
1752 | ||
06b7a7a5 | 1753 | for (i = 0; i < banks; i++) { |
cebe1820 | 1754 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1755 | |
cebe1820 | 1756 | if (b->init) |
a2d32bcb | 1757 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 1758 | } |
973a2dd1 AK |
1759 | return 0; |
1760 | } | |
1761 | ||
1762 | static int mce_suspend(struct sys_device *dev, pm_message_t state) | |
1763 | { | |
5e09954a | 1764 | return mce_disable_error_reporting(); |
973a2dd1 AK |
1765 | } |
1766 | ||
1767 | static int mce_shutdown(struct sys_device *dev) | |
1768 | { | |
5e09954a | 1769 | return mce_disable_error_reporting(); |
973a2dd1 AK |
1770 | } |
1771 | ||
e9eee03e IM |
1772 | /* |
1773 | * On resume clear all MCE state. Don't want to see leftovers from the BIOS. | |
1774 | * Only one CPU is active at this time, the others get re-added later using | |
1775 | * CPU hotplug: | |
1776 | */ | |
1da177e4 LT |
1777 | static int mce_resume(struct sys_device *dev) |
1778 | { | |
5e09954a BP |
1779 | __mcheck_cpu_init_generic(); |
1780 | __mcheck_cpu_init_vendor(¤t_cpu_data); | |
e9eee03e | 1781 | |
1da177e4 LT |
1782 | return 0; |
1783 | } | |
1784 | ||
52d168e2 AK |
1785 | static void mce_cpu_restart(void *data) |
1786 | { | |
1787 | del_timer_sync(&__get_cpu_var(mce_timer)); | |
33edbf02 HS |
1788 | if (!mce_available(¤t_cpu_data)) |
1789 | return; | |
5e09954a BP |
1790 | __mcheck_cpu_init_generic(); |
1791 | __mcheck_cpu_init_timer(); | |
52d168e2 AK |
1792 | } |
1793 | ||
1da177e4 | 1794 | /* Reinit MCEs after user configuration changes */ |
d88203d1 TG |
1795 | static void mce_restart(void) |
1796 | { | |
52d168e2 | 1797 | on_each_cpu(mce_cpu_restart, NULL, 1); |
1da177e4 LT |
1798 | } |
1799 | ||
9af43b54 HS |
1800 | /* Toggle features for corrected errors */ |
1801 | static void mce_disable_ce(void *all) | |
1802 | { | |
1803 | if (!mce_available(¤t_cpu_data)) | |
1804 | return; | |
1805 | if (all) | |
1806 | del_timer_sync(&__get_cpu_var(mce_timer)); | |
1807 | cmci_clear(); | |
1808 | } | |
1809 | ||
1810 | static void mce_enable_ce(void *all) | |
1811 | { | |
1812 | if (!mce_available(¤t_cpu_data)) | |
1813 | return; | |
1814 | cmci_reenable(); | |
1815 | cmci_recheck(); | |
1816 | if (all) | |
5e09954a | 1817 | __mcheck_cpu_init_timer(); |
9af43b54 HS |
1818 | } |
1819 | ||
1da177e4 | 1820 | static struct sysdev_class mce_sysclass = { |
e9eee03e IM |
1821 | .suspend = mce_suspend, |
1822 | .shutdown = mce_shutdown, | |
1823 | .resume = mce_resume, | |
1824 | .name = "machinecheck", | |
1da177e4 LT |
1825 | }; |
1826 | ||
cb491fca | 1827 | DEFINE_PER_CPU(struct sys_device, mce_dev); |
e9eee03e IM |
1828 | |
1829 | __cpuinitdata | |
1830 | void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); | |
1da177e4 | 1831 | |
cebe1820 AK |
1832 | static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr) |
1833 | { | |
1834 | return container_of(attr, struct mce_bank, attr); | |
1835 | } | |
0d7482e3 AK |
1836 | |
1837 | static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
1838 | char *buf) | |
1839 | { | |
cebe1820 | 1840 | return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl); |
0d7482e3 AK |
1841 | } |
1842 | ||
1843 | static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
9319cec8 | 1844 | const char *buf, size_t size) |
0d7482e3 | 1845 | { |
9319cec8 | 1846 | u64 new; |
e9eee03e | 1847 | |
9319cec8 | 1848 | if (strict_strtoull(buf, 0, &new) < 0) |
0d7482e3 | 1849 | return -EINVAL; |
e9eee03e | 1850 | |
cebe1820 | 1851 | attr_to_bank(attr)->ctl = new; |
0d7482e3 | 1852 | mce_restart(); |
e9eee03e | 1853 | |
9319cec8 | 1854 | return size; |
0d7482e3 | 1855 | } |
a98f0dd3 | 1856 | |
e9eee03e IM |
1857 | static ssize_t |
1858 | show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf) | |
a98f0dd3 | 1859 | { |
1020bcbc | 1860 | strcpy(buf, mce_helper); |
a98f0dd3 | 1861 | strcat(buf, "\n"); |
1020bcbc | 1862 | return strlen(mce_helper) + 1; |
a98f0dd3 AK |
1863 | } |
1864 | ||
4a0b2b4d | 1865 | static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr, |
e9eee03e | 1866 | const char *buf, size_t siz) |
a98f0dd3 AK |
1867 | { |
1868 | char *p; | |
e9eee03e | 1869 | |
1020bcbc HS |
1870 | strncpy(mce_helper, buf, sizeof(mce_helper)); |
1871 | mce_helper[sizeof(mce_helper)-1] = 0; | |
1020bcbc | 1872 | p = strchr(mce_helper, '\n'); |
e9eee03e | 1873 | |
e9084ec9 | 1874 | if (p) |
e9eee03e IM |
1875 | *p = 0; |
1876 | ||
e9084ec9 | 1877 | return strlen(mce_helper) + !!p; |
a98f0dd3 AK |
1878 | } |
1879 | ||
9af43b54 HS |
1880 | static ssize_t set_ignore_ce(struct sys_device *s, |
1881 | struct sysdev_attribute *attr, | |
1882 | const char *buf, size_t size) | |
1883 | { | |
1884 | u64 new; | |
1885 | ||
1886 | if (strict_strtoull(buf, 0, &new) < 0) | |
1887 | return -EINVAL; | |
1888 | ||
1889 | if (mce_ignore_ce ^ !!new) { | |
1890 | if (new) { | |
1891 | /* disable ce features */ | |
1892 | on_each_cpu(mce_disable_ce, (void *)1, 1); | |
1893 | mce_ignore_ce = 1; | |
1894 | } else { | |
1895 | /* enable ce features */ | |
1896 | mce_ignore_ce = 0; | |
1897 | on_each_cpu(mce_enable_ce, (void *)1, 1); | |
1898 | } | |
1899 | } | |
1900 | return size; | |
1901 | } | |
1902 | ||
1903 | static ssize_t set_cmci_disabled(struct sys_device *s, | |
1904 | struct sysdev_attribute *attr, | |
1905 | const char *buf, size_t size) | |
1906 | { | |
1907 | u64 new; | |
1908 | ||
1909 | if (strict_strtoull(buf, 0, &new) < 0) | |
1910 | return -EINVAL; | |
1911 | ||
1912 | if (mce_cmci_disabled ^ !!new) { | |
1913 | if (new) { | |
1914 | /* disable cmci */ | |
1915 | on_each_cpu(mce_disable_ce, NULL, 1); | |
1916 | mce_cmci_disabled = 1; | |
1917 | } else { | |
1918 | /* enable cmci */ | |
1919 | mce_cmci_disabled = 0; | |
1920 | on_each_cpu(mce_enable_ce, NULL, 1); | |
1921 | } | |
1922 | } | |
1923 | return size; | |
1924 | } | |
1925 | ||
b56f642d AK |
1926 | static ssize_t store_int_with_restart(struct sys_device *s, |
1927 | struct sysdev_attribute *attr, | |
1928 | const char *buf, size_t size) | |
1929 | { | |
1930 | ssize_t ret = sysdev_store_int(s, attr, buf, size); | |
1931 | mce_restart(); | |
1932 | return ret; | |
1933 | } | |
1934 | ||
a98f0dd3 | 1935 | static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger); |
d95d62c0 | 1936 | static SYSDEV_INT_ATTR(tolerant, 0644, tolerant); |
3c079792 | 1937 | static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout); |
9af43b54 | 1938 | static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce); |
e9eee03e | 1939 | |
b56f642d AK |
1940 | static struct sysdev_ext_attribute attr_check_interval = { |
1941 | _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int, | |
1942 | store_int_with_restart), | |
1943 | &check_interval | |
1944 | }; | |
e9eee03e | 1945 | |
9af43b54 HS |
1946 | static struct sysdev_ext_attribute attr_ignore_ce = { |
1947 | _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce), | |
1948 | &mce_ignore_ce | |
1949 | }; | |
1950 | ||
1951 | static struct sysdev_ext_attribute attr_cmci_disabled = { | |
74b602c7 | 1952 | _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled), |
9af43b54 HS |
1953 | &mce_cmci_disabled |
1954 | }; | |
1955 | ||
cb491fca | 1956 | static struct sysdev_attribute *mce_attrs[] = { |
9af43b54 HS |
1957 | &attr_tolerant.attr, |
1958 | &attr_check_interval.attr, | |
1959 | &attr_trigger, | |
3c079792 | 1960 | &attr_monarch_timeout.attr, |
9af43b54 HS |
1961 | &attr_dont_log_ce.attr, |
1962 | &attr_ignore_ce.attr, | |
1963 | &attr_cmci_disabled.attr, | |
a98f0dd3 AK |
1964 | NULL |
1965 | }; | |
1da177e4 | 1966 | |
cb491fca | 1967 | static cpumask_var_t mce_dev_initialized; |
bae19fe0 | 1968 | |
e9eee03e | 1969 | /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */ |
91c6d400 | 1970 | static __cpuinit int mce_create_device(unsigned int cpu) |
1da177e4 LT |
1971 | { |
1972 | int err; | |
b1f49f95 | 1973 | int i, j; |
92cb7612 | 1974 | |
90367556 | 1975 | if (!mce_available(&boot_cpu_data)) |
91c6d400 AK |
1976 | return -EIO; |
1977 | ||
cb491fca IM |
1978 | memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject)); |
1979 | per_cpu(mce_dev, cpu).id = cpu; | |
1980 | per_cpu(mce_dev, cpu).cls = &mce_sysclass; | |
91c6d400 | 1981 | |
cb491fca | 1982 | err = sysdev_register(&per_cpu(mce_dev, cpu)); |
d435d862 AM |
1983 | if (err) |
1984 | return err; | |
1985 | ||
cb491fca IM |
1986 | for (i = 0; mce_attrs[i]; i++) { |
1987 | err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
d435d862 AM |
1988 | if (err) |
1989 | goto error; | |
1990 | } | |
b1f49f95 | 1991 | for (j = 0; j < banks; j++) { |
cb491fca | 1992 | err = sysdev_create_file(&per_cpu(mce_dev, cpu), |
cebe1820 | 1993 | &mce_banks[j].attr); |
0d7482e3 AK |
1994 | if (err) |
1995 | goto error2; | |
1996 | } | |
cb491fca | 1997 | cpumask_set_cpu(cpu, mce_dev_initialized); |
91c6d400 | 1998 | |
d435d862 | 1999 | return 0; |
0d7482e3 | 2000 | error2: |
b1f49f95 | 2001 | while (--j >= 0) |
cebe1820 | 2002 | sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[j].attr); |
d435d862 | 2003 | error: |
cb491fca | 2004 | while (--i >= 0) |
5c0e9f28 | 2005 | sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); |
cb491fca IM |
2006 | |
2007 | sysdev_unregister(&per_cpu(mce_dev, cpu)); | |
d435d862 | 2008 | |
91c6d400 AK |
2009 | return err; |
2010 | } | |
2011 | ||
2d9cd6c2 | 2012 | static __cpuinit void mce_remove_device(unsigned int cpu) |
91c6d400 | 2013 | { |
73ca5358 SL |
2014 | int i; |
2015 | ||
cb491fca | 2016 | if (!cpumask_test_cpu(cpu, mce_dev_initialized)) |
bae19fe0 AH |
2017 | return; |
2018 | ||
cb491fca IM |
2019 | for (i = 0; mce_attrs[i]; i++) |
2020 | sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
2021 | ||
0d7482e3 | 2022 | for (i = 0; i < banks; i++) |
cebe1820 | 2023 | sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr); |
cb491fca IM |
2024 | |
2025 | sysdev_unregister(&per_cpu(mce_dev, cpu)); | |
2026 | cpumask_clear_cpu(cpu, mce_dev_initialized); | |
91c6d400 | 2027 | } |
91c6d400 | 2028 | |
d6b75584 | 2029 | /* Make sure there are no machine checks on offlined CPUs. */ |
767df1bd | 2030 | static void __cpuinit mce_disable_cpu(void *h) |
d6b75584 | 2031 | { |
88ccbedd | 2032 | unsigned long action = *(unsigned long *)h; |
cb491fca | 2033 | int i; |
d6b75584 AK |
2034 | |
2035 | if (!mce_available(¤t_cpu_data)) | |
2036 | return; | |
767df1bd | 2037 | |
88ccbedd AK |
2038 | if (!(action & CPU_TASKS_FROZEN)) |
2039 | cmci_clear(); | |
06b7a7a5 | 2040 | for (i = 0; i < banks; i++) { |
cebe1820 | 2041 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2042 | |
cebe1820 | 2043 | if (b->init) |
a2d32bcb | 2044 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 2045 | } |
d6b75584 AK |
2046 | } |
2047 | ||
767df1bd | 2048 | static void __cpuinit mce_reenable_cpu(void *h) |
d6b75584 | 2049 | { |
88ccbedd | 2050 | unsigned long action = *(unsigned long *)h; |
e9eee03e | 2051 | int i; |
d6b75584 AK |
2052 | |
2053 | if (!mce_available(¤t_cpu_data)) | |
2054 | return; | |
e9eee03e | 2055 | |
88ccbedd AK |
2056 | if (!(action & CPU_TASKS_FROZEN)) |
2057 | cmci_reenable(); | |
06b7a7a5 | 2058 | for (i = 0; i < banks; i++) { |
cebe1820 | 2059 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2060 | |
cebe1820 | 2061 | if (b->init) |
a2d32bcb | 2062 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
06b7a7a5 | 2063 | } |
d6b75584 AK |
2064 | } |
2065 | ||
91c6d400 | 2066 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ |
e9eee03e IM |
2067 | static int __cpuinit |
2068 | mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) | |
91c6d400 AK |
2069 | { |
2070 | unsigned int cpu = (unsigned long)hcpu; | |
52d168e2 | 2071 | struct timer_list *t = &per_cpu(mce_timer, cpu); |
91c6d400 AK |
2072 | |
2073 | switch (action) { | |
bae19fe0 AH |
2074 | case CPU_ONLINE: |
2075 | case CPU_ONLINE_FROZEN: | |
2076 | mce_create_device(cpu); | |
8735728e RW |
2077 | if (threshold_cpu_callback) |
2078 | threshold_cpu_callback(action, cpu); | |
91c6d400 | 2079 | break; |
91c6d400 | 2080 | case CPU_DEAD: |
8bb78442 | 2081 | case CPU_DEAD_FROZEN: |
8735728e RW |
2082 | if (threshold_cpu_callback) |
2083 | threshold_cpu_callback(action, cpu); | |
91c6d400 AK |
2084 | mce_remove_device(cpu); |
2085 | break; | |
52d168e2 AK |
2086 | case CPU_DOWN_PREPARE: |
2087 | case CPU_DOWN_PREPARE_FROZEN: | |
2088 | del_timer_sync(t); | |
88ccbedd | 2089 | smp_call_function_single(cpu, mce_disable_cpu, &action, 1); |
52d168e2 AK |
2090 | break; |
2091 | case CPU_DOWN_FAILED: | |
2092 | case CPU_DOWN_FAILED_FROZEN: | |
fe5ed91d HS |
2093 | if (!mce_ignore_ce && check_interval) { |
2094 | t->expires = round_jiffies(jiffies + | |
245b2e70 | 2095 | __get_cpu_var(mce_next_interval)); |
fe5ed91d HS |
2096 | add_timer_on(t, cpu); |
2097 | } | |
88ccbedd AK |
2098 | smp_call_function_single(cpu, mce_reenable_cpu, &action, 1); |
2099 | break; | |
2100 | case CPU_POST_DEAD: | |
2101 | /* intentionally ignoring frozen here */ | |
2102 | cmci_rediscover(cpu); | |
52d168e2 | 2103 | break; |
91c6d400 | 2104 | } |
bae19fe0 | 2105 | return NOTIFY_OK; |
91c6d400 AK |
2106 | } |
2107 | ||
1e35669d | 2108 | static struct notifier_block mce_cpu_notifier __cpuinitdata = { |
91c6d400 AK |
2109 | .notifier_call = mce_cpu_callback, |
2110 | }; | |
2111 | ||
cebe1820 | 2112 | static __init void mce_init_banks(void) |
0d7482e3 AK |
2113 | { |
2114 | int i; | |
2115 | ||
0d7482e3 | 2116 | for (i = 0; i < banks; i++) { |
cebe1820 AK |
2117 | struct mce_bank *b = &mce_banks[i]; |
2118 | struct sysdev_attribute *a = &b->attr; | |
e9eee03e | 2119 | |
a07e4156 | 2120 | sysfs_attr_init(&a->attr); |
cebe1820 AK |
2121 | a->attr.name = b->attrname; |
2122 | snprintf(b->attrname, ATTR_LEN, "bank%d", i); | |
e9eee03e IM |
2123 | |
2124 | a->attr.mode = 0644; | |
2125 | a->show = show_bank; | |
2126 | a->store = set_bank; | |
0d7482e3 | 2127 | } |
0d7482e3 AK |
2128 | } |
2129 | ||
5e09954a | 2130 | static __init int mcheck_init_device(void) |
91c6d400 AK |
2131 | { |
2132 | int err; | |
2133 | int i = 0; | |
2134 | ||
1da177e4 LT |
2135 | if (!mce_available(&boot_cpu_data)) |
2136 | return -EIO; | |
0d7482e3 | 2137 | |
e92fae06 | 2138 | zalloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL); |
996867d0 | 2139 | |
cebe1820 | 2140 | mce_init_banks(); |
0d7482e3 | 2141 | |
1da177e4 | 2142 | err = sysdev_class_register(&mce_sysclass); |
d435d862 AM |
2143 | if (err) |
2144 | return err; | |
91c6d400 AK |
2145 | |
2146 | for_each_online_cpu(i) { | |
d435d862 AM |
2147 | err = mce_create_device(i); |
2148 | if (err) | |
2149 | return err; | |
91c6d400 AK |
2150 | } |
2151 | ||
be6b5a35 | 2152 | register_hotcpu_notifier(&mce_cpu_notifier); |
1da177e4 | 2153 | misc_register(&mce_log_device); |
e9eee03e | 2154 | |
1da177e4 | 2155 | return err; |
1da177e4 | 2156 | } |
91c6d400 | 2157 | |
5e09954a | 2158 | device_initcall(mcheck_init_device); |
a988d334 | 2159 | |
d7c3c9a6 AK |
2160 | /* |
2161 | * Old style boot options parsing. Only for compatibility. | |
2162 | */ | |
2163 | static int __init mcheck_disable(char *str) | |
2164 | { | |
2165 | mce_disabled = 1; | |
2166 | return 1; | |
2167 | } | |
2168 | __setup("nomce", mcheck_disable); | |
a988d334 | 2169 | |
5be9ed25 HY |
2170 | #ifdef CONFIG_DEBUG_FS |
2171 | struct dentry *mce_get_debugfs_dir(void) | |
a988d334 | 2172 | { |
5be9ed25 | 2173 | static struct dentry *dmce; |
a988d334 | 2174 | |
5be9ed25 HY |
2175 | if (!dmce) |
2176 | dmce = debugfs_create_dir("mce", NULL); | |
a988d334 | 2177 | |
5be9ed25 HY |
2178 | return dmce; |
2179 | } | |
a988d334 | 2180 | |
bf783f9f HY |
2181 | static void mce_reset(void) |
2182 | { | |
2183 | cpu_missing = 0; | |
2184 | atomic_set(&mce_fake_paniced, 0); | |
2185 | atomic_set(&mce_executing, 0); | |
2186 | atomic_set(&mce_callin, 0); | |
2187 | atomic_set(&global_nwo, 0); | |
2188 | } | |
a988d334 | 2189 | |
bf783f9f HY |
2190 | static int fake_panic_get(void *data, u64 *val) |
2191 | { | |
2192 | *val = fake_panic; | |
2193 | return 0; | |
a988d334 IM |
2194 | } |
2195 | ||
bf783f9f | 2196 | static int fake_panic_set(void *data, u64 val) |
a988d334 | 2197 | { |
bf783f9f HY |
2198 | mce_reset(); |
2199 | fake_panic = val; | |
2200 | return 0; | |
a988d334 | 2201 | } |
a988d334 | 2202 | |
bf783f9f HY |
2203 | DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get, |
2204 | fake_panic_set, "%llu\n"); | |
d7c3c9a6 | 2205 | |
5e09954a | 2206 | static int __init mcheck_debugfs_init(void) |
d7c3c9a6 | 2207 | { |
bf783f9f HY |
2208 | struct dentry *dmce, *ffake_panic; |
2209 | ||
2210 | dmce = mce_get_debugfs_dir(); | |
2211 | if (!dmce) | |
2212 | return -ENOMEM; | |
2213 | ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL, | |
2214 | &fake_panic_fops); | |
2215 | if (!ffake_panic) | |
2216 | return -ENOMEM; | |
2217 | ||
2218 | return 0; | |
d7c3c9a6 | 2219 | } |
5e09954a | 2220 | late_initcall(mcheck_debugfs_init); |
5be9ed25 | 2221 | #endif |