Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Machine check handler. | |
e9eee03e | 3 | * |
1da177e4 | 4 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. |
d88203d1 TG |
5 | * Rest from unknown author(s). |
6 | * 2004 Andi Kleen. Rewrote most of it. | |
b79109c3 AK |
7 | * Copyright 2008 Intel Corporation |
8 | * Author: Andi Kleen | |
1da177e4 | 9 | */ |
e9eee03e IM |
10 | #include <linux/thread_info.h> |
11 | #include <linux/capability.h> | |
12 | #include <linux/miscdevice.h> | |
13 | #include <linux/ratelimit.h> | |
14 | #include <linux/kallsyms.h> | |
15 | #include <linux/rcupdate.h> | |
e9eee03e | 16 | #include <linux/kobject.h> |
14a02530 | 17 | #include <linux/uaccess.h> |
e9eee03e IM |
18 | #include <linux/kdebug.h> |
19 | #include <linux/kernel.h> | |
20 | #include <linux/percpu.h> | |
1da177e4 | 21 | #include <linux/string.h> |
1da177e4 | 22 | #include <linux/sysdev.h> |
f3c6ea1b | 23 | #include <linux/syscore_ops.h> |
3c079792 | 24 | #include <linux/delay.h> |
8c566ef5 | 25 | #include <linux/ctype.h> |
e9eee03e | 26 | #include <linux/sched.h> |
0d7482e3 | 27 | #include <linux/sysfs.h> |
e9eee03e | 28 | #include <linux/types.h> |
5a0e3ad6 | 29 | #include <linux/slab.h> |
e9eee03e IM |
30 | #include <linux/init.h> |
31 | #include <linux/kmod.h> | |
32 | #include <linux/poll.h> | |
3c079792 | 33 | #include <linux/nmi.h> |
e9eee03e | 34 | #include <linux/cpu.h> |
14a02530 | 35 | #include <linux/smp.h> |
e9eee03e | 36 | #include <linux/fs.h> |
9b1beaf2 | 37 | #include <linux/mm.h> |
5be9ed25 | 38 | #include <linux/debugfs.h> |
696e409d | 39 | #include <linux/edac_mce.h> |
b77e70bf | 40 | #include <linux/irq_work.h> |
e9eee03e | 41 | |
d88203d1 | 42 | #include <asm/processor.h> |
e9eee03e IM |
43 | #include <asm/mce.h> |
44 | #include <asm/msr.h> | |
1da177e4 | 45 | |
bd19a5e6 | 46 | #include "mce-internal.h" |
711c2e48 | 47 | |
93b62c3c | 48 | static DEFINE_MUTEX(mce_chrdev_read_mutex); |
2aa2b50d | 49 | |
f56e8a07 | 50 | #define rcu_dereference_check_mce(p) \ |
ec8c27e0 | 51 | rcu_dereference_index_check((p), \ |
f56e8a07 | 52 | rcu_read_lock_sched_held() || \ |
93b62c3c | 53 | lockdep_is_held(&mce_chrdev_read_mutex)) |
f56e8a07 | 54 | |
8968f9d3 HS |
55 | #define CREATE_TRACE_POINTS |
56 | #include <trace/events/mce.h> | |
57 | ||
4e5b3e69 | 58 | int mce_disabled __read_mostly; |
04b2b1a4 | 59 | |
e9eee03e | 60 | #define MISC_MCELOG_MINOR 227 |
0d7482e3 | 61 | |
3c079792 AK |
62 | #define SPINUNIT 100 /* 100ns */ |
63 | ||
553f265f AK |
64 | atomic_t mce_entry; |
65 | ||
01ca79f1 AK |
66 | DEFINE_PER_CPU(unsigned, mce_exception_count); |
67 | ||
bd78432c TH |
68 | /* |
69 | * Tolerant levels: | |
70 | * 0: always panic on uncorrected errors, log corrected errors | |
71 | * 1: panic or SIGBUS on uncorrected errors, log corrected errors | |
72 | * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors | |
73 | * 3: never panic or SIGBUS, log all errors (for testing only) | |
74 | */ | |
4e5b3e69 HS |
75 | static int tolerant __read_mostly = 1; |
76 | static int banks __read_mostly; | |
4e5b3e69 HS |
77 | static int rip_msr __read_mostly; |
78 | static int mce_bootlog __read_mostly = -1; | |
79 | static int monarch_timeout __read_mostly = -1; | |
80 | static int mce_panic_timeout __read_mostly; | |
81 | static int mce_dont_log_ce __read_mostly; | |
82 | int mce_cmci_disabled __read_mostly; | |
83 | int mce_ignore_ce __read_mostly; | |
84 | int mce_ser __read_mostly; | |
a98f0dd3 | 85 | |
cebe1820 AK |
86 | struct mce_bank *mce_banks __read_mostly; |
87 | ||
1020bcbc HS |
88 | /* User mode helper program triggered by machine check event */ |
89 | static unsigned long mce_need_notify; | |
90 | static char mce_helper[128]; | |
91 | static char *mce_helper_argv[2] = { mce_helper, NULL }; | |
1da177e4 | 92 | |
93b62c3c HS |
93 | static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait); |
94 | ||
3c079792 AK |
95 | static DEFINE_PER_CPU(struct mce, mces_seen); |
96 | static int cpu_missing; | |
97 | ||
fb253195 BP |
98 | /* |
99 | * CPU/chipset specific EDAC code can register a notifier call here to print | |
100 | * MCE errors in a human-readable form. | |
101 | */ | |
102 | ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain); | |
103 | EXPORT_SYMBOL_GPL(x86_mce_decoder_chain); | |
104 | ||
ee031c31 AK |
105 | /* MCA banks polled by the period polling timer for corrected events */ |
106 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { | |
107 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL | |
108 | }; | |
109 | ||
9b1beaf2 AK |
110 | static DEFINE_PER_CPU(struct work_struct, mce_work); |
111 | ||
b5f2fa4e AK |
112 | /* Do initial initialization of a struct mce */ |
113 | void mce_setup(struct mce *m) | |
114 | { | |
115 | memset(m, 0, sizeof(struct mce)); | |
d620c67f | 116 | m->cpu = m->extcpu = smp_processor_id(); |
b5f2fa4e | 117 | rdtscll(m->tsc); |
8ee08347 AK |
118 | /* We hope get_seconds stays lockless */ |
119 | m->time = get_seconds(); | |
120 | m->cpuvendor = boot_cpu_data.x86_vendor; | |
121 | m->cpuid = cpuid_eax(1); | |
122 | #ifdef CONFIG_SMP | |
123 | m->socketid = cpu_data(m->extcpu).phys_proc_id; | |
124 | #endif | |
125 | m->apicid = cpu_data(m->extcpu).initial_apicid; | |
126 | rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap); | |
b5f2fa4e AK |
127 | } |
128 | ||
ea149b36 AK |
129 | DEFINE_PER_CPU(struct mce, injectm); |
130 | EXPORT_PER_CPU_SYMBOL_GPL(injectm); | |
131 | ||
1da177e4 LT |
132 | /* |
133 | * Lockless MCE logging infrastructure. | |
134 | * This avoids deadlocks on printk locks without having to break locks. Also | |
135 | * separate MCEs from kernel messages to avoid bogus bug reports. | |
136 | */ | |
137 | ||
231fd906 | 138 | static struct mce_log mcelog = { |
f6fb0ac0 AK |
139 | .signature = MCE_LOG_SIGNATURE, |
140 | .len = MCE_LOG_LEN, | |
141 | .recordlen = sizeof(struct mce), | |
d88203d1 | 142 | }; |
1da177e4 LT |
143 | |
144 | void mce_log(struct mce *mce) | |
145 | { | |
146 | unsigned next, entry; | |
e9eee03e | 147 | |
8968f9d3 HS |
148 | /* Emit the trace record: */ |
149 | trace_mce_record(mce); | |
150 | ||
1da177e4 | 151 | mce->finished = 0; |
7644143c | 152 | wmb(); |
1da177e4 | 153 | for (;;) { |
f56e8a07 | 154 | entry = rcu_dereference_check_mce(mcelog.next); |
673242c1 | 155 | for (;;) { |
696e409d MCC |
156 | /* |
157 | * If edac_mce is enabled, it will check the error type | |
158 | * and will process it, if it is a known error. | |
159 | * Otherwise, the error will be sent through mcelog | |
160 | * interface | |
161 | */ | |
162 | if (edac_mce_parse(mce)) | |
163 | return; | |
164 | ||
e9eee03e IM |
165 | /* |
166 | * When the buffer fills up discard new entries. | |
167 | * Assume that the earlier errors are the more | |
168 | * interesting ones: | |
169 | */ | |
673242c1 | 170 | if (entry >= MCE_LOG_LEN) { |
14a02530 HS |
171 | set_bit(MCE_OVERFLOW, |
172 | (unsigned long *)&mcelog.flags); | |
673242c1 AK |
173 | return; |
174 | } | |
e9eee03e | 175 | /* Old left over entry. Skip: */ |
673242c1 AK |
176 | if (mcelog.entry[entry].finished) { |
177 | entry++; | |
178 | continue; | |
179 | } | |
7644143c | 180 | break; |
1da177e4 | 181 | } |
1da177e4 LT |
182 | smp_rmb(); |
183 | next = entry + 1; | |
184 | if (cmpxchg(&mcelog.next, entry, next) == entry) | |
185 | break; | |
186 | } | |
187 | memcpy(mcelog.entry + entry, mce, sizeof(struct mce)); | |
7644143c | 188 | wmb(); |
1da177e4 | 189 | mcelog.entry[entry].finished = 1; |
7644143c | 190 | wmb(); |
1da177e4 | 191 | |
a0189c70 | 192 | mce->finished = 1; |
1020bcbc | 193 | set_bit(0, &mce_need_notify); |
1da177e4 LT |
194 | } |
195 | ||
77e26cca | 196 | static void print_mce(struct mce *m) |
1da177e4 | 197 | { |
dffa4b2f BP |
198 | int ret = 0; |
199 | ||
a2d7b0d4 | 200 | pr_emerg(HW_ERR "CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n", |
d620c67f | 201 | m->extcpu, m->mcgstatus, m->bank, m->status); |
f436f8bb | 202 | |
65ea5b03 | 203 | if (m->ip) { |
a2d7b0d4 | 204 | pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ", |
f436f8bb IM |
205 | !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", |
206 | m->cs, m->ip); | |
207 | ||
1da177e4 | 208 | if (m->cs == __KERNEL_CS) |
65ea5b03 | 209 | print_symbol("{%s}", m->ip); |
f436f8bb | 210 | pr_cont("\n"); |
1da177e4 | 211 | } |
f436f8bb | 212 | |
a2d7b0d4 | 213 | pr_emerg(HW_ERR "TSC %llx ", m->tsc); |
1da177e4 | 214 | if (m->addr) |
f436f8bb | 215 | pr_cont("ADDR %llx ", m->addr); |
1da177e4 | 216 | if (m->misc) |
f436f8bb | 217 | pr_cont("MISC %llx ", m->misc); |
549d042d | 218 | |
f436f8bb | 219 | pr_cont("\n"); |
506ed6b5 AK |
220 | /* |
221 | * Note this output is parsed by external tools and old fields | |
222 | * should not be changed. | |
223 | */ | |
224 | pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %u\n", | |
225 | m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid, | |
226 | cpu_data(m->extcpu).microcode); | |
f436f8bb IM |
227 | |
228 | /* | |
229 | * Print out human-readable details about the MCE error, | |
fb253195 | 230 | * (if the CPU has an implementation for that) |
f436f8bb | 231 | */ |
dffa4b2f BP |
232 | ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m); |
233 | if (ret == NOTIFY_STOP) | |
234 | return; | |
235 | ||
236 | pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n"); | |
86503560 AK |
237 | } |
238 | ||
f94b61c2 AK |
239 | #define PANIC_TIMEOUT 5 /* 5 seconds */ |
240 | ||
241 | static atomic_t mce_paniced; | |
242 | ||
bf783f9f HY |
243 | static int fake_panic; |
244 | static atomic_t mce_fake_paniced; | |
245 | ||
f94b61c2 AK |
246 | /* Panic in progress. Enable interrupts and wait for final IPI */ |
247 | static void wait_for_panic(void) | |
248 | { | |
249 | long timeout = PANIC_TIMEOUT*USEC_PER_SEC; | |
f436f8bb | 250 | |
f94b61c2 AK |
251 | preempt_disable(); |
252 | local_irq_enable(); | |
253 | while (timeout-- > 0) | |
254 | udelay(1); | |
29b0f591 AK |
255 | if (panic_timeout == 0) |
256 | panic_timeout = mce_panic_timeout; | |
f94b61c2 AK |
257 | panic("Panicing machine check CPU died"); |
258 | } | |
259 | ||
bd19a5e6 | 260 | static void mce_panic(char *msg, struct mce *final, char *exp) |
d88203d1 | 261 | { |
482908b4 | 262 | int i, apei_err = 0; |
e02e68d3 | 263 | |
bf783f9f HY |
264 | if (!fake_panic) { |
265 | /* | |
266 | * Make sure only one CPU runs in machine check panic | |
267 | */ | |
268 | if (atomic_inc_return(&mce_paniced) > 1) | |
269 | wait_for_panic(); | |
270 | barrier(); | |
f94b61c2 | 271 | |
bf783f9f HY |
272 | bust_spinlocks(1); |
273 | console_verbose(); | |
274 | } else { | |
275 | /* Don't log too much for fake panic */ | |
276 | if (atomic_inc_return(&mce_fake_paniced) > 1) | |
277 | return; | |
278 | } | |
a0189c70 | 279 | /* First print corrected ones that are still unlogged */ |
1da177e4 | 280 | for (i = 0; i < MCE_LOG_LEN; i++) { |
a0189c70 | 281 | struct mce *m = &mcelog.entry[i]; |
77e26cca HS |
282 | if (!(m->status & MCI_STATUS_VAL)) |
283 | continue; | |
482908b4 | 284 | if (!(m->status & MCI_STATUS_UC)) { |
77e26cca | 285 | print_mce(m); |
482908b4 HY |
286 | if (!apei_err) |
287 | apei_err = apei_write_mce(m); | |
288 | } | |
a0189c70 AK |
289 | } |
290 | /* Now print uncorrected but with the final one last */ | |
291 | for (i = 0; i < MCE_LOG_LEN; i++) { | |
292 | struct mce *m = &mcelog.entry[i]; | |
293 | if (!(m->status & MCI_STATUS_VAL)) | |
1da177e4 | 294 | continue; |
77e26cca HS |
295 | if (!(m->status & MCI_STATUS_UC)) |
296 | continue; | |
482908b4 | 297 | if (!final || memcmp(m, final, sizeof(struct mce))) { |
77e26cca | 298 | print_mce(m); |
482908b4 HY |
299 | if (!apei_err) |
300 | apei_err = apei_write_mce(m); | |
301 | } | |
1da177e4 | 302 | } |
482908b4 | 303 | if (final) { |
77e26cca | 304 | print_mce(final); |
482908b4 HY |
305 | if (!apei_err) |
306 | apei_err = apei_write_mce(final); | |
307 | } | |
3c079792 | 308 | if (cpu_missing) |
a2d7b0d4 | 309 | pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n"); |
bd19a5e6 | 310 | if (exp) |
a2d7b0d4 | 311 | pr_emerg(HW_ERR "Machine check: %s\n", exp); |
bf783f9f HY |
312 | if (!fake_panic) { |
313 | if (panic_timeout == 0) | |
314 | panic_timeout = mce_panic_timeout; | |
315 | panic(msg); | |
316 | } else | |
a2d7b0d4 | 317 | pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg); |
d88203d1 | 318 | } |
1da177e4 | 319 | |
ea149b36 AK |
320 | /* Support code for software error injection */ |
321 | ||
322 | static int msr_to_offset(u32 msr) | |
323 | { | |
0a3aee0d | 324 | unsigned bank = __this_cpu_read(injectm.bank); |
f436f8bb | 325 | |
ea149b36 AK |
326 | if (msr == rip_msr) |
327 | return offsetof(struct mce, ip); | |
a2d32bcb | 328 | if (msr == MSR_IA32_MCx_STATUS(bank)) |
ea149b36 | 329 | return offsetof(struct mce, status); |
a2d32bcb | 330 | if (msr == MSR_IA32_MCx_ADDR(bank)) |
ea149b36 | 331 | return offsetof(struct mce, addr); |
a2d32bcb | 332 | if (msr == MSR_IA32_MCx_MISC(bank)) |
ea149b36 AK |
333 | return offsetof(struct mce, misc); |
334 | if (msr == MSR_IA32_MCG_STATUS) | |
335 | return offsetof(struct mce, mcgstatus); | |
336 | return -1; | |
337 | } | |
338 | ||
5f8c1a54 AK |
339 | /* MSR access wrappers used for error injection */ |
340 | static u64 mce_rdmsrl(u32 msr) | |
341 | { | |
342 | u64 v; | |
11868a2d | 343 | |
0a3aee0d | 344 | if (__this_cpu_read(injectm.finished)) { |
ea149b36 | 345 | int offset = msr_to_offset(msr); |
11868a2d | 346 | |
ea149b36 AK |
347 | if (offset < 0) |
348 | return 0; | |
349 | return *(u64 *)((char *)&__get_cpu_var(injectm) + offset); | |
350 | } | |
11868a2d IM |
351 | |
352 | if (rdmsrl_safe(msr, &v)) { | |
353 | WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr); | |
354 | /* | |
355 | * Return zero in case the access faulted. This should | |
356 | * not happen normally but can happen if the CPU does | |
357 | * something weird, or if the code is buggy. | |
358 | */ | |
359 | v = 0; | |
360 | } | |
361 | ||
5f8c1a54 AK |
362 | return v; |
363 | } | |
364 | ||
365 | static void mce_wrmsrl(u32 msr, u64 v) | |
366 | { | |
0a3aee0d | 367 | if (__this_cpu_read(injectm.finished)) { |
ea149b36 | 368 | int offset = msr_to_offset(msr); |
11868a2d | 369 | |
ea149b36 AK |
370 | if (offset >= 0) |
371 | *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v; | |
372 | return; | |
373 | } | |
5f8c1a54 AK |
374 | wrmsrl(msr, v); |
375 | } | |
376 | ||
b8325c5b HS |
377 | /* |
378 | * Collect all global (w.r.t. this processor) status about this machine | |
379 | * check into our "mce" struct so that we can use it later to assess | |
380 | * the severity of the problem as we read per-bank specific details. | |
381 | */ | |
382 | static inline void mce_gather_info(struct mce *m, struct pt_regs *regs) | |
383 | { | |
384 | mce_setup(m); | |
385 | ||
386 | m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); | |
387 | if (regs) { | |
388 | /* | |
389 | * Get the address of the instruction at the time of | |
390 | * the machine check error. | |
391 | */ | |
392 | if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) { | |
393 | m->ip = regs->ip; | |
394 | m->cs = regs->cs; | |
395 | } | |
396 | /* Use accurate RIP reporting if available. */ | |
397 | if (rip_msr) | |
398 | m->ip = mce_rdmsrl(rip_msr); | |
399 | } | |
400 | } | |
401 | ||
9b1beaf2 AK |
402 | /* |
403 | * Simple lockless ring to communicate PFNs from the exception handler with the | |
404 | * process context work function. This is vastly simplified because there's | |
405 | * only a single reader and a single writer. | |
406 | */ | |
407 | #define MCE_RING_SIZE 16 /* we use one entry less */ | |
408 | ||
409 | struct mce_ring { | |
410 | unsigned short start; | |
411 | unsigned short end; | |
412 | unsigned long ring[MCE_RING_SIZE]; | |
413 | }; | |
414 | static DEFINE_PER_CPU(struct mce_ring, mce_ring); | |
415 | ||
416 | /* Runs with CPU affinity in workqueue */ | |
417 | static int mce_ring_empty(void) | |
418 | { | |
419 | struct mce_ring *r = &__get_cpu_var(mce_ring); | |
420 | ||
421 | return r->start == r->end; | |
422 | } | |
423 | ||
424 | static int mce_ring_get(unsigned long *pfn) | |
425 | { | |
426 | struct mce_ring *r; | |
427 | int ret = 0; | |
428 | ||
429 | *pfn = 0; | |
430 | get_cpu(); | |
431 | r = &__get_cpu_var(mce_ring); | |
432 | if (r->start == r->end) | |
433 | goto out; | |
434 | *pfn = r->ring[r->start]; | |
435 | r->start = (r->start + 1) % MCE_RING_SIZE; | |
436 | ret = 1; | |
437 | out: | |
438 | put_cpu(); | |
439 | return ret; | |
440 | } | |
441 | ||
442 | /* Always runs in MCE context with preempt off */ | |
443 | static int mce_ring_add(unsigned long pfn) | |
444 | { | |
445 | struct mce_ring *r = &__get_cpu_var(mce_ring); | |
446 | unsigned next; | |
447 | ||
448 | next = (r->end + 1) % MCE_RING_SIZE; | |
449 | if (next == r->start) | |
450 | return -1; | |
451 | r->ring[r->end] = pfn; | |
452 | wmb(); | |
453 | r->end = next; | |
454 | return 0; | |
455 | } | |
456 | ||
88ccbedd | 457 | int mce_available(struct cpuinfo_x86 *c) |
1da177e4 | 458 | { |
04b2b1a4 | 459 | if (mce_disabled) |
5b4408fd | 460 | return 0; |
3d1712c9 | 461 | return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); |
1da177e4 LT |
462 | } |
463 | ||
9b1beaf2 AK |
464 | static void mce_schedule_work(void) |
465 | { | |
466 | if (!mce_ring_empty()) { | |
467 | struct work_struct *work = &__get_cpu_var(mce_work); | |
468 | if (!work_pending(work)) | |
469 | schedule_work(work); | |
470 | } | |
471 | } | |
472 | ||
b77e70bf HS |
473 | DEFINE_PER_CPU(struct irq_work, mce_irq_work); |
474 | ||
475 | static void mce_irq_work_cb(struct irq_work *entry) | |
ccc3c319 | 476 | { |
9ff36ee9 | 477 | mce_notify_irq(); |
9b1beaf2 | 478 | mce_schedule_work(); |
ccc3c319 | 479 | } |
ccc3c319 AK |
480 | |
481 | static void mce_report_event(struct pt_regs *regs) | |
482 | { | |
483 | if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) { | |
9ff36ee9 | 484 | mce_notify_irq(); |
9b1beaf2 AK |
485 | /* |
486 | * Triggering the work queue here is just an insurance | |
487 | * policy in case the syscall exit notify handler | |
488 | * doesn't run soon enough or ends up running on the | |
489 | * wrong CPU (can happen when audit sleeps) | |
490 | */ | |
491 | mce_schedule_work(); | |
ccc3c319 AK |
492 | return; |
493 | } | |
494 | ||
b77e70bf | 495 | irq_work_queue(&__get_cpu_var(mce_irq_work)); |
ccc3c319 AK |
496 | } |
497 | ||
ca84f696 AK |
498 | DEFINE_PER_CPU(unsigned, mce_poll_count); |
499 | ||
d88203d1 | 500 | /* |
b79109c3 AK |
501 | * Poll for corrected events or events that happened before reset. |
502 | * Those are just logged through /dev/mcelog. | |
503 | * | |
504 | * This is executed in standard interrupt context. | |
ed7290d0 AK |
505 | * |
506 | * Note: spec recommends to panic for fatal unsignalled | |
507 | * errors here. However this would be quite problematic -- | |
508 | * we would need to reimplement the Monarch handling and | |
509 | * it would mess up the exclusion between exception handler | |
510 | * and poll hander -- * so we skip this for now. | |
511 | * These cases should not happen anyways, or only when the CPU | |
512 | * is already totally * confused. In this case it's likely it will | |
513 | * not fully execute the machine check handler either. | |
b79109c3 | 514 | */ |
ee031c31 | 515 | void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) |
b79109c3 AK |
516 | { |
517 | struct mce m; | |
518 | int i; | |
519 | ||
402af0d7 | 520 | percpu_inc(mce_poll_count); |
ca84f696 | 521 | |
b8325c5b | 522 | mce_gather_info(&m, NULL); |
b79109c3 | 523 | |
b79109c3 | 524 | for (i = 0; i < banks; i++) { |
cebe1820 | 525 | if (!mce_banks[i].ctl || !test_bit(i, *b)) |
b79109c3 AK |
526 | continue; |
527 | ||
528 | m.misc = 0; | |
529 | m.addr = 0; | |
530 | m.bank = i; | |
531 | m.tsc = 0; | |
532 | ||
533 | barrier(); | |
a2d32bcb | 534 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
b79109c3 AK |
535 | if (!(m.status & MCI_STATUS_VAL)) |
536 | continue; | |
537 | ||
538 | /* | |
ed7290d0 AK |
539 | * Uncorrected or signalled events are handled by the exception |
540 | * handler when it is enabled, so don't process those here. | |
b79109c3 AK |
541 | * |
542 | * TBD do the same check for MCI_STATUS_EN here? | |
543 | */ | |
ed7290d0 AK |
544 | if (!(flags & MCP_UC) && |
545 | (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC))) | |
b79109c3 AK |
546 | continue; |
547 | ||
548 | if (m.status & MCI_STATUS_MISCV) | |
a2d32bcb | 549 | m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i)); |
b79109c3 | 550 | if (m.status & MCI_STATUS_ADDRV) |
a2d32bcb | 551 | m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i)); |
b79109c3 AK |
552 | |
553 | if (!(flags & MCP_TIMESTAMP)) | |
554 | m.tsc = 0; | |
555 | /* | |
556 | * Don't get the IP here because it's unlikely to | |
557 | * have anything to do with the actual error location. | |
558 | */ | |
62fdac59 | 559 | if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) { |
5679af4c | 560 | mce_log(&m); |
98a5ae2d | 561 | atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, &m); |
5679af4c | 562 | } |
b79109c3 AK |
563 | |
564 | /* | |
565 | * Clear state for this bank. | |
566 | */ | |
a2d32bcb | 567 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
b79109c3 AK |
568 | } |
569 | ||
570 | /* | |
571 | * Don't clear MCG_STATUS here because it's only defined for | |
572 | * exceptions. | |
573 | */ | |
88921be3 AK |
574 | |
575 | sync_core(); | |
b79109c3 | 576 | } |
ea149b36 | 577 | EXPORT_SYMBOL_GPL(machine_check_poll); |
b79109c3 | 578 | |
bd19a5e6 AK |
579 | /* |
580 | * Do a quick check if any of the events requires a panic. | |
581 | * This decides if we keep the events around or clear them. | |
582 | */ | |
583 | static int mce_no_way_out(struct mce *m, char **msg) | |
584 | { | |
585 | int i; | |
586 | ||
587 | for (i = 0; i < banks; i++) { | |
a2d32bcb | 588 | m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
bd19a5e6 AK |
589 | if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY) |
590 | return 1; | |
591 | } | |
592 | return 0; | |
593 | } | |
594 | ||
3c079792 AK |
595 | /* |
596 | * Variable to establish order between CPUs while scanning. | |
597 | * Each CPU spins initially until executing is equal its number. | |
598 | */ | |
599 | static atomic_t mce_executing; | |
600 | ||
601 | /* | |
602 | * Defines order of CPUs on entry. First CPU becomes Monarch. | |
603 | */ | |
604 | static atomic_t mce_callin; | |
605 | ||
606 | /* | |
607 | * Check if a timeout waiting for other CPUs happened. | |
608 | */ | |
609 | static int mce_timed_out(u64 *t) | |
610 | { | |
611 | /* | |
612 | * The others already did panic for some reason. | |
613 | * Bail out like in a timeout. | |
614 | * rmb() to tell the compiler that system_state | |
615 | * might have been modified by someone else. | |
616 | */ | |
617 | rmb(); | |
618 | if (atomic_read(&mce_paniced)) | |
619 | wait_for_panic(); | |
620 | if (!monarch_timeout) | |
621 | goto out; | |
622 | if ((s64)*t < SPINUNIT) { | |
623 | /* CHECKME: Make panic default for 1 too? */ | |
624 | if (tolerant < 1) | |
625 | mce_panic("Timeout synchronizing machine check over CPUs", | |
626 | NULL, NULL); | |
627 | cpu_missing = 1; | |
628 | return 1; | |
629 | } | |
630 | *t -= SPINUNIT; | |
631 | out: | |
632 | touch_nmi_watchdog(); | |
633 | return 0; | |
634 | } | |
635 | ||
636 | /* | |
637 | * The Monarch's reign. The Monarch is the CPU who entered | |
638 | * the machine check handler first. It waits for the others to | |
639 | * raise the exception too and then grades them. When any | |
640 | * error is fatal panic. Only then let the others continue. | |
641 | * | |
642 | * The other CPUs entering the MCE handler will be controlled by the | |
643 | * Monarch. They are called Subjects. | |
644 | * | |
645 | * This way we prevent any potential data corruption in a unrecoverable case | |
646 | * and also makes sure always all CPU's errors are examined. | |
647 | * | |
680b6cfd | 648 | * Also this detects the case of a machine check event coming from outer |
3c079792 AK |
649 | * space (not detected by any CPUs) In this case some external agent wants |
650 | * us to shut down, so panic too. | |
651 | * | |
652 | * The other CPUs might still decide to panic if the handler happens | |
653 | * in a unrecoverable place, but in this case the system is in a semi-stable | |
654 | * state and won't corrupt anything by itself. It's ok to let the others | |
655 | * continue for a bit first. | |
656 | * | |
657 | * All the spin loops have timeouts; when a timeout happens a CPU | |
658 | * typically elects itself to be Monarch. | |
659 | */ | |
660 | static void mce_reign(void) | |
661 | { | |
662 | int cpu; | |
663 | struct mce *m = NULL; | |
664 | int global_worst = 0; | |
665 | char *msg = NULL; | |
666 | char *nmsg = NULL; | |
667 | ||
668 | /* | |
669 | * This CPU is the Monarch and the other CPUs have run | |
670 | * through their handlers. | |
671 | * Grade the severity of the errors of all the CPUs. | |
672 | */ | |
673 | for_each_possible_cpu(cpu) { | |
674 | int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant, | |
675 | &nmsg); | |
676 | if (severity > global_worst) { | |
677 | msg = nmsg; | |
678 | global_worst = severity; | |
679 | m = &per_cpu(mces_seen, cpu); | |
680 | } | |
681 | } | |
682 | ||
683 | /* | |
684 | * Cannot recover? Panic here then. | |
685 | * This dumps all the mces in the log buffer and stops the | |
686 | * other CPUs. | |
687 | */ | |
688 | if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3) | |
ac960375 | 689 | mce_panic("Fatal Machine check", m, msg); |
3c079792 AK |
690 | |
691 | /* | |
692 | * For UC somewhere we let the CPU who detects it handle it. | |
693 | * Also must let continue the others, otherwise the handling | |
694 | * CPU could deadlock on a lock. | |
695 | */ | |
696 | ||
697 | /* | |
698 | * No machine check event found. Must be some external | |
699 | * source or one CPU is hung. Panic. | |
700 | */ | |
680b6cfd | 701 | if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3) |
3c079792 AK |
702 | mce_panic("Machine check from unknown source", NULL, NULL); |
703 | ||
704 | /* | |
705 | * Now clear all the mces_seen so that they don't reappear on | |
706 | * the next mce. | |
707 | */ | |
708 | for_each_possible_cpu(cpu) | |
709 | memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce)); | |
710 | } | |
711 | ||
712 | static atomic_t global_nwo; | |
713 | ||
714 | /* | |
715 | * Start of Monarch synchronization. This waits until all CPUs have | |
716 | * entered the exception handler and then determines if any of them | |
717 | * saw a fatal event that requires panic. Then it executes them | |
718 | * in the entry order. | |
719 | * TBD double check parallel CPU hotunplug | |
720 | */ | |
7fb06fc9 | 721 | static int mce_start(int *no_way_out) |
3c079792 | 722 | { |
7fb06fc9 | 723 | int order; |
3c079792 AK |
724 | int cpus = num_online_cpus(); |
725 | u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC; | |
726 | ||
7fb06fc9 HS |
727 | if (!timeout) |
728 | return -1; | |
3c079792 | 729 | |
7fb06fc9 | 730 | atomic_add(*no_way_out, &global_nwo); |
184e1fdf HY |
731 | /* |
732 | * global_nwo should be updated before mce_callin | |
733 | */ | |
734 | smp_wmb(); | |
a95436e4 | 735 | order = atomic_inc_return(&mce_callin); |
3c079792 AK |
736 | |
737 | /* | |
738 | * Wait for everyone. | |
739 | */ | |
740 | while (atomic_read(&mce_callin) != cpus) { | |
741 | if (mce_timed_out(&timeout)) { | |
742 | atomic_set(&global_nwo, 0); | |
7fb06fc9 | 743 | return -1; |
3c079792 AK |
744 | } |
745 | ndelay(SPINUNIT); | |
746 | } | |
747 | ||
184e1fdf HY |
748 | /* |
749 | * mce_callin should be read before global_nwo | |
750 | */ | |
751 | smp_rmb(); | |
3c079792 | 752 | |
7fb06fc9 HS |
753 | if (order == 1) { |
754 | /* | |
755 | * Monarch: Starts executing now, the others wait. | |
756 | */ | |
3c079792 | 757 | atomic_set(&mce_executing, 1); |
7fb06fc9 HS |
758 | } else { |
759 | /* | |
760 | * Subject: Now start the scanning loop one by one in | |
761 | * the original callin order. | |
762 | * This way when there are any shared banks it will be | |
763 | * only seen by one CPU before cleared, avoiding duplicates. | |
764 | */ | |
765 | while (atomic_read(&mce_executing) < order) { | |
766 | if (mce_timed_out(&timeout)) { | |
767 | atomic_set(&global_nwo, 0); | |
768 | return -1; | |
769 | } | |
770 | ndelay(SPINUNIT); | |
771 | } | |
3c079792 AK |
772 | } |
773 | ||
774 | /* | |
7fb06fc9 | 775 | * Cache the global no_way_out state. |
3c079792 | 776 | */ |
7fb06fc9 HS |
777 | *no_way_out = atomic_read(&global_nwo); |
778 | ||
779 | return order; | |
3c079792 AK |
780 | } |
781 | ||
782 | /* | |
783 | * Synchronize between CPUs after main scanning loop. | |
784 | * This invokes the bulk of the Monarch processing. | |
785 | */ | |
786 | static int mce_end(int order) | |
787 | { | |
788 | int ret = -1; | |
789 | u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC; | |
790 | ||
791 | if (!timeout) | |
792 | goto reset; | |
793 | if (order < 0) | |
794 | goto reset; | |
795 | ||
796 | /* | |
797 | * Allow others to run. | |
798 | */ | |
799 | atomic_inc(&mce_executing); | |
800 | ||
801 | if (order == 1) { | |
802 | /* CHECKME: Can this race with a parallel hotplug? */ | |
803 | int cpus = num_online_cpus(); | |
804 | ||
805 | /* | |
806 | * Monarch: Wait for everyone to go through their scanning | |
807 | * loops. | |
808 | */ | |
809 | while (atomic_read(&mce_executing) <= cpus) { | |
810 | if (mce_timed_out(&timeout)) | |
811 | goto reset; | |
812 | ndelay(SPINUNIT); | |
813 | } | |
814 | ||
815 | mce_reign(); | |
816 | barrier(); | |
817 | ret = 0; | |
818 | } else { | |
819 | /* | |
820 | * Subject: Wait for Monarch to finish. | |
821 | */ | |
822 | while (atomic_read(&mce_executing) != 0) { | |
823 | if (mce_timed_out(&timeout)) | |
824 | goto reset; | |
825 | ndelay(SPINUNIT); | |
826 | } | |
827 | ||
828 | /* | |
829 | * Don't reset anything. That's done by the Monarch. | |
830 | */ | |
831 | return 0; | |
832 | } | |
833 | ||
834 | /* | |
835 | * Reset all global state. | |
836 | */ | |
837 | reset: | |
838 | atomic_set(&global_nwo, 0); | |
839 | atomic_set(&mce_callin, 0); | |
840 | barrier(); | |
841 | ||
842 | /* | |
843 | * Let others run again. | |
844 | */ | |
845 | atomic_set(&mce_executing, 0); | |
846 | return ret; | |
847 | } | |
848 | ||
9b1beaf2 AK |
849 | /* |
850 | * Check if the address reported by the CPU is in a format we can parse. | |
851 | * It would be possible to add code for most other cases, but all would | |
852 | * be somewhat complicated (e.g. segment offset would require an instruction | |
0d2eb44f | 853 | * parser). So only support physical addresses up to page granuality for now. |
9b1beaf2 AK |
854 | */ |
855 | static int mce_usable_address(struct mce *m) | |
856 | { | |
857 | if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV)) | |
858 | return 0; | |
2b90e77e | 859 | if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT) |
9b1beaf2 | 860 | return 0; |
2b90e77e | 861 | if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS) |
9b1beaf2 AK |
862 | return 0; |
863 | return 1; | |
864 | } | |
865 | ||
3c079792 AK |
866 | static void mce_clear_state(unsigned long *toclear) |
867 | { | |
868 | int i; | |
869 | ||
870 | for (i = 0; i < banks; i++) { | |
871 | if (test_bit(i, toclear)) | |
a2d32bcb | 872 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
3c079792 AK |
873 | } |
874 | } | |
875 | ||
b79109c3 AK |
876 | /* |
877 | * The actual machine check handler. This only handles real | |
878 | * exceptions when something got corrupted coming in through int 18. | |
879 | * | |
880 | * This is executed in NMI context not subject to normal locking rules. This | |
881 | * implies that most kernel services cannot be safely used. Don't even | |
882 | * think about putting a printk in there! | |
3c079792 AK |
883 | * |
884 | * On Intel systems this is entered on all CPUs in parallel through | |
885 | * MCE broadcast. However some CPUs might be broken beyond repair, | |
886 | * so be always careful when synchronizing with others. | |
1da177e4 | 887 | */ |
e9eee03e | 888 | void do_machine_check(struct pt_regs *regs, long error_code) |
1da177e4 | 889 | { |
3c079792 | 890 | struct mce m, *final; |
1da177e4 | 891 | int i; |
3c079792 AK |
892 | int worst = 0; |
893 | int severity; | |
894 | /* | |
895 | * Establish sequential order between the CPUs entering the machine | |
896 | * check handler. | |
897 | */ | |
7fb06fc9 | 898 | int order; |
bd78432c TH |
899 | /* |
900 | * If no_way_out gets set, there is no safe way to recover from this | |
901 | * MCE. If tolerant is cranked up, we'll try anyway. | |
902 | */ | |
903 | int no_way_out = 0; | |
904 | /* | |
905 | * If kill_it gets set, there might be a way to recover from this | |
906 | * error. | |
907 | */ | |
908 | int kill_it = 0; | |
b79109c3 | 909 | DECLARE_BITMAP(toclear, MAX_NR_BANKS); |
bd19a5e6 | 910 | char *msg = "Unknown"; |
1da177e4 | 911 | |
553f265f AK |
912 | atomic_inc(&mce_entry); |
913 | ||
402af0d7 | 914 | percpu_inc(mce_exception_count); |
01ca79f1 | 915 | |
b79109c3 | 916 | if (notify_die(DIE_NMI, "machine check", regs, error_code, |
22f5991c | 917 | 18, SIGKILL) == NOTIFY_STOP) |
32561696 | 918 | goto out; |
b79109c3 | 919 | if (!banks) |
32561696 | 920 | goto out; |
1da177e4 | 921 | |
b8325c5b | 922 | mce_gather_info(&m, regs); |
b5f2fa4e | 923 | |
3c079792 AK |
924 | final = &__get_cpu_var(mces_seen); |
925 | *final = m; | |
926 | ||
680b6cfd HS |
927 | no_way_out = mce_no_way_out(&m, &msg); |
928 | ||
1da177e4 LT |
929 | barrier(); |
930 | ||
ed7290d0 AK |
931 | /* |
932 | * When no restart IP must always kill or panic. | |
933 | */ | |
934 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) | |
935 | kill_it = 1; | |
936 | ||
3c079792 AK |
937 | /* |
938 | * Go through all the banks in exclusion of the other CPUs. | |
939 | * This way we don't report duplicated events on shared banks | |
940 | * because the first one to see it will clear it. | |
941 | */ | |
7fb06fc9 | 942 | order = mce_start(&no_way_out); |
1da177e4 | 943 | for (i = 0; i < banks; i++) { |
b79109c3 | 944 | __clear_bit(i, toclear); |
cebe1820 | 945 | if (!mce_banks[i].ctl) |
1da177e4 | 946 | continue; |
d88203d1 TG |
947 | |
948 | m.misc = 0; | |
1da177e4 LT |
949 | m.addr = 0; |
950 | m.bank = i; | |
1da177e4 | 951 | |
a2d32bcb | 952 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
1da177e4 LT |
953 | if ((m.status & MCI_STATUS_VAL) == 0) |
954 | continue; | |
955 | ||
b79109c3 | 956 | /* |
ed7290d0 AK |
957 | * Non uncorrected or non signaled errors are handled by |
958 | * machine_check_poll. Leave them alone, unless this panics. | |
b79109c3 | 959 | */ |
ed7290d0 AK |
960 | if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) && |
961 | !no_way_out) | |
b79109c3 AK |
962 | continue; |
963 | ||
964 | /* | |
965 | * Set taint even when machine check was not enabled. | |
966 | */ | |
967 | add_taint(TAINT_MACHINE_CHECK); | |
968 | ||
ed7290d0 | 969 | severity = mce_severity(&m, tolerant, NULL); |
b79109c3 | 970 | |
ed7290d0 AK |
971 | /* |
972 | * When machine check was for corrected handler don't touch, | |
973 | * unless we're panicing. | |
974 | */ | |
975 | if (severity == MCE_KEEP_SEVERITY && !no_way_out) | |
976 | continue; | |
977 | __set_bit(i, toclear); | |
978 | if (severity == MCE_NO_SEVERITY) { | |
b79109c3 AK |
979 | /* |
980 | * Machine check event was not enabled. Clear, but | |
981 | * ignore. | |
982 | */ | |
983 | continue; | |
1da177e4 LT |
984 | } |
985 | ||
ed7290d0 AK |
986 | /* |
987 | * Kill on action required. | |
988 | */ | |
989 | if (severity == MCE_AR_SEVERITY) | |
990 | kill_it = 1; | |
991 | ||
1da177e4 | 992 | if (m.status & MCI_STATUS_MISCV) |
a2d32bcb | 993 | m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i)); |
1da177e4 | 994 | if (m.status & MCI_STATUS_ADDRV) |
a2d32bcb | 995 | m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i)); |
1da177e4 | 996 | |
9b1beaf2 AK |
997 | /* |
998 | * Action optional error. Queue address for later processing. | |
999 | * When the ring overflows we just ignore the AO error. | |
1000 | * RED-PEN add some logging mechanism when | |
1001 | * usable_address or mce_add_ring fails. | |
1002 | * RED-PEN don't ignore overflow for tolerant == 0 | |
1003 | */ | |
1004 | if (severity == MCE_AO_SEVERITY && mce_usable_address(&m)) | |
1005 | mce_ring_add(m.addr >> PAGE_SHIFT); | |
1006 | ||
b79109c3 | 1007 | mce_log(&m); |
1da177e4 | 1008 | |
3c079792 AK |
1009 | if (severity > worst) { |
1010 | *final = m; | |
1011 | worst = severity; | |
1da177e4 | 1012 | } |
1da177e4 LT |
1013 | } |
1014 | ||
3c079792 AK |
1015 | if (!no_way_out) |
1016 | mce_clear_state(toclear); | |
1017 | ||
e9eee03e | 1018 | /* |
3c079792 AK |
1019 | * Do most of the synchronization with other CPUs. |
1020 | * When there's any problem use only local no_way_out state. | |
e9eee03e | 1021 | */ |
3c079792 AK |
1022 | if (mce_end(order) < 0) |
1023 | no_way_out = worst >= MCE_PANIC_SEVERITY; | |
bd78432c TH |
1024 | |
1025 | /* | |
1026 | * If we have decided that we just CAN'T continue, and the user | |
e9eee03e | 1027 | * has not set tolerant to an insane level, give up and die. |
3c079792 AK |
1028 | * |
1029 | * This is mainly used in the case when the system doesn't | |
1030 | * support MCE broadcasting or it has been disabled. | |
bd78432c TH |
1031 | */ |
1032 | if (no_way_out && tolerant < 3) | |
ac960375 | 1033 | mce_panic("Fatal machine check on current CPU", final, msg); |
bd78432c TH |
1034 | |
1035 | /* | |
1036 | * If the error seems to be unrecoverable, something should be | |
1037 | * done. Try to kill as little as possible. If we can kill just | |
1038 | * one task, do that. If the user has set the tolerance very | |
1039 | * high, don't try to do anything at all. | |
1040 | */ | |
bd78432c | 1041 | |
ed7290d0 AK |
1042 | if (kill_it && tolerant < 3) |
1043 | force_sig(SIGBUS, current); | |
1da177e4 | 1044 | |
e02e68d3 TH |
1045 | /* notify userspace ASAP */ |
1046 | set_thread_flag(TIF_MCE_NOTIFY); | |
1047 | ||
3c079792 AK |
1048 | if (worst > 0) |
1049 | mce_report_event(regs); | |
5f8c1a54 | 1050 | mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); |
32561696 | 1051 | out: |
553f265f | 1052 | atomic_dec(&mce_entry); |
88921be3 | 1053 | sync_core(); |
1da177e4 | 1054 | } |
ea149b36 | 1055 | EXPORT_SYMBOL_GPL(do_machine_check); |
1da177e4 | 1056 | |
9b1beaf2 AK |
1057 | /* dummy to break dependency. actual code is in mm/memory-failure.c */ |
1058 | void __attribute__((weak)) memory_failure(unsigned long pfn, int vector) | |
1059 | { | |
1060 | printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn); | |
1061 | } | |
1062 | ||
1063 | /* | |
1064 | * Called after mce notification in process context. This code | |
1065 | * is allowed to sleep. Call the high level VM handler to process | |
1066 | * any corrupted pages. | |
1067 | * Assume that the work queue code only calls this one at a time | |
1068 | * per CPU. | |
1069 | * Note we don't disable preemption, so this code might run on the wrong | |
1070 | * CPU. In this case the event is picked up by the scheduled work queue. | |
1071 | * This is merely a fast path to expedite processing in some common | |
1072 | * cases. | |
1073 | */ | |
1074 | void mce_notify_process(void) | |
1075 | { | |
1076 | unsigned long pfn; | |
1077 | mce_notify_irq(); | |
1078 | while (mce_ring_get(&pfn)) | |
1079 | memory_failure(pfn, MCE_VECTOR); | |
1080 | } | |
1081 | ||
1082 | static void mce_process_work(struct work_struct *dummy) | |
1083 | { | |
1084 | mce_notify_process(); | |
1085 | } | |
1086 | ||
15d5f839 DZ |
1087 | #ifdef CONFIG_X86_MCE_INTEL |
1088 | /*** | |
1089 | * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog | |
676b1855 | 1090 | * @cpu: The CPU on which the event occurred. |
15d5f839 DZ |
1091 | * @status: Event status information |
1092 | * | |
1093 | * This function should be called by the thermal interrupt after the | |
1094 | * event has been processed and the decision was made to log the event | |
1095 | * further. | |
1096 | * | |
1097 | * The status parameter will be saved to the 'status' field of 'struct mce' | |
1098 | * and historically has been the register value of the | |
1099 | * MSR_IA32_THERMAL_STATUS (Intel) msr. | |
1100 | */ | |
b5f2fa4e | 1101 | void mce_log_therm_throt_event(__u64 status) |
15d5f839 DZ |
1102 | { |
1103 | struct mce m; | |
1104 | ||
b5f2fa4e | 1105 | mce_setup(&m); |
15d5f839 DZ |
1106 | m.bank = MCE_THERMAL_BANK; |
1107 | m.status = status; | |
15d5f839 DZ |
1108 | mce_log(&m); |
1109 | } | |
1110 | #endif /* CONFIG_X86_MCE_INTEL */ | |
1111 | ||
1da177e4 | 1112 | /* |
8a336b0a TH |
1113 | * Periodic polling timer for "silent" machine check errors. If the |
1114 | * poller finds an MCE, poll 2x faster. When the poller finds no more | |
1115 | * errors, poll 2x slower (up to check_interval seconds). | |
1da177e4 | 1116 | */ |
1da177e4 | 1117 | static int check_interval = 5 * 60; /* 5 minutes */ |
e9eee03e | 1118 | |
245b2e70 | 1119 | static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */ |
52d168e2 | 1120 | static DEFINE_PER_CPU(struct timer_list, mce_timer); |
1da177e4 | 1121 | |
5e09954a | 1122 | static void mce_start_timer(unsigned long data) |
1da177e4 | 1123 | { |
52d168e2 | 1124 | struct timer_list *t = &per_cpu(mce_timer, data); |
6298c512 | 1125 | int *n; |
52d168e2 AK |
1126 | |
1127 | WARN_ON(smp_processor_id() != data); | |
1128 | ||
7b543a53 | 1129 | if (mce_available(__this_cpu_ptr(&cpu_info))) { |
ee031c31 AK |
1130 | machine_check_poll(MCP_TIMESTAMP, |
1131 | &__get_cpu_var(mce_poll_banks)); | |
e9eee03e | 1132 | } |
1da177e4 LT |
1133 | |
1134 | /* | |
e02e68d3 TH |
1135 | * Alert userspace if needed. If we logged an MCE, reduce the |
1136 | * polling interval, otherwise increase the polling interval. | |
1da177e4 | 1137 | */ |
245b2e70 | 1138 | n = &__get_cpu_var(mce_next_interval); |
9ff36ee9 | 1139 | if (mce_notify_irq()) |
6298c512 | 1140 | *n = max(*n/2, HZ/100); |
14a02530 | 1141 | else |
6298c512 | 1142 | *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ)); |
e02e68d3 | 1143 | |
6298c512 | 1144 | t->expires = jiffies + *n; |
5be6066a | 1145 | add_timer_on(t, smp_processor_id()); |
e02e68d3 TH |
1146 | } |
1147 | ||
9bd98405 AK |
1148 | static void mce_do_trigger(struct work_struct *work) |
1149 | { | |
1020bcbc | 1150 | call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT); |
9bd98405 AK |
1151 | } |
1152 | ||
1153 | static DECLARE_WORK(mce_trigger_work, mce_do_trigger); | |
1154 | ||
e02e68d3 | 1155 | /* |
9bd98405 AK |
1156 | * Notify the user(s) about new machine check events. |
1157 | * Can be called from interrupt context, but not from machine check/NMI | |
1158 | * context. | |
e02e68d3 | 1159 | */ |
9ff36ee9 | 1160 | int mce_notify_irq(void) |
e02e68d3 | 1161 | { |
8457c84d AK |
1162 | /* Not more than two messages every minute */ |
1163 | static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); | |
1164 | ||
e02e68d3 | 1165 | clear_thread_flag(TIF_MCE_NOTIFY); |
e9eee03e | 1166 | |
1020bcbc | 1167 | if (test_and_clear_bit(0, &mce_need_notify)) { |
93b62c3c HS |
1168 | /* wake processes polling /dev/mcelog */ |
1169 | wake_up_interruptible(&mce_chrdev_wait); | |
9bd98405 AK |
1170 | |
1171 | /* | |
1172 | * There is no risk of missing notifications because | |
1173 | * work_pending is always cleared before the function is | |
1174 | * executed. | |
1175 | */ | |
1020bcbc | 1176 | if (mce_helper[0] && !work_pending(&mce_trigger_work)) |
9bd98405 | 1177 | schedule_work(&mce_trigger_work); |
e02e68d3 | 1178 | |
8457c84d | 1179 | if (__ratelimit(&ratelimit)) |
a2d7b0d4 | 1180 | pr_info(HW_ERR "Machine check events logged\n"); |
e02e68d3 TH |
1181 | |
1182 | return 1; | |
1da177e4 | 1183 | } |
e02e68d3 TH |
1184 | return 0; |
1185 | } | |
9ff36ee9 | 1186 | EXPORT_SYMBOL_GPL(mce_notify_irq); |
8a336b0a | 1187 | |
cffd377e | 1188 | static int __cpuinit __mcheck_cpu_mce_banks_init(void) |
cebe1820 AK |
1189 | { |
1190 | int i; | |
1191 | ||
1192 | mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL); | |
1193 | if (!mce_banks) | |
1194 | return -ENOMEM; | |
1195 | for (i = 0; i < banks; i++) { | |
1196 | struct mce_bank *b = &mce_banks[i]; | |
11868a2d | 1197 | |
cebe1820 AK |
1198 | b->ctl = -1ULL; |
1199 | b->init = 1; | |
1200 | } | |
1201 | return 0; | |
1202 | } | |
1203 | ||
d88203d1 | 1204 | /* |
1da177e4 LT |
1205 | * Initialize Machine Checks for a CPU. |
1206 | */ | |
5e09954a | 1207 | static int __cpuinit __mcheck_cpu_cap_init(void) |
1da177e4 | 1208 | { |
0d7482e3 | 1209 | unsigned b; |
e9eee03e | 1210 | u64 cap; |
1da177e4 LT |
1211 | |
1212 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
01c6680a TG |
1213 | |
1214 | b = cap & MCG_BANKCNT_MASK; | |
93ae5012 RD |
1215 | if (!banks) |
1216 | printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b); | |
b659294b | 1217 | |
0d7482e3 AK |
1218 | if (b > MAX_NR_BANKS) { |
1219 | printk(KERN_WARNING | |
1220 | "MCE: Using only %u machine check banks out of %u\n", | |
1221 | MAX_NR_BANKS, b); | |
1222 | b = MAX_NR_BANKS; | |
1223 | } | |
1224 | ||
1225 | /* Don't support asymmetric configurations today */ | |
1226 | WARN_ON(banks != 0 && b != banks); | |
1227 | banks = b; | |
cebe1820 | 1228 | if (!mce_banks) { |
cffd377e | 1229 | int err = __mcheck_cpu_mce_banks_init(); |
11868a2d | 1230 | |
cebe1820 AK |
1231 | if (err) |
1232 | return err; | |
1da177e4 | 1233 | } |
0d7482e3 | 1234 | |
94ad8474 | 1235 | /* Use accurate RIP reporting if available. */ |
01c6680a | 1236 | if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) |
94ad8474 | 1237 | rip_msr = MSR_IA32_MCG_EIP; |
1da177e4 | 1238 | |
ed7290d0 AK |
1239 | if (cap & MCG_SER_P) |
1240 | mce_ser = 1; | |
1241 | ||
0d7482e3 AK |
1242 | return 0; |
1243 | } | |
1244 | ||
5e09954a | 1245 | static void __mcheck_cpu_init_generic(void) |
0d7482e3 | 1246 | { |
e9eee03e | 1247 | mce_banks_t all_banks; |
0d7482e3 AK |
1248 | u64 cap; |
1249 | int i; | |
1250 | ||
b79109c3 AK |
1251 | /* |
1252 | * Log the machine checks left over from the previous reset. | |
1253 | */ | |
ee031c31 | 1254 | bitmap_fill(all_banks, MAX_NR_BANKS); |
5679af4c | 1255 | machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks); |
1da177e4 LT |
1256 | |
1257 | set_in_cr4(X86_CR4_MCE); | |
1258 | ||
0d7482e3 | 1259 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
1da177e4 LT |
1260 | if (cap & MCG_CTL_P) |
1261 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); | |
1262 | ||
1263 | for (i = 0; i < banks; i++) { | |
cebe1820 | 1264 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1265 | |
cebe1820 | 1266 | if (!b->init) |
06b7a7a5 | 1267 | continue; |
a2d32bcb AK |
1268 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
1269 | wrmsrl(MSR_IA32_MCx_STATUS(i), 0); | |
d88203d1 | 1270 | } |
1da177e4 LT |
1271 | } |
1272 | ||
1273 | /* Add per CPU specific workarounds here */ | |
5e09954a | 1274 | static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) |
d88203d1 | 1275 | { |
e412cd25 IM |
1276 | if (c->x86_vendor == X86_VENDOR_UNKNOWN) { |
1277 | pr_info("MCE: unknown CPU type - not enabling MCE support.\n"); | |
1278 | return -EOPNOTSUPP; | |
1279 | } | |
1280 | ||
1da177e4 | 1281 | /* This should be disabled by the BIOS, but isn't always */ |
911f6a7b | 1282 | if (c->x86_vendor == X86_VENDOR_AMD) { |
e9eee03e IM |
1283 | if (c->x86 == 15 && banks > 4) { |
1284 | /* | |
1285 | * disable GART TBL walk error reporting, which | |
1286 | * trips off incorrectly with the IOMMU & 3ware | |
1287 | * & Cerberus: | |
1288 | */ | |
cebe1820 | 1289 | clear_bit(10, (unsigned long *)&mce_banks[4].ctl); |
e9eee03e IM |
1290 | } |
1291 | if (c->x86 <= 17 && mce_bootlog < 0) { | |
1292 | /* | |
1293 | * Lots of broken BIOS around that don't clear them | |
1294 | * by default and leave crap in there. Don't log: | |
1295 | */ | |
911f6a7b | 1296 | mce_bootlog = 0; |
e9eee03e | 1297 | } |
2e6f694f AK |
1298 | /* |
1299 | * Various K7s with broken bank 0 around. Always disable | |
1300 | * by default. | |
1301 | */ | |
203abd67 | 1302 | if (c->x86 == 6 && banks > 0) |
cebe1820 | 1303 | mce_banks[0].ctl = 0; |
1da177e4 | 1304 | } |
e583538f | 1305 | |
06b7a7a5 AK |
1306 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
1307 | /* | |
1308 | * SDM documents that on family 6 bank 0 should not be written | |
1309 | * because it aliases to another special BIOS controlled | |
1310 | * register. | |
1311 | * But it's not aliased anymore on model 0x1a+ | |
1312 | * Don't ignore bank 0 completely because there could be a | |
1313 | * valid event later, merely don't write CTL0. | |
1314 | */ | |
1315 | ||
cebe1820 AK |
1316 | if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0) |
1317 | mce_banks[0].init = 0; | |
3c079792 AK |
1318 | |
1319 | /* | |
1320 | * All newer Intel systems support MCE broadcasting. Enable | |
1321 | * synchronization with a one second timeout. | |
1322 | */ | |
1323 | if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && | |
1324 | monarch_timeout < 0) | |
1325 | monarch_timeout = USEC_PER_SEC; | |
c7f6fa44 | 1326 | |
e412cd25 IM |
1327 | /* |
1328 | * There are also broken BIOSes on some Pentium M and | |
1329 | * earlier systems: | |
1330 | */ | |
1331 | if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0) | |
c7f6fa44 | 1332 | mce_bootlog = 0; |
06b7a7a5 | 1333 | } |
3c079792 AK |
1334 | if (monarch_timeout < 0) |
1335 | monarch_timeout = 0; | |
29b0f591 AK |
1336 | if (mce_bootlog != 0) |
1337 | mce_panic_timeout = 30; | |
e412cd25 IM |
1338 | |
1339 | return 0; | |
d88203d1 | 1340 | } |
1da177e4 | 1341 | |
3a97fc34 | 1342 | static int __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) |
4efc0670 AK |
1343 | { |
1344 | if (c->x86 != 5) | |
3a97fc34 HS |
1345 | return 0; |
1346 | ||
4efc0670 AK |
1347 | switch (c->x86_vendor) { |
1348 | case X86_VENDOR_INTEL: | |
c6978369 | 1349 | intel_p5_mcheck_init(c); |
3a97fc34 | 1350 | return 1; |
4efc0670 AK |
1351 | break; |
1352 | case X86_VENDOR_CENTAUR: | |
1353 | winchip_mcheck_init(c); | |
3a97fc34 | 1354 | return 1; |
4efc0670 AK |
1355 | break; |
1356 | } | |
3a97fc34 HS |
1357 | |
1358 | return 0; | |
4efc0670 AK |
1359 | } |
1360 | ||
5e09954a | 1361 | static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
1362 | { |
1363 | switch (c->x86_vendor) { | |
1364 | case X86_VENDOR_INTEL: | |
1365 | mce_intel_feature_init(c); | |
1366 | break; | |
89b831ef JS |
1367 | case X86_VENDOR_AMD: |
1368 | mce_amd_feature_init(c); | |
1369 | break; | |
1da177e4 LT |
1370 | default: |
1371 | break; | |
1372 | } | |
1373 | } | |
1374 | ||
5e09954a | 1375 | static void __mcheck_cpu_init_timer(void) |
52d168e2 AK |
1376 | { |
1377 | struct timer_list *t = &__get_cpu_var(mce_timer); | |
245b2e70 | 1378 | int *n = &__get_cpu_var(mce_next_interval); |
52d168e2 | 1379 | |
bc09effa JB |
1380 | setup_timer(t, mce_start_timer, smp_processor_id()); |
1381 | ||
62fdac59 HS |
1382 | if (mce_ignore_ce) |
1383 | return; | |
1384 | ||
6298c512 AK |
1385 | *n = check_interval * HZ; |
1386 | if (!*n) | |
52d168e2 | 1387 | return; |
6298c512 | 1388 | t->expires = round_jiffies(jiffies + *n); |
5be6066a | 1389 | add_timer_on(t, smp_processor_id()); |
52d168e2 AK |
1390 | } |
1391 | ||
9eda8cb3 AK |
1392 | /* Handle unconfigured int18 (should never happen) */ |
1393 | static void unexpected_machine_check(struct pt_regs *regs, long error_code) | |
1394 | { | |
1395 | printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n", | |
1396 | smp_processor_id()); | |
1397 | } | |
1398 | ||
1399 | /* Call the installed machine check handler for this CPU setup. */ | |
1400 | void (*machine_check_vector)(struct pt_regs *, long error_code) = | |
1401 | unexpected_machine_check; | |
1402 | ||
d88203d1 | 1403 | /* |
1da177e4 | 1404 | * Called for each booted CPU to set up machine checks. |
e9eee03e | 1405 | * Must be called with preempt off: |
1da177e4 | 1406 | */ |
5e09954a | 1407 | void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c) |
1da177e4 | 1408 | { |
4efc0670 AK |
1409 | if (mce_disabled) |
1410 | return; | |
1411 | ||
3a97fc34 HS |
1412 | if (__mcheck_cpu_ancient_init(c)) |
1413 | return; | |
4efc0670 | 1414 | |
5b4408fd | 1415 | if (!mce_available(c)) |
1da177e4 LT |
1416 | return; |
1417 | ||
5e09954a | 1418 | if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) { |
04b2b1a4 | 1419 | mce_disabled = 1; |
0d7482e3 AK |
1420 | return; |
1421 | } | |
0d7482e3 | 1422 | |
5d727926 AK |
1423 | machine_check_vector = do_machine_check; |
1424 | ||
5e09954a BP |
1425 | __mcheck_cpu_init_generic(); |
1426 | __mcheck_cpu_init_vendor(c); | |
1427 | __mcheck_cpu_init_timer(); | |
9b1beaf2 | 1428 | INIT_WORK(&__get_cpu_var(mce_work), mce_process_work); |
b77e70bf | 1429 | init_irq_work(&__get_cpu_var(mce_irq_work), &mce_irq_work_cb); |
1da177e4 LT |
1430 | } |
1431 | ||
1432 | /* | |
93b62c3c | 1433 | * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log. |
1da177e4 LT |
1434 | */ |
1435 | ||
93b62c3c HS |
1436 | static DEFINE_SPINLOCK(mce_chrdev_state_lock); |
1437 | static int mce_chrdev_open_count; /* #times opened */ | |
1438 | static int mce_chrdev_open_exclu; /* already open exclusive? */ | |
f528e7ba | 1439 | |
93b62c3c | 1440 | static int mce_chrdev_open(struct inode *inode, struct file *file) |
f528e7ba | 1441 | { |
93b62c3c | 1442 | spin_lock(&mce_chrdev_state_lock); |
f528e7ba | 1443 | |
93b62c3c HS |
1444 | if (mce_chrdev_open_exclu || |
1445 | (mce_chrdev_open_count && (file->f_flags & O_EXCL))) { | |
1446 | spin_unlock(&mce_chrdev_state_lock); | |
e9eee03e | 1447 | |
f528e7ba TH |
1448 | return -EBUSY; |
1449 | } | |
1450 | ||
1451 | if (file->f_flags & O_EXCL) | |
93b62c3c HS |
1452 | mce_chrdev_open_exclu = 1; |
1453 | mce_chrdev_open_count++; | |
f528e7ba | 1454 | |
93b62c3c | 1455 | spin_unlock(&mce_chrdev_state_lock); |
f528e7ba | 1456 | |
bd78432c | 1457 | return nonseekable_open(inode, file); |
f528e7ba TH |
1458 | } |
1459 | ||
93b62c3c | 1460 | static int mce_chrdev_release(struct inode *inode, struct file *file) |
f528e7ba | 1461 | { |
93b62c3c | 1462 | spin_lock(&mce_chrdev_state_lock); |
f528e7ba | 1463 | |
93b62c3c HS |
1464 | mce_chrdev_open_count--; |
1465 | mce_chrdev_open_exclu = 0; | |
f528e7ba | 1466 | |
93b62c3c | 1467 | spin_unlock(&mce_chrdev_state_lock); |
f528e7ba TH |
1468 | |
1469 | return 0; | |
1470 | } | |
1471 | ||
d88203d1 TG |
1472 | static void collect_tscs(void *data) |
1473 | { | |
1da177e4 | 1474 | unsigned long *cpu_tsc = (unsigned long *)data; |
d88203d1 | 1475 | |
1da177e4 | 1476 | rdtscll(cpu_tsc[smp_processor_id()]); |
d88203d1 | 1477 | } |
1da177e4 | 1478 | |
482908b4 HY |
1479 | static int mce_apei_read_done; |
1480 | ||
1481 | /* Collect MCE record of previous boot in persistent storage via APEI ERST. */ | |
1482 | static int __mce_read_apei(char __user **ubuf, size_t usize) | |
1483 | { | |
1484 | int rc; | |
1485 | u64 record_id; | |
1486 | struct mce m; | |
1487 | ||
1488 | if (usize < sizeof(struct mce)) | |
1489 | return -EINVAL; | |
1490 | ||
1491 | rc = apei_read_mce(&m, &record_id); | |
1492 | /* Error or no more MCE record */ | |
1493 | if (rc <= 0) { | |
1494 | mce_apei_read_done = 1; | |
1495 | return rc; | |
1496 | } | |
1497 | rc = -EFAULT; | |
1498 | if (copy_to_user(*ubuf, &m, sizeof(struct mce))) | |
1499 | return rc; | |
1500 | /* | |
1501 | * In fact, we should have cleared the record after that has | |
1502 | * been flushed to the disk or sent to network in | |
1503 | * /sbin/mcelog, but we have no interface to support that now, | |
1504 | * so just clear it to avoid duplication. | |
1505 | */ | |
1506 | rc = apei_clear_mce(record_id); | |
1507 | if (rc) { | |
1508 | mce_apei_read_done = 1; | |
1509 | return rc; | |
1510 | } | |
1511 | *ubuf += sizeof(struct mce); | |
1512 | ||
1513 | return 0; | |
1514 | } | |
1515 | ||
93b62c3c HS |
1516 | static ssize_t mce_chrdev_read(struct file *filp, char __user *ubuf, |
1517 | size_t usize, loff_t *off) | |
1da177e4 | 1518 | { |
e9eee03e | 1519 | char __user *buf = ubuf; |
f0de53bb | 1520 | unsigned long *cpu_tsc; |
ef41df43 | 1521 | unsigned prev, next; |
1da177e4 LT |
1522 | int i, err; |
1523 | ||
6bca67f9 | 1524 | cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL); |
f0de53bb AK |
1525 | if (!cpu_tsc) |
1526 | return -ENOMEM; | |
1527 | ||
93b62c3c | 1528 | mutex_lock(&mce_chrdev_read_mutex); |
482908b4 HY |
1529 | |
1530 | if (!mce_apei_read_done) { | |
1531 | err = __mce_read_apei(&buf, usize); | |
1532 | if (err || buf != ubuf) | |
1533 | goto out; | |
1534 | } | |
1535 | ||
f56e8a07 | 1536 | next = rcu_dereference_check_mce(mcelog.next); |
1da177e4 LT |
1537 | |
1538 | /* Only supports full reads right now */ | |
482908b4 HY |
1539 | err = -EINVAL; |
1540 | if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) | |
1541 | goto out; | |
1da177e4 LT |
1542 | |
1543 | err = 0; | |
ef41df43 HY |
1544 | prev = 0; |
1545 | do { | |
1546 | for (i = prev; i < next; i++) { | |
1547 | unsigned long start = jiffies; | |
559faa6b | 1548 | struct mce *m = &mcelog.entry[i]; |
ef41df43 | 1549 | |
559faa6b | 1550 | while (!m->finished) { |
ef41df43 | 1551 | if (time_after_eq(jiffies, start + 2)) { |
559faa6b | 1552 | memset(m, 0, sizeof(*m)); |
ef41df43 HY |
1553 | goto timeout; |
1554 | } | |
1555 | cpu_relax(); | |
673242c1 | 1556 | } |
ef41df43 | 1557 | smp_rmb(); |
559faa6b HS |
1558 | err |= copy_to_user(buf, m, sizeof(*m)); |
1559 | buf += sizeof(*m); | |
ef41df43 HY |
1560 | timeout: |
1561 | ; | |
673242c1 | 1562 | } |
1da177e4 | 1563 | |
ef41df43 HY |
1564 | memset(mcelog.entry + prev, 0, |
1565 | (next - prev) * sizeof(struct mce)); | |
1566 | prev = next; | |
1567 | next = cmpxchg(&mcelog.next, prev, 0); | |
1568 | } while (next != prev); | |
1da177e4 | 1569 | |
b2b18660 | 1570 | synchronize_sched(); |
1da177e4 | 1571 | |
d88203d1 TG |
1572 | /* |
1573 | * Collect entries that were still getting written before the | |
1574 | * synchronize. | |
1575 | */ | |
15c8b6c1 | 1576 | on_each_cpu(collect_tscs, cpu_tsc, 1); |
e9eee03e | 1577 | |
d88203d1 | 1578 | for (i = next; i < MCE_LOG_LEN; i++) { |
559faa6b HS |
1579 | struct mce *m = &mcelog.entry[i]; |
1580 | ||
1581 | if (m->finished && m->tsc < cpu_tsc[m->cpu]) { | |
1582 | err |= copy_to_user(buf, m, sizeof(*m)); | |
1da177e4 | 1583 | smp_rmb(); |
559faa6b HS |
1584 | buf += sizeof(*m); |
1585 | memset(m, 0, sizeof(*m)); | |
1da177e4 | 1586 | } |
d88203d1 | 1587 | } |
482908b4 HY |
1588 | |
1589 | if (err) | |
1590 | err = -EFAULT; | |
1591 | ||
1592 | out: | |
93b62c3c | 1593 | mutex_unlock(&mce_chrdev_read_mutex); |
f0de53bb | 1594 | kfree(cpu_tsc); |
e9eee03e | 1595 | |
482908b4 | 1596 | return err ? err : buf - ubuf; |
1da177e4 LT |
1597 | } |
1598 | ||
93b62c3c | 1599 | static unsigned int mce_chrdev_poll(struct file *file, poll_table *wait) |
e02e68d3 | 1600 | { |
93b62c3c | 1601 | poll_wait(file, &mce_chrdev_wait, wait); |
a4dd9925 | 1602 | if (rcu_access_index(mcelog.next)) |
e02e68d3 | 1603 | return POLLIN | POLLRDNORM; |
482908b4 HY |
1604 | if (!mce_apei_read_done && apei_check_mce()) |
1605 | return POLLIN | POLLRDNORM; | |
e02e68d3 TH |
1606 | return 0; |
1607 | } | |
1608 | ||
93b62c3c HS |
1609 | static long mce_chrdev_ioctl(struct file *f, unsigned int cmd, |
1610 | unsigned long arg) | |
1da177e4 LT |
1611 | { |
1612 | int __user *p = (int __user *)arg; | |
d88203d1 | 1613 | |
1da177e4 | 1614 | if (!capable(CAP_SYS_ADMIN)) |
d88203d1 | 1615 | return -EPERM; |
e9eee03e | 1616 | |
1da177e4 | 1617 | switch (cmd) { |
d88203d1 | 1618 | case MCE_GET_RECORD_LEN: |
1da177e4 LT |
1619 | return put_user(sizeof(struct mce), p); |
1620 | case MCE_GET_LOG_LEN: | |
d88203d1 | 1621 | return put_user(MCE_LOG_LEN, p); |
1da177e4 LT |
1622 | case MCE_GETCLEAR_FLAGS: { |
1623 | unsigned flags; | |
d88203d1 TG |
1624 | |
1625 | do { | |
1da177e4 | 1626 | flags = mcelog.flags; |
d88203d1 | 1627 | } while (cmpxchg(&mcelog.flags, flags, 0) != flags); |
e9eee03e | 1628 | |
d88203d1 | 1629 | return put_user(flags, p); |
1da177e4 LT |
1630 | } |
1631 | default: | |
d88203d1 TG |
1632 | return -ENOTTY; |
1633 | } | |
1da177e4 LT |
1634 | } |
1635 | ||
a1ff41bf | 1636 | /* Modified in mce-inject.c, so not static or const */ |
ea149b36 | 1637 | struct file_operations mce_chrdev_ops = { |
93b62c3c HS |
1638 | .open = mce_chrdev_open, |
1639 | .release = mce_chrdev_release, | |
1640 | .read = mce_chrdev_read, | |
1641 | .poll = mce_chrdev_poll, | |
1642 | .unlocked_ioctl = mce_chrdev_ioctl, | |
1643 | .llseek = no_llseek, | |
1da177e4 | 1644 | }; |
ea149b36 | 1645 | EXPORT_SYMBOL_GPL(mce_chrdev_ops); |
1da177e4 | 1646 | |
93b62c3c | 1647 | static struct miscdevice mce_chrdev_device = { |
1da177e4 LT |
1648 | MISC_MCELOG_MINOR, |
1649 | "mcelog", | |
1650 | &mce_chrdev_ops, | |
1651 | }; | |
1652 | ||
13503fa9 | 1653 | /* |
62fdac59 HS |
1654 | * mce=off Disables machine check |
1655 | * mce=no_cmci Disables CMCI | |
1656 | * mce=dont_log_ce Clears corrected events silently, no log created for CEs. | |
1657 | * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared. | |
3c079792 AK |
1658 | * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above) |
1659 | * monarchtimeout is how long to wait for other CPUs on machine | |
1660 | * check, or 0 to not wait | |
13503fa9 HS |
1661 | * mce=bootlog Log MCEs from before booting. Disabled by default on AMD. |
1662 | * mce=nobootlog Don't log MCEs from before booting. | |
1663 | */ | |
1da177e4 LT |
1664 | static int __init mcheck_enable(char *str) |
1665 | { | |
e3346fc4 | 1666 | if (*str == 0) { |
4efc0670 | 1667 | enable_p5_mce(); |
e3346fc4 BZ |
1668 | return 1; |
1669 | } | |
4efc0670 AK |
1670 | if (*str == '=') |
1671 | str++; | |
1da177e4 | 1672 | if (!strcmp(str, "off")) |
04b2b1a4 | 1673 | mce_disabled = 1; |
62fdac59 HS |
1674 | else if (!strcmp(str, "no_cmci")) |
1675 | mce_cmci_disabled = 1; | |
1676 | else if (!strcmp(str, "dont_log_ce")) | |
1677 | mce_dont_log_ce = 1; | |
1678 | else if (!strcmp(str, "ignore_ce")) | |
1679 | mce_ignore_ce = 1; | |
13503fa9 HS |
1680 | else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) |
1681 | mce_bootlog = (str[0] == 'b'); | |
3c079792 | 1682 | else if (isdigit(str[0])) { |
8c566ef5 | 1683 | get_option(&str, &tolerant); |
3c079792 AK |
1684 | if (*str == ',') { |
1685 | ++str; | |
1686 | get_option(&str, &monarch_timeout); | |
1687 | } | |
1688 | } else { | |
4efc0670 | 1689 | printk(KERN_INFO "mce argument %s ignored. Please use /sys\n", |
13503fa9 HS |
1690 | str); |
1691 | return 0; | |
1692 | } | |
9b41046c | 1693 | return 1; |
1da177e4 | 1694 | } |
4efc0670 | 1695 | __setup("mce", mcheck_enable); |
1da177e4 | 1696 | |
a2202aa2 | 1697 | int __init mcheck_init(void) |
b33a6363 | 1698 | { |
a2202aa2 YW |
1699 | mcheck_intel_therm_init(); |
1700 | ||
b33a6363 BP |
1701 | return 0; |
1702 | } | |
b33a6363 | 1703 | |
d88203d1 | 1704 | /* |
c7cece89 | 1705 | * mce_syscore: PM support |
d88203d1 | 1706 | */ |
1da177e4 | 1707 | |
973a2dd1 AK |
1708 | /* |
1709 | * Disable machine checks on suspend and shutdown. We can't really handle | |
1710 | * them later. | |
1711 | */ | |
5e09954a | 1712 | static int mce_disable_error_reporting(void) |
973a2dd1 AK |
1713 | { |
1714 | int i; | |
1715 | ||
06b7a7a5 | 1716 | for (i = 0; i < banks; i++) { |
cebe1820 | 1717 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1718 | |
cebe1820 | 1719 | if (b->init) |
a2d32bcb | 1720 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 1721 | } |
973a2dd1 AK |
1722 | return 0; |
1723 | } | |
1724 | ||
c7cece89 | 1725 | static int mce_syscore_suspend(void) |
973a2dd1 | 1726 | { |
5e09954a | 1727 | return mce_disable_error_reporting(); |
973a2dd1 AK |
1728 | } |
1729 | ||
c7cece89 | 1730 | static void mce_syscore_shutdown(void) |
973a2dd1 | 1731 | { |
f3c6ea1b | 1732 | mce_disable_error_reporting(); |
973a2dd1 AK |
1733 | } |
1734 | ||
e9eee03e IM |
1735 | /* |
1736 | * On resume clear all MCE state. Don't want to see leftovers from the BIOS. | |
1737 | * Only one CPU is active at this time, the others get re-added later using | |
1738 | * CPU hotplug: | |
1739 | */ | |
c7cece89 | 1740 | static void mce_syscore_resume(void) |
1da177e4 | 1741 | { |
5e09954a | 1742 | __mcheck_cpu_init_generic(); |
7b543a53 | 1743 | __mcheck_cpu_init_vendor(__this_cpu_ptr(&cpu_info)); |
1da177e4 LT |
1744 | } |
1745 | ||
f3c6ea1b | 1746 | static struct syscore_ops mce_syscore_ops = { |
c7cece89 HS |
1747 | .suspend = mce_syscore_suspend, |
1748 | .shutdown = mce_syscore_shutdown, | |
1749 | .resume = mce_syscore_resume, | |
f3c6ea1b RW |
1750 | }; |
1751 | ||
c7cece89 HS |
1752 | /* |
1753 | * mce_sysdev: Sysfs support | |
1754 | */ | |
1755 | ||
52d168e2 AK |
1756 | static void mce_cpu_restart(void *data) |
1757 | { | |
1758 | del_timer_sync(&__get_cpu_var(mce_timer)); | |
7b543a53 | 1759 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
33edbf02 | 1760 | return; |
5e09954a BP |
1761 | __mcheck_cpu_init_generic(); |
1762 | __mcheck_cpu_init_timer(); | |
52d168e2 AK |
1763 | } |
1764 | ||
1da177e4 | 1765 | /* Reinit MCEs after user configuration changes */ |
d88203d1 TG |
1766 | static void mce_restart(void) |
1767 | { | |
52d168e2 | 1768 | on_each_cpu(mce_cpu_restart, NULL, 1); |
1da177e4 LT |
1769 | } |
1770 | ||
9af43b54 HS |
1771 | /* Toggle features for corrected errors */ |
1772 | static void mce_disable_ce(void *all) | |
1773 | { | |
7b543a53 | 1774 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
9af43b54 HS |
1775 | return; |
1776 | if (all) | |
1777 | del_timer_sync(&__get_cpu_var(mce_timer)); | |
1778 | cmci_clear(); | |
1779 | } | |
1780 | ||
1781 | static void mce_enable_ce(void *all) | |
1782 | { | |
7b543a53 | 1783 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
9af43b54 HS |
1784 | return; |
1785 | cmci_reenable(); | |
1786 | cmci_recheck(); | |
1787 | if (all) | |
5e09954a | 1788 | __mcheck_cpu_init_timer(); |
9af43b54 HS |
1789 | } |
1790 | ||
c7cece89 | 1791 | static struct sysdev_class mce_sysdev_class = { |
e9eee03e | 1792 | .name = "machinecheck", |
1da177e4 LT |
1793 | }; |
1794 | ||
c7cece89 | 1795 | DEFINE_PER_CPU(struct sys_device, mce_sysdev); |
e9eee03e IM |
1796 | |
1797 | __cpuinitdata | |
1798 | void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); | |
1da177e4 | 1799 | |
cebe1820 AK |
1800 | static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr) |
1801 | { | |
1802 | return container_of(attr, struct mce_bank, attr); | |
1803 | } | |
0d7482e3 AK |
1804 | |
1805 | static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
1806 | char *buf) | |
1807 | { | |
cebe1820 | 1808 | return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl); |
0d7482e3 AK |
1809 | } |
1810 | ||
1811 | static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
9319cec8 | 1812 | const char *buf, size_t size) |
0d7482e3 | 1813 | { |
9319cec8 | 1814 | u64 new; |
e9eee03e | 1815 | |
9319cec8 | 1816 | if (strict_strtoull(buf, 0, &new) < 0) |
0d7482e3 | 1817 | return -EINVAL; |
e9eee03e | 1818 | |
cebe1820 | 1819 | attr_to_bank(attr)->ctl = new; |
0d7482e3 | 1820 | mce_restart(); |
e9eee03e | 1821 | |
9319cec8 | 1822 | return size; |
0d7482e3 | 1823 | } |
a98f0dd3 | 1824 | |
e9eee03e IM |
1825 | static ssize_t |
1826 | show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf) | |
a98f0dd3 | 1827 | { |
1020bcbc | 1828 | strcpy(buf, mce_helper); |
a98f0dd3 | 1829 | strcat(buf, "\n"); |
1020bcbc | 1830 | return strlen(mce_helper) + 1; |
a98f0dd3 AK |
1831 | } |
1832 | ||
4a0b2b4d | 1833 | static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr, |
e9eee03e | 1834 | const char *buf, size_t siz) |
a98f0dd3 AK |
1835 | { |
1836 | char *p; | |
e9eee03e | 1837 | |
1020bcbc HS |
1838 | strncpy(mce_helper, buf, sizeof(mce_helper)); |
1839 | mce_helper[sizeof(mce_helper)-1] = 0; | |
1020bcbc | 1840 | p = strchr(mce_helper, '\n'); |
e9eee03e | 1841 | |
e9084ec9 | 1842 | if (p) |
e9eee03e IM |
1843 | *p = 0; |
1844 | ||
e9084ec9 | 1845 | return strlen(mce_helper) + !!p; |
a98f0dd3 AK |
1846 | } |
1847 | ||
9af43b54 HS |
1848 | static ssize_t set_ignore_ce(struct sys_device *s, |
1849 | struct sysdev_attribute *attr, | |
1850 | const char *buf, size_t size) | |
1851 | { | |
1852 | u64 new; | |
1853 | ||
1854 | if (strict_strtoull(buf, 0, &new) < 0) | |
1855 | return -EINVAL; | |
1856 | ||
1857 | if (mce_ignore_ce ^ !!new) { | |
1858 | if (new) { | |
1859 | /* disable ce features */ | |
1860 | on_each_cpu(mce_disable_ce, (void *)1, 1); | |
1861 | mce_ignore_ce = 1; | |
1862 | } else { | |
1863 | /* enable ce features */ | |
1864 | mce_ignore_ce = 0; | |
1865 | on_each_cpu(mce_enable_ce, (void *)1, 1); | |
1866 | } | |
1867 | } | |
1868 | return size; | |
1869 | } | |
1870 | ||
1871 | static ssize_t set_cmci_disabled(struct sys_device *s, | |
1872 | struct sysdev_attribute *attr, | |
1873 | const char *buf, size_t size) | |
1874 | { | |
1875 | u64 new; | |
1876 | ||
1877 | if (strict_strtoull(buf, 0, &new) < 0) | |
1878 | return -EINVAL; | |
1879 | ||
1880 | if (mce_cmci_disabled ^ !!new) { | |
1881 | if (new) { | |
1882 | /* disable cmci */ | |
1883 | on_each_cpu(mce_disable_ce, NULL, 1); | |
1884 | mce_cmci_disabled = 1; | |
1885 | } else { | |
1886 | /* enable cmci */ | |
1887 | mce_cmci_disabled = 0; | |
1888 | on_each_cpu(mce_enable_ce, NULL, 1); | |
1889 | } | |
1890 | } | |
1891 | return size; | |
1892 | } | |
1893 | ||
b56f642d AK |
1894 | static ssize_t store_int_with_restart(struct sys_device *s, |
1895 | struct sysdev_attribute *attr, | |
1896 | const char *buf, size_t size) | |
1897 | { | |
1898 | ssize_t ret = sysdev_store_int(s, attr, buf, size); | |
1899 | mce_restart(); | |
1900 | return ret; | |
1901 | } | |
1902 | ||
a98f0dd3 | 1903 | static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger); |
d95d62c0 | 1904 | static SYSDEV_INT_ATTR(tolerant, 0644, tolerant); |
3c079792 | 1905 | static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout); |
9af43b54 | 1906 | static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce); |
e9eee03e | 1907 | |
b56f642d AK |
1908 | static struct sysdev_ext_attribute attr_check_interval = { |
1909 | _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int, | |
1910 | store_int_with_restart), | |
1911 | &check_interval | |
1912 | }; | |
e9eee03e | 1913 | |
9af43b54 HS |
1914 | static struct sysdev_ext_attribute attr_ignore_ce = { |
1915 | _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce), | |
1916 | &mce_ignore_ce | |
1917 | }; | |
1918 | ||
1919 | static struct sysdev_ext_attribute attr_cmci_disabled = { | |
74b602c7 | 1920 | _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled), |
9af43b54 HS |
1921 | &mce_cmci_disabled |
1922 | }; | |
1923 | ||
c7cece89 | 1924 | static struct sysdev_attribute *mce_sysdev_attrs[] = { |
9af43b54 HS |
1925 | &attr_tolerant.attr, |
1926 | &attr_check_interval.attr, | |
1927 | &attr_trigger, | |
3c079792 | 1928 | &attr_monarch_timeout.attr, |
9af43b54 HS |
1929 | &attr_dont_log_ce.attr, |
1930 | &attr_ignore_ce.attr, | |
1931 | &attr_cmci_disabled.attr, | |
a98f0dd3 AK |
1932 | NULL |
1933 | }; | |
1da177e4 | 1934 | |
c7cece89 | 1935 | static cpumask_var_t mce_sysdev_initialized; |
bae19fe0 | 1936 | |
e9eee03e | 1937 | /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */ |
c7cece89 | 1938 | static __cpuinit int mce_sysdev_create(unsigned int cpu) |
1da177e4 | 1939 | { |
c7cece89 | 1940 | struct sys_device *sysdev = &per_cpu(mce_sysdev, cpu); |
1da177e4 | 1941 | int err; |
b1f49f95 | 1942 | int i, j; |
92cb7612 | 1943 | |
90367556 | 1944 | if (!mce_available(&boot_cpu_data)) |
91c6d400 AK |
1945 | return -EIO; |
1946 | ||
f6783c42 HS |
1947 | memset(&sysdev->kobj, 0, sizeof(struct kobject)); |
1948 | sysdev->id = cpu; | |
c7cece89 | 1949 | sysdev->cls = &mce_sysdev_class; |
91c6d400 | 1950 | |
f6783c42 | 1951 | err = sysdev_register(sysdev); |
d435d862 AM |
1952 | if (err) |
1953 | return err; | |
1954 | ||
c7cece89 HS |
1955 | for (i = 0; mce_sysdev_attrs[i]; i++) { |
1956 | err = sysdev_create_file(sysdev, mce_sysdev_attrs[i]); | |
d435d862 AM |
1957 | if (err) |
1958 | goto error; | |
1959 | } | |
b1f49f95 | 1960 | for (j = 0; j < banks; j++) { |
f6783c42 | 1961 | err = sysdev_create_file(sysdev, &mce_banks[j].attr); |
0d7482e3 AK |
1962 | if (err) |
1963 | goto error2; | |
1964 | } | |
c7cece89 | 1965 | cpumask_set_cpu(cpu, mce_sysdev_initialized); |
91c6d400 | 1966 | |
d435d862 | 1967 | return 0; |
0d7482e3 | 1968 | error2: |
b1f49f95 | 1969 | while (--j >= 0) |
f6783c42 | 1970 | sysdev_remove_file(sysdev, &mce_banks[j].attr); |
d435d862 | 1971 | error: |
cb491fca | 1972 | while (--i >= 0) |
c7cece89 | 1973 | sysdev_remove_file(sysdev, mce_sysdev_attrs[i]); |
cb491fca | 1974 | |
f6783c42 | 1975 | sysdev_unregister(sysdev); |
d435d862 | 1976 | |
91c6d400 AK |
1977 | return err; |
1978 | } | |
1979 | ||
c7cece89 | 1980 | static __cpuinit void mce_sysdev_remove(unsigned int cpu) |
91c6d400 | 1981 | { |
c7cece89 | 1982 | struct sys_device *sysdev = &per_cpu(mce_sysdev, cpu); |
73ca5358 SL |
1983 | int i; |
1984 | ||
c7cece89 | 1985 | if (!cpumask_test_cpu(cpu, mce_sysdev_initialized)) |
bae19fe0 AH |
1986 | return; |
1987 | ||
c7cece89 HS |
1988 | for (i = 0; mce_sysdev_attrs[i]; i++) |
1989 | sysdev_remove_file(sysdev, mce_sysdev_attrs[i]); | |
cb491fca | 1990 | |
0d7482e3 | 1991 | for (i = 0; i < banks; i++) |
f6783c42 | 1992 | sysdev_remove_file(sysdev, &mce_banks[i].attr); |
cb491fca | 1993 | |
f6783c42 | 1994 | sysdev_unregister(sysdev); |
c7cece89 | 1995 | cpumask_clear_cpu(cpu, mce_sysdev_initialized); |
91c6d400 | 1996 | } |
91c6d400 | 1997 | |
d6b75584 | 1998 | /* Make sure there are no machine checks on offlined CPUs. */ |
767df1bd | 1999 | static void __cpuinit mce_disable_cpu(void *h) |
d6b75584 | 2000 | { |
88ccbedd | 2001 | unsigned long action = *(unsigned long *)h; |
cb491fca | 2002 | int i; |
d6b75584 | 2003 | |
7b543a53 | 2004 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
d6b75584 | 2005 | return; |
767df1bd | 2006 | |
88ccbedd AK |
2007 | if (!(action & CPU_TASKS_FROZEN)) |
2008 | cmci_clear(); | |
06b7a7a5 | 2009 | for (i = 0; i < banks; i++) { |
cebe1820 | 2010 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2011 | |
cebe1820 | 2012 | if (b->init) |
a2d32bcb | 2013 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 2014 | } |
d6b75584 AK |
2015 | } |
2016 | ||
767df1bd | 2017 | static void __cpuinit mce_reenable_cpu(void *h) |
d6b75584 | 2018 | { |
88ccbedd | 2019 | unsigned long action = *(unsigned long *)h; |
e9eee03e | 2020 | int i; |
d6b75584 | 2021 | |
7b543a53 | 2022 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
d6b75584 | 2023 | return; |
e9eee03e | 2024 | |
88ccbedd AK |
2025 | if (!(action & CPU_TASKS_FROZEN)) |
2026 | cmci_reenable(); | |
06b7a7a5 | 2027 | for (i = 0; i < banks; i++) { |
cebe1820 | 2028 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2029 | |
cebe1820 | 2030 | if (b->init) |
a2d32bcb | 2031 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
06b7a7a5 | 2032 | } |
d6b75584 AK |
2033 | } |
2034 | ||
91c6d400 | 2035 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ |
e9eee03e IM |
2036 | static int __cpuinit |
2037 | mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) | |
91c6d400 AK |
2038 | { |
2039 | unsigned int cpu = (unsigned long)hcpu; | |
52d168e2 | 2040 | struct timer_list *t = &per_cpu(mce_timer, cpu); |
91c6d400 AK |
2041 | |
2042 | switch (action) { | |
bae19fe0 AH |
2043 | case CPU_ONLINE: |
2044 | case CPU_ONLINE_FROZEN: | |
c7cece89 | 2045 | mce_sysdev_create(cpu); |
8735728e RW |
2046 | if (threshold_cpu_callback) |
2047 | threshold_cpu_callback(action, cpu); | |
91c6d400 | 2048 | break; |
91c6d400 | 2049 | case CPU_DEAD: |
8bb78442 | 2050 | case CPU_DEAD_FROZEN: |
8735728e RW |
2051 | if (threshold_cpu_callback) |
2052 | threshold_cpu_callback(action, cpu); | |
c7cece89 | 2053 | mce_sysdev_remove(cpu); |
91c6d400 | 2054 | break; |
52d168e2 AK |
2055 | case CPU_DOWN_PREPARE: |
2056 | case CPU_DOWN_PREPARE_FROZEN: | |
2057 | del_timer_sync(t); | |
88ccbedd | 2058 | smp_call_function_single(cpu, mce_disable_cpu, &action, 1); |
52d168e2 AK |
2059 | break; |
2060 | case CPU_DOWN_FAILED: | |
2061 | case CPU_DOWN_FAILED_FROZEN: | |
fe5ed91d HS |
2062 | if (!mce_ignore_ce && check_interval) { |
2063 | t->expires = round_jiffies(jiffies + | |
245b2e70 | 2064 | __get_cpu_var(mce_next_interval)); |
fe5ed91d HS |
2065 | add_timer_on(t, cpu); |
2066 | } | |
88ccbedd AK |
2067 | smp_call_function_single(cpu, mce_reenable_cpu, &action, 1); |
2068 | break; | |
2069 | case CPU_POST_DEAD: | |
2070 | /* intentionally ignoring frozen here */ | |
2071 | cmci_rediscover(cpu); | |
52d168e2 | 2072 | break; |
91c6d400 | 2073 | } |
bae19fe0 | 2074 | return NOTIFY_OK; |
91c6d400 AK |
2075 | } |
2076 | ||
1e35669d | 2077 | static struct notifier_block mce_cpu_notifier __cpuinitdata = { |
91c6d400 AK |
2078 | .notifier_call = mce_cpu_callback, |
2079 | }; | |
2080 | ||
cebe1820 | 2081 | static __init void mce_init_banks(void) |
0d7482e3 AK |
2082 | { |
2083 | int i; | |
2084 | ||
0d7482e3 | 2085 | for (i = 0; i < banks; i++) { |
cebe1820 AK |
2086 | struct mce_bank *b = &mce_banks[i]; |
2087 | struct sysdev_attribute *a = &b->attr; | |
e9eee03e | 2088 | |
a07e4156 | 2089 | sysfs_attr_init(&a->attr); |
cebe1820 AK |
2090 | a->attr.name = b->attrname; |
2091 | snprintf(b->attrname, ATTR_LEN, "bank%d", i); | |
e9eee03e IM |
2092 | |
2093 | a->attr.mode = 0644; | |
2094 | a->show = show_bank; | |
2095 | a->store = set_bank; | |
0d7482e3 | 2096 | } |
0d7482e3 AK |
2097 | } |
2098 | ||
5e09954a | 2099 | static __init int mcheck_init_device(void) |
91c6d400 AK |
2100 | { |
2101 | int err; | |
2102 | int i = 0; | |
2103 | ||
1da177e4 LT |
2104 | if (!mce_available(&boot_cpu_data)) |
2105 | return -EIO; | |
0d7482e3 | 2106 | |
c7cece89 | 2107 | zalloc_cpumask_var(&mce_sysdev_initialized, GFP_KERNEL); |
996867d0 | 2108 | |
cebe1820 | 2109 | mce_init_banks(); |
0d7482e3 | 2110 | |
c7cece89 | 2111 | err = sysdev_class_register(&mce_sysdev_class); |
d435d862 AM |
2112 | if (err) |
2113 | return err; | |
91c6d400 AK |
2114 | |
2115 | for_each_online_cpu(i) { | |
c7cece89 | 2116 | err = mce_sysdev_create(i); |
d435d862 AM |
2117 | if (err) |
2118 | return err; | |
91c6d400 AK |
2119 | } |
2120 | ||
f3c6ea1b | 2121 | register_syscore_ops(&mce_syscore_ops); |
be6b5a35 | 2122 | register_hotcpu_notifier(&mce_cpu_notifier); |
93b62c3c HS |
2123 | |
2124 | /* register character device /dev/mcelog */ | |
2125 | misc_register(&mce_chrdev_device); | |
e9eee03e | 2126 | |
1da177e4 | 2127 | return err; |
1da177e4 | 2128 | } |
5e09954a | 2129 | device_initcall(mcheck_init_device); |
a988d334 | 2130 | |
d7c3c9a6 AK |
2131 | /* |
2132 | * Old style boot options parsing. Only for compatibility. | |
2133 | */ | |
2134 | static int __init mcheck_disable(char *str) | |
2135 | { | |
2136 | mce_disabled = 1; | |
2137 | return 1; | |
2138 | } | |
2139 | __setup("nomce", mcheck_disable); | |
a988d334 | 2140 | |
5be9ed25 HY |
2141 | #ifdef CONFIG_DEBUG_FS |
2142 | struct dentry *mce_get_debugfs_dir(void) | |
a988d334 | 2143 | { |
5be9ed25 | 2144 | static struct dentry *dmce; |
a988d334 | 2145 | |
5be9ed25 HY |
2146 | if (!dmce) |
2147 | dmce = debugfs_create_dir("mce", NULL); | |
a988d334 | 2148 | |
5be9ed25 HY |
2149 | return dmce; |
2150 | } | |
a988d334 | 2151 | |
bf783f9f HY |
2152 | static void mce_reset(void) |
2153 | { | |
2154 | cpu_missing = 0; | |
2155 | atomic_set(&mce_fake_paniced, 0); | |
2156 | atomic_set(&mce_executing, 0); | |
2157 | atomic_set(&mce_callin, 0); | |
2158 | atomic_set(&global_nwo, 0); | |
2159 | } | |
a988d334 | 2160 | |
bf783f9f HY |
2161 | static int fake_panic_get(void *data, u64 *val) |
2162 | { | |
2163 | *val = fake_panic; | |
2164 | return 0; | |
a988d334 IM |
2165 | } |
2166 | ||
bf783f9f | 2167 | static int fake_panic_set(void *data, u64 val) |
a988d334 | 2168 | { |
bf783f9f HY |
2169 | mce_reset(); |
2170 | fake_panic = val; | |
2171 | return 0; | |
a988d334 | 2172 | } |
a988d334 | 2173 | |
bf783f9f HY |
2174 | DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get, |
2175 | fake_panic_set, "%llu\n"); | |
d7c3c9a6 | 2176 | |
5e09954a | 2177 | static int __init mcheck_debugfs_init(void) |
d7c3c9a6 | 2178 | { |
bf783f9f HY |
2179 | struct dentry *dmce, *ffake_panic; |
2180 | ||
2181 | dmce = mce_get_debugfs_dir(); | |
2182 | if (!dmce) | |
2183 | return -ENOMEM; | |
2184 | ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL, | |
2185 | &fake_panic_fops); | |
2186 | if (!ffake_panic) | |
2187 | return -ENOMEM; | |
2188 | ||
2189 | return 0; | |
d7c3c9a6 | 2190 | } |
5e09954a | 2191 | late_initcall(mcheck_debugfs_init); |
5be9ed25 | 2192 | #endif |