Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Machine check handler. | |
e9eee03e | 3 | * |
1da177e4 | 4 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. |
d88203d1 TG |
5 | * Rest from unknown author(s). |
6 | * 2004 Andi Kleen. Rewrote most of it. | |
b79109c3 AK |
7 | * Copyright 2008 Intel Corporation |
8 | * Author: Andi Kleen | |
1da177e4 | 9 | */ |
e9eee03e IM |
10 | #include <linux/thread_info.h> |
11 | #include <linux/capability.h> | |
12 | #include <linux/miscdevice.h> | |
ccc3c319 | 13 | #include <linux/interrupt.h> |
e9eee03e IM |
14 | #include <linux/ratelimit.h> |
15 | #include <linux/kallsyms.h> | |
16 | #include <linux/rcupdate.h> | |
e9eee03e | 17 | #include <linux/kobject.h> |
14a02530 | 18 | #include <linux/uaccess.h> |
e9eee03e IM |
19 | #include <linux/kdebug.h> |
20 | #include <linux/kernel.h> | |
21 | #include <linux/percpu.h> | |
1da177e4 | 22 | #include <linux/string.h> |
1da177e4 | 23 | #include <linux/sysdev.h> |
3c079792 | 24 | #include <linux/delay.h> |
8c566ef5 | 25 | #include <linux/ctype.h> |
e9eee03e | 26 | #include <linux/sched.h> |
0d7482e3 | 27 | #include <linux/sysfs.h> |
e9eee03e IM |
28 | #include <linux/types.h> |
29 | #include <linux/init.h> | |
30 | #include <linux/kmod.h> | |
31 | #include <linux/poll.h> | |
3c079792 | 32 | #include <linux/nmi.h> |
e9eee03e | 33 | #include <linux/cpu.h> |
14a02530 | 34 | #include <linux/smp.h> |
e9eee03e | 35 | #include <linux/fs.h> |
9b1beaf2 | 36 | #include <linux/mm.h> |
5be9ed25 | 37 | #include <linux/debugfs.h> |
e9eee03e | 38 | |
d88203d1 | 39 | #include <asm/processor.h> |
ccc3c319 AK |
40 | #include <asm/hw_irq.h> |
41 | #include <asm/apic.h> | |
e02e68d3 | 42 | #include <asm/idle.h> |
ccc3c319 | 43 | #include <asm/ipi.h> |
e9eee03e IM |
44 | #include <asm/mce.h> |
45 | #include <asm/msr.h> | |
1da177e4 | 46 | |
bd19a5e6 | 47 | #include "mce-internal.h" |
711c2e48 | 48 | |
8968f9d3 HS |
49 | #define CREATE_TRACE_POINTS |
50 | #include <trace/events/mce.h> | |
51 | ||
4e5b3e69 | 52 | int mce_disabled __read_mostly; |
04b2b1a4 | 53 | |
e9eee03e | 54 | #define MISC_MCELOG_MINOR 227 |
0d7482e3 | 55 | |
3c079792 AK |
56 | #define SPINUNIT 100 /* 100ns */ |
57 | ||
553f265f AK |
58 | atomic_t mce_entry; |
59 | ||
01ca79f1 AK |
60 | DEFINE_PER_CPU(unsigned, mce_exception_count); |
61 | ||
bd78432c TH |
62 | /* |
63 | * Tolerant levels: | |
64 | * 0: always panic on uncorrected errors, log corrected errors | |
65 | * 1: panic or SIGBUS on uncorrected errors, log corrected errors | |
66 | * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors | |
67 | * 3: never panic or SIGBUS, log all errors (for testing only) | |
68 | */ | |
4e5b3e69 HS |
69 | static int tolerant __read_mostly = 1; |
70 | static int banks __read_mostly; | |
4e5b3e69 HS |
71 | static int rip_msr __read_mostly; |
72 | static int mce_bootlog __read_mostly = -1; | |
73 | static int monarch_timeout __read_mostly = -1; | |
74 | static int mce_panic_timeout __read_mostly; | |
75 | static int mce_dont_log_ce __read_mostly; | |
76 | int mce_cmci_disabled __read_mostly; | |
77 | int mce_ignore_ce __read_mostly; | |
78 | int mce_ser __read_mostly; | |
a98f0dd3 | 79 | |
cebe1820 AK |
80 | struct mce_bank *mce_banks __read_mostly; |
81 | ||
1020bcbc HS |
82 | /* User mode helper program triggered by machine check event */ |
83 | static unsigned long mce_need_notify; | |
84 | static char mce_helper[128]; | |
85 | static char *mce_helper_argv[2] = { mce_helper, NULL }; | |
1da177e4 | 86 | |
e02e68d3 | 87 | static DECLARE_WAIT_QUEUE_HEAD(mce_wait); |
3c079792 AK |
88 | static DEFINE_PER_CPU(struct mce, mces_seen); |
89 | static int cpu_missing; | |
90 | ||
fb253195 BP |
91 | /* |
92 | * CPU/chipset specific EDAC code can register a notifier call here to print | |
93 | * MCE errors in a human-readable form. | |
94 | */ | |
95 | ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain); | |
96 | EXPORT_SYMBOL_GPL(x86_mce_decoder_chain); | |
97 | ||
98 | static int default_decode_mce(struct notifier_block *nb, unsigned long val, | |
99 | void *data) | |
f436f8bb IM |
100 | { |
101 | pr_emerg("No human readable MCE decoding support on this CPU type.\n"); | |
102 | pr_emerg("Run the message through 'mcelog --ascii' to decode.\n"); | |
fb253195 BP |
103 | |
104 | return NOTIFY_STOP; | |
f436f8bb IM |
105 | } |
106 | ||
fb253195 BP |
107 | static struct notifier_block mce_dec_nb = { |
108 | .notifier_call = default_decode_mce, | |
109 | .priority = -1, | |
110 | }; | |
e02e68d3 | 111 | |
ee031c31 AK |
112 | /* MCA banks polled by the period polling timer for corrected events */ |
113 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { | |
114 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL | |
115 | }; | |
116 | ||
9b1beaf2 AK |
117 | static DEFINE_PER_CPU(struct work_struct, mce_work); |
118 | ||
b5f2fa4e AK |
119 | /* Do initial initialization of a struct mce */ |
120 | void mce_setup(struct mce *m) | |
121 | { | |
122 | memset(m, 0, sizeof(struct mce)); | |
d620c67f | 123 | m->cpu = m->extcpu = smp_processor_id(); |
b5f2fa4e | 124 | rdtscll(m->tsc); |
8ee08347 AK |
125 | /* We hope get_seconds stays lockless */ |
126 | m->time = get_seconds(); | |
127 | m->cpuvendor = boot_cpu_data.x86_vendor; | |
128 | m->cpuid = cpuid_eax(1); | |
129 | #ifdef CONFIG_SMP | |
130 | m->socketid = cpu_data(m->extcpu).phys_proc_id; | |
131 | #endif | |
132 | m->apicid = cpu_data(m->extcpu).initial_apicid; | |
133 | rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap); | |
b5f2fa4e AK |
134 | } |
135 | ||
ea149b36 AK |
136 | DEFINE_PER_CPU(struct mce, injectm); |
137 | EXPORT_PER_CPU_SYMBOL_GPL(injectm); | |
138 | ||
1da177e4 LT |
139 | /* |
140 | * Lockless MCE logging infrastructure. | |
141 | * This avoids deadlocks on printk locks without having to break locks. Also | |
142 | * separate MCEs from kernel messages to avoid bogus bug reports. | |
143 | */ | |
144 | ||
231fd906 | 145 | static struct mce_log mcelog = { |
f6fb0ac0 AK |
146 | .signature = MCE_LOG_SIGNATURE, |
147 | .len = MCE_LOG_LEN, | |
148 | .recordlen = sizeof(struct mce), | |
d88203d1 | 149 | }; |
1da177e4 LT |
150 | |
151 | void mce_log(struct mce *mce) | |
152 | { | |
153 | unsigned next, entry; | |
e9eee03e | 154 | |
8968f9d3 HS |
155 | /* Emit the trace record: */ |
156 | trace_mce_record(mce); | |
157 | ||
1da177e4 | 158 | mce->finished = 0; |
7644143c | 159 | wmb(); |
1da177e4 LT |
160 | for (;;) { |
161 | entry = rcu_dereference(mcelog.next); | |
673242c1 | 162 | for (;;) { |
e9eee03e IM |
163 | /* |
164 | * When the buffer fills up discard new entries. | |
165 | * Assume that the earlier errors are the more | |
166 | * interesting ones: | |
167 | */ | |
673242c1 | 168 | if (entry >= MCE_LOG_LEN) { |
14a02530 HS |
169 | set_bit(MCE_OVERFLOW, |
170 | (unsigned long *)&mcelog.flags); | |
673242c1 AK |
171 | return; |
172 | } | |
e9eee03e | 173 | /* Old left over entry. Skip: */ |
673242c1 AK |
174 | if (mcelog.entry[entry].finished) { |
175 | entry++; | |
176 | continue; | |
177 | } | |
7644143c | 178 | break; |
1da177e4 | 179 | } |
1da177e4 LT |
180 | smp_rmb(); |
181 | next = entry + 1; | |
182 | if (cmpxchg(&mcelog.next, entry, next) == entry) | |
183 | break; | |
184 | } | |
185 | memcpy(mcelog.entry + entry, mce, sizeof(struct mce)); | |
7644143c | 186 | wmb(); |
1da177e4 | 187 | mcelog.entry[entry].finished = 1; |
7644143c | 188 | wmb(); |
1da177e4 | 189 | |
a0189c70 | 190 | mce->finished = 1; |
1020bcbc | 191 | set_bit(0, &mce_need_notify); |
1da177e4 LT |
192 | } |
193 | ||
77e26cca | 194 | static void print_mce(struct mce *m) |
1da177e4 | 195 | { |
f436f8bb | 196 | pr_emerg("CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n", |
d620c67f | 197 | m->extcpu, m->mcgstatus, m->bank, m->status); |
f436f8bb | 198 | |
65ea5b03 | 199 | if (m->ip) { |
f436f8bb IM |
200 | pr_emerg("RIP%s %02x:<%016Lx> ", |
201 | !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", | |
202 | m->cs, m->ip); | |
203 | ||
1da177e4 | 204 | if (m->cs == __KERNEL_CS) |
65ea5b03 | 205 | print_symbol("{%s}", m->ip); |
f436f8bb | 206 | pr_cont("\n"); |
1da177e4 | 207 | } |
f436f8bb IM |
208 | |
209 | pr_emerg("TSC %llx ", m->tsc); | |
1da177e4 | 210 | if (m->addr) |
f436f8bb | 211 | pr_cont("ADDR %llx ", m->addr); |
1da177e4 | 212 | if (m->misc) |
f436f8bb | 213 | pr_cont("MISC %llx ", m->misc); |
549d042d | 214 | |
f436f8bb IM |
215 | pr_cont("\n"); |
216 | pr_emerg("PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n", | |
217 | m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid); | |
218 | ||
219 | /* | |
220 | * Print out human-readable details about the MCE error, | |
fb253195 | 221 | * (if the CPU has an implementation for that) |
f436f8bb | 222 | */ |
fb253195 | 223 | atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m); |
86503560 AK |
224 | } |
225 | ||
77e26cca HS |
226 | static void print_mce_head(void) |
227 | { | |
f436f8bb | 228 | pr_emerg("\nHARDWARE ERROR\n"); |
77e26cca HS |
229 | } |
230 | ||
86503560 AK |
231 | static void print_mce_tail(void) |
232 | { | |
f436f8bb | 233 | pr_emerg("This is not a software problem!\n"); |
1da177e4 LT |
234 | } |
235 | ||
f94b61c2 AK |
236 | #define PANIC_TIMEOUT 5 /* 5 seconds */ |
237 | ||
238 | static atomic_t mce_paniced; | |
239 | ||
bf783f9f HY |
240 | static int fake_panic; |
241 | static atomic_t mce_fake_paniced; | |
242 | ||
f94b61c2 AK |
243 | /* Panic in progress. Enable interrupts and wait for final IPI */ |
244 | static void wait_for_panic(void) | |
245 | { | |
246 | long timeout = PANIC_TIMEOUT*USEC_PER_SEC; | |
f436f8bb | 247 | |
f94b61c2 AK |
248 | preempt_disable(); |
249 | local_irq_enable(); | |
250 | while (timeout-- > 0) | |
251 | udelay(1); | |
29b0f591 AK |
252 | if (panic_timeout == 0) |
253 | panic_timeout = mce_panic_timeout; | |
f94b61c2 AK |
254 | panic("Panicing machine check CPU died"); |
255 | } | |
256 | ||
bd19a5e6 | 257 | static void mce_panic(char *msg, struct mce *final, char *exp) |
d88203d1 | 258 | { |
1da177e4 | 259 | int i; |
e02e68d3 | 260 | |
bf783f9f HY |
261 | if (!fake_panic) { |
262 | /* | |
263 | * Make sure only one CPU runs in machine check panic | |
264 | */ | |
265 | if (atomic_inc_return(&mce_paniced) > 1) | |
266 | wait_for_panic(); | |
267 | barrier(); | |
f94b61c2 | 268 | |
bf783f9f HY |
269 | bust_spinlocks(1); |
270 | console_verbose(); | |
271 | } else { | |
272 | /* Don't log too much for fake panic */ | |
273 | if (atomic_inc_return(&mce_fake_paniced) > 1) | |
274 | return; | |
275 | } | |
77e26cca | 276 | print_mce_head(); |
a0189c70 | 277 | /* First print corrected ones that are still unlogged */ |
1da177e4 | 278 | for (i = 0; i < MCE_LOG_LEN; i++) { |
a0189c70 | 279 | struct mce *m = &mcelog.entry[i]; |
77e26cca HS |
280 | if (!(m->status & MCI_STATUS_VAL)) |
281 | continue; | |
282 | if (!(m->status & MCI_STATUS_UC)) | |
283 | print_mce(m); | |
a0189c70 AK |
284 | } |
285 | /* Now print uncorrected but with the final one last */ | |
286 | for (i = 0; i < MCE_LOG_LEN; i++) { | |
287 | struct mce *m = &mcelog.entry[i]; | |
288 | if (!(m->status & MCI_STATUS_VAL)) | |
1da177e4 | 289 | continue; |
77e26cca HS |
290 | if (!(m->status & MCI_STATUS_UC)) |
291 | continue; | |
a0189c70 | 292 | if (!final || memcmp(m, final, sizeof(struct mce))) |
77e26cca | 293 | print_mce(m); |
1da177e4 | 294 | } |
a0189c70 | 295 | if (final) |
77e26cca | 296 | print_mce(final); |
3c079792 AK |
297 | if (cpu_missing) |
298 | printk(KERN_EMERG "Some CPUs didn't answer in synchronization\n"); | |
86503560 | 299 | print_mce_tail(); |
bd19a5e6 AK |
300 | if (exp) |
301 | printk(KERN_EMERG "Machine check: %s\n", exp); | |
bf783f9f HY |
302 | if (!fake_panic) { |
303 | if (panic_timeout == 0) | |
304 | panic_timeout = mce_panic_timeout; | |
305 | panic(msg); | |
306 | } else | |
307 | printk(KERN_EMERG "Fake kernel panic: %s\n", msg); | |
d88203d1 | 308 | } |
1da177e4 | 309 | |
ea149b36 AK |
310 | /* Support code for software error injection */ |
311 | ||
312 | static int msr_to_offset(u32 msr) | |
313 | { | |
314 | unsigned bank = __get_cpu_var(injectm.bank); | |
f436f8bb | 315 | |
ea149b36 AK |
316 | if (msr == rip_msr) |
317 | return offsetof(struct mce, ip); | |
a2d32bcb | 318 | if (msr == MSR_IA32_MCx_STATUS(bank)) |
ea149b36 | 319 | return offsetof(struct mce, status); |
a2d32bcb | 320 | if (msr == MSR_IA32_MCx_ADDR(bank)) |
ea149b36 | 321 | return offsetof(struct mce, addr); |
a2d32bcb | 322 | if (msr == MSR_IA32_MCx_MISC(bank)) |
ea149b36 AK |
323 | return offsetof(struct mce, misc); |
324 | if (msr == MSR_IA32_MCG_STATUS) | |
325 | return offsetof(struct mce, mcgstatus); | |
326 | return -1; | |
327 | } | |
328 | ||
5f8c1a54 AK |
329 | /* MSR access wrappers used for error injection */ |
330 | static u64 mce_rdmsrl(u32 msr) | |
331 | { | |
332 | u64 v; | |
11868a2d | 333 | |
ea149b36 AK |
334 | if (__get_cpu_var(injectm).finished) { |
335 | int offset = msr_to_offset(msr); | |
11868a2d | 336 | |
ea149b36 AK |
337 | if (offset < 0) |
338 | return 0; | |
339 | return *(u64 *)((char *)&__get_cpu_var(injectm) + offset); | |
340 | } | |
11868a2d IM |
341 | |
342 | if (rdmsrl_safe(msr, &v)) { | |
343 | WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr); | |
344 | /* | |
345 | * Return zero in case the access faulted. This should | |
346 | * not happen normally but can happen if the CPU does | |
347 | * something weird, or if the code is buggy. | |
348 | */ | |
349 | v = 0; | |
350 | } | |
351 | ||
5f8c1a54 AK |
352 | return v; |
353 | } | |
354 | ||
355 | static void mce_wrmsrl(u32 msr, u64 v) | |
356 | { | |
ea149b36 AK |
357 | if (__get_cpu_var(injectm).finished) { |
358 | int offset = msr_to_offset(msr); | |
11868a2d | 359 | |
ea149b36 AK |
360 | if (offset >= 0) |
361 | *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v; | |
362 | return; | |
363 | } | |
5f8c1a54 AK |
364 | wrmsrl(msr, v); |
365 | } | |
366 | ||
9b1beaf2 AK |
367 | /* |
368 | * Simple lockless ring to communicate PFNs from the exception handler with the | |
369 | * process context work function. This is vastly simplified because there's | |
370 | * only a single reader and a single writer. | |
371 | */ | |
372 | #define MCE_RING_SIZE 16 /* we use one entry less */ | |
373 | ||
374 | struct mce_ring { | |
375 | unsigned short start; | |
376 | unsigned short end; | |
377 | unsigned long ring[MCE_RING_SIZE]; | |
378 | }; | |
379 | static DEFINE_PER_CPU(struct mce_ring, mce_ring); | |
380 | ||
381 | /* Runs with CPU affinity in workqueue */ | |
382 | static int mce_ring_empty(void) | |
383 | { | |
384 | struct mce_ring *r = &__get_cpu_var(mce_ring); | |
385 | ||
386 | return r->start == r->end; | |
387 | } | |
388 | ||
389 | static int mce_ring_get(unsigned long *pfn) | |
390 | { | |
391 | struct mce_ring *r; | |
392 | int ret = 0; | |
393 | ||
394 | *pfn = 0; | |
395 | get_cpu(); | |
396 | r = &__get_cpu_var(mce_ring); | |
397 | if (r->start == r->end) | |
398 | goto out; | |
399 | *pfn = r->ring[r->start]; | |
400 | r->start = (r->start + 1) % MCE_RING_SIZE; | |
401 | ret = 1; | |
402 | out: | |
403 | put_cpu(); | |
404 | return ret; | |
405 | } | |
406 | ||
407 | /* Always runs in MCE context with preempt off */ | |
408 | static int mce_ring_add(unsigned long pfn) | |
409 | { | |
410 | struct mce_ring *r = &__get_cpu_var(mce_ring); | |
411 | unsigned next; | |
412 | ||
413 | next = (r->end + 1) % MCE_RING_SIZE; | |
414 | if (next == r->start) | |
415 | return -1; | |
416 | r->ring[r->end] = pfn; | |
417 | wmb(); | |
418 | r->end = next; | |
419 | return 0; | |
420 | } | |
421 | ||
88ccbedd | 422 | int mce_available(struct cpuinfo_x86 *c) |
1da177e4 | 423 | { |
04b2b1a4 | 424 | if (mce_disabled) |
5b4408fd | 425 | return 0; |
3d1712c9 | 426 | return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); |
1da177e4 LT |
427 | } |
428 | ||
9b1beaf2 AK |
429 | static void mce_schedule_work(void) |
430 | { | |
431 | if (!mce_ring_empty()) { | |
432 | struct work_struct *work = &__get_cpu_var(mce_work); | |
433 | if (!work_pending(work)) | |
434 | schedule_work(work); | |
435 | } | |
436 | } | |
437 | ||
1b2797dc HY |
438 | /* |
439 | * Get the address of the instruction at the time of the machine check | |
440 | * error. | |
441 | */ | |
94ad8474 AK |
442 | static inline void mce_get_rip(struct mce *m, struct pt_regs *regs) |
443 | { | |
1b2797dc HY |
444 | |
445 | if (regs && (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV))) { | |
65ea5b03 | 446 | m->ip = regs->ip; |
94ad8474 AK |
447 | m->cs = regs->cs; |
448 | } else { | |
65ea5b03 | 449 | m->ip = 0; |
94ad8474 AK |
450 | m->cs = 0; |
451 | } | |
1b2797dc | 452 | if (rip_msr) |
5f8c1a54 | 453 | m->ip = mce_rdmsrl(rip_msr); |
94ad8474 AK |
454 | } |
455 | ||
11868a2d | 456 | #ifdef CONFIG_X86_LOCAL_APIC |
ccc3c319 AK |
457 | /* |
458 | * Called after interrupts have been reenabled again | |
459 | * when a MCE happened during an interrupts off region | |
460 | * in the kernel. | |
461 | */ | |
462 | asmlinkage void smp_mce_self_interrupt(struct pt_regs *regs) | |
463 | { | |
464 | ack_APIC_irq(); | |
465 | exit_idle(); | |
466 | irq_enter(); | |
9ff36ee9 | 467 | mce_notify_irq(); |
9b1beaf2 | 468 | mce_schedule_work(); |
ccc3c319 AK |
469 | irq_exit(); |
470 | } | |
471 | #endif | |
472 | ||
473 | static void mce_report_event(struct pt_regs *regs) | |
474 | { | |
475 | if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) { | |
9ff36ee9 | 476 | mce_notify_irq(); |
9b1beaf2 AK |
477 | /* |
478 | * Triggering the work queue here is just an insurance | |
479 | * policy in case the syscall exit notify handler | |
480 | * doesn't run soon enough or ends up running on the | |
481 | * wrong CPU (can happen when audit sleeps) | |
482 | */ | |
483 | mce_schedule_work(); | |
ccc3c319 AK |
484 | return; |
485 | } | |
486 | ||
487 | #ifdef CONFIG_X86_LOCAL_APIC | |
488 | /* | |
489 | * Without APIC do not notify. The event will be picked | |
490 | * up eventually. | |
491 | */ | |
492 | if (!cpu_has_apic) | |
493 | return; | |
494 | ||
495 | /* | |
496 | * When interrupts are disabled we cannot use | |
497 | * kernel services safely. Trigger an self interrupt | |
498 | * through the APIC to instead do the notification | |
499 | * after interrupts are reenabled again. | |
500 | */ | |
501 | apic->send_IPI_self(MCE_SELF_VECTOR); | |
502 | ||
503 | /* | |
504 | * Wait for idle afterwards again so that we don't leave the | |
505 | * APIC in a non idle state because the normal APIC writes | |
506 | * cannot exclude us. | |
507 | */ | |
508 | apic_wait_icr_idle(); | |
509 | #endif | |
510 | } | |
511 | ||
ca84f696 AK |
512 | DEFINE_PER_CPU(unsigned, mce_poll_count); |
513 | ||
d88203d1 | 514 | /* |
b79109c3 AK |
515 | * Poll for corrected events or events that happened before reset. |
516 | * Those are just logged through /dev/mcelog. | |
517 | * | |
518 | * This is executed in standard interrupt context. | |
ed7290d0 AK |
519 | * |
520 | * Note: spec recommends to panic for fatal unsignalled | |
521 | * errors here. However this would be quite problematic -- | |
522 | * we would need to reimplement the Monarch handling and | |
523 | * it would mess up the exclusion between exception handler | |
524 | * and poll hander -- * so we skip this for now. | |
525 | * These cases should not happen anyways, or only when the CPU | |
526 | * is already totally * confused. In this case it's likely it will | |
527 | * not fully execute the machine check handler either. | |
b79109c3 | 528 | */ |
ee031c31 | 529 | void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) |
b79109c3 AK |
530 | { |
531 | struct mce m; | |
532 | int i; | |
533 | ||
ca84f696 AK |
534 | __get_cpu_var(mce_poll_count)++; |
535 | ||
b79109c3 AK |
536 | mce_setup(&m); |
537 | ||
5f8c1a54 | 538 | m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); |
b79109c3 | 539 | for (i = 0; i < banks; i++) { |
cebe1820 | 540 | if (!mce_banks[i].ctl || !test_bit(i, *b)) |
b79109c3 AK |
541 | continue; |
542 | ||
543 | m.misc = 0; | |
544 | m.addr = 0; | |
545 | m.bank = i; | |
546 | m.tsc = 0; | |
547 | ||
548 | barrier(); | |
a2d32bcb | 549 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
b79109c3 AK |
550 | if (!(m.status & MCI_STATUS_VAL)) |
551 | continue; | |
552 | ||
553 | /* | |
ed7290d0 AK |
554 | * Uncorrected or signalled events are handled by the exception |
555 | * handler when it is enabled, so don't process those here. | |
b79109c3 AK |
556 | * |
557 | * TBD do the same check for MCI_STATUS_EN here? | |
558 | */ | |
ed7290d0 AK |
559 | if (!(flags & MCP_UC) && |
560 | (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC))) | |
b79109c3 AK |
561 | continue; |
562 | ||
563 | if (m.status & MCI_STATUS_MISCV) | |
a2d32bcb | 564 | m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i)); |
b79109c3 | 565 | if (m.status & MCI_STATUS_ADDRV) |
a2d32bcb | 566 | m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i)); |
b79109c3 AK |
567 | |
568 | if (!(flags & MCP_TIMESTAMP)) | |
569 | m.tsc = 0; | |
570 | /* | |
571 | * Don't get the IP here because it's unlikely to | |
572 | * have anything to do with the actual error location. | |
573 | */ | |
62fdac59 | 574 | if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) { |
5679af4c AK |
575 | mce_log(&m); |
576 | add_taint(TAINT_MACHINE_CHECK); | |
577 | } | |
b79109c3 AK |
578 | |
579 | /* | |
580 | * Clear state for this bank. | |
581 | */ | |
a2d32bcb | 582 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
b79109c3 AK |
583 | } |
584 | ||
585 | /* | |
586 | * Don't clear MCG_STATUS here because it's only defined for | |
587 | * exceptions. | |
588 | */ | |
88921be3 AK |
589 | |
590 | sync_core(); | |
b79109c3 | 591 | } |
ea149b36 | 592 | EXPORT_SYMBOL_GPL(machine_check_poll); |
b79109c3 | 593 | |
bd19a5e6 AK |
594 | /* |
595 | * Do a quick check if any of the events requires a panic. | |
596 | * This decides if we keep the events around or clear them. | |
597 | */ | |
598 | static int mce_no_way_out(struct mce *m, char **msg) | |
599 | { | |
600 | int i; | |
601 | ||
602 | for (i = 0; i < banks; i++) { | |
a2d32bcb | 603 | m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
bd19a5e6 AK |
604 | if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY) |
605 | return 1; | |
606 | } | |
607 | return 0; | |
608 | } | |
609 | ||
3c079792 AK |
610 | /* |
611 | * Variable to establish order between CPUs while scanning. | |
612 | * Each CPU spins initially until executing is equal its number. | |
613 | */ | |
614 | static atomic_t mce_executing; | |
615 | ||
616 | /* | |
617 | * Defines order of CPUs on entry. First CPU becomes Monarch. | |
618 | */ | |
619 | static atomic_t mce_callin; | |
620 | ||
621 | /* | |
622 | * Check if a timeout waiting for other CPUs happened. | |
623 | */ | |
624 | static int mce_timed_out(u64 *t) | |
625 | { | |
626 | /* | |
627 | * The others already did panic for some reason. | |
628 | * Bail out like in a timeout. | |
629 | * rmb() to tell the compiler that system_state | |
630 | * might have been modified by someone else. | |
631 | */ | |
632 | rmb(); | |
633 | if (atomic_read(&mce_paniced)) | |
634 | wait_for_panic(); | |
635 | if (!monarch_timeout) | |
636 | goto out; | |
637 | if ((s64)*t < SPINUNIT) { | |
638 | /* CHECKME: Make panic default for 1 too? */ | |
639 | if (tolerant < 1) | |
640 | mce_panic("Timeout synchronizing machine check over CPUs", | |
641 | NULL, NULL); | |
642 | cpu_missing = 1; | |
643 | return 1; | |
644 | } | |
645 | *t -= SPINUNIT; | |
646 | out: | |
647 | touch_nmi_watchdog(); | |
648 | return 0; | |
649 | } | |
650 | ||
651 | /* | |
652 | * The Monarch's reign. The Monarch is the CPU who entered | |
653 | * the machine check handler first. It waits for the others to | |
654 | * raise the exception too and then grades them. When any | |
655 | * error is fatal panic. Only then let the others continue. | |
656 | * | |
657 | * The other CPUs entering the MCE handler will be controlled by the | |
658 | * Monarch. They are called Subjects. | |
659 | * | |
660 | * This way we prevent any potential data corruption in a unrecoverable case | |
661 | * and also makes sure always all CPU's errors are examined. | |
662 | * | |
680b6cfd | 663 | * Also this detects the case of a machine check event coming from outer |
3c079792 AK |
664 | * space (not detected by any CPUs) In this case some external agent wants |
665 | * us to shut down, so panic too. | |
666 | * | |
667 | * The other CPUs might still decide to panic if the handler happens | |
668 | * in a unrecoverable place, but in this case the system is in a semi-stable | |
669 | * state and won't corrupt anything by itself. It's ok to let the others | |
670 | * continue for a bit first. | |
671 | * | |
672 | * All the spin loops have timeouts; when a timeout happens a CPU | |
673 | * typically elects itself to be Monarch. | |
674 | */ | |
675 | static void mce_reign(void) | |
676 | { | |
677 | int cpu; | |
678 | struct mce *m = NULL; | |
679 | int global_worst = 0; | |
680 | char *msg = NULL; | |
681 | char *nmsg = NULL; | |
682 | ||
683 | /* | |
684 | * This CPU is the Monarch and the other CPUs have run | |
685 | * through their handlers. | |
686 | * Grade the severity of the errors of all the CPUs. | |
687 | */ | |
688 | for_each_possible_cpu(cpu) { | |
689 | int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant, | |
690 | &nmsg); | |
691 | if (severity > global_worst) { | |
692 | msg = nmsg; | |
693 | global_worst = severity; | |
694 | m = &per_cpu(mces_seen, cpu); | |
695 | } | |
696 | } | |
697 | ||
698 | /* | |
699 | * Cannot recover? Panic here then. | |
700 | * This dumps all the mces in the log buffer and stops the | |
701 | * other CPUs. | |
702 | */ | |
703 | if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3) | |
ac960375 | 704 | mce_panic("Fatal Machine check", m, msg); |
3c079792 AK |
705 | |
706 | /* | |
707 | * For UC somewhere we let the CPU who detects it handle it. | |
708 | * Also must let continue the others, otherwise the handling | |
709 | * CPU could deadlock on a lock. | |
710 | */ | |
711 | ||
712 | /* | |
713 | * No machine check event found. Must be some external | |
714 | * source or one CPU is hung. Panic. | |
715 | */ | |
680b6cfd | 716 | if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3) |
3c079792 AK |
717 | mce_panic("Machine check from unknown source", NULL, NULL); |
718 | ||
719 | /* | |
720 | * Now clear all the mces_seen so that they don't reappear on | |
721 | * the next mce. | |
722 | */ | |
723 | for_each_possible_cpu(cpu) | |
724 | memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce)); | |
725 | } | |
726 | ||
727 | static atomic_t global_nwo; | |
728 | ||
729 | /* | |
730 | * Start of Monarch synchronization. This waits until all CPUs have | |
731 | * entered the exception handler and then determines if any of them | |
732 | * saw a fatal event that requires panic. Then it executes them | |
733 | * in the entry order. | |
734 | * TBD double check parallel CPU hotunplug | |
735 | */ | |
7fb06fc9 | 736 | static int mce_start(int *no_way_out) |
3c079792 | 737 | { |
7fb06fc9 | 738 | int order; |
3c079792 AK |
739 | int cpus = num_online_cpus(); |
740 | u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC; | |
741 | ||
7fb06fc9 HS |
742 | if (!timeout) |
743 | return -1; | |
3c079792 | 744 | |
7fb06fc9 | 745 | atomic_add(*no_way_out, &global_nwo); |
184e1fdf HY |
746 | /* |
747 | * global_nwo should be updated before mce_callin | |
748 | */ | |
749 | smp_wmb(); | |
a95436e4 | 750 | order = atomic_inc_return(&mce_callin); |
3c079792 AK |
751 | |
752 | /* | |
753 | * Wait for everyone. | |
754 | */ | |
755 | while (atomic_read(&mce_callin) != cpus) { | |
756 | if (mce_timed_out(&timeout)) { | |
757 | atomic_set(&global_nwo, 0); | |
7fb06fc9 | 758 | return -1; |
3c079792 AK |
759 | } |
760 | ndelay(SPINUNIT); | |
761 | } | |
762 | ||
184e1fdf HY |
763 | /* |
764 | * mce_callin should be read before global_nwo | |
765 | */ | |
766 | smp_rmb(); | |
3c079792 | 767 | |
7fb06fc9 HS |
768 | if (order == 1) { |
769 | /* | |
770 | * Monarch: Starts executing now, the others wait. | |
771 | */ | |
3c079792 | 772 | atomic_set(&mce_executing, 1); |
7fb06fc9 HS |
773 | } else { |
774 | /* | |
775 | * Subject: Now start the scanning loop one by one in | |
776 | * the original callin order. | |
777 | * This way when there are any shared banks it will be | |
778 | * only seen by one CPU before cleared, avoiding duplicates. | |
779 | */ | |
780 | while (atomic_read(&mce_executing) < order) { | |
781 | if (mce_timed_out(&timeout)) { | |
782 | atomic_set(&global_nwo, 0); | |
783 | return -1; | |
784 | } | |
785 | ndelay(SPINUNIT); | |
786 | } | |
3c079792 AK |
787 | } |
788 | ||
789 | /* | |
7fb06fc9 | 790 | * Cache the global no_way_out state. |
3c079792 | 791 | */ |
7fb06fc9 HS |
792 | *no_way_out = atomic_read(&global_nwo); |
793 | ||
794 | return order; | |
3c079792 AK |
795 | } |
796 | ||
797 | /* | |
798 | * Synchronize between CPUs after main scanning loop. | |
799 | * This invokes the bulk of the Monarch processing. | |
800 | */ | |
801 | static int mce_end(int order) | |
802 | { | |
803 | int ret = -1; | |
804 | u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC; | |
805 | ||
806 | if (!timeout) | |
807 | goto reset; | |
808 | if (order < 0) | |
809 | goto reset; | |
810 | ||
811 | /* | |
812 | * Allow others to run. | |
813 | */ | |
814 | atomic_inc(&mce_executing); | |
815 | ||
816 | if (order == 1) { | |
817 | /* CHECKME: Can this race with a parallel hotplug? */ | |
818 | int cpus = num_online_cpus(); | |
819 | ||
820 | /* | |
821 | * Monarch: Wait for everyone to go through their scanning | |
822 | * loops. | |
823 | */ | |
824 | while (atomic_read(&mce_executing) <= cpus) { | |
825 | if (mce_timed_out(&timeout)) | |
826 | goto reset; | |
827 | ndelay(SPINUNIT); | |
828 | } | |
829 | ||
830 | mce_reign(); | |
831 | barrier(); | |
832 | ret = 0; | |
833 | } else { | |
834 | /* | |
835 | * Subject: Wait for Monarch to finish. | |
836 | */ | |
837 | while (atomic_read(&mce_executing) != 0) { | |
838 | if (mce_timed_out(&timeout)) | |
839 | goto reset; | |
840 | ndelay(SPINUNIT); | |
841 | } | |
842 | ||
843 | /* | |
844 | * Don't reset anything. That's done by the Monarch. | |
845 | */ | |
846 | return 0; | |
847 | } | |
848 | ||
849 | /* | |
850 | * Reset all global state. | |
851 | */ | |
852 | reset: | |
853 | atomic_set(&global_nwo, 0); | |
854 | atomic_set(&mce_callin, 0); | |
855 | barrier(); | |
856 | ||
857 | /* | |
858 | * Let others run again. | |
859 | */ | |
860 | atomic_set(&mce_executing, 0); | |
861 | return ret; | |
862 | } | |
863 | ||
9b1beaf2 AK |
864 | /* |
865 | * Check if the address reported by the CPU is in a format we can parse. | |
866 | * It would be possible to add code for most other cases, but all would | |
867 | * be somewhat complicated (e.g. segment offset would require an instruction | |
868 | * parser). So only support physical addresses upto page granuality for now. | |
869 | */ | |
870 | static int mce_usable_address(struct mce *m) | |
871 | { | |
872 | if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV)) | |
873 | return 0; | |
874 | if ((m->misc & 0x3f) > PAGE_SHIFT) | |
875 | return 0; | |
876 | if (((m->misc >> 6) & 7) != MCM_ADDR_PHYS) | |
877 | return 0; | |
878 | return 1; | |
879 | } | |
880 | ||
3c079792 AK |
881 | static void mce_clear_state(unsigned long *toclear) |
882 | { | |
883 | int i; | |
884 | ||
885 | for (i = 0; i < banks; i++) { | |
886 | if (test_bit(i, toclear)) | |
a2d32bcb | 887 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
3c079792 AK |
888 | } |
889 | } | |
890 | ||
b79109c3 AK |
891 | /* |
892 | * The actual machine check handler. This only handles real | |
893 | * exceptions when something got corrupted coming in through int 18. | |
894 | * | |
895 | * This is executed in NMI context not subject to normal locking rules. This | |
896 | * implies that most kernel services cannot be safely used. Don't even | |
897 | * think about putting a printk in there! | |
3c079792 AK |
898 | * |
899 | * On Intel systems this is entered on all CPUs in parallel through | |
900 | * MCE broadcast. However some CPUs might be broken beyond repair, | |
901 | * so be always careful when synchronizing with others. | |
1da177e4 | 902 | */ |
e9eee03e | 903 | void do_machine_check(struct pt_regs *regs, long error_code) |
1da177e4 | 904 | { |
3c079792 | 905 | struct mce m, *final; |
1da177e4 | 906 | int i; |
3c079792 AK |
907 | int worst = 0; |
908 | int severity; | |
909 | /* | |
910 | * Establish sequential order between the CPUs entering the machine | |
911 | * check handler. | |
912 | */ | |
7fb06fc9 | 913 | int order; |
bd78432c TH |
914 | /* |
915 | * If no_way_out gets set, there is no safe way to recover from this | |
916 | * MCE. If tolerant is cranked up, we'll try anyway. | |
917 | */ | |
918 | int no_way_out = 0; | |
919 | /* | |
920 | * If kill_it gets set, there might be a way to recover from this | |
921 | * error. | |
922 | */ | |
923 | int kill_it = 0; | |
b79109c3 | 924 | DECLARE_BITMAP(toclear, MAX_NR_BANKS); |
bd19a5e6 | 925 | char *msg = "Unknown"; |
1da177e4 | 926 | |
553f265f AK |
927 | atomic_inc(&mce_entry); |
928 | ||
01ca79f1 AK |
929 | __get_cpu_var(mce_exception_count)++; |
930 | ||
b79109c3 | 931 | if (notify_die(DIE_NMI, "machine check", regs, error_code, |
22f5991c | 932 | 18, SIGKILL) == NOTIFY_STOP) |
32561696 | 933 | goto out; |
b79109c3 | 934 | if (!banks) |
32561696 | 935 | goto out; |
1da177e4 | 936 | |
b5f2fa4e AK |
937 | mce_setup(&m); |
938 | ||
5f8c1a54 | 939 | m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); |
3c079792 AK |
940 | final = &__get_cpu_var(mces_seen); |
941 | *final = m; | |
942 | ||
680b6cfd HS |
943 | no_way_out = mce_no_way_out(&m, &msg); |
944 | ||
1da177e4 LT |
945 | barrier(); |
946 | ||
ed7290d0 AK |
947 | /* |
948 | * When no restart IP must always kill or panic. | |
949 | */ | |
950 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) | |
951 | kill_it = 1; | |
952 | ||
3c079792 AK |
953 | /* |
954 | * Go through all the banks in exclusion of the other CPUs. | |
955 | * This way we don't report duplicated events on shared banks | |
956 | * because the first one to see it will clear it. | |
957 | */ | |
7fb06fc9 | 958 | order = mce_start(&no_way_out); |
1da177e4 | 959 | for (i = 0; i < banks; i++) { |
b79109c3 | 960 | __clear_bit(i, toclear); |
cebe1820 | 961 | if (!mce_banks[i].ctl) |
1da177e4 | 962 | continue; |
d88203d1 TG |
963 | |
964 | m.misc = 0; | |
1da177e4 LT |
965 | m.addr = 0; |
966 | m.bank = i; | |
1da177e4 | 967 | |
a2d32bcb | 968 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
1da177e4 LT |
969 | if ((m.status & MCI_STATUS_VAL) == 0) |
970 | continue; | |
971 | ||
b79109c3 | 972 | /* |
ed7290d0 AK |
973 | * Non uncorrected or non signaled errors are handled by |
974 | * machine_check_poll. Leave them alone, unless this panics. | |
b79109c3 | 975 | */ |
ed7290d0 AK |
976 | if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) && |
977 | !no_way_out) | |
b79109c3 AK |
978 | continue; |
979 | ||
980 | /* | |
981 | * Set taint even when machine check was not enabled. | |
982 | */ | |
983 | add_taint(TAINT_MACHINE_CHECK); | |
984 | ||
ed7290d0 | 985 | severity = mce_severity(&m, tolerant, NULL); |
b79109c3 | 986 | |
ed7290d0 AK |
987 | /* |
988 | * When machine check was for corrected handler don't touch, | |
989 | * unless we're panicing. | |
990 | */ | |
991 | if (severity == MCE_KEEP_SEVERITY && !no_way_out) | |
992 | continue; | |
993 | __set_bit(i, toclear); | |
994 | if (severity == MCE_NO_SEVERITY) { | |
b79109c3 AK |
995 | /* |
996 | * Machine check event was not enabled. Clear, but | |
997 | * ignore. | |
998 | */ | |
999 | continue; | |
1da177e4 LT |
1000 | } |
1001 | ||
ed7290d0 AK |
1002 | /* |
1003 | * Kill on action required. | |
1004 | */ | |
1005 | if (severity == MCE_AR_SEVERITY) | |
1006 | kill_it = 1; | |
1007 | ||
1da177e4 | 1008 | if (m.status & MCI_STATUS_MISCV) |
a2d32bcb | 1009 | m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i)); |
1da177e4 | 1010 | if (m.status & MCI_STATUS_ADDRV) |
a2d32bcb | 1011 | m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i)); |
1da177e4 | 1012 | |
9b1beaf2 AK |
1013 | /* |
1014 | * Action optional error. Queue address for later processing. | |
1015 | * When the ring overflows we just ignore the AO error. | |
1016 | * RED-PEN add some logging mechanism when | |
1017 | * usable_address or mce_add_ring fails. | |
1018 | * RED-PEN don't ignore overflow for tolerant == 0 | |
1019 | */ | |
1020 | if (severity == MCE_AO_SEVERITY && mce_usable_address(&m)) | |
1021 | mce_ring_add(m.addr >> PAGE_SHIFT); | |
1022 | ||
94ad8474 | 1023 | mce_get_rip(&m, regs); |
b79109c3 | 1024 | mce_log(&m); |
1da177e4 | 1025 | |
3c079792 AK |
1026 | if (severity > worst) { |
1027 | *final = m; | |
1028 | worst = severity; | |
1da177e4 | 1029 | } |
1da177e4 LT |
1030 | } |
1031 | ||
3c079792 AK |
1032 | if (!no_way_out) |
1033 | mce_clear_state(toclear); | |
1034 | ||
e9eee03e | 1035 | /* |
3c079792 AK |
1036 | * Do most of the synchronization with other CPUs. |
1037 | * When there's any problem use only local no_way_out state. | |
e9eee03e | 1038 | */ |
3c079792 AK |
1039 | if (mce_end(order) < 0) |
1040 | no_way_out = worst >= MCE_PANIC_SEVERITY; | |
bd78432c TH |
1041 | |
1042 | /* | |
1043 | * If we have decided that we just CAN'T continue, and the user | |
e9eee03e | 1044 | * has not set tolerant to an insane level, give up and die. |
3c079792 AK |
1045 | * |
1046 | * This is mainly used in the case when the system doesn't | |
1047 | * support MCE broadcasting or it has been disabled. | |
bd78432c TH |
1048 | */ |
1049 | if (no_way_out && tolerant < 3) | |
ac960375 | 1050 | mce_panic("Fatal machine check on current CPU", final, msg); |
bd78432c TH |
1051 | |
1052 | /* | |
1053 | * If the error seems to be unrecoverable, something should be | |
1054 | * done. Try to kill as little as possible. If we can kill just | |
1055 | * one task, do that. If the user has set the tolerance very | |
1056 | * high, don't try to do anything at all. | |
1057 | */ | |
bd78432c | 1058 | |
ed7290d0 AK |
1059 | if (kill_it && tolerant < 3) |
1060 | force_sig(SIGBUS, current); | |
1da177e4 | 1061 | |
e02e68d3 TH |
1062 | /* notify userspace ASAP */ |
1063 | set_thread_flag(TIF_MCE_NOTIFY); | |
1064 | ||
3c079792 AK |
1065 | if (worst > 0) |
1066 | mce_report_event(regs); | |
5f8c1a54 | 1067 | mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); |
32561696 | 1068 | out: |
553f265f | 1069 | atomic_dec(&mce_entry); |
88921be3 | 1070 | sync_core(); |
1da177e4 | 1071 | } |
ea149b36 | 1072 | EXPORT_SYMBOL_GPL(do_machine_check); |
1da177e4 | 1073 | |
9b1beaf2 AK |
1074 | /* dummy to break dependency. actual code is in mm/memory-failure.c */ |
1075 | void __attribute__((weak)) memory_failure(unsigned long pfn, int vector) | |
1076 | { | |
1077 | printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn); | |
1078 | } | |
1079 | ||
1080 | /* | |
1081 | * Called after mce notification in process context. This code | |
1082 | * is allowed to sleep. Call the high level VM handler to process | |
1083 | * any corrupted pages. | |
1084 | * Assume that the work queue code only calls this one at a time | |
1085 | * per CPU. | |
1086 | * Note we don't disable preemption, so this code might run on the wrong | |
1087 | * CPU. In this case the event is picked up by the scheduled work queue. | |
1088 | * This is merely a fast path to expedite processing in some common | |
1089 | * cases. | |
1090 | */ | |
1091 | void mce_notify_process(void) | |
1092 | { | |
1093 | unsigned long pfn; | |
1094 | mce_notify_irq(); | |
1095 | while (mce_ring_get(&pfn)) | |
1096 | memory_failure(pfn, MCE_VECTOR); | |
1097 | } | |
1098 | ||
1099 | static void mce_process_work(struct work_struct *dummy) | |
1100 | { | |
1101 | mce_notify_process(); | |
1102 | } | |
1103 | ||
15d5f839 DZ |
1104 | #ifdef CONFIG_X86_MCE_INTEL |
1105 | /*** | |
1106 | * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog | |
676b1855 | 1107 | * @cpu: The CPU on which the event occurred. |
15d5f839 DZ |
1108 | * @status: Event status information |
1109 | * | |
1110 | * This function should be called by the thermal interrupt after the | |
1111 | * event has been processed and the decision was made to log the event | |
1112 | * further. | |
1113 | * | |
1114 | * The status parameter will be saved to the 'status' field of 'struct mce' | |
1115 | * and historically has been the register value of the | |
1116 | * MSR_IA32_THERMAL_STATUS (Intel) msr. | |
1117 | */ | |
b5f2fa4e | 1118 | void mce_log_therm_throt_event(__u64 status) |
15d5f839 DZ |
1119 | { |
1120 | struct mce m; | |
1121 | ||
b5f2fa4e | 1122 | mce_setup(&m); |
15d5f839 DZ |
1123 | m.bank = MCE_THERMAL_BANK; |
1124 | m.status = status; | |
15d5f839 DZ |
1125 | mce_log(&m); |
1126 | } | |
1127 | #endif /* CONFIG_X86_MCE_INTEL */ | |
1128 | ||
1da177e4 | 1129 | /* |
8a336b0a TH |
1130 | * Periodic polling timer for "silent" machine check errors. If the |
1131 | * poller finds an MCE, poll 2x faster. When the poller finds no more | |
1132 | * errors, poll 2x slower (up to check_interval seconds). | |
1da177e4 | 1133 | */ |
1da177e4 | 1134 | static int check_interval = 5 * 60; /* 5 minutes */ |
e9eee03e | 1135 | |
245b2e70 | 1136 | static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */ |
52d168e2 | 1137 | static DEFINE_PER_CPU(struct timer_list, mce_timer); |
1da177e4 | 1138 | |
5e09954a | 1139 | static void mce_start_timer(unsigned long data) |
1da177e4 | 1140 | { |
52d168e2 | 1141 | struct timer_list *t = &per_cpu(mce_timer, data); |
6298c512 | 1142 | int *n; |
52d168e2 AK |
1143 | |
1144 | WARN_ON(smp_processor_id() != data); | |
1145 | ||
e9eee03e | 1146 | if (mce_available(¤t_cpu_data)) { |
ee031c31 AK |
1147 | machine_check_poll(MCP_TIMESTAMP, |
1148 | &__get_cpu_var(mce_poll_banks)); | |
e9eee03e | 1149 | } |
1da177e4 LT |
1150 | |
1151 | /* | |
e02e68d3 TH |
1152 | * Alert userspace if needed. If we logged an MCE, reduce the |
1153 | * polling interval, otherwise increase the polling interval. | |
1da177e4 | 1154 | */ |
245b2e70 | 1155 | n = &__get_cpu_var(mce_next_interval); |
9ff36ee9 | 1156 | if (mce_notify_irq()) |
6298c512 | 1157 | *n = max(*n/2, HZ/100); |
14a02530 | 1158 | else |
6298c512 | 1159 | *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ)); |
e02e68d3 | 1160 | |
6298c512 | 1161 | t->expires = jiffies + *n; |
5be6066a | 1162 | add_timer_on(t, smp_processor_id()); |
e02e68d3 TH |
1163 | } |
1164 | ||
9bd98405 AK |
1165 | static void mce_do_trigger(struct work_struct *work) |
1166 | { | |
1020bcbc | 1167 | call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT); |
9bd98405 AK |
1168 | } |
1169 | ||
1170 | static DECLARE_WORK(mce_trigger_work, mce_do_trigger); | |
1171 | ||
e02e68d3 | 1172 | /* |
9bd98405 AK |
1173 | * Notify the user(s) about new machine check events. |
1174 | * Can be called from interrupt context, but not from machine check/NMI | |
1175 | * context. | |
e02e68d3 | 1176 | */ |
9ff36ee9 | 1177 | int mce_notify_irq(void) |
e02e68d3 | 1178 | { |
8457c84d AK |
1179 | /* Not more than two messages every minute */ |
1180 | static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); | |
1181 | ||
e02e68d3 | 1182 | clear_thread_flag(TIF_MCE_NOTIFY); |
e9eee03e | 1183 | |
1020bcbc | 1184 | if (test_and_clear_bit(0, &mce_need_notify)) { |
e02e68d3 | 1185 | wake_up_interruptible(&mce_wait); |
9bd98405 AK |
1186 | |
1187 | /* | |
1188 | * There is no risk of missing notifications because | |
1189 | * work_pending is always cleared before the function is | |
1190 | * executed. | |
1191 | */ | |
1020bcbc | 1192 | if (mce_helper[0] && !work_pending(&mce_trigger_work)) |
9bd98405 | 1193 | schedule_work(&mce_trigger_work); |
e02e68d3 | 1194 | |
8457c84d | 1195 | if (__ratelimit(&ratelimit)) |
8a336b0a | 1196 | printk(KERN_INFO "Machine check events logged\n"); |
e02e68d3 TH |
1197 | |
1198 | return 1; | |
1da177e4 | 1199 | } |
e02e68d3 TH |
1200 | return 0; |
1201 | } | |
9ff36ee9 | 1202 | EXPORT_SYMBOL_GPL(mce_notify_irq); |
8a336b0a | 1203 | |
cebe1820 AK |
1204 | static int mce_banks_init(void) |
1205 | { | |
1206 | int i; | |
1207 | ||
1208 | mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL); | |
1209 | if (!mce_banks) | |
1210 | return -ENOMEM; | |
1211 | for (i = 0; i < banks; i++) { | |
1212 | struct mce_bank *b = &mce_banks[i]; | |
11868a2d | 1213 | |
cebe1820 AK |
1214 | b->ctl = -1ULL; |
1215 | b->init = 1; | |
1216 | } | |
1217 | return 0; | |
1218 | } | |
1219 | ||
d88203d1 | 1220 | /* |
1da177e4 LT |
1221 | * Initialize Machine Checks for a CPU. |
1222 | */ | |
5e09954a | 1223 | static int __cpuinit __mcheck_cpu_cap_init(void) |
1da177e4 | 1224 | { |
0d7482e3 | 1225 | unsigned b; |
e9eee03e | 1226 | u64 cap; |
1da177e4 LT |
1227 | |
1228 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
01c6680a TG |
1229 | |
1230 | b = cap & MCG_BANKCNT_MASK; | |
93ae5012 RD |
1231 | if (!banks) |
1232 | printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b); | |
b659294b | 1233 | |
0d7482e3 AK |
1234 | if (b > MAX_NR_BANKS) { |
1235 | printk(KERN_WARNING | |
1236 | "MCE: Using only %u machine check banks out of %u\n", | |
1237 | MAX_NR_BANKS, b); | |
1238 | b = MAX_NR_BANKS; | |
1239 | } | |
1240 | ||
1241 | /* Don't support asymmetric configurations today */ | |
1242 | WARN_ON(banks != 0 && b != banks); | |
1243 | banks = b; | |
cebe1820 AK |
1244 | if (!mce_banks) { |
1245 | int err = mce_banks_init(); | |
11868a2d | 1246 | |
cebe1820 AK |
1247 | if (err) |
1248 | return err; | |
1da177e4 | 1249 | } |
0d7482e3 | 1250 | |
94ad8474 | 1251 | /* Use accurate RIP reporting if available. */ |
01c6680a | 1252 | if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) |
94ad8474 | 1253 | rip_msr = MSR_IA32_MCG_EIP; |
1da177e4 | 1254 | |
ed7290d0 AK |
1255 | if (cap & MCG_SER_P) |
1256 | mce_ser = 1; | |
1257 | ||
0d7482e3 AK |
1258 | return 0; |
1259 | } | |
1260 | ||
5e09954a | 1261 | static void __mcheck_cpu_init_generic(void) |
0d7482e3 | 1262 | { |
e9eee03e | 1263 | mce_banks_t all_banks; |
0d7482e3 AK |
1264 | u64 cap; |
1265 | int i; | |
1266 | ||
b79109c3 AK |
1267 | /* |
1268 | * Log the machine checks left over from the previous reset. | |
1269 | */ | |
ee031c31 | 1270 | bitmap_fill(all_banks, MAX_NR_BANKS); |
5679af4c | 1271 | machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks); |
1da177e4 LT |
1272 | |
1273 | set_in_cr4(X86_CR4_MCE); | |
1274 | ||
0d7482e3 | 1275 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
1da177e4 LT |
1276 | if (cap & MCG_CTL_P) |
1277 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); | |
1278 | ||
1279 | for (i = 0; i < banks; i++) { | |
cebe1820 | 1280 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1281 | |
cebe1820 | 1282 | if (!b->init) |
06b7a7a5 | 1283 | continue; |
a2d32bcb AK |
1284 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
1285 | wrmsrl(MSR_IA32_MCx_STATUS(i), 0); | |
d88203d1 | 1286 | } |
1da177e4 LT |
1287 | } |
1288 | ||
1289 | /* Add per CPU specific workarounds here */ | |
5e09954a | 1290 | static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) |
d88203d1 | 1291 | { |
e412cd25 IM |
1292 | if (c->x86_vendor == X86_VENDOR_UNKNOWN) { |
1293 | pr_info("MCE: unknown CPU type - not enabling MCE support.\n"); | |
1294 | return -EOPNOTSUPP; | |
1295 | } | |
1296 | ||
1da177e4 | 1297 | /* This should be disabled by the BIOS, but isn't always */ |
911f6a7b | 1298 | if (c->x86_vendor == X86_VENDOR_AMD) { |
e9eee03e IM |
1299 | if (c->x86 == 15 && banks > 4) { |
1300 | /* | |
1301 | * disable GART TBL walk error reporting, which | |
1302 | * trips off incorrectly with the IOMMU & 3ware | |
1303 | * & Cerberus: | |
1304 | */ | |
cebe1820 | 1305 | clear_bit(10, (unsigned long *)&mce_banks[4].ctl); |
e9eee03e IM |
1306 | } |
1307 | if (c->x86 <= 17 && mce_bootlog < 0) { | |
1308 | /* | |
1309 | * Lots of broken BIOS around that don't clear them | |
1310 | * by default and leave crap in there. Don't log: | |
1311 | */ | |
911f6a7b | 1312 | mce_bootlog = 0; |
e9eee03e | 1313 | } |
2e6f694f AK |
1314 | /* |
1315 | * Various K7s with broken bank 0 around. Always disable | |
1316 | * by default. | |
1317 | */ | |
203abd67 | 1318 | if (c->x86 == 6 && banks > 0) |
cebe1820 | 1319 | mce_banks[0].ctl = 0; |
1da177e4 | 1320 | } |
e583538f | 1321 | |
06b7a7a5 AK |
1322 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
1323 | /* | |
1324 | * SDM documents that on family 6 bank 0 should not be written | |
1325 | * because it aliases to another special BIOS controlled | |
1326 | * register. | |
1327 | * But it's not aliased anymore on model 0x1a+ | |
1328 | * Don't ignore bank 0 completely because there could be a | |
1329 | * valid event later, merely don't write CTL0. | |
1330 | */ | |
1331 | ||
cebe1820 AK |
1332 | if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0) |
1333 | mce_banks[0].init = 0; | |
3c079792 AK |
1334 | |
1335 | /* | |
1336 | * All newer Intel systems support MCE broadcasting. Enable | |
1337 | * synchronization with a one second timeout. | |
1338 | */ | |
1339 | if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && | |
1340 | monarch_timeout < 0) | |
1341 | monarch_timeout = USEC_PER_SEC; | |
c7f6fa44 | 1342 | |
e412cd25 IM |
1343 | /* |
1344 | * There are also broken BIOSes on some Pentium M and | |
1345 | * earlier systems: | |
1346 | */ | |
1347 | if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0) | |
c7f6fa44 | 1348 | mce_bootlog = 0; |
06b7a7a5 | 1349 | } |
3c079792 AK |
1350 | if (monarch_timeout < 0) |
1351 | monarch_timeout = 0; | |
29b0f591 AK |
1352 | if (mce_bootlog != 0) |
1353 | mce_panic_timeout = 30; | |
e412cd25 IM |
1354 | |
1355 | return 0; | |
d88203d1 | 1356 | } |
1da177e4 | 1357 | |
5e09954a | 1358 | static void __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) |
4efc0670 AK |
1359 | { |
1360 | if (c->x86 != 5) | |
1361 | return; | |
1362 | switch (c->x86_vendor) { | |
1363 | case X86_VENDOR_INTEL: | |
c6978369 | 1364 | intel_p5_mcheck_init(c); |
4efc0670 AK |
1365 | break; |
1366 | case X86_VENDOR_CENTAUR: | |
1367 | winchip_mcheck_init(c); | |
1368 | break; | |
1369 | } | |
1370 | } | |
1371 | ||
5e09954a | 1372 | static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
1373 | { |
1374 | switch (c->x86_vendor) { | |
1375 | case X86_VENDOR_INTEL: | |
1376 | mce_intel_feature_init(c); | |
1377 | break; | |
89b831ef JS |
1378 | case X86_VENDOR_AMD: |
1379 | mce_amd_feature_init(c); | |
1380 | break; | |
1da177e4 LT |
1381 | default: |
1382 | break; | |
1383 | } | |
1384 | } | |
1385 | ||
5e09954a | 1386 | static void __mcheck_cpu_init_timer(void) |
52d168e2 AK |
1387 | { |
1388 | struct timer_list *t = &__get_cpu_var(mce_timer); | |
245b2e70 | 1389 | int *n = &__get_cpu_var(mce_next_interval); |
52d168e2 | 1390 | |
62fdac59 HS |
1391 | if (mce_ignore_ce) |
1392 | return; | |
1393 | ||
6298c512 AK |
1394 | *n = check_interval * HZ; |
1395 | if (!*n) | |
52d168e2 | 1396 | return; |
5e09954a | 1397 | setup_timer(t, mce_start_timer, smp_processor_id()); |
6298c512 | 1398 | t->expires = round_jiffies(jiffies + *n); |
5be6066a | 1399 | add_timer_on(t, smp_processor_id()); |
52d168e2 AK |
1400 | } |
1401 | ||
9eda8cb3 AK |
1402 | /* Handle unconfigured int18 (should never happen) */ |
1403 | static void unexpected_machine_check(struct pt_regs *regs, long error_code) | |
1404 | { | |
1405 | printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n", | |
1406 | smp_processor_id()); | |
1407 | } | |
1408 | ||
1409 | /* Call the installed machine check handler for this CPU setup. */ | |
1410 | void (*machine_check_vector)(struct pt_regs *, long error_code) = | |
1411 | unexpected_machine_check; | |
1412 | ||
d88203d1 | 1413 | /* |
1da177e4 | 1414 | * Called for each booted CPU to set up machine checks. |
e9eee03e | 1415 | * Must be called with preempt off: |
1da177e4 | 1416 | */ |
5e09954a | 1417 | void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c) |
1da177e4 | 1418 | { |
4efc0670 AK |
1419 | if (mce_disabled) |
1420 | return; | |
1421 | ||
5e09954a | 1422 | __mcheck_cpu_ancient_init(c); |
4efc0670 | 1423 | |
5b4408fd | 1424 | if (!mce_available(c)) |
1da177e4 LT |
1425 | return; |
1426 | ||
5e09954a | 1427 | if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) { |
04b2b1a4 | 1428 | mce_disabled = 1; |
0d7482e3 AK |
1429 | return; |
1430 | } | |
0d7482e3 | 1431 | |
5d727926 AK |
1432 | machine_check_vector = do_machine_check; |
1433 | ||
5e09954a BP |
1434 | __mcheck_cpu_init_generic(); |
1435 | __mcheck_cpu_init_vendor(c); | |
1436 | __mcheck_cpu_init_timer(); | |
9b1beaf2 | 1437 | INIT_WORK(&__get_cpu_var(mce_work), mce_process_work); |
fb253195 | 1438 | |
1da177e4 LT |
1439 | } |
1440 | ||
1441 | /* | |
1442 | * Character device to read and clear the MCE log. | |
1443 | */ | |
1444 | ||
f528e7ba | 1445 | static DEFINE_SPINLOCK(mce_state_lock); |
e9eee03e IM |
1446 | static int open_count; /* #times opened */ |
1447 | static int open_exclu; /* already open exclusive? */ | |
f528e7ba TH |
1448 | |
1449 | static int mce_open(struct inode *inode, struct file *file) | |
1450 | { | |
1451 | spin_lock(&mce_state_lock); | |
1452 | ||
1453 | if (open_exclu || (open_count && (file->f_flags & O_EXCL))) { | |
1454 | spin_unlock(&mce_state_lock); | |
e9eee03e | 1455 | |
f528e7ba TH |
1456 | return -EBUSY; |
1457 | } | |
1458 | ||
1459 | if (file->f_flags & O_EXCL) | |
1460 | open_exclu = 1; | |
1461 | open_count++; | |
1462 | ||
1463 | spin_unlock(&mce_state_lock); | |
1464 | ||
bd78432c | 1465 | return nonseekable_open(inode, file); |
f528e7ba TH |
1466 | } |
1467 | ||
1468 | static int mce_release(struct inode *inode, struct file *file) | |
1469 | { | |
1470 | spin_lock(&mce_state_lock); | |
1471 | ||
1472 | open_count--; | |
1473 | open_exclu = 0; | |
1474 | ||
1475 | spin_unlock(&mce_state_lock); | |
1476 | ||
1477 | return 0; | |
1478 | } | |
1479 | ||
d88203d1 TG |
1480 | static void collect_tscs(void *data) |
1481 | { | |
1da177e4 | 1482 | unsigned long *cpu_tsc = (unsigned long *)data; |
d88203d1 | 1483 | |
1da177e4 | 1484 | rdtscll(cpu_tsc[smp_processor_id()]); |
d88203d1 | 1485 | } |
1da177e4 | 1486 | |
e9eee03e IM |
1487 | static DEFINE_MUTEX(mce_read_mutex); |
1488 | ||
d88203d1 TG |
1489 | static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize, |
1490 | loff_t *off) | |
1da177e4 | 1491 | { |
e9eee03e | 1492 | char __user *buf = ubuf; |
f0de53bb | 1493 | unsigned long *cpu_tsc; |
ef41df43 | 1494 | unsigned prev, next; |
1da177e4 LT |
1495 | int i, err; |
1496 | ||
6bca67f9 | 1497 | cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL); |
f0de53bb AK |
1498 | if (!cpu_tsc) |
1499 | return -ENOMEM; | |
1500 | ||
8c8b8859 | 1501 | mutex_lock(&mce_read_mutex); |
1da177e4 LT |
1502 | next = rcu_dereference(mcelog.next); |
1503 | ||
1504 | /* Only supports full reads right now */ | |
d88203d1 | 1505 | if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) { |
8c8b8859 | 1506 | mutex_unlock(&mce_read_mutex); |
f0de53bb | 1507 | kfree(cpu_tsc); |
e9eee03e | 1508 | |
1da177e4 LT |
1509 | return -EINVAL; |
1510 | } | |
1511 | ||
1512 | err = 0; | |
ef41df43 HY |
1513 | prev = 0; |
1514 | do { | |
1515 | for (i = prev; i < next; i++) { | |
1516 | unsigned long start = jiffies; | |
1517 | ||
1518 | while (!mcelog.entry[i].finished) { | |
1519 | if (time_after_eq(jiffies, start + 2)) { | |
1520 | memset(mcelog.entry + i, 0, | |
1521 | sizeof(struct mce)); | |
1522 | goto timeout; | |
1523 | } | |
1524 | cpu_relax(); | |
673242c1 | 1525 | } |
ef41df43 HY |
1526 | smp_rmb(); |
1527 | err |= copy_to_user(buf, mcelog.entry + i, | |
1528 | sizeof(struct mce)); | |
1529 | buf += sizeof(struct mce); | |
1530 | timeout: | |
1531 | ; | |
673242c1 | 1532 | } |
1da177e4 | 1533 | |
ef41df43 HY |
1534 | memset(mcelog.entry + prev, 0, |
1535 | (next - prev) * sizeof(struct mce)); | |
1536 | prev = next; | |
1537 | next = cmpxchg(&mcelog.next, prev, 0); | |
1538 | } while (next != prev); | |
1da177e4 | 1539 | |
b2b18660 | 1540 | synchronize_sched(); |
1da177e4 | 1541 | |
d88203d1 TG |
1542 | /* |
1543 | * Collect entries that were still getting written before the | |
1544 | * synchronize. | |
1545 | */ | |
15c8b6c1 | 1546 | on_each_cpu(collect_tscs, cpu_tsc, 1); |
e9eee03e | 1547 | |
d88203d1 TG |
1548 | for (i = next; i < MCE_LOG_LEN; i++) { |
1549 | if (mcelog.entry[i].finished && | |
1550 | mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) { | |
1551 | err |= copy_to_user(buf, mcelog.entry+i, | |
1552 | sizeof(struct mce)); | |
1da177e4 LT |
1553 | smp_rmb(); |
1554 | buf += sizeof(struct mce); | |
1555 | memset(&mcelog.entry[i], 0, sizeof(struct mce)); | |
1556 | } | |
d88203d1 | 1557 | } |
8c8b8859 | 1558 | mutex_unlock(&mce_read_mutex); |
f0de53bb | 1559 | kfree(cpu_tsc); |
e9eee03e | 1560 | |
d88203d1 | 1561 | return err ? -EFAULT : buf - ubuf; |
1da177e4 LT |
1562 | } |
1563 | ||
e02e68d3 TH |
1564 | static unsigned int mce_poll(struct file *file, poll_table *wait) |
1565 | { | |
1566 | poll_wait(file, &mce_wait, wait); | |
1567 | if (rcu_dereference(mcelog.next)) | |
1568 | return POLLIN | POLLRDNORM; | |
1569 | return 0; | |
1570 | } | |
1571 | ||
c68461b6 | 1572 | static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg) |
1da177e4 LT |
1573 | { |
1574 | int __user *p = (int __user *)arg; | |
d88203d1 | 1575 | |
1da177e4 | 1576 | if (!capable(CAP_SYS_ADMIN)) |
d88203d1 | 1577 | return -EPERM; |
e9eee03e | 1578 | |
1da177e4 | 1579 | switch (cmd) { |
d88203d1 | 1580 | case MCE_GET_RECORD_LEN: |
1da177e4 LT |
1581 | return put_user(sizeof(struct mce), p); |
1582 | case MCE_GET_LOG_LEN: | |
d88203d1 | 1583 | return put_user(MCE_LOG_LEN, p); |
1da177e4 LT |
1584 | case MCE_GETCLEAR_FLAGS: { |
1585 | unsigned flags; | |
d88203d1 TG |
1586 | |
1587 | do { | |
1da177e4 | 1588 | flags = mcelog.flags; |
d88203d1 | 1589 | } while (cmpxchg(&mcelog.flags, flags, 0) != flags); |
e9eee03e | 1590 | |
d88203d1 | 1591 | return put_user(flags, p); |
1da177e4 LT |
1592 | } |
1593 | default: | |
d88203d1 TG |
1594 | return -ENOTTY; |
1595 | } | |
1da177e4 LT |
1596 | } |
1597 | ||
a1ff41bf | 1598 | /* Modified in mce-inject.c, so not static or const */ |
ea149b36 | 1599 | struct file_operations mce_chrdev_ops = { |
e9eee03e IM |
1600 | .open = mce_open, |
1601 | .release = mce_release, | |
1602 | .read = mce_read, | |
1603 | .poll = mce_poll, | |
1604 | .unlocked_ioctl = mce_ioctl, | |
1da177e4 | 1605 | }; |
ea149b36 | 1606 | EXPORT_SYMBOL_GPL(mce_chrdev_ops); |
1da177e4 LT |
1607 | |
1608 | static struct miscdevice mce_log_device = { | |
1609 | MISC_MCELOG_MINOR, | |
1610 | "mcelog", | |
1611 | &mce_chrdev_ops, | |
1612 | }; | |
1613 | ||
13503fa9 | 1614 | /* |
62fdac59 HS |
1615 | * mce=off Disables machine check |
1616 | * mce=no_cmci Disables CMCI | |
1617 | * mce=dont_log_ce Clears corrected events silently, no log created for CEs. | |
1618 | * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared. | |
3c079792 AK |
1619 | * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above) |
1620 | * monarchtimeout is how long to wait for other CPUs on machine | |
1621 | * check, or 0 to not wait | |
13503fa9 HS |
1622 | * mce=bootlog Log MCEs from before booting. Disabled by default on AMD. |
1623 | * mce=nobootlog Don't log MCEs from before booting. | |
1624 | */ | |
1da177e4 LT |
1625 | static int __init mcheck_enable(char *str) |
1626 | { | |
e3346fc4 | 1627 | if (*str == 0) { |
4efc0670 | 1628 | enable_p5_mce(); |
e3346fc4 BZ |
1629 | return 1; |
1630 | } | |
4efc0670 AK |
1631 | if (*str == '=') |
1632 | str++; | |
1da177e4 | 1633 | if (!strcmp(str, "off")) |
04b2b1a4 | 1634 | mce_disabled = 1; |
62fdac59 HS |
1635 | else if (!strcmp(str, "no_cmci")) |
1636 | mce_cmci_disabled = 1; | |
1637 | else if (!strcmp(str, "dont_log_ce")) | |
1638 | mce_dont_log_ce = 1; | |
1639 | else if (!strcmp(str, "ignore_ce")) | |
1640 | mce_ignore_ce = 1; | |
13503fa9 HS |
1641 | else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) |
1642 | mce_bootlog = (str[0] == 'b'); | |
3c079792 | 1643 | else if (isdigit(str[0])) { |
8c566ef5 | 1644 | get_option(&str, &tolerant); |
3c079792 AK |
1645 | if (*str == ',') { |
1646 | ++str; | |
1647 | get_option(&str, &monarch_timeout); | |
1648 | } | |
1649 | } else { | |
4efc0670 | 1650 | printk(KERN_INFO "mce argument %s ignored. Please use /sys\n", |
13503fa9 HS |
1651 | str); |
1652 | return 0; | |
1653 | } | |
9b41046c | 1654 | return 1; |
1da177e4 | 1655 | } |
4efc0670 | 1656 | __setup("mce", mcheck_enable); |
1da177e4 | 1657 | |
a2202aa2 | 1658 | int __init mcheck_init(void) |
b33a6363 BP |
1659 | { |
1660 | atomic_notifier_chain_register(&x86_mce_decoder_chain, &mce_dec_nb); | |
1661 | ||
a2202aa2 YW |
1662 | mcheck_intel_therm_init(); |
1663 | ||
b33a6363 BP |
1664 | return 0; |
1665 | } | |
b33a6363 | 1666 | |
d88203d1 | 1667 | /* |
1da177e4 | 1668 | * Sysfs support |
d88203d1 | 1669 | */ |
1da177e4 | 1670 | |
973a2dd1 AK |
1671 | /* |
1672 | * Disable machine checks on suspend and shutdown. We can't really handle | |
1673 | * them later. | |
1674 | */ | |
5e09954a | 1675 | static int mce_disable_error_reporting(void) |
973a2dd1 AK |
1676 | { |
1677 | int i; | |
1678 | ||
06b7a7a5 | 1679 | for (i = 0; i < banks; i++) { |
cebe1820 | 1680 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1681 | |
cebe1820 | 1682 | if (b->init) |
a2d32bcb | 1683 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 1684 | } |
973a2dd1 AK |
1685 | return 0; |
1686 | } | |
1687 | ||
1688 | static int mce_suspend(struct sys_device *dev, pm_message_t state) | |
1689 | { | |
5e09954a | 1690 | return mce_disable_error_reporting(); |
973a2dd1 AK |
1691 | } |
1692 | ||
1693 | static int mce_shutdown(struct sys_device *dev) | |
1694 | { | |
5e09954a | 1695 | return mce_disable_error_reporting(); |
973a2dd1 AK |
1696 | } |
1697 | ||
e9eee03e IM |
1698 | /* |
1699 | * On resume clear all MCE state. Don't want to see leftovers from the BIOS. | |
1700 | * Only one CPU is active at this time, the others get re-added later using | |
1701 | * CPU hotplug: | |
1702 | */ | |
1da177e4 LT |
1703 | static int mce_resume(struct sys_device *dev) |
1704 | { | |
5e09954a BP |
1705 | __mcheck_cpu_init_generic(); |
1706 | __mcheck_cpu_init_vendor(¤t_cpu_data); | |
e9eee03e | 1707 | |
1da177e4 LT |
1708 | return 0; |
1709 | } | |
1710 | ||
52d168e2 AK |
1711 | static void mce_cpu_restart(void *data) |
1712 | { | |
1713 | del_timer_sync(&__get_cpu_var(mce_timer)); | |
33edbf02 HS |
1714 | if (!mce_available(¤t_cpu_data)) |
1715 | return; | |
5e09954a BP |
1716 | __mcheck_cpu_init_generic(); |
1717 | __mcheck_cpu_init_timer(); | |
52d168e2 AK |
1718 | } |
1719 | ||
1da177e4 | 1720 | /* Reinit MCEs after user configuration changes */ |
d88203d1 TG |
1721 | static void mce_restart(void) |
1722 | { | |
52d168e2 | 1723 | on_each_cpu(mce_cpu_restart, NULL, 1); |
1da177e4 LT |
1724 | } |
1725 | ||
9af43b54 HS |
1726 | /* Toggle features for corrected errors */ |
1727 | static void mce_disable_ce(void *all) | |
1728 | { | |
1729 | if (!mce_available(¤t_cpu_data)) | |
1730 | return; | |
1731 | if (all) | |
1732 | del_timer_sync(&__get_cpu_var(mce_timer)); | |
1733 | cmci_clear(); | |
1734 | } | |
1735 | ||
1736 | static void mce_enable_ce(void *all) | |
1737 | { | |
1738 | if (!mce_available(¤t_cpu_data)) | |
1739 | return; | |
1740 | cmci_reenable(); | |
1741 | cmci_recheck(); | |
1742 | if (all) | |
5e09954a | 1743 | __mcheck_cpu_init_timer(); |
9af43b54 HS |
1744 | } |
1745 | ||
1da177e4 | 1746 | static struct sysdev_class mce_sysclass = { |
e9eee03e IM |
1747 | .suspend = mce_suspend, |
1748 | .shutdown = mce_shutdown, | |
1749 | .resume = mce_resume, | |
1750 | .name = "machinecheck", | |
1da177e4 LT |
1751 | }; |
1752 | ||
cb491fca | 1753 | DEFINE_PER_CPU(struct sys_device, mce_dev); |
e9eee03e IM |
1754 | |
1755 | __cpuinitdata | |
1756 | void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); | |
1da177e4 | 1757 | |
cebe1820 AK |
1758 | static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr) |
1759 | { | |
1760 | return container_of(attr, struct mce_bank, attr); | |
1761 | } | |
0d7482e3 AK |
1762 | |
1763 | static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
1764 | char *buf) | |
1765 | { | |
cebe1820 | 1766 | return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl); |
0d7482e3 AK |
1767 | } |
1768 | ||
1769 | static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
9319cec8 | 1770 | const char *buf, size_t size) |
0d7482e3 | 1771 | { |
9319cec8 | 1772 | u64 new; |
e9eee03e | 1773 | |
9319cec8 | 1774 | if (strict_strtoull(buf, 0, &new) < 0) |
0d7482e3 | 1775 | return -EINVAL; |
e9eee03e | 1776 | |
cebe1820 | 1777 | attr_to_bank(attr)->ctl = new; |
0d7482e3 | 1778 | mce_restart(); |
e9eee03e | 1779 | |
9319cec8 | 1780 | return size; |
0d7482e3 | 1781 | } |
a98f0dd3 | 1782 | |
e9eee03e IM |
1783 | static ssize_t |
1784 | show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf) | |
a98f0dd3 | 1785 | { |
1020bcbc | 1786 | strcpy(buf, mce_helper); |
a98f0dd3 | 1787 | strcat(buf, "\n"); |
1020bcbc | 1788 | return strlen(mce_helper) + 1; |
a98f0dd3 AK |
1789 | } |
1790 | ||
4a0b2b4d | 1791 | static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr, |
e9eee03e | 1792 | const char *buf, size_t siz) |
a98f0dd3 AK |
1793 | { |
1794 | char *p; | |
e9eee03e | 1795 | |
1020bcbc HS |
1796 | strncpy(mce_helper, buf, sizeof(mce_helper)); |
1797 | mce_helper[sizeof(mce_helper)-1] = 0; | |
1020bcbc | 1798 | p = strchr(mce_helper, '\n'); |
e9eee03e | 1799 | |
e9084ec9 | 1800 | if (p) |
e9eee03e IM |
1801 | *p = 0; |
1802 | ||
e9084ec9 | 1803 | return strlen(mce_helper) + !!p; |
a98f0dd3 AK |
1804 | } |
1805 | ||
9af43b54 HS |
1806 | static ssize_t set_ignore_ce(struct sys_device *s, |
1807 | struct sysdev_attribute *attr, | |
1808 | const char *buf, size_t size) | |
1809 | { | |
1810 | u64 new; | |
1811 | ||
1812 | if (strict_strtoull(buf, 0, &new) < 0) | |
1813 | return -EINVAL; | |
1814 | ||
1815 | if (mce_ignore_ce ^ !!new) { | |
1816 | if (new) { | |
1817 | /* disable ce features */ | |
1818 | on_each_cpu(mce_disable_ce, (void *)1, 1); | |
1819 | mce_ignore_ce = 1; | |
1820 | } else { | |
1821 | /* enable ce features */ | |
1822 | mce_ignore_ce = 0; | |
1823 | on_each_cpu(mce_enable_ce, (void *)1, 1); | |
1824 | } | |
1825 | } | |
1826 | return size; | |
1827 | } | |
1828 | ||
1829 | static ssize_t set_cmci_disabled(struct sys_device *s, | |
1830 | struct sysdev_attribute *attr, | |
1831 | const char *buf, size_t size) | |
1832 | { | |
1833 | u64 new; | |
1834 | ||
1835 | if (strict_strtoull(buf, 0, &new) < 0) | |
1836 | return -EINVAL; | |
1837 | ||
1838 | if (mce_cmci_disabled ^ !!new) { | |
1839 | if (new) { | |
1840 | /* disable cmci */ | |
1841 | on_each_cpu(mce_disable_ce, NULL, 1); | |
1842 | mce_cmci_disabled = 1; | |
1843 | } else { | |
1844 | /* enable cmci */ | |
1845 | mce_cmci_disabled = 0; | |
1846 | on_each_cpu(mce_enable_ce, NULL, 1); | |
1847 | } | |
1848 | } | |
1849 | return size; | |
1850 | } | |
1851 | ||
b56f642d AK |
1852 | static ssize_t store_int_with_restart(struct sys_device *s, |
1853 | struct sysdev_attribute *attr, | |
1854 | const char *buf, size_t size) | |
1855 | { | |
1856 | ssize_t ret = sysdev_store_int(s, attr, buf, size); | |
1857 | mce_restart(); | |
1858 | return ret; | |
1859 | } | |
1860 | ||
a98f0dd3 | 1861 | static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger); |
d95d62c0 | 1862 | static SYSDEV_INT_ATTR(tolerant, 0644, tolerant); |
3c079792 | 1863 | static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout); |
9af43b54 | 1864 | static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce); |
e9eee03e | 1865 | |
b56f642d AK |
1866 | static struct sysdev_ext_attribute attr_check_interval = { |
1867 | _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int, | |
1868 | store_int_with_restart), | |
1869 | &check_interval | |
1870 | }; | |
e9eee03e | 1871 | |
9af43b54 HS |
1872 | static struct sysdev_ext_attribute attr_ignore_ce = { |
1873 | _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce), | |
1874 | &mce_ignore_ce | |
1875 | }; | |
1876 | ||
1877 | static struct sysdev_ext_attribute attr_cmci_disabled = { | |
74b602c7 | 1878 | _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled), |
9af43b54 HS |
1879 | &mce_cmci_disabled |
1880 | }; | |
1881 | ||
cb491fca | 1882 | static struct sysdev_attribute *mce_attrs[] = { |
9af43b54 HS |
1883 | &attr_tolerant.attr, |
1884 | &attr_check_interval.attr, | |
1885 | &attr_trigger, | |
3c079792 | 1886 | &attr_monarch_timeout.attr, |
9af43b54 HS |
1887 | &attr_dont_log_ce.attr, |
1888 | &attr_ignore_ce.attr, | |
1889 | &attr_cmci_disabled.attr, | |
a98f0dd3 AK |
1890 | NULL |
1891 | }; | |
1da177e4 | 1892 | |
cb491fca | 1893 | static cpumask_var_t mce_dev_initialized; |
bae19fe0 | 1894 | |
e9eee03e | 1895 | /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */ |
91c6d400 | 1896 | static __cpuinit int mce_create_device(unsigned int cpu) |
1da177e4 LT |
1897 | { |
1898 | int err; | |
b1f49f95 | 1899 | int i, j; |
92cb7612 | 1900 | |
90367556 | 1901 | if (!mce_available(&boot_cpu_data)) |
91c6d400 AK |
1902 | return -EIO; |
1903 | ||
cb491fca IM |
1904 | memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject)); |
1905 | per_cpu(mce_dev, cpu).id = cpu; | |
1906 | per_cpu(mce_dev, cpu).cls = &mce_sysclass; | |
91c6d400 | 1907 | |
cb491fca | 1908 | err = sysdev_register(&per_cpu(mce_dev, cpu)); |
d435d862 AM |
1909 | if (err) |
1910 | return err; | |
1911 | ||
cb491fca IM |
1912 | for (i = 0; mce_attrs[i]; i++) { |
1913 | err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
d435d862 AM |
1914 | if (err) |
1915 | goto error; | |
1916 | } | |
b1f49f95 | 1917 | for (j = 0; j < banks; j++) { |
cb491fca | 1918 | err = sysdev_create_file(&per_cpu(mce_dev, cpu), |
cebe1820 | 1919 | &mce_banks[j].attr); |
0d7482e3 AK |
1920 | if (err) |
1921 | goto error2; | |
1922 | } | |
cb491fca | 1923 | cpumask_set_cpu(cpu, mce_dev_initialized); |
91c6d400 | 1924 | |
d435d862 | 1925 | return 0; |
0d7482e3 | 1926 | error2: |
b1f49f95 | 1927 | while (--j >= 0) |
cebe1820 | 1928 | sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[j].attr); |
d435d862 | 1929 | error: |
cb491fca | 1930 | while (--i >= 0) |
cebe1820 | 1931 | sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr); |
cb491fca IM |
1932 | |
1933 | sysdev_unregister(&per_cpu(mce_dev, cpu)); | |
d435d862 | 1934 | |
91c6d400 AK |
1935 | return err; |
1936 | } | |
1937 | ||
2d9cd6c2 | 1938 | static __cpuinit void mce_remove_device(unsigned int cpu) |
91c6d400 | 1939 | { |
73ca5358 SL |
1940 | int i; |
1941 | ||
cb491fca | 1942 | if (!cpumask_test_cpu(cpu, mce_dev_initialized)) |
bae19fe0 AH |
1943 | return; |
1944 | ||
cb491fca IM |
1945 | for (i = 0; mce_attrs[i]; i++) |
1946 | sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
1947 | ||
0d7482e3 | 1948 | for (i = 0; i < banks; i++) |
cebe1820 | 1949 | sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr); |
cb491fca IM |
1950 | |
1951 | sysdev_unregister(&per_cpu(mce_dev, cpu)); | |
1952 | cpumask_clear_cpu(cpu, mce_dev_initialized); | |
91c6d400 | 1953 | } |
91c6d400 | 1954 | |
d6b75584 | 1955 | /* Make sure there are no machine checks on offlined CPUs. */ |
ec5b3d32 | 1956 | static void mce_disable_cpu(void *h) |
d6b75584 | 1957 | { |
88ccbedd | 1958 | unsigned long action = *(unsigned long *)h; |
cb491fca | 1959 | int i; |
d6b75584 AK |
1960 | |
1961 | if (!mce_available(¤t_cpu_data)) | |
1962 | return; | |
88ccbedd AK |
1963 | if (!(action & CPU_TASKS_FROZEN)) |
1964 | cmci_clear(); | |
06b7a7a5 | 1965 | for (i = 0; i < banks; i++) { |
cebe1820 | 1966 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1967 | |
cebe1820 | 1968 | if (b->init) |
a2d32bcb | 1969 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 1970 | } |
d6b75584 AK |
1971 | } |
1972 | ||
ec5b3d32 | 1973 | static void mce_reenable_cpu(void *h) |
d6b75584 | 1974 | { |
88ccbedd | 1975 | unsigned long action = *(unsigned long *)h; |
e9eee03e | 1976 | int i; |
d6b75584 AK |
1977 | |
1978 | if (!mce_available(¤t_cpu_data)) | |
1979 | return; | |
e9eee03e | 1980 | |
88ccbedd AK |
1981 | if (!(action & CPU_TASKS_FROZEN)) |
1982 | cmci_reenable(); | |
06b7a7a5 | 1983 | for (i = 0; i < banks; i++) { |
cebe1820 | 1984 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1985 | |
cebe1820 | 1986 | if (b->init) |
a2d32bcb | 1987 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
06b7a7a5 | 1988 | } |
d6b75584 AK |
1989 | } |
1990 | ||
91c6d400 | 1991 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ |
e9eee03e IM |
1992 | static int __cpuinit |
1993 | mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) | |
91c6d400 AK |
1994 | { |
1995 | unsigned int cpu = (unsigned long)hcpu; | |
52d168e2 | 1996 | struct timer_list *t = &per_cpu(mce_timer, cpu); |
91c6d400 AK |
1997 | |
1998 | switch (action) { | |
bae19fe0 AH |
1999 | case CPU_ONLINE: |
2000 | case CPU_ONLINE_FROZEN: | |
2001 | mce_create_device(cpu); | |
8735728e RW |
2002 | if (threshold_cpu_callback) |
2003 | threshold_cpu_callback(action, cpu); | |
91c6d400 | 2004 | break; |
91c6d400 | 2005 | case CPU_DEAD: |
8bb78442 | 2006 | case CPU_DEAD_FROZEN: |
8735728e RW |
2007 | if (threshold_cpu_callback) |
2008 | threshold_cpu_callback(action, cpu); | |
91c6d400 AK |
2009 | mce_remove_device(cpu); |
2010 | break; | |
52d168e2 AK |
2011 | case CPU_DOWN_PREPARE: |
2012 | case CPU_DOWN_PREPARE_FROZEN: | |
2013 | del_timer_sync(t); | |
88ccbedd | 2014 | smp_call_function_single(cpu, mce_disable_cpu, &action, 1); |
52d168e2 AK |
2015 | break; |
2016 | case CPU_DOWN_FAILED: | |
2017 | case CPU_DOWN_FAILED_FROZEN: | |
6298c512 | 2018 | t->expires = round_jiffies(jiffies + |
245b2e70 | 2019 | __get_cpu_var(mce_next_interval)); |
52d168e2 | 2020 | add_timer_on(t, cpu); |
88ccbedd AK |
2021 | smp_call_function_single(cpu, mce_reenable_cpu, &action, 1); |
2022 | break; | |
2023 | case CPU_POST_DEAD: | |
2024 | /* intentionally ignoring frozen here */ | |
2025 | cmci_rediscover(cpu); | |
52d168e2 | 2026 | break; |
91c6d400 | 2027 | } |
bae19fe0 | 2028 | return NOTIFY_OK; |
91c6d400 AK |
2029 | } |
2030 | ||
1e35669d | 2031 | static struct notifier_block mce_cpu_notifier __cpuinitdata = { |
91c6d400 AK |
2032 | .notifier_call = mce_cpu_callback, |
2033 | }; | |
2034 | ||
cebe1820 | 2035 | static __init void mce_init_banks(void) |
0d7482e3 AK |
2036 | { |
2037 | int i; | |
2038 | ||
0d7482e3 | 2039 | for (i = 0; i < banks; i++) { |
cebe1820 AK |
2040 | struct mce_bank *b = &mce_banks[i]; |
2041 | struct sysdev_attribute *a = &b->attr; | |
e9eee03e | 2042 | |
cebe1820 AK |
2043 | a->attr.name = b->attrname; |
2044 | snprintf(b->attrname, ATTR_LEN, "bank%d", i); | |
e9eee03e IM |
2045 | |
2046 | a->attr.mode = 0644; | |
2047 | a->show = show_bank; | |
2048 | a->store = set_bank; | |
0d7482e3 | 2049 | } |
0d7482e3 AK |
2050 | } |
2051 | ||
5e09954a | 2052 | static __init int mcheck_init_device(void) |
91c6d400 AK |
2053 | { |
2054 | int err; | |
2055 | int i = 0; | |
2056 | ||
1da177e4 LT |
2057 | if (!mce_available(&boot_cpu_data)) |
2058 | return -EIO; | |
0d7482e3 | 2059 | |
e92fae06 | 2060 | zalloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL); |
996867d0 | 2061 | |
cebe1820 | 2062 | mce_init_banks(); |
0d7482e3 | 2063 | |
1da177e4 | 2064 | err = sysdev_class_register(&mce_sysclass); |
d435d862 AM |
2065 | if (err) |
2066 | return err; | |
91c6d400 AK |
2067 | |
2068 | for_each_online_cpu(i) { | |
d435d862 AM |
2069 | err = mce_create_device(i); |
2070 | if (err) | |
2071 | return err; | |
91c6d400 AK |
2072 | } |
2073 | ||
be6b5a35 | 2074 | register_hotcpu_notifier(&mce_cpu_notifier); |
1da177e4 | 2075 | misc_register(&mce_log_device); |
e9eee03e | 2076 | |
1da177e4 | 2077 | return err; |
1da177e4 | 2078 | } |
91c6d400 | 2079 | |
5e09954a | 2080 | device_initcall(mcheck_init_device); |
a988d334 | 2081 | |
d7c3c9a6 AK |
2082 | /* |
2083 | * Old style boot options parsing. Only for compatibility. | |
2084 | */ | |
2085 | static int __init mcheck_disable(char *str) | |
2086 | { | |
2087 | mce_disabled = 1; | |
2088 | return 1; | |
2089 | } | |
2090 | __setup("nomce", mcheck_disable); | |
a988d334 | 2091 | |
5be9ed25 HY |
2092 | #ifdef CONFIG_DEBUG_FS |
2093 | struct dentry *mce_get_debugfs_dir(void) | |
a988d334 | 2094 | { |
5be9ed25 | 2095 | static struct dentry *dmce; |
a988d334 | 2096 | |
5be9ed25 HY |
2097 | if (!dmce) |
2098 | dmce = debugfs_create_dir("mce", NULL); | |
a988d334 | 2099 | |
5be9ed25 HY |
2100 | return dmce; |
2101 | } | |
a988d334 | 2102 | |
bf783f9f HY |
2103 | static void mce_reset(void) |
2104 | { | |
2105 | cpu_missing = 0; | |
2106 | atomic_set(&mce_fake_paniced, 0); | |
2107 | atomic_set(&mce_executing, 0); | |
2108 | atomic_set(&mce_callin, 0); | |
2109 | atomic_set(&global_nwo, 0); | |
2110 | } | |
a988d334 | 2111 | |
bf783f9f HY |
2112 | static int fake_panic_get(void *data, u64 *val) |
2113 | { | |
2114 | *val = fake_panic; | |
2115 | return 0; | |
a988d334 IM |
2116 | } |
2117 | ||
bf783f9f | 2118 | static int fake_panic_set(void *data, u64 val) |
a988d334 | 2119 | { |
bf783f9f HY |
2120 | mce_reset(); |
2121 | fake_panic = val; | |
2122 | return 0; | |
a988d334 | 2123 | } |
a988d334 | 2124 | |
bf783f9f HY |
2125 | DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get, |
2126 | fake_panic_set, "%llu\n"); | |
d7c3c9a6 | 2127 | |
5e09954a | 2128 | static int __init mcheck_debugfs_init(void) |
d7c3c9a6 | 2129 | { |
bf783f9f HY |
2130 | struct dentry *dmce, *ffake_panic; |
2131 | ||
2132 | dmce = mce_get_debugfs_dir(); | |
2133 | if (!dmce) | |
2134 | return -ENOMEM; | |
2135 | ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL, | |
2136 | &fake_panic_fops); | |
2137 | if (!ffake_panic) | |
2138 | return -ENOMEM; | |
2139 | ||
2140 | return 0; | |
d7c3c9a6 | 2141 | } |
5e09954a | 2142 | late_initcall(mcheck_debugfs_init); |
5be9ed25 | 2143 | #endif |