Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Machine check handler. | |
e9eee03e | 3 | * |
1da177e4 | 4 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. |
d88203d1 TG |
5 | * Rest from unknown author(s). |
6 | * 2004 Andi Kleen. Rewrote most of it. | |
b79109c3 AK |
7 | * Copyright 2008 Intel Corporation |
8 | * Author: Andi Kleen | |
1da177e4 | 9 | */ |
c767a54b JP |
10 | |
11 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
12 | ||
e9eee03e IM |
13 | #include <linux/thread_info.h> |
14 | #include <linux/capability.h> | |
15 | #include <linux/miscdevice.h> | |
16 | #include <linux/ratelimit.h> | |
17 | #include <linux/kallsyms.h> | |
18 | #include <linux/rcupdate.h> | |
e9eee03e | 19 | #include <linux/kobject.h> |
14a02530 | 20 | #include <linux/uaccess.h> |
e9eee03e IM |
21 | #include <linux/kdebug.h> |
22 | #include <linux/kernel.h> | |
23 | #include <linux/percpu.h> | |
1da177e4 | 24 | #include <linux/string.h> |
8a25a2fd | 25 | #include <linux/device.h> |
f3c6ea1b | 26 | #include <linux/syscore_ops.h> |
3c079792 | 27 | #include <linux/delay.h> |
8c566ef5 | 28 | #include <linux/ctype.h> |
e9eee03e | 29 | #include <linux/sched.h> |
0d7482e3 | 30 | #include <linux/sysfs.h> |
e9eee03e | 31 | #include <linux/types.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
e9eee03e IM |
33 | #include <linux/init.h> |
34 | #include <linux/kmod.h> | |
35 | #include <linux/poll.h> | |
3c079792 | 36 | #include <linux/nmi.h> |
e9eee03e | 37 | #include <linux/cpu.h> |
14a02530 | 38 | #include <linux/smp.h> |
e9eee03e | 39 | #include <linux/fs.h> |
9b1beaf2 | 40 | #include <linux/mm.h> |
5be9ed25 | 41 | #include <linux/debugfs.h> |
b77e70bf | 42 | #include <linux/irq_work.h> |
69c60c88 | 43 | #include <linux/export.h> |
e9eee03e | 44 | |
d88203d1 | 45 | #include <asm/processor.h> |
e9eee03e IM |
46 | #include <asm/mce.h> |
47 | #include <asm/msr.h> | |
1da177e4 | 48 | |
bd19a5e6 | 49 | #include "mce-internal.h" |
711c2e48 | 50 | |
93b62c3c | 51 | static DEFINE_MUTEX(mce_chrdev_read_mutex); |
2aa2b50d | 52 | |
f56e8a07 | 53 | #define rcu_dereference_check_mce(p) \ |
ec8c27e0 | 54 | rcu_dereference_index_check((p), \ |
f56e8a07 | 55 | rcu_read_lock_sched_held() || \ |
93b62c3c | 56 | lockdep_is_held(&mce_chrdev_read_mutex)) |
f56e8a07 | 57 | |
8968f9d3 HS |
58 | #define CREATE_TRACE_POINTS |
59 | #include <trace/events/mce.h> | |
60 | ||
4e5b3e69 | 61 | int mce_disabled __read_mostly; |
04b2b1a4 | 62 | |
3c079792 AK |
63 | #define SPINUNIT 100 /* 100ns */ |
64 | ||
553f265f AK |
65 | atomic_t mce_entry; |
66 | ||
01ca79f1 AK |
67 | DEFINE_PER_CPU(unsigned, mce_exception_count); |
68 | ||
4e5b3e69 HS |
69 | static int rip_msr __read_mostly; |
70 | static int mce_bootlog __read_mostly = -1; | |
71 | static int monarch_timeout __read_mostly = -1; | |
72 | static int mce_panic_timeout __read_mostly; | |
4e5b3e69 HS |
73 | int mce_cmci_disabled __read_mostly; |
74 | int mce_ignore_ce __read_mostly; | |
75 | int mce_ser __read_mostly; | |
450cc201 | 76 | int mce_bios_cmci_threshold __read_mostly; |
a98f0dd3 | 77 | |
cebe1820 AK |
78 | struct mce_bank *mce_banks __read_mostly; |
79 | ||
d203f0b8 BP |
80 | struct mca_config mca_cfg __read_mostly = { |
81 | /* | |
82 | * Tolerant levels: | |
83 | * 0: always panic on uncorrected errors, log corrected errors | |
84 | * 1: panic or SIGBUS on uncorrected errors, log corrected errors | |
85 | * 2: SIGBUS or log uncorrected errors (if possible), log corr. errors | |
86 | * 3: never panic or SIGBUS, log all errors (for testing only) | |
87 | */ | |
88 | .tolerant = 1 | |
89 | }; | |
90 | ||
1020bcbc HS |
91 | /* User mode helper program triggered by machine check event */ |
92 | static unsigned long mce_need_notify; | |
93 | static char mce_helper[128]; | |
94 | static char *mce_helper_argv[2] = { mce_helper, NULL }; | |
1da177e4 | 95 | |
93b62c3c HS |
96 | static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait); |
97 | ||
3c079792 AK |
98 | static DEFINE_PER_CPU(struct mce, mces_seen); |
99 | static int cpu_missing; | |
100 | ||
ee031c31 AK |
101 | /* MCA banks polled by the period polling timer for corrected events */ |
102 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { | |
103 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL | |
104 | }; | |
105 | ||
9b1beaf2 AK |
106 | static DEFINE_PER_CPU(struct work_struct, mce_work); |
107 | ||
61b0fccd TL |
108 | static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs); |
109 | ||
3653ada5 BP |
110 | /* |
111 | * CPU/chipset specific EDAC code can register a notifier call here to print | |
112 | * MCE errors in a human-readable form. | |
113 | */ | |
114 | ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain); | |
115 | ||
b5f2fa4e AK |
116 | /* Do initial initialization of a struct mce */ |
117 | void mce_setup(struct mce *m) | |
118 | { | |
119 | memset(m, 0, sizeof(struct mce)); | |
d620c67f | 120 | m->cpu = m->extcpu = smp_processor_id(); |
b5f2fa4e | 121 | rdtscll(m->tsc); |
8ee08347 AK |
122 | /* We hope get_seconds stays lockless */ |
123 | m->time = get_seconds(); | |
124 | m->cpuvendor = boot_cpu_data.x86_vendor; | |
125 | m->cpuid = cpuid_eax(1); | |
8ee08347 | 126 | m->socketid = cpu_data(m->extcpu).phys_proc_id; |
8ee08347 AK |
127 | m->apicid = cpu_data(m->extcpu).initial_apicid; |
128 | rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap); | |
b5f2fa4e AK |
129 | } |
130 | ||
ea149b36 AK |
131 | DEFINE_PER_CPU(struct mce, injectm); |
132 | EXPORT_PER_CPU_SYMBOL_GPL(injectm); | |
133 | ||
1da177e4 LT |
134 | /* |
135 | * Lockless MCE logging infrastructure. | |
136 | * This avoids deadlocks on printk locks without having to break locks. Also | |
137 | * separate MCEs from kernel messages to avoid bogus bug reports. | |
138 | */ | |
139 | ||
231fd906 | 140 | static struct mce_log mcelog = { |
f6fb0ac0 AK |
141 | .signature = MCE_LOG_SIGNATURE, |
142 | .len = MCE_LOG_LEN, | |
143 | .recordlen = sizeof(struct mce), | |
d88203d1 | 144 | }; |
1da177e4 LT |
145 | |
146 | void mce_log(struct mce *mce) | |
147 | { | |
148 | unsigned next, entry; | |
f0cb5452 | 149 | int ret = 0; |
e9eee03e | 150 | |
8968f9d3 HS |
151 | /* Emit the trace record: */ |
152 | trace_mce_record(mce); | |
153 | ||
f0cb5452 BP |
154 | ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, mce); |
155 | if (ret == NOTIFY_STOP) | |
156 | return; | |
157 | ||
1da177e4 | 158 | mce->finished = 0; |
7644143c | 159 | wmb(); |
1da177e4 | 160 | for (;;) { |
f56e8a07 | 161 | entry = rcu_dereference_check_mce(mcelog.next); |
673242c1 | 162 | for (;;) { |
696e409d | 163 | |
e9eee03e IM |
164 | /* |
165 | * When the buffer fills up discard new entries. | |
166 | * Assume that the earlier errors are the more | |
167 | * interesting ones: | |
168 | */ | |
673242c1 | 169 | if (entry >= MCE_LOG_LEN) { |
14a02530 HS |
170 | set_bit(MCE_OVERFLOW, |
171 | (unsigned long *)&mcelog.flags); | |
673242c1 AK |
172 | return; |
173 | } | |
e9eee03e | 174 | /* Old left over entry. Skip: */ |
673242c1 AK |
175 | if (mcelog.entry[entry].finished) { |
176 | entry++; | |
177 | continue; | |
178 | } | |
7644143c | 179 | break; |
1da177e4 | 180 | } |
1da177e4 LT |
181 | smp_rmb(); |
182 | next = entry + 1; | |
183 | if (cmpxchg(&mcelog.next, entry, next) == entry) | |
184 | break; | |
185 | } | |
186 | memcpy(mcelog.entry + entry, mce, sizeof(struct mce)); | |
7644143c | 187 | wmb(); |
1da177e4 | 188 | mcelog.entry[entry].finished = 1; |
7644143c | 189 | wmb(); |
1da177e4 | 190 | |
a0189c70 | 191 | mce->finished = 1; |
1020bcbc | 192 | set_bit(0, &mce_need_notify); |
1da177e4 LT |
193 | } |
194 | ||
09371957 BP |
195 | static void drain_mcelog_buffer(void) |
196 | { | |
197 | unsigned int next, i, prev = 0; | |
198 | ||
b11e3d78 | 199 | next = ACCESS_ONCE(mcelog.next); |
09371957 BP |
200 | |
201 | do { | |
202 | struct mce *m; | |
203 | ||
204 | /* drain what was logged during boot */ | |
205 | for (i = prev; i < next; i++) { | |
206 | unsigned long start = jiffies; | |
207 | unsigned retries = 1; | |
208 | ||
209 | m = &mcelog.entry[i]; | |
210 | ||
211 | while (!m->finished) { | |
212 | if (time_after_eq(jiffies, start + 2*retries)) | |
213 | retries++; | |
214 | ||
215 | cpu_relax(); | |
216 | ||
217 | if (!m->finished && retries >= 4) { | |
c767a54b | 218 | pr_err("skipping error being logged currently!\n"); |
09371957 BP |
219 | break; |
220 | } | |
221 | } | |
222 | smp_rmb(); | |
223 | atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m); | |
224 | } | |
225 | ||
226 | memset(mcelog.entry + prev, 0, (next - prev) * sizeof(*m)); | |
227 | prev = next; | |
228 | next = cmpxchg(&mcelog.next, prev, 0); | |
229 | } while (next != prev); | |
230 | } | |
231 | ||
232 | ||
3653ada5 BP |
233 | void mce_register_decode_chain(struct notifier_block *nb) |
234 | { | |
235 | atomic_notifier_chain_register(&x86_mce_decoder_chain, nb); | |
09371957 | 236 | drain_mcelog_buffer(); |
3653ada5 BP |
237 | } |
238 | EXPORT_SYMBOL_GPL(mce_register_decode_chain); | |
239 | ||
240 | void mce_unregister_decode_chain(struct notifier_block *nb) | |
241 | { | |
242 | atomic_notifier_chain_unregister(&x86_mce_decoder_chain, nb); | |
243 | } | |
244 | EXPORT_SYMBOL_GPL(mce_unregister_decode_chain); | |
245 | ||
77e26cca | 246 | static void print_mce(struct mce *m) |
1da177e4 | 247 | { |
dffa4b2f BP |
248 | int ret = 0; |
249 | ||
a2d7b0d4 | 250 | pr_emerg(HW_ERR "CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n", |
d620c67f | 251 | m->extcpu, m->mcgstatus, m->bank, m->status); |
f436f8bb | 252 | |
65ea5b03 | 253 | if (m->ip) { |
a2d7b0d4 | 254 | pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ", |
f436f8bb IM |
255 | !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", |
256 | m->cs, m->ip); | |
257 | ||
1da177e4 | 258 | if (m->cs == __KERNEL_CS) |
65ea5b03 | 259 | print_symbol("{%s}", m->ip); |
f436f8bb | 260 | pr_cont("\n"); |
1da177e4 | 261 | } |
f436f8bb | 262 | |
a2d7b0d4 | 263 | pr_emerg(HW_ERR "TSC %llx ", m->tsc); |
1da177e4 | 264 | if (m->addr) |
f436f8bb | 265 | pr_cont("ADDR %llx ", m->addr); |
1da177e4 | 266 | if (m->misc) |
f436f8bb | 267 | pr_cont("MISC %llx ", m->misc); |
549d042d | 268 | |
f436f8bb | 269 | pr_cont("\n"); |
506ed6b5 AK |
270 | /* |
271 | * Note this output is parsed by external tools and old fields | |
272 | * should not be changed. | |
273 | */ | |
881e23e5 | 274 | pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n", |
506ed6b5 AK |
275 | m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid, |
276 | cpu_data(m->extcpu).microcode); | |
f436f8bb IM |
277 | |
278 | /* | |
279 | * Print out human-readable details about the MCE error, | |
fb253195 | 280 | * (if the CPU has an implementation for that) |
f436f8bb | 281 | */ |
dffa4b2f BP |
282 | ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m); |
283 | if (ret == NOTIFY_STOP) | |
284 | return; | |
285 | ||
286 | pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n"); | |
86503560 AK |
287 | } |
288 | ||
f94b61c2 AK |
289 | #define PANIC_TIMEOUT 5 /* 5 seconds */ |
290 | ||
291 | static atomic_t mce_paniced; | |
292 | ||
bf783f9f HY |
293 | static int fake_panic; |
294 | static atomic_t mce_fake_paniced; | |
295 | ||
f94b61c2 AK |
296 | /* Panic in progress. Enable interrupts and wait for final IPI */ |
297 | static void wait_for_panic(void) | |
298 | { | |
299 | long timeout = PANIC_TIMEOUT*USEC_PER_SEC; | |
f436f8bb | 300 | |
f94b61c2 AK |
301 | preempt_disable(); |
302 | local_irq_enable(); | |
303 | while (timeout-- > 0) | |
304 | udelay(1); | |
29b0f591 AK |
305 | if (panic_timeout == 0) |
306 | panic_timeout = mce_panic_timeout; | |
f94b61c2 AK |
307 | panic("Panicing machine check CPU died"); |
308 | } | |
309 | ||
bd19a5e6 | 310 | static void mce_panic(char *msg, struct mce *final, char *exp) |
d88203d1 | 311 | { |
482908b4 | 312 | int i, apei_err = 0; |
e02e68d3 | 313 | |
bf783f9f HY |
314 | if (!fake_panic) { |
315 | /* | |
316 | * Make sure only one CPU runs in machine check panic | |
317 | */ | |
318 | if (atomic_inc_return(&mce_paniced) > 1) | |
319 | wait_for_panic(); | |
320 | barrier(); | |
f94b61c2 | 321 | |
bf783f9f HY |
322 | bust_spinlocks(1); |
323 | console_verbose(); | |
324 | } else { | |
325 | /* Don't log too much for fake panic */ | |
326 | if (atomic_inc_return(&mce_fake_paniced) > 1) | |
327 | return; | |
328 | } | |
a0189c70 | 329 | /* First print corrected ones that are still unlogged */ |
1da177e4 | 330 | for (i = 0; i < MCE_LOG_LEN; i++) { |
a0189c70 | 331 | struct mce *m = &mcelog.entry[i]; |
77e26cca HS |
332 | if (!(m->status & MCI_STATUS_VAL)) |
333 | continue; | |
482908b4 | 334 | if (!(m->status & MCI_STATUS_UC)) { |
77e26cca | 335 | print_mce(m); |
482908b4 HY |
336 | if (!apei_err) |
337 | apei_err = apei_write_mce(m); | |
338 | } | |
a0189c70 AK |
339 | } |
340 | /* Now print uncorrected but with the final one last */ | |
341 | for (i = 0; i < MCE_LOG_LEN; i++) { | |
342 | struct mce *m = &mcelog.entry[i]; | |
343 | if (!(m->status & MCI_STATUS_VAL)) | |
1da177e4 | 344 | continue; |
77e26cca HS |
345 | if (!(m->status & MCI_STATUS_UC)) |
346 | continue; | |
482908b4 | 347 | if (!final || memcmp(m, final, sizeof(struct mce))) { |
77e26cca | 348 | print_mce(m); |
482908b4 HY |
349 | if (!apei_err) |
350 | apei_err = apei_write_mce(m); | |
351 | } | |
1da177e4 | 352 | } |
482908b4 | 353 | if (final) { |
77e26cca | 354 | print_mce(final); |
482908b4 HY |
355 | if (!apei_err) |
356 | apei_err = apei_write_mce(final); | |
357 | } | |
3c079792 | 358 | if (cpu_missing) |
a2d7b0d4 | 359 | pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n"); |
bd19a5e6 | 360 | if (exp) |
a2d7b0d4 | 361 | pr_emerg(HW_ERR "Machine check: %s\n", exp); |
bf783f9f HY |
362 | if (!fake_panic) { |
363 | if (panic_timeout == 0) | |
364 | panic_timeout = mce_panic_timeout; | |
365 | panic(msg); | |
366 | } else | |
a2d7b0d4 | 367 | pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg); |
d88203d1 | 368 | } |
1da177e4 | 369 | |
ea149b36 AK |
370 | /* Support code for software error injection */ |
371 | ||
372 | static int msr_to_offset(u32 msr) | |
373 | { | |
0a3aee0d | 374 | unsigned bank = __this_cpu_read(injectm.bank); |
f436f8bb | 375 | |
ea149b36 AK |
376 | if (msr == rip_msr) |
377 | return offsetof(struct mce, ip); | |
a2d32bcb | 378 | if (msr == MSR_IA32_MCx_STATUS(bank)) |
ea149b36 | 379 | return offsetof(struct mce, status); |
a2d32bcb | 380 | if (msr == MSR_IA32_MCx_ADDR(bank)) |
ea149b36 | 381 | return offsetof(struct mce, addr); |
a2d32bcb | 382 | if (msr == MSR_IA32_MCx_MISC(bank)) |
ea149b36 AK |
383 | return offsetof(struct mce, misc); |
384 | if (msr == MSR_IA32_MCG_STATUS) | |
385 | return offsetof(struct mce, mcgstatus); | |
386 | return -1; | |
387 | } | |
388 | ||
5f8c1a54 AK |
389 | /* MSR access wrappers used for error injection */ |
390 | static u64 mce_rdmsrl(u32 msr) | |
391 | { | |
392 | u64 v; | |
11868a2d | 393 | |
0a3aee0d | 394 | if (__this_cpu_read(injectm.finished)) { |
ea149b36 | 395 | int offset = msr_to_offset(msr); |
11868a2d | 396 | |
ea149b36 AK |
397 | if (offset < 0) |
398 | return 0; | |
399 | return *(u64 *)((char *)&__get_cpu_var(injectm) + offset); | |
400 | } | |
11868a2d IM |
401 | |
402 | if (rdmsrl_safe(msr, &v)) { | |
403 | WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr); | |
404 | /* | |
405 | * Return zero in case the access faulted. This should | |
406 | * not happen normally but can happen if the CPU does | |
407 | * something weird, or if the code is buggy. | |
408 | */ | |
409 | v = 0; | |
410 | } | |
411 | ||
5f8c1a54 AK |
412 | return v; |
413 | } | |
414 | ||
415 | static void mce_wrmsrl(u32 msr, u64 v) | |
416 | { | |
0a3aee0d | 417 | if (__this_cpu_read(injectm.finished)) { |
ea149b36 | 418 | int offset = msr_to_offset(msr); |
11868a2d | 419 | |
ea149b36 AK |
420 | if (offset >= 0) |
421 | *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v; | |
422 | return; | |
423 | } | |
5f8c1a54 AK |
424 | wrmsrl(msr, v); |
425 | } | |
426 | ||
b8325c5b HS |
427 | /* |
428 | * Collect all global (w.r.t. this processor) status about this machine | |
429 | * check into our "mce" struct so that we can use it later to assess | |
430 | * the severity of the problem as we read per-bank specific details. | |
431 | */ | |
432 | static inline void mce_gather_info(struct mce *m, struct pt_regs *regs) | |
433 | { | |
434 | mce_setup(m); | |
435 | ||
436 | m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); | |
437 | if (regs) { | |
438 | /* | |
439 | * Get the address of the instruction at the time of | |
440 | * the machine check error. | |
441 | */ | |
442 | if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) { | |
443 | m->ip = regs->ip; | |
444 | m->cs = regs->cs; | |
a129a7c8 AK |
445 | |
446 | /* | |
447 | * When in VM86 mode make the cs look like ring 3 | |
448 | * always. This is a lie, but it's better than passing | |
449 | * the additional vm86 bit around everywhere. | |
450 | */ | |
451 | if (v8086_mode(regs)) | |
452 | m->cs |= 3; | |
b8325c5b HS |
453 | } |
454 | /* Use accurate RIP reporting if available. */ | |
455 | if (rip_msr) | |
456 | m->ip = mce_rdmsrl(rip_msr); | |
457 | } | |
458 | } | |
459 | ||
9b1beaf2 AK |
460 | /* |
461 | * Simple lockless ring to communicate PFNs from the exception handler with the | |
462 | * process context work function. This is vastly simplified because there's | |
463 | * only a single reader and a single writer. | |
464 | */ | |
465 | #define MCE_RING_SIZE 16 /* we use one entry less */ | |
466 | ||
467 | struct mce_ring { | |
468 | unsigned short start; | |
469 | unsigned short end; | |
470 | unsigned long ring[MCE_RING_SIZE]; | |
471 | }; | |
472 | static DEFINE_PER_CPU(struct mce_ring, mce_ring); | |
473 | ||
474 | /* Runs with CPU affinity in workqueue */ | |
475 | static int mce_ring_empty(void) | |
476 | { | |
477 | struct mce_ring *r = &__get_cpu_var(mce_ring); | |
478 | ||
479 | return r->start == r->end; | |
480 | } | |
481 | ||
482 | static int mce_ring_get(unsigned long *pfn) | |
483 | { | |
484 | struct mce_ring *r; | |
485 | int ret = 0; | |
486 | ||
487 | *pfn = 0; | |
488 | get_cpu(); | |
489 | r = &__get_cpu_var(mce_ring); | |
490 | if (r->start == r->end) | |
491 | goto out; | |
492 | *pfn = r->ring[r->start]; | |
493 | r->start = (r->start + 1) % MCE_RING_SIZE; | |
494 | ret = 1; | |
495 | out: | |
496 | put_cpu(); | |
497 | return ret; | |
498 | } | |
499 | ||
500 | /* Always runs in MCE context with preempt off */ | |
501 | static int mce_ring_add(unsigned long pfn) | |
502 | { | |
503 | struct mce_ring *r = &__get_cpu_var(mce_ring); | |
504 | unsigned next; | |
505 | ||
506 | next = (r->end + 1) % MCE_RING_SIZE; | |
507 | if (next == r->start) | |
508 | return -1; | |
509 | r->ring[r->end] = pfn; | |
510 | wmb(); | |
511 | r->end = next; | |
512 | return 0; | |
513 | } | |
514 | ||
88ccbedd | 515 | int mce_available(struct cpuinfo_x86 *c) |
1da177e4 | 516 | { |
04b2b1a4 | 517 | if (mce_disabled) |
5b4408fd | 518 | return 0; |
3d1712c9 | 519 | return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); |
1da177e4 LT |
520 | } |
521 | ||
9b1beaf2 AK |
522 | static void mce_schedule_work(void) |
523 | { | |
524 | if (!mce_ring_empty()) { | |
525 | struct work_struct *work = &__get_cpu_var(mce_work); | |
526 | if (!work_pending(work)) | |
527 | schedule_work(work); | |
528 | } | |
529 | } | |
530 | ||
b77e70bf HS |
531 | DEFINE_PER_CPU(struct irq_work, mce_irq_work); |
532 | ||
533 | static void mce_irq_work_cb(struct irq_work *entry) | |
ccc3c319 | 534 | { |
9ff36ee9 | 535 | mce_notify_irq(); |
9b1beaf2 | 536 | mce_schedule_work(); |
ccc3c319 | 537 | } |
ccc3c319 AK |
538 | |
539 | static void mce_report_event(struct pt_regs *regs) | |
540 | { | |
541 | if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) { | |
9ff36ee9 | 542 | mce_notify_irq(); |
9b1beaf2 AK |
543 | /* |
544 | * Triggering the work queue here is just an insurance | |
545 | * policy in case the syscall exit notify handler | |
546 | * doesn't run soon enough or ends up running on the | |
547 | * wrong CPU (can happen when audit sleeps) | |
548 | */ | |
549 | mce_schedule_work(); | |
ccc3c319 AK |
550 | return; |
551 | } | |
552 | ||
b77e70bf | 553 | irq_work_queue(&__get_cpu_var(mce_irq_work)); |
ccc3c319 AK |
554 | } |
555 | ||
85f92694 TL |
556 | /* |
557 | * Read ADDR and MISC registers. | |
558 | */ | |
559 | static void mce_read_aux(struct mce *m, int i) | |
560 | { | |
561 | if (m->status & MCI_STATUS_MISCV) | |
562 | m->misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i)); | |
563 | if (m->status & MCI_STATUS_ADDRV) { | |
564 | m->addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i)); | |
565 | ||
566 | /* | |
567 | * Mask the reported address by the reported granularity. | |
568 | */ | |
569 | if (mce_ser && (m->status & MCI_STATUS_MISCV)) { | |
570 | u8 shift = MCI_MISC_ADDR_LSB(m->misc); | |
571 | m->addr >>= shift; | |
572 | m->addr <<= shift; | |
573 | } | |
574 | } | |
575 | } | |
576 | ||
ca84f696 AK |
577 | DEFINE_PER_CPU(unsigned, mce_poll_count); |
578 | ||
d88203d1 | 579 | /* |
b79109c3 AK |
580 | * Poll for corrected events or events that happened before reset. |
581 | * Those are just logged through /dev/mcelog. | |
582 | * | |
583 | * This is executed in standard interrupt context. | |
ed7290d0 AK |
584 | * |
585 | * Note: spec recommends to panic for fatal unsignalled | |
586 | * errors here. However this would be quite problematic -- | |
587 | * we would need to reimplement the Monarch handling and | |
588 | * it would mess up the exclusion between exception handler | |
589 | * and poll hander -- * so we skip this for now. | |
590 | * These cases should not happen anyways, or only when the CPU | |
591 | * is already totally * confused. In this case it's likely it will | |
592 | * not fully execute the machine check handler either. | |
b79109c3 | 593 | */ |
ee031c31 | 594 | void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) |
b79109c3 AK |
595 | { |
596 | struct mce m; | |
597 | int i; | |
598 | ||
c6ae41e7 | 599 | this_cpu_inc(mce_poll_count); |
ca84f696 | 600 | |
b8325c5b | 601 | mce_gather_info(&m, NULL); |
b79109c3 | 602 | |
d203f0b8 | 603 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 604 | if (!mce_banks[i].ctl || !test_bit(i, *b)) |
b79109c3 AK |
605 | continue; |
606 | ||
607 | m.misc = 0; | |
608 | m.addr = 0; | |
609 | m.bank = i; | |
610 | m.tsc = 0; | |
611 | ||
612 | barrier(); | |
a2d32bcb | 613 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
b79109c3 AK |
614 | if (!(m.status & MCI_STATUS_VAL)) |
615 | continue; | |
616 | ||
617 | /* | |
ed7290d0 AK |
618 | * Uncorrected or signalled events are handled by the exception |
619 | * handler when it is enabled, so don't process those here. | |
b79109c3 AK |
620 | * |
621 | * TBD do the same check for MCI_STATUS_EN here? | |
622 | */ | |
ed7290d0 AK |
623 | if (!(flags & MCP_UC) && |
624 | (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC))) | |
b79109c3 AK |
625 | continue; |
626 | ||
85f92694 | 627 | mce_read_aux(&m, i); |
b79109c3 AK |
628 | |
629 | if (!(flags & MCP_TIMESTAMP)) | |
630 | m.tsc = 0; | |
631 | /* | |
632 | * Don't get the IP here because it's unlikely to | |
633 | * have anything to do with the actual error location. | |
634 | */ | |
d203f0b8 | 635 | if (!(flags & MCP_DONTLOG) && !mca_cfg.dont_log_ce) |
5679af4c | 636 | mce_log(&m); |
b79109c3 AK |
637 | |
638 | /* | |
639 | * Clear state for this bank. | |
640 | */ | |
a2d32bcb | 641 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
b79109c3 AK |
642 | } |
643 | ||
644 | /* | |
645 | * Don't clear MCG_STATUS here because it's only defined for | |
646 | * exceptions. | |
647 | */ | |
88921be3 AK |
648 | |
649 | sync_core(); | |
b79109c3 | 650 | } |
ea149b36 | 651 | EXPORT_SYMBOL_GPL(machine_check_poll); |
b79109c3 | 652 | |
bd19a5e6 AK |
653 | /* |
654 | * Do a quick check if any of the events requires a panic. | |
655 | * This decides if we keep the events around or clear them. | |
656 | */ | |
61b0fccd TL |
657 | static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp, |
658 | struct pt_regs *regs) | |
bd19a5e6 | 659 | { |
95022b8c | 660 | int i, ret = 0; |
bd19a5e6 | 661 | |
d203f0b8 | 662 | for (i = 0; i < mca_cfg.banks; i++) { |
a2d32bcb | 663 | m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
61b0fccd | 664 | if (m->status & MCI_STATUS_VAL) { |
95022b8c | 665 | __set_bit(i, validp); |
61b0fccd TL |
666 | if (quirk_no_way_out) |
667 | quirk_no_way_out(i, m, regs); | |
668 | } | |
d203f0b8 | 669 | if (mce_severity(m, mca_cfg.tolerant, msg) >= MCE_PANIC_SEVERITY) |
95022b8c | 670 | ret = 1; |
bd19a5e6 | 671 | } |
95022b8c | 672 | return ret; |
bd19a5e6 AK |
673 | } |
674 | ||
3c079792 AK |
675 | /* |
676 | * Variable to establish order between CPUs while scanning. | |
677 | * Each CPU spins initially until executing is equal its number. | |
678 | */ | |
679 | static atomic_t mce_executing; | |
680 | ||
681 | /* | |
682 | * Defines order of CPUs on entry. First CPU becomes Monarch. | |
683 | */ | |
684 | static atomic_t mce_callin; | |
685 | ||
686 | /* | |
687 | * Check if a timeout waiting for other CPUs happened. | |
688 | */ | |
689 | static int mce_timed_out(u64 *t) | |
690 | { | |
691 | /* | |
692 | * The others already did panic for some reason. | |
693 | * Bail out like in a timeout. | |
694 | * rmb() to tell the compiler that system_state | |
695 | * might have been modified by someone else. | |
696 | */ | |
697 | rmb(); | |
698 | if (atomic_read(&mce_paniced)) | |
699 | wait_for_panic(); | |
700 | if (!monarch_timeout) | |
701 | goto out; | |
702 | if ((s64)*t < SPINUNIT) { | |
703 | /* CHECKME: Make panic default for 1 too? */ | |
d203f0b8 | 704 | if (mca_cfg.tolerant < 1) |
3c079792 AK |
705 | mce_panic("Timeout synchronizing machine check over CPUs", |
706 | NULL, NULL); | |
707 | cpu_missing = 1; | |
708 | return 1; | |
709 | } | |
710 | *t -= SPINUNIT; | |
711 | out: | |
712 | touch_nmi_watchdog(); | |
713 | return 0; | |
714 | } | |
715 | ||
716 | /* | |
717 | * The Monarch's reign. The Monarch is the CPU who entered | |
718 | * the machine check handler first. It waits for the others to | |
719 | * raise the exception too and then grades them. When any | |
720 | * error is fatal panic. Only then let the others continue. | |
721 | * | |
722 | * The other CPUs entering the MCE handler will be controlled by the | |
723 | * Monarch. They are called Subjects. | |
724 | * | |
725 | * This way we prevent any potential data corruption in a unrecoverable case | |
726 | * and also makes sure always all CPU's errors are examined. | |
727 | * | |
680b6cfd | 728 | * Also this detects the case of a machine check event coming from outer |
3c079792 AK |
729 | * space (not detected by any CPUs) In this case some external agent wants |
730 | * us to shut down, so panic too. | |
731 | * | |
732 | * The other CPUs might still decide to panic if the handler happens | |
733 | * in a unrecoverable place, but in this case the system is in a semi-stable | |
734 | * state and won't corrupt anything by itself. It's ok to let the others | |
735 | * continue for a bit first. | |
736 | * | |
737 | * All the spin loops have timeouts; when a timeout happens a CPU | |
738 | * typically elects itself to be Monarch. | |
739 | */ | |
740 | static void mce_reign(void) | |
741 | { | |
742 | int cpu; | |
743 | struct mce *m = NULL; | |
744 | int global_worst = 0; | |
745 | char *msg = NULL; | |
746 | char *nmsg = NULL; | |
747 | ||
748 | /* | |
749 | * This CPU is the Monarch and the other CPUs have run | |
750 | * through their handlers. | |
751 | * Grade the severity of the errors of all the CPUs. | |
752 | */ | |
753 | for_each_possible_cpu(cpu) { | |
d203f0b8 BP |
754 | int severity = mce_severity(&per_cpu(mces_seen, cpu), |
755 | mca_cfg.tolerant, | |
3c079792 AK |
756 | &nmsg); |
757 | if (severity > global_worst) { | |
758 | msg = nmsg; | |
759 | global_worst = severity; | |
760 | m = &per_cpu(mces_seen, cpu); | |
761 | } | |
762 | } | |
763 | ||
764 | /* | |
765 | * Cannot recover? Panic here then. | |
766 | * This dumps all the mces in the log buffer and stops the | |
767 | * other CPUs. | |
768 | */ | |
d203f0b8 | 769 | if (m && global_worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) |
ac960375 | 770 | mce_panic("Fatal Machine check", m, msg); |
3c079792 AK |
771 | |
772 | /* | |
773 | * For UC somewhere we let the CPU who detects it handle it. | |
774 | * Also must let continue the others, otherwise the handling | |
775 | * CPU could deadlock on a lock. | |
776 | */ | |
777 | ||
778 | /* | |
779 | * No machine check event found. Must be some external | |
780 | * source or one CPU is hung. Panic. | |
781 | */ | |
d203f0b8 | 782 | if (global_worst <= MCE_KEEP_SEVERITY && mca_cfg.tolerant < 3) |
3c079792 AK |
783 | mce_panic("Machine check from unknown source", NULL, NULL); |
784 | ||
785 | /* | |
786 | * Now clear all the mces_seen so that they don't reappear on | |
787 | * the next mce. | |
788 | */ | |
789 | for_each_possible_cpu(cpu) | |
790 | memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce)); | |
791 | } | |
792 | ||
793 | static atomic_t global_nwo; | |
794 | ||
795 | /* | |
796 | * Start of Monarch synchronization. This waits until all CPUs have | |
797 | * entered the exception handler and then determines if any of them | |
798 | * saw a fatal event that requires panic. Then it executes them | |
799 | * in the entry order. | |
800 | * TBD double check parallel CPU hotunplug | |
801 | */ | |
7fb06fc9 | 802 | static int mce_start(int *no_way_out) |
3c079792 | 803 | { |
7fb06fc9 | 804 | int order; |
3c079792 AK |
805 | int cpus = num_online_cpus(); |
806 | u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC; | |
807 | ||
7fb06fc9 HS |
808 | if (!timeout) |
809 | return -1; | |
3c079792 | 810 | |
7fb06fc9 | 811 | atomic_add(*no_way_out, &global_nwo); |
184e1fdf HY |
812 | /* |
813 | * global_nwo should be updated before mce_callin | |
814 | */ | |
815 | smp_wmb(); | |
a95436e4 | 816 | order = atomic_inc_return(&mce_callin); |
3c079792 AK |
817 | |
818 | /* | |
819 | * Wait for everyone. | |
820 | */ | |
821 | while (atomic_read(&mce_callin) != cpus) { | |
822 | if (mce_timed_out(&timeout)) { | |
823 | atomic_set(&global_nwo, 0); | |
7fb06fc9 | 824 | return -1; |
3c079792 AK |
825 | } |
826 | ndelay(SPINUNIT); | |
827 | } | |
828 | ||
184e1fdf HY |
829 | /* |
830 | * mce_callin should be read before global_nwo | |
831 | */ | |
832 | smp_rmb(); | |
3c079792 | 833 | |
7fb06fc9 HS |
834 | if (order == 1) { |
835 | /* | |
836 | * Monarch: Starts executing now, the others wait. | |
837 | */ | |
3c079792 | 838 | atomic_set(&mce_executing, 1); |
7fb06fc9 HS |
839 | } else { |
840 | /* | |
841 | * Subject: Now start the scanning loop one by one in | |
842 | * the original callin order. | |
843 | * This way when there are any shared banks it will be | |
844 | * only seen by one CPU before cleared, avoiding duplicates. | |
845 | */ | |
846 | while (atomic_read(&mce_executing) < order) { | |
847 | if (mce_timed_out(&timeout)) { | |
848 | atomic_set(&global_nwo, 0); | |
849 | return -1; | |
850 | } | |
851 | ndelay(SPINUNIT); | |
852 | } | |
3c079792 AK |
853 | } |
854 | ||
855 | /* | |
7fb06fc9 | 856 | * Cache the global no_way_out state. |
3c079792 | 857 | */ |
7fb06fc9 HS |
858 | *no_way_out = atomic_read(&global_nwo); |
859 | ||
860 | return order; | |
3c079792 AK |
861 | } |
862 | ||
863 | /* | |
864 | * Synchronize between CPUs after main scanning loop. | |
865 | * This invokes the bulk of the Monarch processing. | |
866 | */ | |
867 | static int mce_end(int order) | |
868 | { | |
869 | int ret = -1; | |
870 | u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC; | |
871 | ||
872 | if (!timeout) | |
873 | goto reset; | |
874 | if (order < 0) | |
875 | goto reset; | |
876 | ||
877 | /* | |
878 | * Allow others to run. | |
879 | */ | |
880 | atomic_inc(&mce_executing); | |
881 | ||
882 | if (order == 1) { | |
883 | /* CHECKME: Can this race with a parallel hotplug? */ | |
884 | int cpus = num_online_cpus(); | |
885 | ||
886 | /* | |
887 | * Monarch: Wait for everyone to go through their scanning | |
888 | * loops. | |
889 | */ | |
890 | while (atomic_read(&mce_executing) <= cpus) { | |
891 | if (mce_timed_out(&timeout)) | |
892 | goto reset; | |
893 | ndelay(SPINUNIT); | |
894 | } | |
895 | ||
896 | mce_reign(); | |
897 | barrier(); | |
898 | ret = 0; | |
899 | } else { | |
900 | /* | |
901 | * Subject: Wait for Monarch to finish. | |
902 | */ | |
903 | while (atomic_read(&mce_executing) != 0) { | |
904 | if (mce_timed_out(&timeout)) | |
905 | goto reset; | |
906 | ndelay(SPINUNIT); | |
907 | } | |
908 | ||
909 | /* | |
910 | * Don't reset anything. That's done by the Monarch. | |
911 | */ | |
912 | return 0; | |
913 | } | |
914 | ||
915 | /* | |
916 | * Reset all global state. | |
917 | */ | |
918 | reset: | |
919 | atomic_set(&global_nwo, 0); | |
920 | atomic_set(&mce_callin, 0); | |
921 | barrier(); | |
922 | ||
923 | /* | |
924 | * Let others run again. | |
925 | */ | |
926 | atomic_set(&mce_executing, 0); | |
927 | return ret; | |
928 | } | |
929 | ||
9b1beaf2 AK |
930 | /* |
931 | * Check if the address reported by the CPU is in a format we can parse. | |
932 | * It would be possible to add code for most other cases, but all would | |
933 | * be somewhat complicated (e.g. segment offset would require an instruction | |
0d2eb44f | 934 | * parser). So only support physical addresses up to page granuality for now. |
9b1beaf2 AK |
935 | */ |
936 | static int mce_usable_address(struct mce *m) | |
937 | { | |
938 | if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV)) | |
939 | return 0; | |
2b90e77e | 940 | if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT) |
9b1beaf2 | 941 | return 0; |
2b90e77e | 942 | if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS) |
9b1beaf2 AK |
943 | return 0; |
944 | return 1; | |
945 | } | |
946 | ||
3c079792 AK |
947 | static void mce_clear_state(unsigned long *toclear) |
948 | { | |
949 | int i; | |
950 | ||
d203f0b8 | 951 | for (i = 0; i < mca_cfg.banks; i++) { |
3c079792 | 952 | if (test_bit(i, toclear)) |
a2d32bcb | 953 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
3c079792 AK |
954 | } |
955 | } | |
956 | ||
af104e39 TL |
957 | /* |
958 | * Need to save faulting physical address associated with a process | |
959 | * in the machine check handler some place where we can grab it back | |
960 | * later in mce_notify_process() | |
961 | */ | |
962 | #define MCE_INFO_MAX 16 | |
963 | ||
964 | struct mce_info { | |
965 | atomic_t inuse; | |
966 | struct task_struct *t; | |
967 | __u64 paddr; | |
dad1743e | 968 | int restartable; |
af104e39 TL |
969 | } mce_info[MCE_INFO_MAX]; |
970 | ||
dad1743e | 971 | static void mce_save_info(__u64 addr, int c) |
af104e39 TL |
972 | { |
973 | struct mce_info *mi; | |
974 | ||
975 | for (mi = mce_info; mi < &mce_info[MCE_INFO_MAX]; mi++) { | |
976 | if (atomic_cmpxchg(&mi->inuse, 0, 1) == 0) { | |
977 | mi->t = current; | |
978 | mi->paddr = addr; | |
dad1743e | 979 | mi->restartable = c; |
af104e39 TL |
980 | return; |
981 | } | |
982 | } | |
983 | ||
984 | mce_panic("Too many concurrent recoverable errors", NULL, NULL); | |
985 | } | |
986 | ||
987 | static struct mce_info *mce_find_info(void) | |
988 | { | |
989 | struct mce_info *mi; | |
990 | ||
991 | for (mi = mce_info; mi < &mce_info[MCE_INFO_MAX]; mi++) | |
992 | if (atomic_read(&mi->inuse) && mi->t == current) | |
993 | return mi; | |
994 | return NULL; | |
995 | } | |
996 | ||
997 | static void mce_clear_info(struct mce_info *mi) | |
998 | { | |
999 | atomic_set(&mi->inuse, 0); | |
1000 | } | |
1001 | ||
b79109c3 AK |
1002 | /* |
1003 | * The actual machine check handler. This only handles real | |
1004 | * exceptions when something got corrupted coming in through int 18. | |
1005 | * | |
1006 | * This is executed in NMI context not subject to normal locking rules. This | |
1007 | * implies that most kernel services cannot be safely used. Don't even | |
1008 | * think about putting a printk in there! | |
3c079792 AK |
1009 | * |
1010 | * On Intel systems this is entered on all CPUs in parallel through | |
1011 | * MCE broadcast. However some CPUs might be broken beyond repair, | |
1012 | * so be always careful when synchronizing with others. | |
1da177e4 | 1013 | */ |
e9eee03e | 1014 | void do_machine_check(struct pt_regs *regs, long error_code) |
1da177e4 | 1015 | { |
3c079792 | 1016 | struct mce m, *final; |
1da177e4 | 1017 | int i; |
3c079792 AK |
1018 | int worst = 0; |
1019 | int severity; | |
1020 | /* | |
1021 | * Establish sequential order between the CPUs entering the machine | |
1022 | * check handler. | |
1023 | */ | |
7fb06fc9 | 1024 | int order; |
bd78432c TH |
1025 | /* |
1026 | * If no_way_out gets set, there is no safe way to recover from this | |
d203f0b8 | 1027 | * MCE. If mca_cfg.tolerant is cranked up, we'll try anyway. |
bd78432c TH |
1028 | */ |
1029 | int no_way_out = 0; | |
1030 | /* | |
1031 | * If kill_it gets set, there might be a way to recover from this | |
1032 | * error. | |
1033 | */ | |
1034 | int kill_it = 0; | |
b79109c3 | 1035 | DECLARE_BITMAP(toclear, MAX_NR_BANKS); |
95022b8c | 1036 | DECLARE_BITMAP(valid_banks, MAX_NR_BANKS); |
bd19a5e6 | 1037 | char *msg = "Unknown"; |
1da177e4 | 1038 | |
553f265f AK |
1039 | atomic_inc(&mce_entry); |
1040 | ||
c6ae41e7 | 1041 | this_cpu_inc(mce_exception_count); |
01ca79f1 | 1042 | |
d203f0b8 | 1043 | if (!mca_cfg.banks) |
32561696 | 1044 | goto out; |
1da177e4 | 1045 | |
b8325c5b | 1046 | mce_gather_info(&m, regs); |
b5f2fa4e | 1047 | |
3c079792 AK |
1048 | final = &__get_cpu_var(mces_seen); |
1049 | *final = m; | |
1050 | ||
95022b8c | 1051 | memset(valid_banks, 0, sizeof(valid_banks)); |
61b0fccd | 1052 | no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs); |
680b6cfd | 1053 | |
1da177e4 LT |
1054 | barrier(); |
1055 | ||
ed7290d0 | 1056 | /* |
a8c321fb TL |
1057 | * When no restart IP might need to kill or panic. |
1058 | * Assume the worst for now, but if we find the | |
1059 | * severity is MCE_AR_SEVERITY we have other options. | |
ed7290d0 AK |
1060 | */ |
1061 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) | |
1062 | kill_it = 1; | |
1063 | ||
3c079792 AK |
1064 | /* |
1065 | * Go through all the banks in exclusion of the other CPUs. | |
1066 | * This way we don't report duplicated events on shared banks | |
1067 | * because the first one to see it will clear it. | |
1068 | */ | |
7fb06fc9 | 1069 | order = mce_start(&no_way_out); |
d203f0b8 | 1070 | for (i = 0; i < mca_cfg.banks; i++) { |
b79109c3 | 1071 | __clear_bit(i, toclear); |
95022b8c TL |
1072 | if (!test_bit(i, valid_banks)) |
1073 | continue; | |
cebe1820 | 1074 | if (!mce_banks[i].ctl) |
1da177e4 | 1075 | continue; |
d88203d1 TG |
1076 | |
1077 | m.misc = 0; | |
1da177e4 LT |
1078 | m.addr = 0; |
1079 | m.bank = i; | |
1da177e4 | 1080 | |
a2d32bcb | 1081 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
1da177e4 LT |
1082 | if ((m.status & MCI_STATUS_VAL) == 0) |
1083 | continue; | |
1084 | ||
b79109c3 | 1085 | /* |
ed7290d0 AK |
1086 | * Non uncorrected or non signaled errors are handled by |
1087 | * machine_check_poll. Leave them alone, unless this panics. | |
b79109c3 | 1088 | */ |
ed7290d0 AK |
1089 | if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) && |
1090 | !no_way_out) | |
b79109c3 AK |
1091 | continue; |
1092 | ||
1093 | /* | |
1094 | * Set taint even when machine check was not enabled. | |
1095 | */ | |
1096 | add_taint(TAINT_MACHINE_CHECK); | |
1097 | ||
d203f0b8 | 1098 | severity = mce_severity(&m, mca_cfg.tolerant, NULL); |
b79109c3 | 1099 | |
ed7290d0 AK |
1100 | /* |
1101 | * When machine check was for corrected handler don't touch, | |
1102 | * unless we're panicing. | |
1103 | */ | |
1104 | if (severity == MCE_KEEP_SEVERITY && !no_way_out) | |
1105 | continue; | |
1106 | __set_bit(i, toclear); | |
1107 | if (severity == MCE_NO_SEVERITY) { | |
b79109c3 AK |
1108 | /* |
1109 | * Machine check event was not enabled. Clear, but | |
1110 | * ignore. | |
1111 | */ | |
1112 | continue; | |
1da177e4 LT |
1113 | } |
1114 | ||
85f92694 | 1115 | mce_read_aux(&m, i); |
1da177e4 | 1116 | |
9b1beaf2 AK |
1117 | /* |
1118 | * Action optional error. Queue address for later processing. | |
1119 | * When the ring overflows we just ignore the AO error. | |
1120 | * RED-PEN add some logging mechanism when | |
1121 | * usable_address or mce_add_ring fails. | |
d203f0b8 | 1122 | * RED-PEN don't ignore overflow for mca_cfg.tolerant == 0 |
9b1beaf2 AK |
1123 | */ |
1124 | if (severity == MCE_AO_SEVERITY && mce_usable_address(&m)) | |
1125 | mce_ring_add(m.addr >> PAGE_SHIFT); | |
1126 | ||
b79109c3 | 1127 | mce_log(&m); |
1da177e4 | 1128 | |
3c079792 AK |
1129 | if (severity > worst) { |
1130 | *final = m; | |
1131 | worst = severity; | |
1da177e4 | 1132 | } |
1da177e4 LT |
1133 | } |
1134 | ||
a8c321fb TL |
1135 | /* mce_clear_state will clear *final, save locally for use later */ |
1136 | m = *final; | |
1137 | ||
3c079792 AK |
1138 | if (!no_way_out) |
1139 | mce_clear_state(toclear); | |
1140 | ||
e9eee03e | 1141 | /* |
3c079792 AK |
1142 | * Do most of the synchronization with other CPUs. |
1143 | * When there's any problem use only local no_way_out state. | |
e9eee03e | 1144 | */ |
3c079792 AK |
1145 | if (mce_end(order) < 0) |
1146 | no_way_out = worst >= MCE_PANIC_SEVERITY; | |
bd78432c TH |
1147 | |
1148 | /* | |
a8c321fb TL |
1149 | * At insane "tolerant" levels we take no action. Otherwise |
1150 | * we only die if we have no other choice. For less serious | |
1151 | * issues we try to recover, or limit damage to the current | |
1152 | * process. | |
bd78432c | 1153 | */ |
d203f0b8 | 1154 | if (mca_cfg.tolerant < 3) { |
a8c321fb TL |
1155 | if (no_way_out) |
1156 | mce_panic("Fatal machine check on current CPU", &m, msg); | |
1157 | if (worst == MCE_AR_SEVERITY) { | |
1158 | /* schedule action before return to userland */ | |
dad1743e | 1159 | mce_save_info(m.addr, m.mcgstatus & MCG_STATUS_RIPV); |
a8c321fb TL |
1160 | set_thread_flag(TIF_MCE_NOTIFY); |
1161 | } else if (kill_it) { | |
1162 | force_sig(SIGBUS, current); | |
1163 | } | |
1164 | } | |
e02e68d3 | 1165 | |
3c079792 AK |
1166 | if (worst > 0) |
1167 | mce_report_event(regs); | |
5f8c1a54 | 1168 | mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); |
32561696 | 1169 | out: |
553f265f | 1170 | atomic_dec(&mce_entry); |
88921be3 | 1171 | sync_core(); |
1da177e4 | 1172 | } |
ea149b36 | 1173 | EXPORT_SYMBOL_GPL(do_machine_check); |
1da177e4 | 1174 | |
cd42f4a3 TL |
1175 | #ifndef CONFIG_MEMORY_FAILURE |
1176 | int memory_failure(unsigned long pfn, int vector, int flags) | |
9b1beaf2 | 1177 | { |
a8c321fb TL |
1178 | /* mce_severity() should not hand us an ACTION_REQUIRED error */ |
1179 | BUG_ON(flags & MF_ACTION_REQUIRED); | |
c767a54b JP |
1180 | pr_err("Uncorrected memory error in page 0x%lx ignored\n" |
1181 | "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n", | |
1182 | pfn); | |
cd42f4a3 TL |
1183 | |
1184 | return 0; | |
9b1beaf2 | 1185 | } |
cd42f4a3 | 1186 | #endif |
9b1beaf2 AK |
1187 | |
1188 | /* | |
a8c321fb TL |
1189 | * Called in process context that interrupted by MCE and marked with |
1190 | * TIF_MCE_NOTIFY, just before returning to erroneous userland. | |
1191 | * This code is allowed to sleep. | |
1192 | * Attempt possible recovery such as calling the high level VM handler to | |
1193 | * process any corrupted pages, and kill/signal current process if required. | |
1194 | * Action required errors are handled here. | |
9b1beaf2 AK |
1195 | */ |
1196 | void mce_notify_process(void) | |
1197 | { | |
1198 | unsigned long pfn; | |
a8c321fb | 1199 | struct mce_info *mi = mce_find_info(); |
6751ed65 | 1200 | int flags = MF_ACTION_REQUIRED; |
a8c321fb TL |
1201 | |
1202 | if (!mi) | |
1203 | mce_panic("Lost physical address for unconsumed uncorrectable error", NULL, NULL); | |
1204 | pfn = mi->paddr >> PAGE_SHIFT; | |
1205 | ||
1206 | clear_thread_flag(TIF_MCE_NOTIFY); | |
1207 | ||
1208 | pr_err("Uncorrected hardware memory error in user-access at %llx", | |
1209 | mi->paddr); | |
dad1743e TL |
1210 | /* |
1211 | * We must call memory_failure() here even if the current process is | |
1212 | * doomed. We still need to mark the page as poisoned and alert any | |
1213 | * other users of the page. | |
1214 | */ | |
6751ed65 TL |
1215 | if (!mi->restartable) |
1216 | flags |= MF_MUST_KILL; | |
1217 | if (memory_failure(pfn, MCE_VECTOR, flags) < 0) { | |
a8c321fb TL |
1218 | pr_err("Memory error not recovered"); |
1219 | force_sig(SIGBUS, current); | |
1220 | } | |
1221 | mce_clear_info(mi); | |
9b1beaf2 AK |
1222 | } |
1223 | ||
a8c321fb TL |
1224 | /* |
1225 | * Action optional processing happens here (picking up | |
1226 | * from the list of faulting pages that do_machine_check() | |
1227 | * placed into the "ring"). | |
1228 | */ | |
9b1beaf2 AK |
1229 | static void mce_process_work(struct work_struct *dummy) |
1230 | { | |
a8c321fb TL |
1231 | unsigned long pfn; |
1232 | ||
1233 | while (mce_ring_get(&pfn)) | |
1234 | memory_failure(pfn, MCE_VECTOR, 0); | |
9b1beaf2 AK |
1235 | } |
1236 | ||
15d5f839 DZ |
1237 | #ifdef CONFIG_X86_MCE_INTEL |
1238 | /*** | |
1239 | * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog | |
676b1855 | 1240 | * @cpu: The CPU on which the event occurred. |
15d5f839 DZ |
1241 | * @status: Event status information |
1242 | * | |
1243 | * This function should be called by the thermal interrupt after the | |
1244 | * event has been processed and the decision was made to log the event | |
1245 | * further. | |
1246 | * | |
1247 | * The status parameter will be saved to the 'status' field of 'struct mce' | |
1248 | * and historically has been the register value of the | |
1249 | * MSR_IA32_THERMAL_STATUS (Intel) msr. | |
1250 | */ | |
b5f2fa4e | 1251 | void mce_log_therm_throt_event(__u64 status) |
15d5f839 DZ |
1252 | { |
1253 | struct mce m; | |
1254 | ||
b5f2fa4e | 1255 | mce_setup(&m); |
15d5f839 DZ |
1256 | m.bank = MCE_THERMAL_BANK; |
1257 | m.status = status; | |
15d5f839 DZ |
1258 | mce_log(&m); |
1259 | } | |
1260 | #endif /* CONFIG_X86_MCE_INTEL */ | |
1261 | ||
1da177e4 | 1262 | /* |
8a336b0a TH |
1263 | * Periodic polling timer for "silent" machine check errors. If the |
1264 | * poller finds an MCE, poll 2x faster. When the poller finds no more | |
1265 | * errors, poll 2x slower (up to check_interval seconds). | |
1da177e4 | 1266 | */ |
82f7af09 | 1267 | static unsigned long check_interval = 5 * 60; /* 5 minutes */ |
e9eee03e | 1268 | |
82f7af09 | 1269 | static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */ |
52d168e2 | 1270 | static DEFINE_PER_CPU(struct timer_list, mce_timer); |
1da177e4 | 1271 | |
55babd8f CG |
1272 | static unsigned long mce_adjust_timer_default(unsigned long interval) |
1273 | { | |
1274 | return interval; | |
1275 | } | |
1276 | ||
1277 | static unsigned long (*mce_adjust_timer)(unsigned long interval) = | |
1278 | mce_adjust_timer_default; | |
1279 | ||
82f7af09 | 1280 | static void mce_timer_fn(unsigned long data) |
1da177e4 | 1281 | { |
82f7af09 TG |
1282 | struct timer_list *t = &__get_cpu_var(mce_timer); |
1283 | unsigned long iv; | |
52d168e2 AK |
1284 | |
1285 | WARN_ON(smp_processor_id() != data); | |
1286 | ||
7b543a53 | 1287 | if (mce_available(__this_cpu_ptr(&cpu_info))) { |
ee031c31 AK |
1288 | machine_check_poll(MCP_TIMESTAMP, |
1289 | &__get_cpu_var(mce_poll_banks)); | |
55babd8f | 1290 | mce_intel_cmci_poll(); |
e9eee03e | 1291 | } |
1da177e4 LT |
1292 | |
1293 | /* | |
e02e68d3 TH |
1294 | * Alert userspace if needed. If we logged an MCE, reduce the |
1295 | * polling interval, otherwise increase the polling interval. | |
1da177e4 | 1296 | */ |
82f7af09 | 1297 | iv = __this_cpu_read(mce_next_interval); |
55babd8f | 1298 | if (mce_notify_irq()) { |
958fb3c5 | 1299 | iv = max(iv / 2, (unsigned long) HZ/100); |
55babd8f | 1300 | } else { |
82f7af09 | 1301 | iv = min(iv * 2, round_jiffies_relative(check_interval * HZ)); |
55babd8f CG |
1302 | iv = mce_adjust_timer(iv); |
1303 | } | |
82f7af09 | 1304 | __this_cpu_write(mce_next_interval, iv); |
55babd8f CG |
1305 | /* Might have become 0 after CMCI storm subsided */ |
1306 | if (iv) { | |
1307 | t->expires = jiffies + iv; | |
1308 | add_timer_on(t, smp_processor_id()); | |
1309 | } | |
1310 | } | |
e02e68d3 | 1311 | |
55babd8f CG |
1312 | /* |
1313 | * Ensure that the timer is firing in @interval from now. | |
1314 | */ | |
1315 | void mce_timer_kick(unsigned long interval) | |
1316 | { | |
1317 | struct timer_list *t = &__get_cpu_var(mce_timer); | |
1318 | unsigned long when = jiffies + interval; | |
1319 | unsigned long iv = __this_cpu_read(mce_next_interval); | |
1320 | ||
1321 | if (timer_pending(t)) { | |
1322 | if (time_before(when, t->expires)) | |
1323 | mod_timer_pinned(t, when); | |
1324 | } else { | |
1325 | t->expires = round_jiffies(when); | |
1326 | add_timer_on(t, smp_processor_id()); | |
1327 | } | |
1328 | if (interval < iv) | |
1329 | __this_cpu_write(mce_next_interval, interval); | |
e02e68d3 TH |
1330 | } |
1331 | ||
9aaef96f HS |
1332 | /* Must not be called in IRQ context where del_timer_sync() can deadlock */ |
1333 | static void mce_timer_delete_all(void) | |
1334 | { | |
1335 | int cpu; | |
1336 | ||
1337 | for_each_online_cpu(cpu) | |
1338 | del_timer_sync(&per_cpu(mce_timer, cpu)); | |
1339 | } | |
1340 | ||
9bd98405 AK |
1341 | static void mce_do_trigger(struct work_struct *work) |
1342 | { | |
1020bcbc | 1343 | call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT); |
9bd98405 AK |
1344 | } |
1345 | ||
1346 | static DECLARE_WORK(mce_trigger_work, mce_do_trigger); | |
1347 | ||
e02e68d3 | 1348 | /* |
9bd98405 AK |
1349 | * Notify the user(s) about new machine check events. |
1350 | * Can be called from interrupt context, but not from machine check/NMI | |
1351 | * context. | |
e02e68d3 | 1352 | */ |
9ff36ee9 | 1353 | int mce_notify_irq(void) |
e02e68d3 | 1354 | { |
8457c84d AK |
1355 | /* Not more than two messages every minute */ |
1356 | static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); | |
1357 | ||
1020bcbc | 1358 | if (test_and_clear_bit(0, &mce_need_notify)) { |
93b62c3c HS |
1359 | /* wake processes polling /dev/mcelog */ |
1360 | wake_up_interruptible(&mce_chrdev_wait); | |
9bd98405 AK |
1361 | |
1362 | /* | |
1363 | * There is no risk of missing notifications because | |
1364 | * work_pending is always cleared before the function is | |
1365 | * executed. | |
1366 | */ | |
1020bcbc | 1367 | if (mce_helper[0] && !work_pending(&mce_trigger_work)) |
9bd98405 | 1368 | schedule_work(&mce_trigger_work); |
e02e68d3 | 1369 | |
8457c84d | 1370 | if (__ratelimit(&ratelimit)) |
a2d7b0d4 | 1371 | pr_info(HW_ERR "Machine check events logged\n"); |
e02e68d3 TH |
1372 | |
1373 | return 1; | |
1da177e4 | 1374 | } |
e02e68d3 TH |
1375 | return 0; |
1376 | } | |
9ff36ee9 | 1377 | EXPORT_SYMBOL_GPL(mce_notify_irq); |
8a336b0a | 1378 | |
cffd377e | 1379 | static int __cpuinit __mcheck_cpu_mce_banks_init(void) |
cebe1820 AK |
1380 | { |
1381 | int i; | |
d203f0b8 | 1382 | u8 num_banks = mca_cfg.banks; |
cebe1820 | 1383 | |
d203f0b8 | 1384 | mce_banks = kzalloc(num_banks * sizeof(struct mce_bank), GFP_KERNEL); |
cebe1820 AK |
1385 | if (!mce_banks) |
1386 | return -ENOMEM; | |
d203f0b8 BP |
1387 | |
1388 | for (i = 0; i < num_banks; i++) { | |
cebe1820 | 1389 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1390 | |
cebe1820 AK |
1391 | b->ctl = -1ULL; |
1392 | b->init = 1; | |
1393 | } | |
1394 | return 0; | |
1395 | } | |
1396 | ||
d88203d1 | 1397 | /* |
1da177e4 LT |
1398 | * Initialize Machine Checks for a CPU. |
1399 | */ | |
5e09954a | 1400 | static int __cpuinit __mcheck_cpu_cap_init(void) |
1da177e4 | 1401 | { |
0d7482e3 | 1402 | unsigned b; |
e9eee03e | 1403 | u64 cap; |
1da177e4 LT |
1404 | |
1405 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
01c6680a TG |
1406 | |
1407 | b = cap & MCG_BANKCNT_MASK; | |
d203f0b8 | 1408 | if (!mca_cfg.banks) |
c767a54b | 1409 | pr_info("CPU supports %d MCE banks\n", b); |
b659294b | 1410 | |
0d7482e3 | 1411 | if (b > MAX_NR_BANKS) { |
c767a54b | 1412 | pr_warn("Using only %u machine check banks out of %u\n", |
0d7482e3 AK |
1413 | MAX_NR_BANKS, b); |
1414 | b = MAX_NR_BANKS; | |
1415 | } | |
1416 | ||
1417 | /* Don't support asymmetric configurations today */ | |
d203f0b8 BP |
1418 | WARN_ON(mca_cfg.banks != 0 && b != mca_cfg.banks); |
1419 | mca_cfg.banks = b; | |
1420 | ||
cebe1820 | 1421 | if (!mce_banks) { |
cffd377e | 1422 | int err = __mcheck_cpu_mce_banks_init(); |
11868a2d | 1423 | |
cebe1820 AK |
1424 | if (err) |
1425 | return err; | |
1da177e4 | 1426 | } |
0d7482e3 | 1427 | |
94ad8474 | 1428 | /* Use accurate RIP reporting if available. */ |
01c6680a | 1429 | if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) |
94ad8474 | 1430 | rip_msr = MSR_IA32_MCG_EIP; |
1da177e4 | 1431 | |
ed7290d0 AK |
1432 | if (cap & MCG_SER_P) |
1433 | mce_ser = 1; | |
1434 | ||
0d7482e3 AK |
1435 | return 0; |
1436 | } | |
1437 | ||
5e09954a | 1438 | static void __mcheck_cpu_init_generic(void) |
0d7482e3 | 1439 | { |
e9eee03e | 1440 | mce_banks_t all_banks; |
0d7482e3 AK |
1441 | u64 cap; |
1442 | int i; | |
1443 | ||
b79109c3 AK |
1444 | /* |
1445 | * Log the machine checks left over from the previous reset. | |
1446 | */ | |
ee031c31 | 1447 | bitmap_fill(all_banks, MAX_NR_BANKS); |
5679af4c | 1448 | machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks); |
1da177e4 LT |
1449 | |
1450 | set_in_cr4(X86_CR4_MCE); | |
1451 | ||
0d7482e3 | 1452 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
1da177e4 LT |
1453 | if (cap & MCG_CTL_P) |
1454 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); | |
1455 | ||
d203f0b8 | 1456 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 1457 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1458 | |
cebe1820 | 1459 | if (!b->init) |
06b7a7a5 | 1460 | continue; |
a2d32bcb AK |
1461 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
1462 | wrmsrl(MSR_IA32_MCx_STATUS(i), 0); | |
d88203d1 | 1463 | } |
1da177e4 LT |
1464 | } |
1465 | ||
61b0fccd TL |
1466 | /* |
1467 | * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and | |
1468 | * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM | |
1469 | * Vol 3B Table 15-20). But this confuses both the code that determines | |
1470 | * whether the machine check occurred in kernel or user mode, and also | |
1471 | * the severity assessment code. Pretend that EIPV was set, and take the | |
1472 | * ip/cs values from the pt_regs that mce_gather_info() ignored earlier. | |
1473 | */ | |
1474 | static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs) | |
1475 | { | |
1476 | if (bank != 0) | |
1477 | return; | |
1478 | if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0) | |
1479 | return; | |
1480 | if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC| | |
1481 | MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV| | |
1482 | MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR| | |
1483 | MCACOD)) != | |
1484 | (MCI_STATUS_UC|MCI_STATUS_EN| | |
1485 | MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S| | |
1486 | MCI_STATUS_AR|MCACOD_INSTR)) | |
1487 | return; | |
1488 | ||
1489 | m->mcgstatus |= MCG_STATUS_EIPV; | |
1490 | m->ip = regs->ip; | |
1491 | m->cs = regs->cs; | |
1492 | } | |
1493 | ||
1da177e4 | 1494 | /* Add per CPU specific workarounds here */ |
5e09954a | 1495 | static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) |
d88203d1 | 1496 | { |
d203f0b8 BP |
1497 | struct mca_config *cfg = &mca_cfg; |
1498 | ||
e412cd25 | 1499 | if (c->x86_vendor == X86_VENDOR_UNKNOWN) { |
c767a54b | 1500 | pr_info("unknown CPU type - not enabling MCE support\n"); |
e412cd25 IM |
1501 | return -EOPNOTSUPP; |
1502 | } | |
1503 | ||
1da177e4 | 1504 | /* This should be disabled by the BIOS, but isn't always */ |
911f6a7b | 1505 | if (c->x86_vendor == X86_VENDOR_AMD) { |
d203f0b8 | 1506 | if (c->x86 == 15 && cfg->banks > 4) { |
e9eee03e IM |
1507 | /* |
1508 | * disable GART TBL walk error reporting, which | |
1509 | * trips off incorrectly with the IOMMU & 3ware | |
1510 | * & Cerberus: | |
1511 | */ | |
cebe1820 | 1512 | clear_bit(10, (unsigned long *)&mce_banks[4].ctl); |
e9eee03e IM |
1513 | } |
1514 | if (c->x86 <= 17 && mce_bootlog < 0) { | |
1515 | /* | |
1516 | * Lots of broken BIOS around that don't clear them | |
1517 | * by default and leave crap in there. Don't log: | |
1518 | */ | |
911f6a7b | 1519 | mce_bootlog = 0; |
e9eee03e | 1520 | } |
2e6f694f AK |
1521 | /* |
1522 | * Various K7s with broken bank 0 around. Always disable | |
1523 | * by default. | |
1524 | */ | |
d203f0b8 | 1525 | if (c->x86 == 6 && cfg->banks > 0) |
cebe1820 | 1526 | mce_banks[0].ctl = 0; |
575203b4 BP |
1527 | |
1528 | /* | |
1529 | * Turn off MC4_MISC thresholding banks on those models since | |
1530 | * they're not supported there. | |
1531 | */ | |
1532 | if (c->x86 == 0x15 && | |
1533 | (c->x86_model >= 0x10 && c->x86_model <= 0x1f)) { | |
1534 | int i; | |
1535 | u64 val, hwcr; | |
1536 | bool need_toggle; | |
1537 | u32 msrs[] = { | |
1538 | 0x00000413, /* MC4_MISC0 */ | |
1539 | 0xc0000408, /* MC4_MISC1 */ | |
1540 | }; | |
1541 | ||
1542 | rdmsrl(MSR_K7_HWCR, hwcr); | |
1543 | ||
1544 | /* McStatusWrEn has to be set */ | |
1545 | need_toggle = !(hwcr & BIT(18)); | |
1546 | ||
1547 | if (need_toggle) | |
1548 | wrmsrl(MSR_K7_HWCR, hwcr | BIT(18)); | |
1549 | ||
1550 | for (i = 0; i < ARRAY_SIZE(msrs); i++) { | |
1551 | rdmsrl(msrs[i], val); | |
1552 | ||
1553 | /* CntP bit set? */ | |
80f03361 BP |
1554 | if (val & BIT_64(62)) { |
1555 | val &= ~BIT_64(62); | |
1556 | wrmsrl(msrs[i], val); | |
575203b4 BP |
1557 | } |
1558 | } | |
1559 | ||
1560 | /* restore old settings */ | |
1561 | if (need_toggle) | |
1562 | wrmsrl(MSR_K7_HWCR, hwcr); | |
1563 | } | |
1da177e4 | 1564 | } |
e583538f | 1565 | |
06b7a7a5 AK |
1566 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
1567 | /* | |
1568 | * SDM documents that on family 6 bank 0 should not be written | |
1569 | * because it aliases to another special BIOS controlled | |
1570 | * register. | |
1571 | * But it's not aliased anymore on model 0x1a+ | |
1572 | * Don't ignore bank 0 completely because there could be a | |
1573 | * valid event later, merely don't write CTL0. | |
1574 | */ | |
1575 | ||
d203f0b8 | 1576 | if (c->x86 == 6 && c->x86_model < 0x1A && cfg->banks > 0) |
cebe1820 | 1577 | mce_banks[0].init = 0; |
3c079792 AK |
1578 | |
1579 | /* | |
1580 | * All newer Intel systems support MCE broadcasting. Enable | |
1581 | * synchronization with a one second timeout. | |
1582 | */ | |
1583 | if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && | |
1584 | monarch_timeout < 0) | |
1585 | monarch_timeout = USEC_PER_SEC; | |
c7f6fa44 | 1586 | |
e412cd25 IM |
1587 | /* |
1588 | * There are also broken BIOSes on some Pentium M and | |
1589 | * earlier systems: | |
1590 | */ | |
1591 | if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0) | |
c7f6fa44 | 1592 | mce_bootlog = 0; |
61b0fccd TL |
1593 | |
1594 | if (c->x86 == 6 && c->x86_model == 45) | |
1595 | quirk_no_way_out = quirk_sandybridge_ifu; | |
06b7a7a5 | 1596 | } |
3c079792 AK |
1597 | if (monarch_timeout < 0) |
1598 | monarch_timeout = 0; | |
29b0f591 AK |
1599 | if (mce_bootlog != 0) |
1600 | mce_panic_timeout = 30; | |
e412cd25 IM |
1601 | |
1602 | return 0; | |
d88203d1 | 1603 | } |
1da177e4 | 1604 | |
3a97fc34 | 1605 | static int __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) |
4efc0670 AK |
1606 | { |
1607 | if (c->x86 != 5) | |
3a97fc34 HS |
1608 | return 0; |
1609 | ||
4efc0670 AK |
1610 | switch (c->x86_vendor) { |
1611 | case X86_VENDOR_INTEL: | |
c6978369 | 1612 | intel_p5_mcheck_init(c); |
3a97fc34 | 1613 | return 1; |
4efc0670 AK |
1614 | break; |
1615 | case X86_VENDOR_CENTAUR: | |
1616 | winchip_mcheck_init(c); | |
3a97fc34 | 1617 | return 1; |
4efc0670 AK |
1618 | break; |
1619 | } | |
3a97fc34 HS |
1620 | |
1621 | return 0; | |
4efc0670 AK |
1622 | } |
1623 | ||
5e09954a | 1624 | static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
1625 | { |
1626 | switch (c->x86_vendor) { | |
1627 | case X86_VENDOR_INTEL: | |
1628 | mce_intel_feature_init(c); | |
55babd8f | 1629 | mce_adjust_timer = mce_intel_adjust_timer; |
1da177e4 | 1630 | break; |
89b831ef JS |
1631 | case X86_VENDOR_AMD: |
1632 | mce_amd_feature_init(c); | |
1633 | break; | |
1da177e4 LT |
1634 | default: |
1635 | break; | |
1636 | } | |
1637 | } | |
1638 | ||
26c3c283 | 1639 | static void mce_start_timer(unsigned int cpu, struct timer_list *t) |
52d168e2 | 1640 | { |
55babd8f | 1641 | unsigned long iv = mce_adjust_timer(check_interval * HZ); |
52d168e2 | 1642 | |
26c3c283 | 1643 | __this_cpu_write(mce_next_interval, iv); |
bc09effa | 1644 | |
26c3c283 | 1645 | if (mce_ignore_ce || !iv) |
62fdac59 HS |
1646 | return; |
1647 | ||
82f7af09 | 1648 | t->expires = round_jiffies(jiffies + iv); |
5be6066a | 1649 | add_timer_on(t, smp_processor_id()); |
52d168e2 AK |
1650 | } |
1651 | ||
26c3c283 TG |
1652 | static void __mcheck_cpu_init_timer(void) |
1653 | { | |
1654 | struct timer_list *t = &__get_cpu_var(mce_timer); | |
1655 | unsigned int cpu = smp_processor_id(); | |
1656 | ||
1657 | setup_timer(t, mce_timer_fn, cpu); | |
1658 | mce_start_timer(cpu, t); | |
1659 | } | |
1660 | ||
9eda8cb3 AK |
1661 | /* Handle unconfigured int18 (should never happen) */ |
1662 | static void unexpected_machine_check(struct pt_regs *regs, long error_code) | |
1663 | { | |
c767a54b | 1664 | pr_err("CPU#%d: Unexpected int18 (Machine Check)\n", |
9eda8cb3 AK |
1665 | smp_processor_id()); |
1666 | } | |
1667 | ||
1668 | /* Call the installed machine check handler for this CPU setup. */ | |
1669 | void (*machine_check_vector)(struct pt_regs *, long error_code) = | |
1670 | unexpected_machine_check; | |
1671 | ||
d88203d1 | 1672 | /* |
1da177e4 | 1673 | * Called for each booted CPU to set up machine checks. |
e9eee03e | 1674 | * Must be called with preempt off: |
1da177e4 | 1675 | */ |
5e09954a | 1676 | void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c) |
1da177e4 | 1677 | { |
4efc0670 AK |
1678 | if (mce_disabled) |
1679 | return; | |
1680 | ||
3a97fc34 HS |
1681 | if (__mcheck_cpu_ancient_init(c)) |
1682 | return; | |
4efc0670 | 1683 | |
5b4408fd | 1684 | if (!mce_available(c)) |
1da177e4 LT |
1685 | return; |
1686 | ||
5e09954a | 1687 | if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) { |
04b2b1a4 | 1688 | mce_disabled = 1; |
0d7482e3 AK |
1689 | return; |
1690 | } | |
0d7482e3 | 1691 | |
5d727926 AK |
1692 | machine_check_vector = do_machine_check; |
1693 | ||
5e09954a BP |
1694 | __mcheck_cpu_init_generic(); |
1695 | __mcheck_cpu_init_vendor(c); | |
1696 | __mcheck_cpu_init_timer(); | |
9b1beaf2 | 1697 | INIT_WORK(&__get_cpu_var(mce_work), mce_process_work); |
b77e70bf | 1698 | init_irq_work(&__get_cpu_var(mce_irq_work), &mce_irq_work_cb); |
1da177e4 LT |
1699 | } |
1700 | ||
1701 | /* | |
93b62c3c | 1702 | * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log. |
1da177e4 LT |
1703 | */ |
1704 | ||
93b62c3c HS |
1705 | static DEFINE_SPINLOCK(mce_chrdev_state_lock); |
1706 | static int mce_chrdev_open_count; /* #times opened */ | |
1707 | static int mce_chrdev_open_exclu; /* already open exclusive? */ | |
f528e7ba | 1708 | |
93b62c3c | 1709 | static int mce_chrdev_open(struct inode *inode, struct file *file) |
f528e7ba | 1710 | { |
93b62c3c | 1711 | spin_lock(&mce_chrdev_state_lock); |
f528e7ba | 1712 | |
93b62c3c HS |
1713 | if (mce_chrdev_open_exclu || |
1714 | (mce_chrdev_open_count && (file->f_flags & O_EXCL))) { | |
1715 | spin_unlock(&mce_chrdev_state_lock); | |
e9eee03e | 1716 | |
f528e7ba TH |
1717 | return -EBUSY; |
1718 | } | |
1719 | ||
1720 | if (file->f_flags & O_EXCL) | |
93b62c3c HS |
1721 | mce_chrdev_open_exclu = 1; |
1722 | mce_chrdev_open_count++; | |
f528e7ba | 1723 | |
93b62c3c | 1724 | spin_unlock(&mce_chrdev_state_lock); |
f528e7ba | 1725 | |
bd78432c | 1726 | return nonseekable_open(inode, file); |
f528e7ba TH |
1727 | } |
1728 | ||
93b62c3c | 1729 | static int mce_chrdev_release(struct inode *inode, struct file *file) |
f528e7ba | 1730 | { |
93b62c3c | 1731 | spin_lock(&mce_chrdev_state_lock); |
f528e7ba | 1732 | |
93b62c3c HS |
1733 | mce_chrdev_open_count--; |
1734 | mce_chrdev_open_exclu = 0; | |
f528e7ba | 1735 | |
93b62c3c | 1736 | spin_unlock(&mce_chrdev_state_lock); |
f528e7ba TH |
1737 | |
1738 | return 0; | |
1739 | } | |
1740 | ||
d88203d1 TG |
1741 | static void collect_tscs(void *data) |
1742 | { | |
1da177e4 | 1743 | unsigned long *cpu_tsc = (unsigned long *)data; |
d88203d1 | 1744 | |
1da177e4 | 1745 | rdtscll(cpu_tsc[smp_processor_id()]); |
d88203d1 | 1746 | } |
1da177e4 | 1747 | |
482908b4 HY |
1748 | static int mce_apei_read_done; |
1749 | ||
1750 | /* Collect MCE record of previous boot in persistent storage via APEI ERST. */ | |
1751 | static int __mce_read_apei(char __user **ubuf, size_t usize) | |
1752 | { | |
1753 | int rc; | |
1754 | u64 record_id; | |
1755 | struct mce m; | |
1756 | ||
1757 | if (usize < sizeof(struct mce)) | |
1758 | return -EINVAL; | |
1759 | ||
1760 | rc = apei_read_mce(&m, &record_id); | |
1761 | /* Error or no more MCE record */ | |
1762 | if (rc <= 0) { | |
1763 | mce_apei_read_done = 1; | |
fadd85f1 NH |
1764 | /* |
1765 | * When ERST is disabled, mce_chrdev_read() should return | |
1766 | * "no record" instead of "no device." | |
1767 | */ | |
1768 | if (rc == -ENODEV) | |
1769 | return 0; | |
482908b4 HY |
1770 | return rc; |
1771 | } | |
1772 | rc = -EFAULT; | |
1773 | if (copy_to_user(*ubuf, &m, sizeof(struct mce))) | |
1774 | return rc; | |
1775 | /* | |
1776 | * In fact, we should have cleared the record after that has | |
1777 | * been flushed to the disk or sent to network in | |
1778 | * /sbin/mcelog, but we have no interface to support that now, | |
1779 | * so just clear it to avoid duplication. | |
1780 | */ | |
1781 | rc = apei_clear_mce(record_id); | |
1782 | if (rc) { | |
1783 | mce_apei_read_done = 1; | |
1784 | return rc; | |
1785 | } | |
1786 | *ubuf += sizeof(struct mce); | |
1787 | ||
1788 | return 0; | |
1789 | } | |
1790 | ||
93b62c3c HS |
1791 | static ssize_t mce_chrdev_read(struct file *filp, char __user *ubuf, |
1792 | size_t usize, loff_t *off) | |
1da177e4 | 1793 | { |
e9eee03e | 1794 | char __user *buf = ubuf; |
f0de53bb | 1795 | unsigned long *cpu_tsc; |
ef41df43 | 1796 | unsigned prev, next; |
1da177e4 LT |
1797 | int i, err; |
1798 | ||
6bca67f9 | 1799 | cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL); |
f0de53bb AK |
1800 | if (!cpu_tsc) |
1801 | return -ENOMEM; | |
1802 | ||
93b62c3c | 1803 | mutex_lock(&mce_chrdev_read_mutex); |
482908b4 HY |
1804 | |
1805 | if (!mce_apei_read_done) { | |
1806 | err = __mce_read_apei(&buf, usize); | |
1807 | if (err || buf != ubuf) | |
1808 | goto out; | |
1809 | } | |
1810 | ||
f56e8a07 | 1811 | next = rcu_dereference_check_mce(mcelog.next); |
1da177e4 LT |
1812 | |
1813 | /* Only supports full reads right now */ | |
482908b4 HY |
1814 | err = -EINVAL; |
1815 | if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) | |
1816 | goto out; | |
1da177e4 LT |
1817 | |
1818 | err = 0; | |
ef41df43 HY |
1819 | prev = 0; |
1820 | do { | |
1821 | for (i = prev; i < next; i++) { | |
1822 | unsigned long start = jiffies; | |
559faa6b | 1823 | struct mce *m = &mcelog.entry[i]; |
ef41df43 | 1824 | |
559faa6b | 1825 | while (!m->finished) { |
ef41df43 | 1826 | if (time_after_eq(jiffies, start + 2)) { |
559faa6b | 1827 | memset(m, 0, sizeof(*m)); |
ef41df43 HY |
1828 | goto timeout; |
1829 | } | |
1830 | cpu_relax(); | |
673242c1 | 1831 | } |
ef41df43 | 1832 | smp_rmb(); |
559faa6b HS |
1833 | err |= copy_to_user(buf, m, sizeof(*m)); |
1834 | buf += sizeof(*m); | |
ef41df43 HY |
1835 | timeout: |
1836 | ; | |
673242c1 | 1837 | } |
1da177e4 | 1838 | |
ef41df43 HY |
1839 | memset(mcelog.entry + prev, 0, |
1840 | (next - prev) * sizeof(struct mce)); | |
1841 | prev = next; | |
1842 | next = cmpxchg(&mcelog.next, prev, 0); | |
1843 | } while (next != prev); | |
1da177e4 | 1844 | |
b2b18660 | 1845 | synchronize_sched(); |
1da177e4 | 1846 | |
d88203d1 TG |
1847 | /* |
1848 | * Collect entries that were still getting written before the | |
1849 | * synchronize. | |
1850 | */ | |
15c8b6c1 | 1851 | on_each_cpu(collect_tscs, cpu_tsc, 1); |
e9eee03e | 1852 | |
d88203d1 | 1853 | for (i = next; i < MCE_LOG_LEN; i++) { |
559faa6b HS |
1854 | struct mce *m = &mcelog.entry[i]; |
1855 | ||
1856 | if (m->finished && m->tsc < cpu_tsc[m->cpu]) { | |
1857 | err |= copy_to_user(buf, m, sizeof(*m)); | |
1da177e4 | 1858 | smp_rmb(); |
559faa6b HS |
1859 | buf += sizeof(*m); |
1860 | memset(m, 0, sizeof(*m)); | |
1da177e4 | 1861 | } |
d88203d1 | 1862 | } |
482908b4 HY |
1863 | |
1864 | if (err) | |
1865 | err = -EFAULT; | |
1866 | ||
1867 | out: | |
93b62c3c | 1868 | mutex_unlock(&mce_chrdev_read_mutex); |
f0de53bb | 1869 | kfree(cpu_tsc); |
e9eee03e | 1870 | |
482908b4 | 1871 | return err ? err : buf - ubuf; |
1da177e4 LT |
1872 | } |
1873 | ||
93b62c3c | 1874 | static unsigned int mce_chrdev_poll(struct file *file, poll_table *wait) |
e02e68d3 | 1875 | { |
93b62c3c | 1876 | poll_wait(file, &mce_chrdev_wait, wait); |
a4dd9925 | 1877 | if (rcu_access_index(mcelog.next)) |
e02e68d3 | 1878 | return POLLIN | POLLRDNORM; |
482908b4 HY |
1879 | if (!mce_apei_read_done && apei_check_mce()) |
1880 | return POLLIN | POLLRDNORM; | |
e02e68d3 TH |
1881 | return 0; |
1882 | } | |
1883 | ||
93b62c3c HS |
1884 | static long mce_chrdev_ioctl(struct file *f, unsigned int cmd, |
1885 | unsigned long arg) | |
1da177e4 LT |
1886 | { |
1887 | int __user *p = (int __user *)arg; | |
d88203d1 | 1888 | |
1da177e4 | 1889 | if (!capable(CAP_SYS_ADMIN)) |
d88203d1 | 1890 | return -EPERM; |
e9eee03e | 1891 | |
1da177e4 | 1892 | switch (cmd) { |
d88203d1 | 1893 | case MCE_GET_RECORD_LEN: |
1da177e4 LT |
1894 | return put_user(sizeof(struct mce), p); |
1895 | case MCE_GET_LOG_LEN: | |
d88203d1 | 1896 | return put_user(MCE_LOG_LEN, p); |
1da177e4 LT |
1897 | case MCE_GETCLEAR_FLAGS: { |
1898 | unsigned flags; | |
d88203d1 TG |
1899 | |
1900 | do { | |
1da177e4 | 1901 | flags = mcelog.flags; |
d88203d1 | 1902 | } while (cmpxchg(&mcelog.flags, flags, 0) != flags); |
e9eee03e | 1903 | |
d88203d1 | 1904 | return put_user(flags, p); |
1da177e4 LT |
1905 | } |
1906 | default: | |
d88203d1 TG |
1907 | return -ENOTTY; |
1908 | } | |
1da177e4 LT |
1909 | } |
1910 | ||
66f5ddf3 LT |
1911 | static ssize_t (*mce_write)(struct file *filp, const char __user *ubuf, |
1912 | size_t usize, loff_t *off); | |
1913 | ||
1914 | void register_mce_write_callback(ssize_t (*fn)(struct file *filp, | |
1915 | const char __user *ubuf, | |
1916 | size_t usize, loff_t *off)) | |
1917 | { | |
1918 | mce_write = fn; | |
1919 | } | |
1920 | EXPORT_SYMBOL_GPL(register_mce_write_callback); | |
1921 | ||
1922 | ssize_t mce_chrdev_write(struct file *filp, const char __user *ubuf, | |
1923 | size_t usize, loff_t *off) | |
1924 | { | |
1925 | if (mce_write) | |
1926 | return mce_write(filp, ubuf, usize, off); | |
1927 | else | |
1928 | return -EINVAL; | |
1929 | } | |
1930 | ||
1931 | static const struct file_operations mce_chrdev_ops = { | |
93b62c3c HS |
1932 | .open = mce_chrdev_open, |
1933 | .release = mce_chrdev_release, | |
1934 | .read = mce_chrdev_read, | |
66f5ddf3 | 1935 | .write = mce_chrdev_write, |
93b62c3c HS |
1936 | .poll = mce_chrdev_poll, |
1937 | .unlocked_ioctl = mce_chrdev_ioctl, | |
1938 | .llseek = no_llseek, | |
1da177e4 LT |
1939 | }; |
1940 | ||
93b62c3c | 1941 | static struct miscdevice mce_chrdev_device = { |
1da177e4 LT |
1942 | MISC_MCELOG_MINOR, |
1943 | "mcelog", | |
1944 | &mce_chrdev_ops, | |
1945 | }; | |
1946 | ||
13503fa9 | 1947 | /* |
62fdac59 HS |
1948 | * mce=off Disables machine check |
1949 | * mce=no_cmci Disables CMCI | |
1950 | * mce=dont_log_ce Clears corrected events silently, no log created for CEs. | |
1951 | * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared. | |
3c079792 AK |
1952 | * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above) |
1953 | * monarchtimeout is how long to wait for other CPUs on machine | |
1954 | * check, or 0 to not wait | |
13503fa9 HS |
1955 | * mce=bootlog Log MCEs from before booting. Disabled by default on AMD. |
1956 | * mce=nobootlog Don't log MCEs from before booting. | |
450cc201 | 1957 | * mce=bios_cmci_threshold Don't program the CMCI threshold |
13503fa9 | 1958 | */ |
1da177e4 LT |
1959 | static int __init mcheck_enable(char *str) |
1960 | { | |
d203f0b8 BP |
1961 | struct mca_config *cfg = &mca_cfg; |
1962 | ||
e3346fc4 | 1963 | if (*str == 0) { |
4efc0670 | 1964 | enable_p5_mce(); |
e3346fc4 BZ |
1965 | return 1; |
1966 | } | |
4efc0670 AK |
1967 | if (*str == '=') |
1968 | str++; | |
1da177e4 | 1969 | if (!strcmp(str, "off")) |
04b2b1a4 | 1970 | mce_disabled = 1; |
62fdac59 HS |
1971 | else if (!strcmp(str, "no_cmci")) |
1972 | mce_cmci_disabled = 1; | |
1973 | else if (!strcmp(str, "dont_log_ce")) | |
d203f0b8 | 1974 | cfg->dont_log_ce = true; |
62fdac59 HS |
1975 | else if (!strcmp(str, "ignore_ce")) |
1976 | mce_ignore_ce = 1; | |
13503fa9 HS |
1977 | else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) |
1978 | mce_bootlog = (str[0] == 'b'); | |
450cc201 NR |
1979 | else if (!strcmp(str, "bios_cmci_threshold")) |
1980 | mce_bios_cmci_threshold = 1; | |
3c079792 | 1981 | else if (isdigit(str[0])) { |
d203f0b8 | 1982 | get_option(&str, &(cfg->tolerant)); |
3c079792 AK |
1983 | if (*str == ',') { |
1984 | ++str; | |
1985 | get_option(&str, &monarch_timeout); | |
1986 | } | |
1987 | } else { | |
c767a54b | 1988 | pr_info("mce argument %s ignored. Please use /sys\n", str); |
13503fa9 HS |
1989 | return 0; |
1990 | } | |
9b41046c | 1991 | return 1; |
1da177e4 | 1992 | } |
4efc0670 | 1993 | __setup("mce", mcheck_enable); |
1da177e4 | 1994 | |
a2202aa2 | 1995 | int __init mcheck_init(void) |
b33a6363 | 1996 | { |
a2202aa2 YW |
1997 | mcheck_intel_therm_init(); |
1998 | ||
b33a6363 BP |
1999 | return 0; |
2000 | } | |
b33a6363 | 2001 | |
d88203d1 | 2002 | /* |
c7cece89 | 2003 | * mce_syscore: PM support |
d88203d1 | 2004 | */ |
1da177e4 | 2005 | |
973a2dd1 AK |
2006 | /* |
2007 | * Disable machine checks on suspend and shutdown. We can't really handle | |
2008 | * them later. | |
2009 | */ | |
5e09954a | 2010 | static int mce_disable_error_reporting(void) |
973a2dd1 AK |
2011 | { |
2012 | int i; | |
2013 | ||
d203f0b8 | 2014 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2015 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2016 | |
cebe1820 | 2017 | if (b->init) |
a2d32bcb | 2018 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 2019 | } |
973a2dd1 AK |
2020 | return 0; |
2021 | } | |
2022 | ||
c7cece89 | 2023 | static int mce_syscore_suspend(void) |
973a2dd1 | 2024 | { |
5e09954a | 2025 | return mce_disable_error_reporting(); |
973a2dd1 AK |
2026 | } |
2027 | ||
c7cece89 | 2028 | static void mce_syscore_shutdown(void) |
973a2dd1 | 2029 | { |
f3c6ea1b | 2030 | mce_disable_error_reporting(); |
973a2dd1 AK |
2031 | } |
2032 | ||
e9eee03e IM |
2033 | /* |
2034 | * On resume clear all MCE state. Don't want to see leftovers from the BIOS. | |
2035 | * Only one CPU is active at this time, the others get re-added later using | |
2036 | * CPU hotplug: | |
2037 | */ | |
c7cece89 | 2038 | static void mce_syscore_resume(void) |
1da177e4 | 2039 | { |
5e09954a | 2040 | __mcheck_cpu_init_generic(); |
7b543a53 | 2041 | __mcheck_cpu_init_vendor(__this_cpu_ptr(&cpu_info)); |
1da177e4 LT |
2042 | } |
2043 | ||
f3c6ea1b | 2044 | static struct syscore_ops mce_syscore_ops = { |
c7cece89 HS |
2045 | .suspend = mce_syscore_suspend, |
2046 | .shutdown = mce_syscore_shutdown, | |
2047 | .resume = mce_syscore_resume, | |
f3c6ea1b RW |
2048 | }; |
2049 | ||
c7cece89 | 2050 | /* |
8a25a2fd | 2051 | * mce_device: Sysfs support |
c7cece89 HS |
2052 | */ |
2053 | ||
52d168e2 AK |
2054 | static void mce_cpu_restart(void *data) |
2055 | { | |
7b543a53 | 2056 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
33edbf02 | 2057 | return; |
5e09954a BP |
2058 | __mcheck_cpu_init_generic(); |
2059 | __mcheck_cpu_init_timer(); | |
52d168e2 AK |
2060 | } |
2061 | ||
1da177e4 | 2062 | /* Reinit MCEs after user configuration changes */ |
d88203d1 TG |
2063 | static void mce_restart(void) |
2064 | { | |
9aaef96f | 2065 | mce_timer_delete_all(); |
52d168e2 | 2066 | on_each_cpu(mce_cpu_restart, NULL, 1); |
1da177e4 LT |
2067 | } |
2068 | ||
9af43b54 | 2069 | /* Toggle features for corrected errors */ |
9aaef96f | 2070 | static void mce_disable_cmci(void *data) |
9af43b54 | 2071 | { |
7b543a53 | 2072 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
9af43b54 | 2073 | return; |
9af43b54 HS |
2074 | cmci_clear(); |
2075 | } | |
2076 | ||
2077 | static void mce_enable_ce(void *all) | |
2078 | { | |
7b543a53 | 2079 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
9af43b54 HS |
2080 | return; |
2081 | cmci_reenable(); | |
2082 | cmci_recheck(); | |
2083 | if (all) | |
5e09954a | 2084 | __mcheck_cpu_init_timer(); |
9af43b54 HS |
2085 | } |
2086 | ||
8a25a2fd | 2087 | static struct bus_type mce_subsys = { |
e9eee03e | 2088 | .name = "machinecheck", |
8a25a2fd | 2089 | .dev_name = "machinecheck", |
1da177e4 LT |
2090 | }; |
2091 | ||
d6126ef5 | 2092 | DEFINE_PER_CPU(struct device *, mce_device); |
e9eee03e IM |
2093 | |
2094 | __cpuinitdata | |
2095 | void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); | |
1da177e4 | 2096 | |
8a25a2fd | 2097 | static inline struct mce_bank *attr_to_bank(struct device_attribute *attr) |
cebe1820 AK |
2098 | { |
2099 | return container_of(attr, struct mce_bank, attr); | |
2100 | } | |
0d7482e3 | 2101 | |
8a25a2fd | 2102 | static ssize_t show_bank(struct device *s, struct device_attribute *attr, |
0d7482e3 AK |
2103 | char *buf) |
2104 | { | |
cebe1820 | 2105 | return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl); |
0d7482e3 AK |
2106 | } |
2107 | ||
8a25a2fd | 2108 | static ssize_t set_bank(struct device *s, struct device_attribute *attr, |
9319cec8 | 2109 | const char *buf, size_t size) |
0d7482e3 | 2110 | { |
9319cec8 | 2111 | u64 new; |
e9eee03e | 2112 | |
9319cec8 | 2113 | if (strict_strtoull(buf, 0, &new) < 0) |
0d7482e3 | 2114 | return -EINVAL; |
e9eee03e | 2115 | |
cebe1820 | 2116 | attr_to_bank(attr)->ctl = new; |
0d7482e3 | 2117 | mce_restart(); |
e9eee03e | 2118 | |
9319cec8 | 2119 | return size; |
0d7482e3 | 2120 | } |
a98f0dd3 | 2121 | |
e9eee03e | 2122 | static ssize_t |
8a25a2fd | 2123 | show_trigger(struct device *s, struct device_attribute *attr, char *buf) |
a98f0dd3 | 2124 | { |
1020bcbc | 2125 | strcpy(buf, mce_helper); |
a98f0dd3 | 2126 | strcat(buf, "\n"); |
1020bcbc | 2127 | return strlen(mce_helper) + 1; |
a98f0dd3 AK |
2128 | } |
2129 | ||
8a25a2fd | 2130 | static ssize_t set_trigger(struct device *s, struct device_attribute *attr, |
e9eee03e | 2131 | const char *buf, size_t siz) |
a98f0dd3 AK |
2132 | { |
2133 | char *p; | |
e9eee03e | 2134 | |
1020bcbc HS |
2135 | strncpy(mce_helper, buf, sizeof(mce_helper)); |
2136 | mce_helper[sizeof(mce_helper)-1] = 0; | |
1020bcbc | 2137 | p = strchr(mce_helper, '\n'); |
e9eee03e | 2138 | |
e9084ec9 | 2139 | if (p) |
e9eee03e IM |
2140 | *p = 0; |
2141 | ||
e9084ec9 | 2142 | return strlen(mce_helper) + !!p; |
a98f0dd3 AK |
2143 | } |
2144 | ||
8a25a2fd KS |
2145 | static ssize_t set_ignore_ce(struct device *s, |
2146 | struct device_attribute *attr, | |
9af43b54 HS |
2147 | const char *buf, size_t size) |
2148 | { | |
2149 | u64 new; | |
2150 | ||
2151 | if (strict_strtoull(buf, 0, &new) < 0) | |
2152 | return -EINVAL; | |
2153 | ||
2154 | if (mce_ignore_ce ^ !!new) { | |
2155 | if (new) { | |
2156 | /* disable ce features */ | |
9aaef96f HS |
2157 | mce_timer_delete_all(); |
2158 | on_each_cpu(mce_disable_cmci, NULL, 1); | |
9af43b54 HS |
2159 | mce_ignore_ce = 1; |
2160 | } else { | |
2161 | /* enable ce features */ | |
2162 | mce_ignore_ce = 0; | |
2163 | on_each_cpu(mce_enable_ce, (void *)1, 1); | |
2164 | } | |
2165 | } | |
2166 | return size; | |
2167 | } | |
2168 | ||
8a25a2fd KS |
2169 | static ssize_t set_cmci_disabled(struct device *s, |
2170 | struct device_attribute *attr, | |
9af43b54 HS |
2171 | const char *buf, size_t size) |
2172 | { | |
2173 | u64 new; | |
2174 | ||
2175 | if (strict_strtoull(buf, 0, &new) < 0) | |
2176 | return -EINVAL; | |
2177 | ||
2178 | if (mce_cmci_disabled ^ !!new) { | |
2179 | if (new) { | |
2180 | /* disable cmci */ | |
9aaef96f | 2181 | on_each_cpu(mce_disable_cmci, NULL, 1); |
9af43b54 HS |
2182 | mce_cmci_disabled = 1; |
2183 | } else { | |
2184 | /* enable cmci */ | |
2185 | mce_cmci_disabled = 0; | |
2186 | on_each_cpu(mce_enable_ce, NULL, 1); | |
2187 | } | |
2188 | } | |
2189 | return size; | |
2190 | } | |
2191 | ||
8a25a2fd KS |
2192 | static ssize_t store_int_with_restart(struct device *s, |
2193 | struct device_attribute *attr, | |
b56f642d AK |
2194 | const char *buf, size_t size) |
2195 | { | |
8a25a2fd | 2196 | ssize_t ret = device_store_int(s, attr, buf, size); |
b56f642d AK |
2197 | mce_restart(); |
2198 | return ret; | |
2199 | } | |
2200 | ||
8a25a2fd | 2201 | static DEVICE_ATTR(trigger, 0644, show_trigger, set_trigger); |
d203f0b8 | 2202 | static DEVICE_INT_ATTR(tolerant, 0644, mca_cfg.tolerant); |
8a25a2fd | 2203 | static DEVICE_INT_ATTR(monarch_timeout, 0644, monarch_timeout); |
d203f0b8 | 2204 | static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce); |
e9eee03e | 2205 | |
8a25a2fd KS |
2206 | static struct dev_ext_attribute dev_attr_check_interval = { |
2207 | __ATTR(check_interval, 0644, device_show_int, store_int_with_restart), | |
b56f642d AK |
2208 | &check_interval |
2209 | }; | |
e9eee03e | 2210 | |
8a25a2fd KS |
2211 | static struct dev_ext_attribute dev_attr_ignore_ce = { |
2212 | __ATTR(ignore_ce, 0644, device_show_int, set_ignore_ce), | |
9af43b54 HS |
2213 | &mce_ignore_ce |
2214 | }; | |
2215 | ||
8a25a2fd KS |
2216 | static struct dev_ext_attribute dev_attr_cmci_disabled = { |
2217 | __ATTR(cmci_disabled, 0644, device_show_int, set_cmci_disabled), | |
9af43b54 HS |
2218 | &mce_cmci_disabled |
2219 | }; | |
2220 | ||
8a25a2fd KS |
2221 | static struct device_attribute *mce_device_attrs[] = { |
2222 | &dev_attr_tolerant.attr, | |
2223 | &dev_attr_check_interval.attr, | |
2224 | &dev_attr_trigger, | |
2225 | &dev_attr_monarch_timeout.attr, | |
2226 | &dev_attr_dont_log_ce.attr, | |
2227 | &dev_attr_ignore_ce.attr, | |
2228 | &dev_attr_cmci_disabled.attr, | |
a98f0dd3 AK |
2229 | NULL |
2230 | }; | |
1da177e4 | 2231 | |
8a25a2fd | 2232 | static cpumask_var_t mce_device_initialized; |
bae19fe0 | 2233 | |
e032d807 GKH |
2234 | static void mce_device_release(struct device *dev) |
2235 | { | |
2236 | kfree(dev); | |
2237 | } | |
2238 | ||
8a25a2fd KS |
2239 | /* Per cpu device init. All of the cpus still share the same ctrl bank: */ |
2240 | static __cpuinit int mce_device_create(unsigned int cpu) | |
1da177e4 | 2241 | { |
e032d807 | 2242 | struct device *dev; |
1da177e4 | 2243 | int err; |
b1f49f95 | 2244 | int i, j; |
92cb7612 | 2245 | |
90367556 | 2246 | if (!mce_available(&boot_cpu_data)) |
91c6d400 AK |
2247 | return -EIO; |
2248 | ||
e032d807 GKH |
2249 | dev = kzalloc(sizeof *dev, GFP_KERNEL); |
2250 | if (!dev) | |
2251 | return -ENOMEM; | |
8a25a2fd KS |
2252 | dev->id = cpu; |
2253 | dev->bus = &mce_subsys; | |
e032d807 | 2254 | dev->release = &mce_device_release; |
91c6d400 | 2255 | |
8a25a2fd | 2256 | err = device_register(dev); |
d435d862 AM |
2257 | if (err) |
2258 | return err; | |
2259 | ||
8a25a2fd KS |
2260 | for (i = 0; mce_device_attrs[i]; i++) { |
2261 | err = device_create_file(dev, mce_device_attrs[i]); | |
d435d862 AM |
2262 | if (err) |
2263 | goto error; | |
2264 | } | |
d203f0b8 | 2265 | for (j = 0; j < mca_cfg.banks; j++) { |
8a25a2fd | 2266 | err = device_create_file(dev, &mce_banks[j].attr); |
0d7482e3 AK |
2267 | if (err) |
2268 | goto error2; | |
2269 | } | |
8a25a2fd | 2270 | cpumask_set_cpu(cpu, mce_device_initialized); |
d6126ef5 | 2271 | per_cpu(mce_device, cpu) = dev; |
91c6d400 | 2272 | |
d435d862 | 2273 | return 0; |
0d7482e3 | 2274 | error2: |
b1f49f95 | 2275 | while (--j >= 0) |
8a25a2fd | 2276 | device_remove_file(dev, &mce_banks[j].attr); |
d435d862 | 2277 | error: |
cb491fca | 2278 | while (--i >= 0) |
8a25a2fd | 2279 | device_remove_file(dev, mce_device_attrs[i]); |
cb491fca | 2280 | |
8a25a2fd | 2281 | device_unregister(dev); |
d435d862 | 2282 | |
91c6d400 AK |
2283 | return err; |
2284 | } | |
2285 | ||
8a25a2fd | 2286 | static __cpuinit void mce_device_remove(unsigned int cpu) |
91c6d400 | 2287 | { |
d6126ef5 | 2288 | struct device *dev = per_cpu(mce_device, cpu); |
73ca5358 SL |
2289 | int i; |
2290 | ||
8a25a2fd | 2291 | if (!cpumask_test_cpu(cpu, mce_device_initialized)) |
bae19fe0 AH |
2292 | return; |
2293 | ||
8a25a2fd KS |
2294 | for (i = 0; mce_device_attrs[i]; i++) |
2295 | device_remove_file(dev, mce_device_attrs[i]); | |
cb491fca | 2296 | |
d203f0b8 | 2297 | for (i = 0; i < mca_cfg.banks; i++) |
8a25a2fd | 2298 | device_remove_file(dev, &mce_banks[i].attr); |
cb491fca | 2299 | |
8a25a2fd KS |
2300 | device_unregister(dev); |
2301 | cpumask_clear_cpu(cpu, mce_device_initialized); | |
d6126ef5 | 2302 | per_cpu(mce_device, cpu) = NULL; |
91c6d400 | 2303 | } |
91c6d400 | 2304 | |
d6b75584 | 2305 | /* Make sure there are no machine checks on offlined CPUs. */ |
767df1bd | 2306 | static void __cpuinit mce_disable_cpu(void *h) |
d6b75584 | 2307 | { |
88ccbedd | 2308 | unsigned long action = *(unsigned long *)h; |
cb491fca | 2309 | int i; |
d6b75584 | 2310 | |
7b543a53 | 2311 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
d6b75584 | 2312 | return; |
767df1bd | 2313 | |
88ccbedd AK |
2314 | if (!(action & CPU_TASKS_FROZEN)) |
2315 | cmci_clear(); | |
d203f0b8 | 2316 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2317 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2318 | |
cebe1820 | 2319 | if (b->init) |
a2d32bcb | 2320 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 2321 | } |
d6b75584 AK |
2322 | } |
2323 | ||
767df1bd | 2324 | static void __cpuinit mce_reenable_cpu(void *h) |
d6b75584 | 2325 | { |
88ccbedd | 2326 | unsigned long action = *(unsigned long *)h; |
e9eee03e | 2327 | int i; |
d6b75584 | 2328 | |
7b543a53 | 2329 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
d6b75584 | 2330 | return; |
e9eee03e | 2331 | |
88ccbedd AK |
2332 | if (!(action & CPU_TASKS_FROZEN)) |
2333 | cmci_reenable(); | |
d203f0b8 | 2334 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2335 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2336 | |
cebe1820 | 2337 | if (b->init) |
a2d32bcb | 2338 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
06b7a7a5 | 2339 | } |
d6b75584 AK |
2340 | } |
2341 | ||
91c6d400 | 2342 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ |
e9eee03e IM |
2343 | static int __cpuinit |
2344 | mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) | |
91c6d400 AK |
2345 | { |
2346 | unsigned int cpu = (unsigned long)hcpu; | |
52d168e2 | 2347 | struct timer_list *t = &per_cpu(mce_timer, cpu); |
91c6d400 | 2348 | |
1a65f970 | 2349 | switch (action & ~CPU_TASKS_FROZEN) { |
bae19fe0 | 2350 | case CPU_ONLINE: |
8a25a2fd | 2351 | mce_device_create(cpu); |
8735728e RW |
2352 | if (threshold_cpu_callback) |
2353 | threshold_cpu_callback(action, cpu); | |
91c6d400 | 2354 | break; |
91c6d400 | 2355 | case CPU_DEAD: |
8735728e RW |
2356 | if (threshold_cpu_callback) |
2357 | threshold_cpu_callback(action, cpu); | |
8a25a2fd | 2358 | mce_device_remove(cpu); |
55babd8f | 2359 | mce_intel_hcpu_update(cpu); |
91c6d400 | 2360 | break; |
52d168e2 | 2361 | case CPU_DOWN_PREPARE: |
88ccbedd | 2362 | smp_call_function_single(cpu, mce_disable_cpu, &action, 1); |
55babd8f | 2363 | del_timer_sync(t); |
52d168e2 AK |
2364 | break; |
2365 | case CPU_DOWN_FAILED: | |
88ccbedd | 2366 | smp_call_function_single(cpu, mce_reenable_cpu, &action, 1); |
26c3c283 | 2367 | mce_start_timer(cpu, t); |
88ccbedd | 2368 | break; |
1a65f970 TG |
2369 | } |
2370 | ||
2371 | if (action == CPU_POST_DEAD) { | |
88ccbedd AK |
2372 | /* intentionally ignoring frozen here */ |
2373 | cmci_rediscover(cpu); | |
91c6d400 | 2374 | } |
1a65f970 | 2375 | |
bae19fe0 | 2376 | return NOTIFY_OK; |
91c6d400 AK |
2377 | } |
2378 | ||
1e35669d | 2379 | static struct notifier_block mce_cpu_notifier __cpuinitdata = { |
91c6d400 AK |
2380 | .notifier_call = mce_cpu_callback, |
2381 | }; | |
2382 | ||
cebe1820 | 2383 | static __init void mce_init_banks(void) |
0d7482e3 AK |
2384 | { |
2385 | int i; | |
2386 | ||
d203f0b8 | 2387 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2388 | struct mce_bank *b = &mce_banks[i]; |
8a25a2fd | 2389 | struct device_attribute *a = &b->attr; |
e9eee03e | 2390 | |
a07e4156 | 2391 | sysfs_attr_init(&a->attr); |
cebe1820 AK |
2392 | a->attr.name = b->attrname; |
2393 | snprintf(b->attrname, ATTR_LEN, "bank%d", i); | |
e9eee03e IM |
2394 | |
2395 | a->attr.mode = 0644; | |
2396 | a->show = show_bank; | |
2397 | a->store = set_bank; | |
0d7482e3 | 2398 | } |
0d7482e3 AK |
2399 | } |
2400 | ||
5e09954a | 2401 | static __init int mcheck_init_device(void) |
91c6d400 AK |
2402 | { |
2403 | int err; | |
2404 | int i = 0; | |
2405 | ||
1da177e4 LT |
2406 | if (!mce_available(&boot_cpu_data)) |
2407 | return -EIO; | |
0d7482e3 | 2408 | |
8a25a2fd | 2409 | zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL); |
996867d0 | 2410 | |
cebe1820 | 2411 | mce_init_banks(); |
0d7482e3 | 2412 | |
8a25a2fd | 2413 | err = subsys_system_register(&mce_subsys, NULL); |
d435d862 AM |
2414 | if (err) |
2415 | return err; | |
91c6d400 AK |
2416 | |
2417 | for_each_online_cpu(i) { | |
8a25a2fd | 2418 | err = mce_device_create(i); |
d435d862 AM |
2419 | if (err) |
2420 | return err; | |
91c6d400 AK |
2421 | } |
2422 | ||
f3c6ea1b | 2423 | register_syscore_ops(&mce_syscore_ops); |
be6b5a35 | 2424 | register_hotcpu_notifier(&mce_cpu_notifier); |
93b62c3c HS |
2425 | |
2426 | /* register character device /dev/mcelog */ | |
2427 | misc_register(&mce_chrdev_device); | |
e9eee03e | 2428 | |
1da177e4 | 2429 | return err; |
1da177e4 | 2430 | } |
cef12ee5 | 2431 | device_initcall_sync(mcheck_init_device); |
a988d334 | 2432 | |
d7c3c9a6 AK |
2433 | /* |
2434 | * Old style boot options parsing. Only for compatibility. | |
2435 | */ | |
2436 | static int __init mcheck_disable(char *str) | |
2437 | { | |
2438 | mce_disabled = 1; | |
2439 | return 1; | |
2440 | } | |
2441 | __setup("nomce", mcheck_disable); | |
a988d334 | 2442 | |
5be9ed25 HY |
2443 | #ifdef CONFIG_DEBUG_FS |
2444 | struct dentry *mce_get_debugfs_dir(void) | |
a988d334 | 2445 | { |
5be9ed25 | 2446 | static struct dentry *dmce; |
a988d334 | 2447 | |
5be9ed25 HY |
2448 | if (!dmce) |
2449 | dmce = debugfs_create_dir("mce", NULL); | |
a988d334 | 2450 | |
5be9ed25 HY |
2451 | return dmce; |
2452 | } | |
a988d334 | 2453 | |
bf783f9f HY |
2454 | static void mce_reset(void) |
2455 | { | |
2456 | cpu_missing = 0; | |
2457 | atomic_set(&mce_fake_paniced, 0); | |
2458 | atomic_set(&mce_executing, 0); | |
2459 | atomic_set(&mce_callin, 0); | |
2460 | atomic_set(&global_nwo, 0); | |
2461 | } | |
a988d334 | 2462 | |
bf783f9f HY |
2463 | static int fake_panic_get(void *data, u64 *val) |
2464 | { | |
2465 | *val = fake_panic; | |
2466 | return 0; | |
a988d334 IM |
2467 | } |
2468 | ||
bf783f9f | 2469 | static int fake_panic_set(void *data, u64 val) |
a988d334 | 2470 | { |
bf783f9f HY |
2471 | mce_reset(); |
2472 | fake_panic = val; | |
2473 | return 0; | |
a988d334 | 2474 | } |
a988d334 | 2475 | |
bf783f9f HY |
2476 | DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get, |
2477 | fake_panic_set, "%llu\n"); | |
d7c3c9a6 | 2478 | |
5e09954a | 2479 | static int __init mcheck_debugfs_init(void) |
d7c3c9a6 | 2480 | { |
bf783f9f HY |
2481 | struct dentry *dmce, *ffake_panic; |
2482 | ||
2483 | dmce = mce_get_debugfs_dir(); | |
2484 | if (!dmce) | |
2485 | return -ENOMEM; | |
2486 | ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL, | |
2487 | &fake_panic_fops); | |
2488 | if (!ffake_panic) | |
2489 | return -ENOMEM; | |
2490 | ||
2491 | return 0; | |
d7c3c9a6 | 2492 | } |
5e09954a | 2493 | late_initcall(mcheck_debugfs_init); |
5be9ed25 | 2494 | #endif |