Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Machine check handler. | |
e9eee03e | 3 | * |
1da177e4 | 4 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. |
d88203d1 TG |
5 | * Rest from unknown author(s). |
6 | * 2004 Andi Kleen. Rewrote most of it. | |
b79109c3 AK |
7 | * Copyright 2008 Intel Corporation |
8 | * Author: Andi Kleen | |
1da177e4 | 9 | */ |
e9eee03e IM |
10 | #include <linux/thread_info.h> |
11 | #include <linux/capability.h> | |
12 | #include <linux/miscdevice.h> | |
13 | #include <linux/ratelimit.h> | |
14 | #include <linux/kallsyms.h> | |
15 | #include <linux/rcupdate.h> | |
38c4c97c | 16 | #include <linux/smp_lock.h> |
e9eee03e IM |
17 | #include <linux/kobject.h> |
18 | #include <linux/kdebug.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/percpu.h> | |
1da177e4 | 21 | #include <linux/string.h> |
1da177e4 | 22 | #include <linux/sysdev.h> |
8c566ef5 | 23 | #include <linux/ctype.h> |
e9eee03e | 24 | #include <linux/sched.h> |
0d7482e3 | 25 | #include <linux/sysfs.h> |
e9eee03e IM |
26 | #include <linux/types.h> |
27 | #include <linux/init.h> | |
28 | #include <linux/kmod.h> | |
29 | #include <linux/poll.h> | |
30 | #include <linux/cpu.h> | |
31 | #include <linux/fs.h> | |
32 | ||
d88203d1 | 33 | #include <asm/processor.h> |
1da177e4 | 34 | #include <asm/uaccess.h> |
e02e68d3 | 35 | #include <asm/idle.h> |
e9eee03e IM |
36 | #include <asm/mce.h> |
37 | #include <asm/msr.h> | |
38 | #include <asm/smp.h> | |
1da177e4 | 39 | |
711c2e48 IM |
40 | #include "mce.h" |
41 | ||
5d727926 AK |
42 | /* Handle unconfigured int18 (should never happen) */ |
43 | static void unexpected_machine_check(struct pt_regs *regs, long error_code) | |
44 | { | |
45 | printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n", | |
46 | smp_processor_id()); | |
47 | } | |
48 | ||
49 | /* Call the installed machine check handler for this CPU setup. */ | |
50 | void (*machine_check_vector)(struct pt_regs *, long error_code) = | |
51 | unexpected_machine_check; | |
04b2b1a4 AK |
52 | |
53 | int mce_disabled; | |
54 | ||
711c2e48 IM |
55 | #ifdef CONFIG_X86_64 |
56 | ||
e9eee03e | 57 | #define MISC_MCELOG_MINOR 227 |
0d7482e3 | 58 | |
553f265f AK |
59 | atomic_t mce_entry; |
60 | ||
bd78432c TH |
61 | /* |
62 | * Tolerant levels: | |
63 | * 0: always panic on uncorrected errors, log corrected errors | |
64 | * 1: panic or SIGBUS on uncorrected errors, log corrected errors | |
65 | * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors | |
66 | * 3: never panic or SIGBUS, log all errors (for testing only) | |
67 | */ | |
e9eee03e IM |
68 | static int tolerant = 1; |
69 | static int banks; | |
70 | static u64 *bank; | |
71 | static unsigned long notify_user; | |
72 | static int rip_msr; | |
73 | static int mce_bootlog = -1; | |
74 | static atomic_t mce_events; | |
a98f0dd3 | 75 | |
e9eee03e IM |
76 | static char trigger[128]; |
77 | static char *trigger_argv[2] = { trigger, NULL }; | |
1da177e4 | 78 | |
06b7a7a5 AK |
79 | static unsigned long dont_init_banks; |
80 | ||
e02e68d3 TH |
81 | static DECLARE_WAIT_QUEUE_HEAD(mce_wait); |
82 | ||
ee031c31 AK |
83 | /* MCA banks polled by the period polling timer for corrected events */ |
84 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { | |
85 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL | |
86 | }; | |
87 | ||
06b7a7a5 AK |
88 | static inline int skip_bank_init(int i) |
89 | { | |
90 | return i < BITS_PER_LONG && test_bit(i, &dont_init_banks); | |
91 | } | |
92 | ||
b5f2fa4e AK |
93 | /* Do initial initialization of a struct mce */ |
94 | void mce_setup(struct mce *m) | |
95 | { | |
96 | memset(m, 0, sizeof(struct mce)); | |
97 | m->cpu = smp_processor_id(); | |
98 | rdtscll(m->tsc); | |
99 | } | |
100 | ||
1da177e4 LT |
101 | /* |
102 | * Lockless MCE logging infrastructure. | |
103 | * This avoids deadlocks on printk locks without having to break locks. Also | |
104 | * separate MCEs from kernel messages to avoid bogus bug reports. | |
105 | */ | |
106 | ||
231fd906 | 107 | static struct mce_log mcelog = { |
1da177e4 LT |
108 | MCE_LOG_SIGNATURE, |
109 | MCE_LOG_LEN, | |
d88203d1 | 110 | }; |
1da177e4 LT |
111 | |
112 | void mce_log(struct mce *mce) | |
113 | { | |
114 | unsigned next, entry; | |
e9eee03e | 115 | |
a98f0dd3 | 116 | atomic_inc(&mce_events); |
1da177e4 | 117 | mce->finished = 0; |
7644143c | 118 | wmb(); |
1da177e4 LT |
119 | for (;;) { |
120 | entry = rcu_dereference(mcelog.next); | |
673242c1 | 121 | for (;;) { |
e9eee03e IM |
122 | /* |
123 | * When the buffer fills up discard new entries. | |
124 | * Assume that the earlier errors are the more | |
125 | * interesting ones: | |
126 | */ | |
673242c1 | 127 | if (entry >= MCE_LOG_LEN) { |
53756d37 | 128 | set_bit(MCE_OVERFLOW, (unsigned long *)&mcelog.flags); |
673242c1 AK |
129 | return; |
130 | } | |
e9eee03e | 131 | /* Old left over entry. Skip: */ |
673242c1 AK |
132 | if (mcelog.entry[entry].finished) { |
133 | entry++; | |
134 | continue; | |
135 | } | |
7644143c | 136 | break; |
1da177e4 | 137 | } |
1da177e4 LT |
138 | smp_rmb(); |
139 | next = entry + 1; | |
140 | if (cmpxchg(&mcelog.next, entry, next) == entry) | |
141 | break; | |
142 | } | |
143 | memcpy(mcelog.entry + entry, mce, sizeof(struct mce)); | |
7644143c | 144 | wmb(); |
1da177e4 | 145 | mcelog.entry[entry].finished = 1; |
7644143c | 146 | wmb(); |
1da177e4 | 147 | |
e02e68d3 | 148 | set_bit(0, ¬ify_user); |
1da177e4 LT |
149 | } |
150 | ||
151 | static void print_mce(struct mce *m) | |
152 | { | |
153 | printk(KERN_EMERG "\n" | |
4855170f | 154 | KERN_EMERG "HARDWARE ERROR\n" |
1da177e4 LT |
155 | KERN_EMERG |
156 | "CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n", | |
157 | m->cpu, m->mcgstatus, m->bank, m->status); | |
65ea5b03 | 158 | if (m->ip) { |
d88203d1 | 159 | printk(KERN_EMERG "RIP%s %02x:<%016Lx> ", |
1da177e4 | 160 | !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", |
65ea5b03 | 161 | m->cs, m->ip); |
1da177e4 | 162 | if (m->cs == __KERNEL_CS) |
65ea5b03 | 163 | print_symbol("{%s}", m->ip); |
1da177e4 LT |
164 | printk("\n"); |
165 | } | |
f6d1826d | 166 | printk(KERN_EMERG "TSC %llx ", m->tsc); |
1da177e4 | 167 | if (m->addr) |
f6d1826d | 168 | printk("ADDR %llx ", m->addr); |
1da177e4 | 169 | if (m->misc) |
f6d1826d | 170 | printk("MISC %llx ", m->misc); |
1da177e4 | 171 | printk("\n"); |
4855170f | 172 | printk(KERN_EMERG "This is not a software problem!\n"); |
d88203d1 TG |
173 | printk(KERN_EMERG "Run through mcelog --ascii to decode " |
174 | "and contact your hardware vendor\n"); | |
1da177e4 LT |
175 | } |
176 | ||
3cde5c8c | 177 | static void mce_panic(char *msg, struct mce *backup, u64 start) |
d88203d1 | 178 | { |
1da177e4 | 179 | int i; |
e02e68d3 | 180 | |
1da177e4 LT |
181 | oops_begin(); |
182 | for (i = 0; i < MCE_LOG_LEN; i++) { | |
3cde5c8c | 183 | u64 tsc = mcelog.entry[i].tsc; |
d88203d1 | 184 | |
3cde5c8c | 185 | if ((s64)(tsc - start) < 0) |
1da177e4 | 186 | continue; |
d88203d1 | 187 | print_mce(&mcelog.entry[i]); |
1da177e4 LT |
188 | if (backup && mcelog.entry[i].tsc == backup->tsc) |
189 | backup = NULL; | |
190 | } | |
191 | if (backup) | |
192 | print_mce(backup); | |
e02e68d3 | 193 | panic(msg); |
d88203d1 | 194 | } |
1da177e4 | 195 | |
88ccbedd | 196 | int mce_available(struct cpuinfo_x86 *c) |
1da177e4 | 197 | { |
04b2b1a4 | 198 | if (mce_disabled) |
5b4408fd | 199 | return 0; |
3d1712c9 | 200 | return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); |
1da177e4 LT |
201 | } |
202 | ||
94ad8474 AK |
203 | static inline void mce_get_rip(struct mce *m, struct pt_regs *regs) |
204 | { | |
205 | if (regs && (m->mcgstatus & MCG_STATUS_RIPV)) { | |
65ea5b03 | 206 | m->ip = regs->ip; |
94ad8474 AK |
207 | m->cs = regs->cs; |
208 | } else { | |
65ea5b03 | 209 | m->ip = 0; |
94ad8474 AK |
210 | m->cs = 0; |
211 | } | |
212 | if (rip_msr) { | |
213 | /* Assume the RIP in the MSR is exact. Is this true? */ | |
214 | m->mcgstatus |= MCG_STATUS_EIPV; | |
65ea5b03 | 215 | rdmsrl(rip_msr, m->ip); |
94ad8474 AK |
216 | m->cs = 0; |
217 | } | |
218 | } | |
219 | ||
d88203d1 | 220 | /* |
b79109c3 AK |
221 | * Poll for corrected events or events that happened before reset. |
222 | * Those are just logged through /dev/mcelog. | |
223 | * | |
224 | * This is executed in standard interrupt context. | |
225 | */ | |
ee031c31 | 226 | void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) |
b79109c3 AK |
227 | { |
228 | struct mce m; | |
229 | int i; | |
230 | ||
231 | mce_setup(&m); | |
232 | ||
233 | rdmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus); | |
234 | for (i = 0; i < banks; i++) { | |
ee031c31 | 235 | if (!bank[i] || !test_bit(i, *b)) |
b79109c3 AK |
236 | continue; |
237 | ||
238 | m.misc = 0; | |
239 | m.addr = 0; | |
240 | m.bank = i; | |
241 | m.tsc = 0; | |
242 | ||
243 | barrier(); | |
244 | rdmsrl(MSR_IA32_MC0_STATUS + i*4, m.status); | |
245 | if (!(m.status & MCI_STATUS_VAL)) | |
246 | continue; | |
247 | ||
248 | /* | |
249 | * Uncorrected events are handled by the exception handler | |
250 | * when it is enabled. But when the exception is disabled log | |
251 | * everything. | |
252 | * | |
253 | * TBD do the same check for MCI_STATUS_EN here? | |
254 | */ | |
255 | if ((m.status & MCI_STATUS_UC) && !(flags & MCP_UC)) | |
256 | continue; | |
257 | ||
258 | if (m.status & MCI_STATUS_MISCV) | |
259 | rdmsrl(MSR_IA32_MC0_MISC + i*4, m.misc); | |
260 | if (m.status & MCI_STATUS_ADDRV) | |
261 | rdmsrl(MSR_IA32_MC0_ADDR + i*4, m.addr); | |
262 | ||
263 | if (!(flags & MCP_TIMESTAMP)) | |
264 | m.tsc = 0; | |
265 | /* | |
266 | * Don't get the IP here because it's unlikely to | |
267 | * have anything to do with the actual error location. | |
268 | */ | |
5679af4c AK |
269 | if (!(flags & MCP_DONTLOG)) { |
270 | mce_log(&m); | |
271 | add_taint(TAINT_MACHINE_CHECK); | |
272 | } | |
b79109c3 AK |
273 | |
274 | /* | |
275 | * Clear state for this bank. | |
276 | */ | |
277 | wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); | |
278 | } | |
279 | ||
280 | /* | |
281 | * Don't clear MCG_STATUS here because it's only defined for | |
282 | * exceptions. | |
283 | */ | |
284 | } | |
285 | ||
286 | /* | |
287 | * The actual machine check handler. This only handles real | |
288 | * exceptions when something got corrupted coming in through int 18. | |
289 | * | |
290 | * This is executed in NMI context not subject to normal locking rules. This | |
291 | * implies that most kernel services cannot be safely used. Don't even | |
292 | * think about putting a printk in there! | |
1da177e4 | 293 | */ |
e9eee03e | 294 | void do_machine_check(struct pt_regs *regs, long error_code) |
1da177e4 LT |
295 | { |
296 | struct mce m, panicm; | |
e9eee03e | 297 | int panicm_found = 0; |
1da177e4 LT |
298 | u64 mcestart = 0; |
299 | int i; | |
bd78432c TH |
300 | /* |
301 | * If no_way_out gets set, there is no safe way to recover from this | |
302 | * MCE. If tolerant is cranked up, we'll try anyway. | |
303 | */ | |
304 | int no_way_out = 0; | |
305 | /* | |
306 | * If kill_it gets set, there might be a way to recover from this | |
307 | * error. | |
308 | */ | |
309 | int kill_it = 0; | |
b79109c3 | 310 | DECLARE_BITMAP(toclear, MAX_NR_BANKS); |
1da177e4 | 311 | |
553f265f AK |
312 | atomic_inc(&mce_entry); |
313 | ||
b79109c3 | 314 | if (notify_die(DIE_NMI, "machine check", regs, error_code, |
22f5991c | 315 | 18, SIGKILL) == NOTIFY_STOP) |
b79109c3 AK |
316 | goto out2; |
317 | if (!banks) | |
553f265f | 318 | goto out2; |
1da177e4 | 319 | |
b5f2fa4e AK |
320 | mce_setup(&m); |
321 | ||
1da177e4 | 322 | rdmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus); |
e9eee03e | 323 | |
bd78432c | 324 | /* if the restart IP is not valid, we're done for */ |
1da177e4 | 325 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) |
bd78432c | 326 | no_way_out = 1; |
d88203d1 | 327 | |
1da177e4 LT |
328 | rdtscll(mcestart); |
329 | barrier(); | |
330 | ||
331 | for (i = 0; i < banks; i++) { | |
b79109c3 | 332 | __clear_bit(i, toclear); |
0d7482e3 | 333 | if (!bank[i]) |
1da177e4 | 334 | continue; |
d88203d1 TG |
335 | |
336 | m.misc = 0; | |
1da177e4 LT |
337 | m.addr = 0; |
338 | m.bank = i; | |
1da177e4 LT |
339 | |
340 | rdmsrl(MSR_IA32_MC0_STATUS + i*4, m.status); | |
341 | if ((m.status & MCI_STATUS_VAL) == 0) | |
342 | continue; | |
343 | ||
b79109c3 AK |
344 | /* |
345 | * Non uncorrected errors are handled by machine_check_poll | |
346 | * Leave them alone. | |
347 | */ | |
348 | if ((m.status & MCI_STATUS_UC) == 0) | |
349 | continue; | |
350 | ||
351 | /* | |
352 | * Set taint even when machine check was not enabled. | |
353 | */ | |
354 | add_taint(TAINT_MACHINE_CHECK); | |
355 | ||
356 | __set_bit(i, toclear); | |
357 | ||
1da177e4 | 358 | if (m.status & MCI_STATUS_EN) { |
bd78432c TH |
359 | /* if PCC was set, there's no way out */ |
360 | no_way_out |= !!(m.status & MCI_STATUS_PCC); | |
361 | /* | |
362 | * If this error was uncorrectable and there was | |
363 | * an overflow, we're in trouble. If no overflow, | |
364 | * we might get away with just killing a task. | |
365 | */ | |
366 | if (m.status & MCI_STATUS_UC) { | |
367 | if (tolerant < 1 || m.status & MCI_STATUS_OVER) | |
368 | no_way_out = 1; | |
369 | kill_it = 1; | |
370 | } | |
b79109c3 AK |
371 | } else { |
372 | /* | |
373 | * Machine check event was not enabled. Clear, but | |
374 | * ignore. | |
375 | */ | |
376 | continue; | |
1da177e4 LT |
377 | } |
378 | ||
379 | if (m.status & MCI_STATUS_MISCV) | |
380 | rdmsrl(MSR_IA32_MC0_MISC + i*4, m.misc); | |
381 | if (m.status & MCI_STATUS_ADDRV) | |
382 | rdmsrl(MSR_IA32_MC0_ADDR + i*4, m.addr); | |
383 | ||
94ad8474 | 384 | mce_get_rip(&m, regs); |
b79109c3 | 385 | mce_log(&m); |
1da177e4 | 386 | |
e9eee03e IM |
387 | /* |
388 | * Did this bank cause the exception? | |
389 | * | |
390 | * Assume that the bank with uncorrectable errors did it, | |
391 | * and that there is only a single one: | |
392 | */ | |
393 | if ((m.status & MCI_STATUS_UC) && | |
394 | (m.status & MCI_STATUS_EN)) { | |
1da177e4 LT |
395 | panicm = m; |
396 | panicm_found = 1; | |
397 | } | |
1da177e4 LT |
398 | } |
399 | ||
e9eee03e IM |
400 | /* |
401 | * If we didn't find an uncorrectable error, pick | |
402 | * the last one (shouldn't happen, just being safe). | |
403 | */ | |
1da177e4 LT |
404 | if (!panicm_found) |
405 | panicm = m; | |
bd78432c TH |
406 | |
407 | /* | |
408 | * If we have decided that we just CAN'T continue, and the user | |
e9eee03e | 409 | * has not set tolerant to an insane level, give up and die. |
bd78432c TH |
410 | */ |
411 | if (no_way_out && tolerant < 3) | |
1da177e4 | 412 | mce_panic("Machine check", &panicm, mcestart); |
bd78432c TH |
413 | |
414 | /* | |
415 | * If the error seems to be unrecoverable, something should be | |
416 | * done. Try to kill as little as possible. If we can kill just | |
417 | * one task, do that. If the user has set the tolerance very | |
418 | * high, don't try to do anything at all. | |
419 | */ | |
420 | if (kill_it && tolerant < 3) { | |
1da177e4 LT |
421 | int user_space = 0; |
422 | ||
bd78432c TH |
423 | /* |
424 | * If the EIPV bit is set, it means the saved IP is the | |
425 | * instruction which caused the MCE. | |
426 | */ | |
427 | if (m.mcgstatus & MCG_STATUS_EIPV) | |
65ea5b03 | 428 | user_space = panicm.ip && (panicm.cs & 3); |
bd78432c TH |
429 | |
430 | /* | |
431 | * If we know that the error was in user space, send a | |
432 | * SIGBUS. Otherwise, panic if tolerance is low. | |
433 | * | |
380851bc | 434 | * force_sig() takes an awful lot of locks and has a slight |
bd78432c TH |
435 | * risk of deadlocking. |
436 | */ | |
437 | if (user_space) { | |
380851bc | 438 | force_sig(SIGBUS, current); |
bd78432c TH |
439 | } else if (panic_on_oops || tolerant < 2) { |
440 | mce_panic("Uncorrected machine check", | |
441 | &panicm, mcestart); | |
442 | } | |
1da177e4 LT |
443 | } |
444 | ||
e02e68d3 TH |
445 | /* notify userspace ASAP */ |
446 | set_thread_flag(TIF_MCE_NOTIFY); | |
447 | ||
bd78432c | 448 | /* the last thing we do is clear state */ |
b79109c3 AK |
449 | for (i = 0; i < banks; i++) { |
450 | if (test_bit(i, toclear)) | |
451 | wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); | |
452 | } | |
1da177e4 | 453 | wrmsrl(MSR_IA32_MCG_STATUS, 0); |
553f265f AK |
454 | out2: |
455 | atomic_dec(&mce_entry); | |
1da177e4 LT |
456 | } |
457 | ||
15d5f839 DZ |
458 | #ifdef CONFIG_X86_MCE_INTEL |
459 | /*** | |
460 | * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog | |
676b1855 | 461 | * @cpu: The CPU on which the event occurred. |
15d5f839 DZ |
462 | * @status: Event status information |
463 | * | |
464 | * This function should be called by the thermal interrupt after the | |
465 | * event has been processed and the decision was made to log the event | |
466 | * further. | |
467 | * | |
468 | * The status parameter will be saved to the 'status' field of 'struct mce' | |
469 | * and historically has been the register value of the | |
470 | * MSR_IA32_THERMAL_STATUS (Intel) msr. | |
471 | */ | |
b5f2fa4e | 472 | void mce_log_therm_throt_event(__u64 status) |
15d5f839 DZ |
473 | { |
474 | struct mce m; | |
475 | ||
b5f2fa4e | 476 | mce_setup(&m); |
15d5f839 DZ |
477 | m.bank = MCE_THERMAL_BANK; |
478 | m.status = status; | |
15d5f839 DZ |
479 | mce_log(&m); |
480 | } | |
481 | #endif /* CONFIG_X86_MCE_INTEL */ | |
482 | ||
1da177e4 | 483 | /* |
8a336b0a TH |
484 | * Periodic polling timer for "silent" machine check errors. If the |
485 | * poller finds an MCE, poll 2x faster. When the poller finds no more | |
486 | * errors, poll 2x slower (up to check_interval seconds). | |
1da177e4 | 487 | */ |
1da177e4 | 488 | static int check_interval = 5 * 60; /* 5 minutes */ |
e9eee03e | 489 | |
6298c512 | 490 | static DEFINE_PER_CPU(int, next_interval); /* in jiffies */ |
52d168e2 | 491 | static DEFINE_PER_CPU(struct timer_list, mce_timer); |
1da177e4 | 492 | |
52d168e2 | 493 | static void mcheck_timer(unsigned long data) |
1da177e4 | 494 | { |
52d168e2 | 495 | struct timer_list *t = &per_cpu(mce_timer, data); |
6298c512 | 496 | int *n; |
52d168e2 AK |
497 | |
498 | WARN_ON(smp_processor_id() != data); | |
499 | ||
e9eee03e | 500 | if (mce_available(¤t_cpu_data)) { |
ee031c31 AK |
501 | machine_check_poll(MCP_TIMESTAMP, |
502 | &__get_cpu_var(mce_poll_banks)); | |
e9eee03e | 503 | } |
1da177e4 LT |
504 | |
505 | /* | |
e02e68d3 TH |
506 | * Alert userspace if needed. If we logged an MCE, reduce the |
507 | * polling interval, otherwise increase the polling interval. | |
1da177e4 | 508 | */ |
6298c512 | 509 | n = &__get_cpu_var(next_interval); |
e02e68d3 | 510 | if (mce_notify_user()) { |
6298c512 | 511 | *n = max(*n/2, HZ/100); |
e02e68d3 | 512 | } else { |
6298c512 | 513 | *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ)); |
e02e68d3 TH |
514 | } |
515 | ||
6298c512 | 516 | t->expires = jiffies + *n; |
52d168e2 | 517 | add_timer(t); |
e02e68d3 TH |
518 | } |
519 | ||
9bd98405 AK |
520 | static void mce_do_trigger(struct work_struct *work) |
521 | { | |
522 | call_usermodehelper(trigger, trigger_argv, NULL, UMH_NO_WAIT); | |
523 | } | |
524 | ||
525 | static DECLARE_WORK(mce_trigger_work, mce_do_trigger); | |
526 | ||
e02e68d3 | 527 | /* |
9bd98405 AK |
528 | * Notify the user(s) about new machine check events. |
529 | * Can be called from interrupt context, but not from machine check/NMI | |
530 | * context. | |
e02e68d3 TH |
531 | */ |
532 | int mce_notify_user(void) | |
533 | { | |
8457c84d AK |
534 | /* Not more than two messages every minute */ |
535 | static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); | |
536 | ||
e02e68d3 | 537 | clear_thread_flag(TIF_MCE_NOTIFY); |
e9eee03e | 538 | |
e02e68d3 | 539 | if (test_and_clear_bit(0, ¬ify_user)) { |
e02e68d3 | 540 | wake_up_interruptible(&mce_wait); |
9bd98405 AK |
541 | |
542 | /* | |
543 | * There is no risk of missing notifications because | |
544 | * work_pending is always cleared before the function is | |
545 | * executed. | |
546 | */ | |
547 | if (trigger[0] && !work_pending(&mce_trigger_work)) | |
548 | schedule_work(&mce_trigger_work); | |
e02e68d3 | 549 | |
8457c84d | 550 | if (__ratelimit(&ratelimit)) |
8a336b0a | 551 | printk(KERN_INFO "Machine check events logged\n"); |
e02e68d3 TH |
552 | |
553 | return 1; | |
1da177e4 | 554 | } |
e02e68d3 TH |
555 | return 0; |
556 | } | |
8a336b0a | 557 | |
e9eee03e | 558 | /* see if the idle task needs to notify userspace: */ |
e02e68d3 | 559 | static int |
e9eee03e IM |
560 | mce_idle_callback(struct notifier_block *nfb, unsigned long action, |
561 | void *unused) | |
e02e68d3 TH |
562 | { |
563 | /* IDLE_END should be safe - interrupts are back on */ | |
564 | if (action == IDLE_END && test_thread_flag(TIF_MCE_NOTIFY)) | |
565 | mce_notify_user(); | |
566 | ||
567 | return NOTIFY_OK; | |
1da177e4 LT |
568 | } |
569 | ||
e02e68d3 | 570 | static struct notifier_block mce_idle_notifier = { |
e9eee03e | 571 | .notifier_call = mce_idle_callback, |
e02e68d3 | 572 | }; |
1da177e4 LT |
573 | |
574 | static __init int periodic_mcheck_init(void) | |
d88203d1 | 575 | { |
52d168e2 AK |
576 | idle_notifier_register(&mce_idle_notifier); |
577 | return 0; | |
d88203d1 | 578 | } |
1da177e4 LT |
579 | __initcall(periodic_mcheck_init); |
580 | ||
d88203d1 | 581 | /* |
1da177e4 LT |
582 | * Initialize Machine Checks for a CPU. |
583 | */ | |
0d7482e3 | 584 | static int mce_cap_init(void) |
1da177e4 | 585 | { |
0d7482e3 | 586 | unsigned b; |
e9eee03e | 587 | u64 cap; |
1da177e4 LT |
588 | |
589 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
01c6680a TG |
590 | |
591 | b = cap & MCG_BANKCNT_MASK; | |
b659294b IM |
592 | printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b); |
593 | ||
0d7482e3 AK |
594 | if (b > MAX_NR_BANKS) { |
595 | printk(KERN_WARNING | |
596 | "MCE: Using only %u machine check banks out of %u\n", | |
597 | MAX_NR_BANKS, b); | |
598 | b = MAX_NR_BANKS; | |
599 | } | |
600 | ||
601 | /* Don't support asymmetric configurations today */ | |
602 | WARN_ON(banks != 0 && b != banks); | |
603 | banks = b; | |
604 | if (!bank) { | |
605 | bank = kmalloc(banks * sizeof(u64), GFP_KERNEL); | |
606 | if (!bank) | |
607 | return -ENOMEM; | |
608 | memset(bank, 0xff, banks * sizeof(u64)); | |
1da177e4 | 609 | } |
0d7482e3 | 610 | |
94ad8474 | 611 | /* Use accurate RIP reporting if available. */ |
01c6680a | 612 | if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) |
94ad8474 | 613 | rip_msr = MSR_IA32_MCG_EIP; |
1da177e4 | 614 | |
0d7482e3 AK |
615 | return 0; |
616 | } | |
617 | ||
618 | static void mce_init(void *dummy) | |
619 | { | |
e9eee03e | 620 | mce_banks_t all_banks; |
0d7482e3 AK |
621 | u64 cap; |
622 | int i; | |
623 | ||
b79109c3 AK |
624 | /* |
625 | * Log the machine checks left over from the previous reset. | |
626 | */ | |
ee031c31 | 627 | bitmap_fill(all_banks, MAX_NR_BANKS); |
5679af4c | 628 | machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks); |
1da177e4 LT |
629 | |
630 | set_in_cr4(X86_CR4_MCE); | |
631 | ||
0d7482e3 | 632 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
1da177e4 LT |
633 | if (cap & MCG_CTL_P) |
634 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); | |
635 | ||
636 | for (i = 0; i < banks; i++) { | |
06b7a7a5 AK |
637 | if (skip_bank_init(i)) |
638 | continue; | |
0d7482e3 | 639 | wrmsrl(MSR_IA32_MC0_CTL+4*i, bank[i]); |
1da177e4 | 640 | wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); |
d88203d1 | 641 | } |
1da177e4 LT |
642 | } |
643 | ||
644 | /* Add per CPU specific workarounds here */ | |
ec5b3d32 | 645 | static void mce_cpu_quirks(struct cpuinfo_x86 *c) |
d88203d1 | 646 | { |
1da177e4 | 647 | /* This should be disabled by the BIOS, but isn't always */ |
911f6a7b | 648 | if (c->x86_vendor == X86_VENDOR_AMD) { |
e9eee03e IM |
649 | if (c->x86 == 15 && banks > 4) { |
650 | /* | |
651 | * disable GART TBL walk error reporting, which | |
652 | * trips off incorrectly with the IOMMU & 3ware | |
653 | * & Cerberus: | |
654 | */ | |
0d7482e3 | 655 | clear_bit(10, (unsigned long *)&bank[4]); |
e9eee03e IM |
656 | } |
657 | if (c->x86 <= 17 && mce_bootlog < 0) { | |
658 | /* | |
659 | * Lots of broken BIOS around that don't clear them | |
660 | * by default and leave crap in there. Don't log: | |
661 | */ | |
911f6a7b | 662 | mce_bootlog = 0; |
e9eee03e | 663 | } |
2e6f694f AK |
664 | /* |
665 | * Various K7s with broken bank 0 around. Always disable | |
666 | * by default. | |
667 | */ | |
668 | if (c->x86 == 6) | |
669 | bank[0] = 0; | |
1da177e4 | 670 | } |
e583538f | 671 | |
06b7a7a5 AK |
672 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
673 | /* | |
674 | * SDM documents that on family 6 bank 0 should not be written | |
675 | * because it aliases to another special BIOS controlled | |
676 | * register. | |
677 | * But it's not aliased anymore on model 0x1a+ | |
678 | * Don't ignore bank 0 completely because there could be a | |
679 | * valid event later, merely don't write CTL0. | |
680 | */ | |
681 | ||
682 | if (c->x86 == 6 && c->x86_model < 0x1A) | |
683 | __set_bit(0, &dont_init_banks); | |
684 | } | |
d88203d1 | 685 | } |
1da177e4 | 686 | |
cc3ca220 | 687 | static void mce_cpu_features(struct cpuinfo_x86 *c) |
1da177e4 LT |
688 | { |
689 | switch (c->x86_vendor) { | |
690 | case X86_VENDOR_INTEL: | |
691 | mce_intel_feature_init(c); | |
692 | break; | |
89b831ef JS |
693 | case X86_VENDOR_AMD: |
694 | mce_amd_feature_init(c); | |
695 | break; | |
1da177e4 LT |
696 | default: |
697 | break; | |
698 | } | |
699 | } | |
700 | ||
52d168e2 AK |
701 | static void mce_init_timer(void) |
702 | { | |
703 | struct timer_list *t = &__get_cpu_var(mce_timer); | |
6298c512 | 704 | int *n = &__get_cpu_var(next_interval); |
52d168e2 | 705 | |
6298c512 AK |
706 | *n = check_interval * HZ; |
707 | if (!*n) | |
52d168e2 AK |
708 | return; |
709 | setup_timer(t, mcheck_timer, smp_processor_id()); | |
6298c512 | 710 | t->expires = round_jiffies(jiffies + *n); |
52d168e2 AK |
711 | add_timer(t); |
712 | } | |
713 | ||
d88203d1 | 714 | /* |
1da177e4 | 715 | * Called for each booted CPU to set up machine checks. |
e9eee03e | 716 | * Must be called with preempt off: |
1da177e4 | 717 | */ |
e6982c67 | 718 | void __cpuinit mcheck_init(struct cpuinfo_x86 *c) |
1da177e4 | 719 | { |
5b4408fd | 720 | if (!mce_available(c)) |
1da177e4 LT |
721 | return; |
722 | ||
0d7482e3 | 723 | if (mce_cap_init() < 0) { |
04b2b1a4 | 724 | mce_disabled = 1; |
0d7482e3 AK |
725 | return; |
726 | } | |
727 | mce_cpu_quirks(c); | |
728 | ||
5d727926 AK |
729 | machine_check_vector = do_machine_check; |
730 | ||
1da177e4 LT |
731 | mce_init(NULL); |
732 | mce_cpu_features(c); | |
52d168e2 | 733 | mce_init_timer(); |
1da177e4 LT |
734 | } |
735 | ||
736 | /* | |
737 | * Character device to read and clear the MCE log. | |
738 | */ | |
739 | ||
f528e7ba | 740 | static DEFINE_SPINLOCK(mce_state_lock); |
e9eee03e IM |
741 | static int open_count; /* #times opened */ |
742 | static int open_exclu; /* already open exclusive? */ | |
f528e7ba TH |
743 | |
744 | static int mce_open(struct inode *inode, struct file *file) | |
745 | { | |
38c4c97c | 746 | lock_kernel(); |
f528e7ba TH |
747 | spin_lock(&mce_state_lock); |
748 | ||
749 | if (open_exclu || (open_count && (file->f_flags & O_EXCL))) { | |
750 | spin_unlock(&mce_state_lock); | |
38c4c97c | 751 | unlock_kernel(); |
e9eee03e | 752 | |
f528e7ba TH |
753 | return -EBUSY; |
754 | } | |
755 | ||
756 | if (file->f_flags & O_EXCL) | |
757 | open_exclu = 1; | |
758 | open_count++; | |
759 | ||
760 | spin_unlock(&mce_state_lock); | |
38c4c97c | 761 | unlock_kernel(); |
f528e7ba | 762 | |
bd78432c | 763 | return nonseekable_open(inode, file); |
f528e7ba TH |
764 | } |
765 | ||
766 | static int mce_release(struct inode *inode, struct file *file) | |
767 | { | |
768 | spin_lock(&mce_state_lock); | |
769 | ||
770 | open_count--; | |
771 | open_exclu = 0; | |
772 | ||
773 | spin_unlock(&mce_state_lock); | |
774 | ||
775 | return 0; | |
776 | } | |
777 | ||
d88203d1 TG |
778 | static void collect_tscs(void *data) |
779 | { | |
1da177e4 | 780 | unsigned long *cpu_tsc = (unsigned long *)data; |
d88203d1 | 781 | |
1da177e4 | 782 | rdtscll(cpu_tsc[smp_processor_id()]); |
d88203d1 | 783 | } |
1da177e4 | 784 | |
e9eee03e IM |
785 | static DEFINE_MUTEX(mce_read_mutex); |
786 | ||
d88203d1 TG |
787 | static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize, |
788 | loff_t *off) | |
1da177e4 | 789 | { |
e9eee03e | 790 | char __user *buf = ubuf; |
f0de53bb | 791 | unsigned long *cpu_tsc; |
ef41df43 | 792 | unsigned prev, next; |
1da177e4 LT |
793 | int i, err; |
794 | ||
6bca67f9 | 795 | cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL); |
f0de53bb AK |
796 | if (!cpu_tsc) |
797 | return -ENOMEM; | |
798 | ||
8c8b8859 | 799 | mutex_lock(&mce_read_mutex); |
1da177e4 LT |
800 | next = rcu_dereference(mcelog.next); |
801 | ||
802 | /* Only supports full reads right now */ | |
d88203d1 | 803 | if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) { |
8c8b8859 | 804 | mutex_unlock(&mce_read_mutex); |
f0de53bb | 805 | kfree(cpu_tsc); |
e9eee03e | 806 | |
1da177e4 LT |
807 | return -EINVAL; |
808 | } | |
809 | ||
810 | err = 0; | |
ef41df43 HY |
811 | prev = 0; |
812 | do { | |
813 | for (i = prev; i < next; i++) { | |
814 | unsigned long start = jiffies; | |
815 | ||
816 | while (!mcelog.entry[i].finished) { | |
817 | if (time_after_eq(jiffies, start + 2)) { | |
818 | memset(mcelog.entry + i, 0, | |
819 | sizeof(struct mce)); | |
820 | goto timeout; | |
821 | } | |
822 | cpu_relax(); | |
673242c1 | 823 | } |
ef41df43 HY |
824 | smp_rmb(); |
825 | err |= copy_to_user(buf, mcelog.entry + i, | |
826 | sizeof(struct mce)); | |
827 | buf += sizeof(struct mce); | |
828 | timeout: | |
829 | ; | |
673242c1 | 830 | } |
1da177e4 | 831 | |
ef41df43 HY |
832 | memset(mcelog.entry + prev, 0, |
833 | (next - prev) * sizeof(struct mce)); | |
834 | prev = next; | |
835 | next = cmpxchg(&mcelog.next, prev, 0); | |
836 | } while (next != prev); | |
1da177e4 | 837 | |
b2b18660 | 838 | synchronize_sched(); |
1da177e4 | 839 | |
d88203d1 TG |
840 | /* |
841 | * Collect entries that were still getting written before the | |
842 | * synchronize. | |
843 | */ | |
15c8b6c1 | 844 | on_each_cpu(collect_tscs, cpu_tsc, 1); |
e9eee03e | 845 | |
d88203d1 TG |
846 | for (i = next; i < MCE_LOG_LEN; i++) { |
847 | if (mcelog.entry[i].finished && | |
848 | mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) { | |
849 | err |= copy_to_user(buf, mcelog.entry+i, | |
850 | sizeof(struct mce)); | |
1da177e4 LT |
851 | smp_rmb(); |
852 | buf += sizeof(struct mce); | |
853 | memset(&mcelog.entry[i], 0, sizeof(struct mce)); | |
854 | } | |
d88203d1 | 855 | } |
8c8b8859 | 856 | mutex_unlock(&mce_read_mutex); |
f0de53bb | 857 | kfree(cpu_tsc); |
e9eee03e | 858 | |
d88203d1 | 859 | return err ? -EFAULT : buf - ubuf; |
1da177e4 LT |
860 | } |
861 | ||
e02e68d3 TH |
862 | static unsigned int mce_poll(struct file *file, poll_table *wait) |
863 | { | |
864 | poll_wait(file, &mce_wait, wait); | |
865 | if (rcu_dereference(mcelog.next)) | |
866 | return POLLIN | POLLRDNORM; | |
867 | return 0; | |
868 | } | |
869 | ||
c68461b6 | 870 | static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg) |
1da177e4 LT |
871 | { |
872 | int __user *p = (int __user *)arg; | |
d88203d1 | 873 | |
1da177e4 | 874 | if (!capable(CAP_SYS_ADMIN)) |
d88203d1 | 875 | return -EPERM; |
e9eee03e | 876 | |
1da177e4 | 877 | switch (cmd) { |
d88203d1 | 878 | case MCE_GET_RECORD_LEN: |
1da177e4 LT |
879 | return put_user(sizeof(struct mce), p); |
880 | case MCE_GET_LOG_LEN: | |
d88203d1 | 881 | return put_user(MCE_LOG_LEN, p); |
1da177e4 LT |
882 | case MCE_GETCLEAR_FLAGS: { |
883 | unsigned flags; | |
d88203d1 TG |
884 | |
885 | do { | |
1da177e4 | 886 | flags = mcelog.flags; |
d88203d1 | 887 | } while (cmpxchg(&mcelog.flags, flags, 0) != flags); |
e9eee03e | 888 | |
d88203d1 | 889 | return put_user(flags, p); |
1da177e4 LT |
890 | } |
891 | default: | |
d88203d1 TG |
892 | return -ENOTTY; |
893 | } | |
1da177e4 LT |
894 | } |
895 | ||
5dfe4c96 | 896 | static const struct file_operations mce_chrdev_ops = { |
e9eee03e IM |
897 | .open = mce_open, |
898 | .release = mce_release, | |
899 | .read = mce_read, | |
900 | .poll = mce_poll, | |
901 | .unlocked_ioctl = mce_ioctl, | |
1da177e4 LT |
902 | }; |
903 | ||
904 | static struct miscdevice mce_log_device = { | |
905 | MISC_MCELOG_MINOR, | |
906 | "mcelog", | |
907 | &mce_chrdev_ops, | |
908 | }; | |
909 | ||
13503fa9 HS |
910 | /* |
911 | * mce=off disables machine check | |
912 | * mce=TOLERANCELEVEL (number, see above) | |
913 | * mce=bootlog Log MCEs from before booting. Disabled by default on AMD. | |
914 | * mce=nobootlog Don't log MCEs from before booting. | |
915 | */ | |
1da177e4 LT |
916 | static int __init mcheck_enable(char *str) |
917 | { | |
918 | if (!strcmp(str, "off")) | |
04b2b1a4 | 919 | mce_disabled = 1; |
13503fa9 HS |
920 | else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) |
921 | mce_bootlog = (str[0] == 'b'); | |
8c566ef5 AK |
922 | else if (isdigit(str[0])) |
923 | get_option(&str, &tolerant); | |
13503fa9 HS |
924 | else { |
925 | printk(KERN_INFO "mce= argument %s ignored. Please use /sys\n", | |
926 | str); | |
927 | return 0; | |
928 | } | |
9b41046c | 929 | return 1; |
1da177e4 | 930 | } |
909dd324 | 931 | __setup("mce=", mcheck_enable); |
1da177e4 | 932 | |
d88203d1 | 933 | /* |
1da177e4 | 934 | * Sysfs support |
d88203d1 | 935 | */ |
1da177e4 | 936 | |
973a2dd1 AK |
937 | /* |
938 | * Disable machine checks on suspend and shutdown. We can't really handle | |
939 | * them later. | |
940 | */ | |
941 | static int mce_disable(void) | |
942 | { | |
943 | int i; | |
944 | ||
06b7a7a5 AK |
945 | for (i = 0; i < banks; i++) { |
946 | if (!skip_bank_init(i)) | |
947 | wrmsrl(MSR_IA32_MC0_CTL + i*4, 0); | |
948 | } | |
973a2dd1 AK |
949 | return 0; |
950 | } | |
951 | ||
952 | static int mce_suspend(struct sys_device *dev, pm_message_t state) | |
953 | { | |
954 | return mce_disable(); | |
955 | } | |
956 | ||
957 | static int mce_shutdown(struct sys_device *dev) | |
958 | { | |
959 | return mce_disable(); | |
960 | } | |
961 | ||
e9eee03e IM |
962 | /* |
963 | * On resume clear all MCE state. Don't want to see leftovers from the BIOS. | |
964 | * Only one CPU is active at this time, the others get re-added later using | |
965 | * CPU hotplug: | |
966 | */ | |
1da177e4 LT |
967 | static int mce_resume(struct sys_device *dev) |
968 | { | |
413588c7 | 969 | mce_init(NULL); |
6ec68bff | 970 | mce_cpu_features(¤t_cpu_data); |
e9eee03e | 971 | |
1da177e4 LT |
972 | return 0; |
973 | } | |
974 | ||
52d168e2 AK |
975 | static void mce_cpu_restart(void *data) |
976 | { | |
977 | del_timer_sync(&__get_cpu_var(mce_timer)); | |
978 | if (mce_available(¤t_cpu_data)) | |
979 | mce_init(NULL); | |
980 | mce_init_timer(); | |
981 | } | |
982 | ||
1da177e4 | 983 | /* Reinit MCEs after user configuration changes */ |
d88203d1 TG |
984 | static void mce_restart(void) |
985 | { | |
52d168e2 | 986 | on_each_cpu(mce_cpu_restart, NULL, 1); |
1da177e4 LT |
987 | } |
988 | ||
989 | static struct sysdev_class mce_sysclass = { | |
e9eee03e IM |
990 | .suspend = mce_suspend, |
991 | .shutdown = mce_shutdown, | |
992 | .resume = mce_resume, | |
993 | .name = "machinecheck", | |
1da177e4 LT |
994 | }; |
995 | ||
cb491fca | 996 | DEFINE_PER_CPU(struct sys_device, mce_dev); |
e9eee03e IM |
997 | |
998 | __cpuinitdata | |
999 | void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); | |
1da177e4 LT |
1000 | |
1001 | /* Why are there no generic functions for this? */ | |
1002 | #define ACCESSOR(name, var, start) \ | |
4a0b2b4d AK |
1003 | static ssize_t show_ ## name(struct sys_device *s, \ |
1004 | struct sysdev_attribute *attr, \ | |
1005 | char *buf) { \ | |
3cde5c8c | 1006 | return sprintf(buf, "%Lx\n", (u64)var); \ |
d88203d1 | 1007 | } \ |
4a0b2b4d AK |
1008 | static ssize_t set_ ## name(struct sys_device *s, \ |
1009 | struct sysdev_attribute *attr, \ | |
1010 | const char *buf, size_t siz) { \ | |
d88203d1 | 1011 | char *end; \ |
3cde5c8c | 1012 | u64 new = simple_strtoull(buf, &end, 0); \ |
e9eee03e IM |
1013 | \ |
1014 | if (end == buf) \ | |
1015 | return -EINVAL; \ | |
d88203d1 TG |
1016 | var = new; \ |
1017 | start; \ | |
e9eee03e | 1018 | \ |
d88203d1 TG |
1019 | return end-buf; \ |
1020 | } \ | |
1da177e4 LT |
1021 | static SYSDEV_ATTR(name, 0644, show_ ## name, set_ ## name); |
1022 | ||
0d7482e3 AK |
1023 | static struct sysdev_attribute *bank_attrs; |
1024 | ||
1025 | static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
1026 | char *buf) | |
1027 | { | |
1028 | u64 b = bank[attr - bank_attrs]; | |
e9eee03e | 1029 | |
f6d1826d | 1030 | return sprintf(buf, "%llx\n", b); |
0d7482e3 AK |
1031 | } |
1032 | ||
1033 | static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
1034 | const char *buf, size_t siz) | |
1035 | { | |
1036 | char *end; | |
1037 | u64 new = simple_strtoull(buf, &end, 0); | |
e9eee03e | 1038 | |
0d7482e3 AK |
1039 | if (end == buf) |
1040 | return -EINVAL; | |
e9eee03e | 1041 | |
0d7482e3 AK |
1042 | bank[attr - bank_attrs] = new; |
1043 | mce_restart(); | |
e9eee03e | 1044 | |
0d7482e3 AK |
1045 | return end-buf; |
1046 | } | |
a98f0dd3 | 1047 | |
e9eee03e IM |
1048 | static ssize_t |
1049 | show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf) | |
a98f0dd3 AK |
1050 | { |
1051 | strcpy(buf, trigger); | |
1052 | strcat(buf, "\n"); | |
1053 | return strlen(trigger) + 1; | |
1054 | } | |
1055 | ||
4a0b2b4d | 1056 | static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr, |
e9eee03e | 1057 | const char *buf, size_t siz) |
a98f0dd3 AK |
1058 | { |
1059 | char *p; | |
1060 | int len; | |
e9eee03e | 1061 | |
a98f0dd3 AK |
1062 | strncpy(trigger, buf, sizeof(trigger)); |
1063 | trigger[sizeof(trigger)-1] = 0; | |
1064 | len = strlen(trigger); | |
1065 | p = strchr(trigger, '\n'); | |
e9eee03e IM |
1066 | |
1067 | if (*p) | |
1068 | *p = 0; | |
1069 | ||
a98f0dd3 AK |
1070 | return len; |
1071 | } | |
1072 | ||
1073 | static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger); | |
d95d62c0 | 1074 | static SYSDEV_INT_ATTR(tolerant, 0644, tolerant); |
e9eee03e IM |
1075 | |
1076 | ACCESSOR(check_interval, check_interval, mce_restart()) | |
1077 | ||
cb491fca | 1078 | static struct sysdev_attribute *mce_attrs[] = { |
d95d62c0 | 1079 | &attr_tolerant.attr, &attr_check_interval, &attr_trigger, |
a98f0dd3 AK |
1080 | NULL |
1081 | }; | |
1da177e4 | 1082 | |
cb491fca | 1083 | static cpumask_var_t mce_dev_initialized; |
bae19fe0 | 1084 | |
e9eee03e | 1085 | /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */ |
91c6d400 | 1086 | static __cpuinit int mce_create_device(unsigned int cpu) |
1da177e4 LT |
1087 | { |
1088 | int err; | |
73ca5358 | 1089 | int i; |
92cb7612 | 1090 | |
90367556 | 1091 | if (!mce_available(&boot_cpu_data)) |
91c6d400 AK |
1092 | return -EIO; |
1093 | ||
cb491fca IM |
1094 | memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject)); |
1095 | per_cpu(mce_dev, cpu).id = cpu; | |
1096 | per_cpu(mce_dev, cpu).cls = &mce_sysclass; | |
91c6d400 | 1097 | |
cb491fca | 1098 | err = sysdev_register(&per_cpu(mce_dev, cpu)); |
d435d862 AM |
1099 | if (err) |
1100 | return err; | |
1101 | ||
cb491fca IM |
1102 | for (i = 0; mce_attrs[i]; i++) { |
1103 | err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
d435d862 AM |
1104 | if (err) |
1105 | goto error; | |
1106 | } | |
0d7482e3 | 1107 | for (i = 0; i < banks; i++) { |
cb491fca | 1108 | err = sysdev_create_file(&per_cpu(mce_dev, cpu), |
0d7482e3 AK |
1109 | &bank_attrs[i]); |
1110 | if (err) | |
1111 | goto error2; | |
1112 | } | |
cb491fca | 1113 | cpumask_set_cpu(cpu, mce_dev_initialized); |
91c6d400 | 1114 | |
d435d862 | 1115 | return 0; |
0d7482e3 | 1116 | error2: |
cb491fca IM |
1117 | while (--i >= 0) |
1118 | sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[i]); | |
d435d862 | 1119 | error: |
cb491fca IM |
1120 | while (--i >= 0) |
1121 | sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
1122 | ||
1123 | sysdev_unregister(&per_cpu(mce_dev, cpu)); | |
d435d862 | 1124 | |
91c6d400 AK |
1125 | return err; |
1126 | } | |
1127 | ||
2d9cd6c2 | 1128 | static __cpuinit void mce_remove_device(unsigned int cpu) |
91c6d400 | 1129 | { |
73ca5358 SL |
1130 | int i; |
1131 | ||
cb491fca | 1132 | if (!cpumask_test_cpu(cpu, mce_dev_initialized)) |
bae19fe0 AH |
1133 | return; |
1134 | ||
cb491fca IM |
1135 | for (i = 0; mce_attrs[i]; i++) |
1136 | sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
1137 | ||
0d7482e3 | 1138 | for (i = 0; i < banks; i++) |
cb491fca IM |
1139 | sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[i]); |
1140 | ||
1141 | sysdev_unregister(&per_cpu(mce_dev, cpu)); | |
1142 | cpumask_clear_cpu(cpu, mce_dev_initialized); | |
91c6d400 | 1143 | } |
91c6d400 | 1144 | |
d6b75584 | 1145 | /* Make sure there are no machine checks on offlined CPUs. */ |
ec5b3d32 | 1146 | static void mce_disable_cpu(void *h) |
d6b75584 | 1147 | { |
88ccbedd | 1148 | unsigned long action = *(unsigned long *)h; |
cb491fca | 1149 | int i; |
d6b75584 AK |
1150 | |
1151 | if (!mce_available(¤t_cpu_data)) | |
1152 | return; | |
88ccbedd AK |
1153 | if (!(action & CPU_TASKS_FROZEN)) |
1154 | cmci_clear(); | |
06b7a7a5 AK |
1155 | for (i = 0; i < banks; i++) { |
1156 | if (!skip_bank_init(i)) | |
1157 | wrmsrl(MSR_IA32_MC0_CTL + i*4, 0); | |
1158 | } | |
d6b75584 AK |
1159 | } |
1160 | ||
ec5b3d32 | 1161 | static void mce_reenable_cpu(void *h) |
d6b75584 | 1162 | { |
88ccbedd | 1163 | unsigned long action = *(unsigned long *)h; |
e9eee03e | 1164 | int i; |
d6b75584 AK |
1165 | |
1166 | if (!mce_available(¤t_cpu_data)) | |
1167 | return; | |
e9eee03e | 1168 | |
88ccbedd AK |
1169 | if (!(action & CPU_TASKS_FROZEN)) |
1170 | cmci_reenable(); | |
06b7a7a5 AK |
1171 | for (i = 0; i < banks; i++) { |
1172 | if (!skip_bank_init(i)) | |
1173 | wrmsrl(MSR_IA32_MC0_CTL + i*4, bank[i]); | |
1174 | } | |
d6b75584 AK |
1175 | } |
1176 | ||
91c6d400 | 1177 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ |
e9eee03e IM |
1178 | static int __cpuinit |
1179 | mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) | |
91c6d400 AK |
1180 | { |
1181 | unsigned int cpu = (unsigned long)hcpu; | |
52d168e2 | 1182 | struct timer_list *t = &per_cpu(mce_timer, cpu); |
91c6d400 AK |
1183 | |
1184 | switch (action) { | |
bae19fe0 AH |
1185 | case CPU_ONLINE: |
1186 | case CPU_ONLINE_FROZEN: | |
1187 | mce_create_device(cpu); | |
8735728e RW |
1188 | if (threshold_cpu_callback) |
1189 | threshold_cpu_callback(action, cpu); | |
91c6d400 | 1190 | break; |
91c6d400 | 1191 | case CPU_DEAD: |
8bb78442 | 1192 | case CPU_DEAD_FROZEN: |
8735728e RW |
1193 | if (threshold_cpu_callback) |
1194 | threshold_cpu_callback(action, cpu); | |
91c6d400 AK |
1195 | mce_remove_device(cpu); |
1196 | break; | |
52d168e2 AK |
1197 | case CPU_DOWN_PREPARE: |
1198 | case CPU_DOWN_PREPARE_FROZEN: | |
1199 | del_timer_sync(t); | |
88ccbedd | 1200 | smp_call_function_single(cpu, mce_disable_cpu, &action, 1); |
52d168e2 AK |
1201 | break; |
1202 | case CPU_DOWN_FAILED: | |
1203 | case CPU_DOWN_FAILED_FROZEN: | |
6298c512 AK |
1204 | t->expires = round_jiffies(jiffies + |
1205 | __get_cpu_var(next_interval)); | |
52d168e2 | 1206 | add_timer_on(t, cpu); |
88ccbedd AK |
1207 | smp_call_function_single(cpu, mce_reenable_cpu, &action, 1); |
1208 | break; | |
1209 | case CPU_POST_DEAD: | |
1210 | /* intentionally ignoring frozen here */ | |
1211 | cmci_rediscover(cpu); | |
52d168e2 | 1212 | break; |
91c6d400 | 1213 | } |
bae19fe0 | 1214 | return NOTIFY_OK; |
91c6d400 AK |
1215 | } |
1216 | ||
1e35669d | 1217 | static struct notifier_block mce_cpu_notifier __cpuinitdata = { |
91c6d400 AK |
1218 | .notifier_call = mce_cpu_callback, |
1219 | }; | |
1220 | ||
0d7482e3 AK |
1221 | static __init int mce_init_banks(void) |
1222 | { | |
1223 | int i; | |
1224 | ||
1225 | bank_attrs = kzalloc(sizeof(struct sysdev_attribute) * banks, | |
1226 | GFP_KERNEL); | |
1227 | if (!bank_attrs) | |
1228 | return -ENOMEM; | |
1229 | ||
1230 | for (i = 0; i < banks; i++) { | |
1231 | struct sysdev_attribute *a = &bank_attrs[i]; | |
e9eee03e IM |
1232 | |
1233 | a->attr.name = kasprintf(GFP_KERNEL, "bank%d", i); | |
0d7482e3 AK |
1234 | if (!a->attr.name) |
1235 | goto nomem; | |
e9eee03e IM |
1236 | |
1237 | a->attr.mode = 0644; | |
1238 | a->show = show_bank; | |
1239 | a->store = set_bank; | |
0d7482e3 AK |
1240 | } |
1241 | return 0; | |
1242 | ||
1243 | nomem: | |
1244 | while (--i >= 0) | |
1245 | kfree(bank_attrs[i].attr.name); | |
1246 | kfree(bank_attrs); | |
1247 | bank_attrs = NULL; | |
e9eee03e | 1248 | |
0d7482e3 AK |
1249 | return -ENOMEM; |
1250 | } | |
1251 | ||
91c6d400 AK |
1252 | static __init int mce_init_device(void) |
1253 | { | |
1254 | int err; | |
1255 | int i = 0; | |
1256 | ||
1da177e4 LT |
1257 | if (!mce_available(&boot_cpu_data)) |
1258 | return -EIO; | |
0d7482e3 | 1259 | |
cb491fca | 1260 | alloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL); |
996867d0 | 1261 | |
0d7482e3 AK |
1262 | err = mce_init_banks(); |
1263 | if (err) | |
1264 | return err; | |
1265 | ||
1da177e4 | 1266 | err = sysdev_class_register(&mce_sysclass); |
d435d862 AM |
1267 | if (err) |
1268 | return err; | |
91c6d400 AK |
1269 | |
1270 | for_each_online_cpu(i) { | |
d435d862 AM |
1271 | err = mce_create_device(i); |
1272 | if (err) | |
1273 | return err; | |
91c6d400 AK |
1274 | } |
1275 | ||
be6b5a35 | 1276 | register_hotcpu_notifier(&mce_cpu_notifier); |
1da177e4 | 1277 | misc_register(&mce_log_device); |
e9eee03e | 1278 | |
1da177e4 | 1279 | return err; |
1da177e4 | 1280 | } |
91c6d400 | 1281 | |
1da177e4 | 1282 | device_initcall(mce_init_device); |
a988d334 | 1283 | |
711c2e48 | 1284 | #else /* CONFIG_X86_32: */ |
a988d334 | 1285 | |
a988d334 IM |
1286 | int nr_mce_banks; |
1287 | EXPORT_SYMBOL_GPL(nr_mce_banks); /* non-fatal.o */ | |
1288 | ||
a988d334 IM |
1289 | /* This has to be run for each processor */ |
1290 | void mcheck_init(struct cpuinfo_x86 *c) | |
1291 | { | |
1292 | if (mce_disabled == 1) | |
1293 | return; | |
1294 | ||
1295 | switch (c->x86_vendor) { | |
1296 | case X86_VENDOR_AMD: | |
1297 | amd_mcheck_init(c); | |
1298 | break; | |
1299 | ||
1300 | case X86_VENDOR_INTEL: | |
1301 | if (c->x86 == 5) | |
1302 | intel_p5_mcheck_init(c); | |
1303 | if (c->x86 == 6) | |
1304 | intel_p6_mcheck_init(c); | |
1305 | if (c->x86 == 15) | |
1306 | intel_p4_mcheck_init(c); | |
1307 | break; | |
1308 | ||
1309 | case X86_VENDOR_CENTAUR: | |
1310 | if (c->x86 == 5) | |
1311 | winchip_mcheck_init(c); | |
1312 | break; | |
1313 | ||
1314 | default: | |
1315 | break; | |
1316 | } | |
b659294b | 1317 | printk(KERN_INFO "mce: CPU supports %d MCE banks\n", nr_mce_banks); |
a988d334 IM |
1318 | } |
1319 | ||
a988d334 IM |
1320 | static int __init mcheck_enable(char *str) |
1321 | { | |
1322 | mce_disabled = -1; | |
1323 | return 1; | |
1324 | } | |
1325 | ||
a988d334 IM |
1326 | __setup("mce", mcheck_enable); |
1327 | ||
d7c3c9a6 AK |
1328 | #endif /* CONFIG_X86_OLD_MCE */ |
1329 | ||
1330 | /* | |
1331 | * Old style boot options parsing. Only for compatibility. | |
1332 | */ | |
1333 | static int __init mcheck_disable(char *str) | |
1334 | { | |
1335 | mce_disabled = 1; | |
1336 | return 1; | |
1337 | } | |
1338 | __setup("nomce", mcheck_disable); |