Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Machine check handler. | |
e9eee03e | 3 | * |
1da177e4 | 4 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. |
d88203d1 TG |
5 | * Rest from unknown author(s). |
6 | * 2004 Andi Kleen. Rewrote most of it. | |
b79109c3 AK |
7 | * Copyright 2008 Intel Corporation |
8 | * Author: Andi Kleen | |
1da177e4 | 9 | */ |
e9eee03e IM |
10 | #include <linux/thread_info.h> |
11 | #include <linux/capability.h> | |
12 | #include <linux/miscdevice.h> | |
ccc3c319 | 13 | #include <linux/interrupt.h> |
e9eee03e IM |
14 | #include <linux/ratelimit.h> |
15 | #include <linux/kallsyms.h> | |
16 | #include <linux/rcupdate.h> | |
e9eee03e | 17 | #include <linux/kobject.h> |
14a02530 | 18 | #include <linux/uaccess.h> |
e9eee03e IM |
19 | #include <linux/kdebug.h> |
20 | #include <linux/kernel.h> | |
21 | #include <linux/percpu.h> | |
1da177e4 | 22 | #include <linux/string.h> |
1da177e4 | 23 | #include <linux/sysdev.h> |
3c079792 | 24 | #include <linux/delay.h> |
8c566ef5 | 25 | #include <linux/ctype.h> |
e9eee03e | 26 | #include <linux/sched.h> |
0d7482e3 | 27 | #include <linux/sysfs.h> |
e9eee03e IM |
28 | #include <linux/types.h> |
29 | #include <linux/init.h> | |
30 | #include <linux/kmod.h> | |
31 | #include <linux/poll.h> | |
3c079792 | 32 | #include <linux/nmi.h> |
e9eee03e | 33 | #include <linux/cpu.h> |
14a02530 | 34 | #include <linux/smp.h> |
e9eee03e | 35 | #include <linux/fs.h> |
9b1beaf2 | 36 | #include <linux/mm.h> |
5be9ed25 | 37 | #include <linux/debugfs.h> |
e9eee03e | 38 | |
d88203d1 | 39 | #include <asm/processor.h> |
ccc3c319 AK |
40 | #include <asm/hw_irq.h> |
41 | #include <asm/apic.h> | |
e02e68d3 | 42 | #include <asm/idle.h> |
ccc3c319 | 43 | #include <asm/ipi.h> |
e9eee03e IM |
44 | #include <asm/mce.h> |
45 | #include <asm/msr.h> | |
1da177e4 | 46 | |
bd19a5e6 | 47 | #include "mce-internal.h" |
711c2e48 | 48 | |
4e5b3e69 | 49 | int mce_disabled __read_mostly; |
04b2b1a4 | 50 | |
e9eee03e | 51 | #define MISC_MCELOG_MINOR 227 |
0d7482e3 | 52 | |
3c079792 AK |
53 | #define SPINUNIT 100 /* 100ns */ |
54 | ||
553f265f AK |
55 | atomic_t mce_entry; |
56 | ||
01ca79f1 AK |
57 | DEFINE_PER_CPU(unsigned, mce_exception_count); |
58 | ||
bd78432c TH |
59 | /* |
60 | * Tolerant levels: | |
61 | * 0: always panic on uncorrected errors, log corrected errors | |
62 | * 1: panic or SIGBUS on uncorrected errors, log corrected errors | |
63 | * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors | |
64 | * 3: never panic or SIGBUS, log all errors (for testing only) | |
65 | */ | |
4e5b3e69 HS |
66 | static int tolerant __read_mostly = 1; |
67 | static int banks __read_mostly; | |
4e5b3e69 HS |
68 | static int rip_msr __read_mostly; |
69 | static int mce_bootlog __read_mostly = -1; | |
70 | static int monarch_timeout __read_mostly = -1; | |
71 | static int mce_panic_timeout __read_mostly; | |
72 | static int mce_dont_log_ce __read_mostly; | |
73 | int mce_cmci_disabled __read_mostly; | |
74 | int mce_ignore_ce __read_mostly; | |
75 | int mce_ser __read_mostly; | |
a98f0dd3 | 76 | |
cebe1820 AK |
77 | struct mce_bank *mce_banks __read_mostly; |
78 | ||
1020bcbc HS |
79 | /* User mode helper program triggered by machine check event */ |
80 | static unsigned long mce_need_notify; | |
81 | static char mce_helper[128]; | |
82 | static char *mce_helper_argv[2] = { mce_helper, NULL }; | |
1da177e4 | 83 | |
e02e68d3 | 84 | static DECLARE_WAIT_QUEUE_HEAD(mce_wait); |
3c079792 AK |
85 | static DEFINE_PER_CPU(struct mce, mces_seen); |
86 | static int cpu_missing; | |
87 | ||
f436f8bb IM |
88 | static void default_decode_mce(struct mce *m) |
89 | { | |
90 | pr_emerg("No human readable MCE decoding support on this CPU type.\n"); | |
91 | pr_emerg("Run the message through 'mcelog --ascii' to decode.\n"); | |
92 | } | |
93 | ||
94 | /* | |
95 | * CPU/chipset specific EDAC code can register a callback here to print | |
96 | * MCE errors in a human-readable form: | |
97 | */ | |
98 | void (*x86_mce_decode_callback)(struct mce *m) = default_decode_mce; | |
99 | EXPORT_SYMBOL(x86_mce_decode_callback); | |
e02e68d3 | 100 | |
ee031c31 AK |
101 | /* MCA banks polled by the period polling timer for corrected events */ |
102 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { | |
103 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL | |
104 | }; | |
105 | ||
9b1beaf2 AK |
106 | static DEFINE_PER_CPU(struct work_struct, mce_work); |
107 | ||
b5f2fa4e AK |
108 | /* Do initial initialization of a struct mce */ |
109 | void mce_setup(struct mce *m) | |
110 | { | |
111 | memset(m, 0, sizeof(struct mce)); | |
d620c67f | 112 | m->cpu = m->extcpu = smp_processor_id(); |
b5f2fa4e | 113 | rdtscll(m->tsc); |
8ee08347 AK |
114 | /* We hope get_seconds stays lockless */ |
115 | m->time = get_seconds(); | |
116 | m->cpuvendor = boot_cpu_data.x86_vendor; | |
117 | m->cpuid = cpuid_eax(1); | |
118 | #ifdef CONFIG_SMP | |
119 | m->socketid = cpu_data(m->extcpu).phys_proc_id; | |
120 | #endif | |
121 | m->apicid = cpu_data(m->extcpu).initial_apicid; | |
122 | rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap); | |
b5f2fa4e AK |
123 | } |
124 | ||
ea149b36 AK |
125 | DEFINE_PER_CPU(struct mce, injectm); |
126 | EXPORT_PER_CPU_SYMBOL_GPL(injectm); | |
127 | ||
1da177e4 LT |
128 | /* |
129 | * Lockless MCE logging infrastructure. | |
130 | * This avoids deadlocks on printk locks without having to break locks. Also | |
131 | * separate MCEs from kernel messages to avoid bogus bug reports. | |
132 | */ | |
133 | ||
231fd906 | 134 | static struct mce_log mcelog = { |
f6fb0ac0 AK |
135 | .signature = MCE_LOG_SIGNATURE, |
136 | .len = MCE_LOG_LEN, | |
137 | .recordlen = sizeof(struct mce), | |
d88203d1 | 138 | }; |
1da177e4 LT |
139 | |
140 | void mce_log(struct mce *mce) | |
141 | { | |
142 | unsigned next, entry; | |
e9eee03e | 143 | |
1da177e4 | 144 | mce->finished = 0; |
7644143c | 145 | wmb(); |
1da177e4 LT |
146 | for (;;) { |
147 | entry = rcu_dereference(mcelog.next); | |
673242c1 | 148 | for (;;) { |
e9eee03e IM |
149 | /* |
150 | * When the buffer fills up discard new entries. | |
151 | * Assume that the earlier errors are the more | |
152 | * interesting ones: | |
153 | */ | |
673242c1 | 154 | if (entry >= MCE_LOG_LEN) { |
14a02530 HS |
155 | set_bit(MCE_OVERFLOW, |
156 | (unsigned long *)&mcelog.flags); | |
673242c1 AK |
157 | return; |
158 | } | |
e9eee03e | 159 | /* Old left over entry. Skip: */ |
673242c1 AK |
160 | if (mcelog.entry[entry].finished) { |
161 | entry++; | |
162 | continue; | |
163 | } | |
7644143c | 164 | break; |
1da177e4 | 165 | } |
1da177e4 LT |
166 | smp_rmb(); |
167 | next = entry + 1; | |
168 | if (cmpxchg(&mcelog.next, entry, next) == entry) | |
169 | break; | |
170 | } | |
171 | memcpy(mcelog.entry + entry, mce, sizeof(struct mce)); | |
7644143c | 172 | wmb(); |
1da177e4 | 173 | mcelog.entry[entry].finished = 1; |
7644143c | 174 | wmb(); |
1da177e4 | 175 | |
a0189c70 | 176 | mce->finished = 1; |
1020bcbc | 177 | set_bit(0, &mce_need_notify); |
1da177e4 LT |
178 | } |
179 | ||
77e26cca | 180 | static void print_mce(struct mce *m) |
1da177e4 | 181 | { |
f436f8bb | 182 | pr_emerg("CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n", |
d620c67f | 183 | m->extcpu, m->mcgstatus, m->bank, m->status); |
f436f8bb | 184 | |
65ea5b03 | 185 | if (m->ip) { |
f436f8bb IM |
186 | pr_emerg("RIP%s %02x:<%016Lx> ", |
187 | !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", | |
188 | m->cs, m->ip); | |
189 | ||
1da177e4 | 190 | if (m->cs == __KERNEL_CS) |
65ea5b03 | 191 | print_symbol("{%s}", m->ip); |
f436f8bb | 192 | pr_cont("\n"); |
1da177e4 | 193 | } |
f436f8bb IM |
194 | |
195 | pr_emerg("TSC %llx ", m->tsc); | |
1da177e4 | 196 | if (m->addr) |
f436f8bb | 197 | pr_cont("ADDR %llx ", m->addr); |
1da177e4 | 198 | if (m->misc) |
f436f8bb | 199 | pr_cont("MISC %llx ", m->misc); |
549d042d | 200 | |
f436f8bb IM |
201 | pr_cont("\n"); |
202 | pr_emerg("PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n", | |
203 | m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid); | |
204 | ||
205 | /* | |
206 | * Print out human-readable details about the MCE error, | |
207 | * (if the CPU has an implementation for that): | |
208 | */ | |
209 | x86_mce_decode_callback(m); | |
86503560 AK |
210 | } |
211 | ||
77e26cca HS |
212 | static void print_mce_head(void) |
213 | { | |
f436f8bb | 214 | pr_emerg("\nHARDWARE ERROR\n"); |
77e26cca HS |
215 | } |
216 | ||
86503560 AK |
217 | static void print_mce_tail(void) |
218 | { | |
f436f8bb | 219 | pr_emerg("This is not a software problem!\n"); |
1da177e4 LT |
220 | } |
221 | ||
f94b61c2 AK |
222 | #define PANIC_TIMEOUT 5 /* 5 seconds */ |
223 | ||
224 | static atomic_t mce_paniced; | |
225 | ||
bf783f9f HY |
226 | static int fake_panic; |
227 | static atomic_t mce_fake_paniced; | |
228 | ||
f94b61c2 AK |
229 | /* Panic in progress. Enable interrupts and wait for final IPI */ |
230 | static void wait_for_panic(void) | |
231 | { | |
232 | long timeout = PANIC_TIMEOUT*USEC_PER_SEC; | |
f436f8bb | 233 | |
f94b61c2 AK |
234 | preempt_disable(); |
235 | local_irq_enable(); | |
236 | while (timeout-- > 0) | |
237 | udelay(1); | |
29b0f591 AK |
238 | if (panic_timeout == 0) |
239 | panic_timeout = mce_panic_timeout; | |
f94b61c2 AK |
240 | panic("Panicing machine check CPU died"); |
241 | } | |
242 | ||
bd19a5e6 | 243 | static void mce_panic(char *msg, struct mce *final, char *exp) |
d88203d1 | 244 | { |
1da177e4 | 245 | int i; |
e02e68d3 | 246 | |
bf783f9f HY |
247 | if (!fake_panic) { |
248 | /* | |
249 | * Make sure only one CPU runs in machine check panic | |
250 | */ | |
251 | if (atomic_inc_return(&mce_paniced) > 1) | |
252 | wait_for_panic(); | |
253 | barrier(); | |
f94b61c2 | 254 | |
bf783f9f HY |
255 | bust_spinlocks(1); |
256 | console_verbose(); | |
257 | } else { | |
258 | /* Don't log too much for fake panic */ | |
259 | if (atomic_inc_return(&mce_fake_paniced) > 1) | |
260 | return; | |
261 | } | |
77e26cca | 262 | print_mce_head(); |
a0189c70 | 263 | /* First print corrected ones that are still unlogged */ |
1da177e4 | 264 | for (i = 0; i < MCE_LOG_LEN; i++) { |
a0189c70 | 265 | struct mce *m = &mcelog.entry[i]; |
77e26cca HS |
266 | if (!(m->status & MCI_STATUS_VAL)) |
267 | continue; | |
268 | if (!(m->status & MCI_STATUS_UC)) | |
269 | print_mce(m); | |
a0189c70 AK |
270 | } |
271 | /* Now print uncorrected but with the final one last */ | |
272 | for (i = 0; i < MCE_LOG_LEN; i++) { | |
273 | struct mce *m = &mcelog.entry[i]; | |
274 | if (!(m->status & MCI_STATUS_VAL)) | |
1da177e4 | 275 | continue; |
77e26cca HS |
276 | if (!(m->status & MCI_STATUS_UC)) |
277 | continue; | |
a0189c70 | 278 | if (!final || memcmp(m, final, sizeof(struct mce))) |
77e26cca | 279 | print_mce(m); |
1da177e4 | 280 | } |
a0189c70 | 281 | if (final) |
77e26cca | 282 | print_mce(final); |
3c079792 AK |
283 | if (cpu_missing) |
284 | printk(KERN_EMERG "Some CPUs didn't answer in synchronization\n"); | |
86503560 | 285 | print_mce_tail(); |
bd19a5e6 AK |
286 | if (exp) |
287 | printk(KERN_EMERG "Machine check: %s\n", exp); | |
bf783f9f HY |
288 | if (!fake_panic) { |
289 | if (panic_timeout == 0) | |
290 | panic_timeout = mce_panic_timeout; | |
291 | panic(msg); | |
292 | } else | |
293 | printk(KERN_EMERG "Fake kernel panic: %s\n", msg); | |
d88203d1 | 294 | } |
1da177e4 | 295 | |
ea149b36 AK |
296 | /* Support code for software error injection */ |
297 | ||
298 | static int msr_to_offset(u32 msr) | |
299 | { | |
300 | unsigned bank = __get_cpu_var(injectm.bank); | |
f436f8bb | 301 | |
ea149b36 AK |
302 | if (msr == rip_msr) |
303 | return offsetof(struct mce, ip); | |
a2d32bcb | 304 | if (msr == MSR_IA32_MCx_STATUS(bank)) |
ea149b36 | 305 | return offsetof(struct mce, status); |
a2d32bcb | 306 | if (msr == MSR_IA32_MCx_ADDR(bank)) |
ea149b36 | 307 | return offsetof(struct mce, addr); |
a2d32bcb | 308 | if (msr == MSR_IA32_MCx_MISC(bank)) |
ea149b36 AK |
309 | return offsetof(struct mce, misc); |
310 | if (msr == MSR_IA32_MCG_STATUS) | |
311 | return offsetof(struct mce, mcgstatus); | |
312 | return -1; | |
313 | } | |
314 | ||
5f8c1a54 AK |
315 | /* MSR access wrappers used for error injection */ |
316 | static u64 mce_rdmsrl(u32 msr) | |
317 | { | |
318 | u64 v; | |
11868a2d | 319 | |
ea149b36 AK |
320 | if (__get_cpu_var(injectm).finished) { |
321 | int offset = msr_to_offset(msr); | |
11868a2d | 322 | |
ea149b36 AK |
323 | if (offset < 0) |
324 | return 0; | |
325 | return *(u64 *)((char *)&__get_cpu_var(injectm) + offset); | |
326 | } | |
11868a2d IM |
327 | |
328 | if (rdmsrl_safe(msr, &v)) { | |
329 | WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr); | |
330 | /* | |
331 | * Return zero in case the access faulted. This should | |
332 | * not happen normally but can happen if the CPU does | |
333 | * something weird, or if the code is buggy. | |
334 | */ | |
335 | v = 0; | |
336 | } | |
337 | ||
5f8c1a54 AK |
338 | return v; |
339 | } | |
340 | ||
341 | static void mce_wrmsrl(u32 msr, u64 v) | |
342 | { | |
ea149b36 AK |
343 | if (__get_cpu_var(injectm).finished) { |
344 | int offset = msr_to_offset(msr); | |
11868a2d | 345 | |
ea149b36 AK |
346 | if (offset >= 0) |
347 | *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v; | |
348 | return; | |
349 | } | |
5f8c1a54 AK |
350 | wrmsrl(msr, v); |
351 | } | |
352 | ||
9b1beaf2 AK |
353 | /* |
354 | * Simple lockless ring to communicate PFNs from the exception handler with the | |
355 | * process context work function. This is vastly simplified because there's | |
356 | * only a single reader and a single writer. | |
357 | */ | |
358 | #define MCE_RING_SIZE 16 /* we use one entry less */ | |
359 | ||
360 | struct mce_ring { | |
361 | unsigned short start; | |
362 | unsigned short end; | |
363 | unsigned long ring[MCE_RING_SIZE]; | |
364 | }; | |
365 | static DEFINE_PER_CPU(struct mce_ring, mce_ring); | |
366 | ||
367 | /* Runs with CPU affinity in workqueue */ | |
368 | static int mce_ring_empty(void) | |
369 | { | |
370 | struct mce_ring *r = &__get_cpu_var(mce_ring); | |
371 | ||
372 | return r->start == r->end; | |
373 | } | |
374 | ||
375 | static int mce_ring_get(unsigned long *pfn) | |
376 | { | |
377 | struct mce_ring *r; | |
378 | int ret = 0; | |
379 | ||
380 | *pfn = 0; | |
381 | get_cpu(); | |
382 | r = &__get_cpu_var(mce_ring); | |
383 | if (r->start == r->end) | |
384 | goto out; | |
385 | *pfn = r->ring[r->start]; | |
386 | r->start = (r->start + 1) % MCE_RING_SIZE; | |
387 | ret = 1; | |
388 | out: | |
389 | put_cpu(); | |
390 | return ret; | |
391 | } | |
392 | ||
393 | /* Always runs in MCE context with preempt off */ | |
394 | static int mce_ring_add(unsigned long pfn) | |
395 | { | |
396 | struct mce_ring *r = &__get_cpu_var(mce_ring); | |
397 | unsigned next; | |
398 | ||
399 | next = (r->end + 1) % MCE_RING_SIZE; | |
400 | if (next == r->start) | |
401 | return -1; | |
402 | r->ring[r->end] = pfn; | |
403 | wmb(); | |
404 | r->end = next; | |
405 | return 0; | |
406 | } | |
407 | ||
88ccbedd | 408 | int mce_available(struct cpuinfo_x86 *c) |
1da177e4 | 409 | { |
04b2b1a4 | 410 | if (mce_disabled) |
5b4408fd | 411 | return 0; |
3d1712c9 | 412 | return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); |
1da177e4 LT |
413 | } |
414 | ||
9b1beaf2 AK |
415 | static void mce_schedule_work(void) |
416 | { | |
417 | if (!mce_ring_empty()) { | |
418 | struct work_struct *work = &__get_cpu_var(mce_work); | |
419 | if (!work_pending(work)) | |
420 | schedule_work(work); | |
421 | } | |
422 | } | |
423 | ||
1b2797dc HY |
424 | /* |
425 | * Get the address of the instruction at the time of the machine check | |
426 | * error. | |
427 | */ | |
94ad8474 AK |
428 | static inline void mce_get_rip(struct mce *m, struct pt_regs *regs) |
429 | { | |
1b2797dc HY |
430 | |
431 | if (regs && (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV))) { | |
65ea5b03 | 432 | m->ip = regs->ip; |
94ad8474 AK |
433 | m->cs = regs->cs; |
434 | } else { | |
65ea5b03 | 435 | m->ip = 0; |
94ad8474 AK |
436 | m->cs = 0; |
437 | } | |
1b2797dc | 438 | if (rip_msr) |
5f8c1a54 | 439 | m->ip = mce_rdmsrl(rip_msr); |
94ad8474 AK |
440 | } |
441 | ||
11868a2d | 442 | #ifdef CONFIG_X86_LOCAL_APIC |
ccc3c319 AK |
443 | /* |
444 | * Called after interrupts have been reenabled again | |
445 | * when a MCE happened during an interrupts off region | |
446 | * in the kernel. | |
447 | */ | |
448 | asmlinkage void smp_mce_self_interrupt(struct pt_regs *regs) | |
449 | { | |
450 | ack_APIC_irq(); | |
451 | exit_idle(); | |
452 | irq_enter(); | |
9ff36ee9 | 453 | mce_notify_irq(); |
9b1beaf2 | 454 | mce_schedule_work(); |
ccc3c319 AK |
455 | irq_exit(); |
456 | } | |
457 | #endif | |
458 | ||
459 | static void mce_report_event(struct pt_regs *regs) | |
460 | { | |
461 | if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) { | |
9ff36ee9 | 462 | mce_notify_irq(); |
9b1beaf2 AK |
463 | /* |
464 | * Triggering the work queue here is just an insurance | |
465 | * policy in case the syscall exit notify handler | |
466 | * doesn't run soon enough or ends up running on the | |
467 | * wrong CPU (can happen when audit sleeps) | |
468 | */ | |
469 | mce_schedule_work(); | |
ccc3c319 AK |
470 | return; |
471 | } | |
472 | ||
473 | #ifdef CONFIG_X86_LOCAL_APIC | |
474 | /* | |
475 | * Without APIC do not notify. The event will be picked | |
476 | * up eventually. | |
477 | */ | |
478 | if (!cpu_has_apic) | |
479 | return; | |
480 | ||
481 | /* | |
482 | * When interrupts are disabled we cannot use | |
483 | * kernel services safely. Trigger an self interrupt | |
484 | * through the APIC to instead do the notification | |
485 | * after interrupts are reenabled again. | |
486 | */ | |
487 | apic->send_IPI_self(MCE_SELF_VECTOR); | |
488 | ||
489 | /* | |
490 | * Wait for idle afterwards again so that we don't leave the | |
491 | * APIC in a non idle state because the normal APIC writes | |
492 | * cannot exclude us. | |
493 | */ | |
494 | apic_wait_icr_idle(); | |
495 | #endif | |
496 | } | |
497 | ||
ca84f696 AK |
498 | DEFINE_PER_CPU(unsigned, mce_poll_count); |
499 | ||
d88203d1 | 500 | /* |
b79109c3 AK |
501 | * Poll for corrected events or events that happened before reset. |
502 | * Those are just logged through /dev/mcelog. | |
503 | * | |
504 | * This is executed in standard interrupt context. | |
ed7290d0 AK |
505 | * |
506 | * Note: spec recommends to panic for fatal unsignalled | |
507 | * errors here. However this would be quite problematic -- | |
508 | * we would need to reimplement the Monarch handling and | |
509 | * it would mess up the exclusion between exception handler | |
510 | * and poll hander -- * so we skip this for now. | |
511 | * These cases should not happen anyways, or only when the CPU | |
512 | * is already totally * confused. In this case it's likely it will | |
513 | * not fully execute the machine check handler either. | |
b79109c3 | 514 | */ |
ee031c31 | 515 | void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) |
b79109c3 AK |
516 | { |
517 | struct mce m; | |
518 | int i; | |
519 | ||
ca84f696 AK |
520 | __get_cpu_var(mce_poll_count)++; |
521 | ||
b79109c3 AK |
522 | mce_setup(&m); |
523 | ||
5f8c1a54 | 524 | m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); |
b79109c3 | 525 | for (i = 0; i < banks; i++) { |
cebe1820 | 526 | if (!mce_banks[i].ctl || !test_bit(i, *b)) |
b79109c3 AK |
527 | continue; |
528 | ||
529 | m.misc = 0; | |
530 | m.addr = 0; | |
531 | m.bank = i; | |
532 | m.tsc = 0; | |
533 | ||
534 | barrier(); | |
a2d32bcb | 535 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
b79109c3 AK |
536 | if (!(m.status & MCI_STATUS_VAL)) |
537 | continue; | |
538 | ||
539 | /* | |
ed7290d0 AK |
540 | * Uncorrected or signalled events are handled by the exception |
541 | * handler when it is enabled, so don't process those here. | |
b79109c3 AK |
542 | * |
543 | * TBD do the same check for MCI_STATUS_EN here? | |
544 | */ | |
ed7290d0 AK |
545 | if (!(flags & MCP_UC) && |
546 | (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC))) | |
b79109c3 AK |
547 | continue; |
548 | ||
549 | if (m.status & MCI_STATUS_MISCV) | |
a2d32bcb | 550 | m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i)); |
b79109c3 | 551 | if (m.status & MCI_STATUS_ADDRV) |
a2d32bcb | 552 | m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i)); |
b79109c3 AK |
553 | |
554 | if (!(flags & MCP_TIMESTAMP)) | |
555 | m.tsc = 0; | |
556 | /* | |
557 | * Don't get the IP here because it's unlikely to | |
558 | * have anything to do with the actual error location. | |
559 | */ | |
62fdac59 | 560 | if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) { |
5679af4c AK |
561 | mce_log(&m); |
562 | add_taint(TAINT_MACHINE_CHECK); | |
563 | } | |
b79109c3 AK |
564 | |
565 | /* | |
566 | * Clear state for this bank. | |
567 | */ | |
a2d32bcb | 568 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
b79109c3 AK |
569 | } |
570 | ||
571 | /* | |
572 | * Don't clear MCG_STATUS here because it's only defined for | |
573 | * exceptions. | |
574 | */ | |
88921be3 AK |
575 | |
576 | sync_core(); | |
b79109c3 | 577 | } |
ea149b36 | 578 | EXPORT_SYMBOL_GPL(machine_check_poll); |
b79109c3 | 579 | |
bd19a5e6 AK |
580 | /* |
581 | * Do a quick check if any of the events requires a panic. | |
582 | * This decides if we keep the events around or clear them. | |
583 | */ | |
584 | static int mce_no_way_out(struct mce *m, char **msg) | |
585 | { | |
586 | int i; | |
587 | ||
588 | for (i = 0; i < banks; i++) { | |
a2d32bcb | 589 | m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
bd19a5e6 AK |
590 | if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY) |
591 | return 1; | |
592 | } | |
593 | return 0; | |
594 | } | |
595 | ||
3c079792 AK |
596 | /* |
597 | * Variable to establish order between CPUs while scanning. | |
598 | * Each CPU spins initially until executing is equal its number. | |
599 | */ | |
600 | static atomic_t mce_executing; | |
601 | ||
602 | /* | |
603 | * Defines order of CPUs on entry. First CPU becomes Monarch. | |
604 | */ | |
605 | static atomic_t mce_callin; | |
606 | ||
607 | /* | |
608 | * Check if a timeout waiting for other CPUs happened. | |
609 | */ | |
610 | static int mce_timed_out(u64 *t) | |
611 | { | |
612 | /* | |
613 | * The others already did panic for some reason. | |
614 | * Bail out like in a timeout. | |
615 | * rmb() to tell the compiler that system_state | |
616 | * might have been modified by someone else. | |
617 | */ | |
618 | rmb(); | |
619 | if (atomic_read(&mce_paniced)) | |
620 | wait_for_panic(); | |
621 | if (!monarch_timeout) | |
622 | goto out; | |
623 | if ((s64)*t < SPINUNIT) { | |
624 | /* CHECKME: Make panic default for 1 too? */ | |
625 | if (tolerant < 1) | |
626 | mce_panic("Timeout synchronizing machine check over CPUs", | |
627 | NULL, NULL); | |
628 | cpu_missing = 1; | |
629 | return 1; | |
630 | } | |
631 | *t -= SPINUNIT; | |
632 | out: | |
633 | touch_nmi_watchdog(); | |
634 | return 0; | |
635 | } | |
636 | ||
637 | /* | |
638 | * The Monarch's reign. The Monarch is the CPU who entered | |
639 | * the machine check handler first. It waits for the others to | |
640 | * raise the exception too and then grades them. When any | |
641 | * error is fatal panic. Only then let the others continue. | |
642 | * | |
643 | * The other CPUs entering the MCE handler will be controlled by the | |
644 | * Monarch. They are called Subjects. | |
645 | * | |
646 | * This way we prevent any potential data corruption in a unrecoverable case | |
647 | * and also makes sure always all CPU's errors are examined. | |
648 | * | |
680b6cfd | 649 | * Also this detects the case of a machine check event coming from outer |
3c079792 AK |
650 | * space (not detected by any CPUs) In this case some external agent wants |
651 | * us to shut down, so panic too. | |
652 | * | |
653 | * The other CPUs might still decide to panic if the handler happens | |
654 | * in a unrecoverable place, but in this case the system is in a semi-stable | |
655 | * state and won't corrupt anything by itself. It's ok to let the others | |
656 | * continue for a bit first. | |
657 | * | |
658 | * All the spin loops have timeouts; when a timeout happens a CPU | |
659 | * typically elects itself to be Monarch. | |
660 | */ | |
661 | static void mce_reign(void) | |
662 | { | |
663 | int cpu; | |
664 | struct mce *m = NULL; | |
665 | int global_worst = 0; | |
666 | char *msg = NULL; | |
667 | char *nmsg = NULL; | |
668 | ||
669 | /* | |
670 | * This CPU is the Monarch and the other CPUs have run | |
671 | * through their handlers. | |
672 | * Grade the severity of the errors of all the CPUs. | |
673 | */ | |
674 | for_each_possible_cpu(cpu) { | |
675 | int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant, | |
676 | &nmsg); | |
677 | if (severity > global_worst) { | |
678 | msg = nmsg; | |
679 | global_worst = severity; | |
680 | m = &per_cpu(mces_seen, cpu); | |
681 | } | |
682 | } | |
683 | ||
684 | /* | |
685 | * Cannot recover? Panic here then. | |
686 | * This dumps all the mces in the log buffer and stops the | |
687 | * other CPUs. | |
688 | */ | |
689 | if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3) | |
ac960375 | 690 | mce_panic("Fatal Machine check", m, msg); |
3c079792 AK |
691 | |
692 | /* | |
693 | * For UC somewhere we let the CPU who detects it handle it. | |
694 | * Also must let continue the others, otherwise the handling | |
695 | * CPU could deadlock on a lock. | |
696 | */ | |
697 | ||
698 | /* | |
699 | * No machine check event found. Must be some external | |
700 | * source or one CPU is hung. Panic. | |
701 | */ | |
680b6cfd | 702 | if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3) |
3c079792 AK |
703 | mce_panic("Machine check from unknown source", NULL, NULL); |
704 | ||
705 | /* | |
706 | * Now clear all the mces_seen so that they don't reappear on | |
707 | * the next mce. | |
708 | */ | |
709 | for_each_possible_cpu(cpu) | |
710 | memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce)); | |
711 | } | |
712 | ||
713 | static atomic_t global_nwo; | |
714 | ||
715 | /* | |
716 | * Start of Monarch synchronization. This waits until all CPUs have | |
717 | * entered the exception handler and then determines if any of them | |
718 | * saw a fatal event that requires panic. Then it executes them | |
719 | * in the entry order. | |
720 | * TBD double check parallel CPU hotunplug | |
721 | */ | |
7fb06fc9 | 722 | static int mce_start(int *no_way_out) |
3c079792 | 723 | { |
7fb06fc9 | 724 | int order; |
3c079792 AK |
725 | int cpus = num_online_cpus(); |
726 | u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC; | |
727 | ||
7fb06fc9 HS |
728 | if (!timeout) |
729 | return -1; | |
3c079792 | 730 | |
7fb06fc9 | 731 | atomic_add(*no_way_out, &global_nwo); |
184e1fdf HY |
732 | /* |
733 | * global_nwo should be updated before mce_callin | |
734 | */ | |
735 | smp_wmb(); | |
a95436e4 | 736 | order = atomic_inc_return(&mce_callin); |
3c079792 AK |
737 | |
738 | /* | |
739 | * Wait for everyone. | |
740 | */ | |
741 | while (atomic_read(&mce_callin) != cpus) { | |
742 | if (mce_timed_out(&timeout)) { | |
743 | atomic_set(&global_nwo, 0); | |
7fb06fc9 | 744 | return -1; |
3c079792 AK |
745 | } |
746 | ndelay(SPINUNIT); | |
747 | } | |
748 | ||
184e1fdf HY |
749 | /* |
750 | * mce_callin should be read before global_nwo | |
751 | */ | |
752 | smp_rmb(); | |
3c079792 | 753 | |
7fb06fc9 HS |
754 | if (order == 1) { |
755 | /* | |
756 | * Monarch: Starts executing now, the others wait. | |
757 | */ | |
3c079792 | 758 | atomic_set(&mce_executing, 1); |
7fb06fc9 HS |
759 | } else { |
760 | /* | |
761 | * Subject: Now start the scanning loop one by one in | |
762 | * the original callin order. | |
763 | * This way when there are any shared banks it will be | |
764 | * only seen by one CPU before cleared, avoiding duplicates. | |
765 | */ | |
766 | while (atomic_read(&mce_executing) < order) { | |
767 | if (mce_timed_out(&timeout)) { | |
768 | atomic_set(&global_nwo, 0); | |
769 | return -1; | |
770 | } | |
771 | ndelay(SPINUNIT); | |
772 | } | |
3c079792 AK |
773 | } |
774 | ||
775 | /* | |
7fb06fc9 | 776 | * Cache the global no_way_out state. |
3c079792 | 777 | */ |
7fb06fc9 HS |
778 | *no_way_out = atomic_read(&global_nwo); |
779 | ||
780 | return order; | |
3c079792 AK |
781 | } |
782 | ||
783 | /* | |
784 | * Synchronize between CPUs after main scanning loop. | |
785 | * This invokes the bulk of the Monarch processing. | |
786 | */ | |
787 | static int mce_end(int order) | |
788 | { | |
789 | int ret = -1; | |
790 | u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC; | |
791 | ||
792 | if (!timeout) | |
793 | goto reset; | |
794 | if (order < 0) | |
795 | goto reset; | |
796 | ||
797 | /* | |
798 | * Allow others to run. | |
799 | */ | |
800 | atomic_inc(&mce_executing); | |
801 | ||
802 | if (order == 1) { | |
803 | /* CHECKME: Can this race with a parallel hotplug? */ | |
804 | int cpus = num_online_cpus(); | |
805 | ||
806 | /* | |
807 | * Monarch: Wait for everyone to go through their scanning | |
808 | * loops. | |
809 | */ | |
810 | while (atomic_read(&mce_executing) <= cpus) { | |
811 | if (mce_timed_out(&timeout)) | |
812 | goto reset; | |
813 | ndelay(SPINUNIT); | |
814 | } | |
815 | ||
816 | mce_reign(); | |
817 | barrier(); | |
818 | ret = 0; | |
819 | } else { | |
820 | /* | |
821 | * Subject: Wait for Monarch to finish. | |
822 | */ | |
823 | while (atomic_read(&mce_executing) != 0) { | |
824 | if (mce_timed_out(&timeout)) | |
825 | goto reset; | |
826 | ndelay(SPINUNIT); | |
827 | } | |
828 | ||
829 | /* | |
830 | * Don't reset anything. That's done by the Monarch. | |
831 | */ | |
832 | return 0; | |
833 | } | |
834 | ||
835 | /* | |
836 | * Reset all global state. | |
837 | */ | |
838 | reset: | |
839 | atomic_set(&global_nwo, 0); | |
840 | atomic_set(&mce_callin, 0); | |
841 | barrier(); | |
842 | ||
843 | /* | |
844 | * Let others run again. | |
845 | */ | |
846 | atomic_set(&mce_executing, 0); | |
847 | return ret; | |
848 | } | |
849 | ||
9b1beaf2 AK |
850 | /* |
851 | * Check if the address reported by the CPU is in a format we can parse. | |
852 | * It would be possible to add code for most other cases, but all would | |
853 | * be somewhat complicated (e.g. segment offset would require an instruction | |
854 | * parser). So only support physical addresses upto page granuality for now. | |
855 | */ | |
856 | static int mce_usable_address(struct mce *m) | |
857 | { | |
858 | if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV)) | |
859 | return 0; | |
860 | if ((m->misc & 0x3f) > PAGE_SHIFT) | |
861 | return 0; | |
862 | if (((m->misc >> 6) & 7) != MCM_ADDR_PHYS) | |
863 | return 0; | |
864 | return 1; | |
865 | } | |
866 | ||
3c079792 AK |
867 | static void mce_clear_state(unsigned long *toclear) |
868 | { | |
869 | int i; | |
870 | ||
871 | for (i = 0; i < banks; i++) { | |
872 | if (test_bit(i, toclear)) | |
a2d32bcb | 873 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
3c079792 AK |
874 | } |
875 | } | |
876 | ||
b79109c3 AK |
877 | /* |
878 | * The actual machine check handler. This only handles real | |
879 | * exceptions when something got corrupted coming in through int 18. | |
880 | * | |
881 | * This is executed in NMI context not subject to normal locking rules. This | |
882 | * implies that most kernel services cannot be safely used. Don't even | |
883 | * think about putting a printk in there! | |
3c079792 AK |
884 | * |
885 | * On Intel systems this is entered on all CPUs in parallel through | |
886 | * MCE broadcast. However some CPUs might be broken beyond repair, | |
887 | * so be always careful when synchronizing with others. | |
1da177e4 | 888 | */ |
e9eee03e | 889 | void do_machine_check(struct pt_regs *regs, long error_code) |
1da177e4 | 890 | { |
3c079792 | 891 | struct mce m, *final; |
1da177e4 | 892 | int i; |
3c079792 AK |
893 | int worst = 0; |
894 | int severity; | |
895 | /* | |
896 | * Establish sequential order between the CPUs entering the machine | |
897 | * check handler. | |
898 | */ | |
7fb06fc9 | 899 | int order; |
bd78432c TH |
900 | /* |
901 | * If no_way_out gets set, there is no safe way to recover from this | |
902 | * MCE. If tolerant is cranked up, we'll try anyway. | |
903 | */ | |
904 | int no_way_out = 0; | |
905 | /* | |
906 | * If kill_it gets set, there might be a way to recover from this | |
907 | * error. | |
908 | */ | |
909 | int kill_it = 0; | |
b79109c3 | 910 | DECLARE_BITMAP(toclear, MAX_NR_BANKS); |
bd19a5e6 | 911 | char *msg = "Unknown"; |
1da177e4 | 912 | |
553f265f AK |
913 | atomic_inc(&mce_entry); |
914 | ||
01ca79f1 AK |
915 | __get_cpu_var(mce_exception_count)++; |
916 | ||
b79109c3 | 917 | if (notify_die(DIE_NMI, "machine check", regs, error_code, |
22f5991c | 918 | 18, SIGKILL) == NOTIFY_STOP) |
32561696 | 919 | goto out; |
b79109c3 | 920 | if (!banks) |
32561696 | 921 | goto out; |
1da177e4 | 922 | |
b5f2fa4e AK |
923 | mce_setup(&m); |
924 | ||
5f8c1a54 | 925 | m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); |
3c079792 AK |
926 | final = &__get_cpu_var(mces_seen); |
927 | *final = m; | |
928 | ||
680b6cfd HS |
929 | no_way_out = mce_no_way_out(&m, &msg); |
930 | ||
1da177e4 LT |
931 | barrier(); |
932 | ||
ed7290d0 AK |
933 | /* |
934 | * When no restart IP must always kill or panic. | |
935 | */ | |
936 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) | |
937 | kill_it = 1; | |
938 | ||
3c079792 AK |
939 | /* |
940 | * Go through all the banks in exclusion of the other CPUs. | |
941 | * This way we don't report duplicated events on shared banks | |
942 | * because the first one to see it will clear it. | |
943 | */ | |
7fb06fc9 | 944 | order = mce_start(&no_way_out); |
1da177e4 | 945 | for (i = 0; i < banks; i++) { |
b79109c3 | 946 | __clear_bit(i, toclear); |
cebe1820 | 947 | if (!mce_banks[i].ctl) |
1da177e4 | 948 | continue; |
d88203d1 TG |
949 | |
950 | m.misc = 0; | |
1da177e4 LT |
951 | m.addr = 0; |
952 | m.bank = i; | |
1da177e4 | 953 | |
a2d32bcb | 954 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
1da177e4 LT |
955 | if ((m.status & MCI_STATUS_VAL) == 0) |
956 | continue; | |
957 | ||
b79109c3 | 958 | /* |
ed7290d0 AK |
959 | * Non uncorrected or non signaled errors are handled by |
960 | * machine_check_poll. Leave them alone, unless this panics. | |
b79109c3 | 961 | */ |
ed7290d0 AK |
962 | if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) && |
963 | !no_way_out) | |
b79109c3 AK |
964 | continue; |
965 | ||
966 | /* | |
967 | * Set taint even when machine check was not enabled. | |
968 | */ | |
969 | add_taint(TAINT_MACHINE_CHECK); | |
970 | ||
ed7290d0 | 971 | severity = mce_severity(&m, tolerant, NULL); |
b79109c3 | 972 | |
ed7290d0 AK |
973 | /* |
974 | * When machine check was for corrected handler don't touch, | |
975 | * unless we're panicing. | |
976 | */ | |
977 | if (severity == MCE_KEEP_SEVERITY && !no_way_out) | |
978 | continue; | |
979 | __set_bit(i, toclear); | |
980 | if (severity == MCE_NO_SEVERITY) { | |
b79109c3 AK |
981 | /* |
982 | * Machine check event was not enabled. Clear, but | |
983 | * ignore. | |
984 | */ | |
985 | continue; | |
1da177e4 LT |
986 | } |
987 | ||
ed7290d0 AK |
988 | /* |
989 | * Kill on action required. | |
990 | */ | |
991 | if (severity == MCE_AR_SEVERITY) | |
992 | kill_it = 1; | |
993 | ||
1da177e4 | 994 | if (m.status & MCI_STATUS_MISCV) |
a2d32bcb | 995 | m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i)); |
1da177e4 | 996 | if (m.status & MCI_STATUS_ADDRV) |
a2d32bcb | 997 | m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i)); |
1da177e4 | 998 | |
9b1beaf2 AK |
999 | /* |
1000 | * Action optional error. Queue address for later processing. | |
1001 | * When the ring overflows we just ignore the AO error. | |
1002 | * RED-PEN add some logging mechanism when | |
1003 | * usable_address or mce_add_ring fails. | |
1004 | * RED-PEN don't ignore overflow for tolerant == 0 | |
1005 | */ | |
1006 | if (severity == MCE_AO_SEVERITY && mce_usable_address(&m)) | |
1007 | mce_ring_add(m.addr >> PAGE_SHIFT); | |
1008 | ||
94ad8474 | 1009 | mce_get_rip(&m, regs); |
b79109c3 | 1010 | mce_log(&m); |
1da177e4 | 1011 | |
3c079792 AK |
1012 | if (severity > worst) { |
1013 | *final = m; | |
1014 | worst = severity; | |
1da177e4 | 1015 | } |
1da177e4 LT |
1016 | } |
1017 | ||
3c079792 AK |
1018 | if (!no_way_out) |
1019 | mce_clear_state(toclear); | |
1020 | ||
e9eee03e | 1021 | /* |
3c079792 AK |
1022 | * Do most of the synchronization with other CPUs. |
1023 | * When there's any problem use only local no_way_out state. | |
e9eee03e | 1024 | */ |
3c079792 AK |
1025 | if (mce_end(order) < 0) |
1026 | no_way_out = worst >= MCE_PANIC_SEVERITY; | |
bd78432c TH |
1027 | |
1028 | /* | |
1029 | * If we have decided that we just CAN'T continue, and the user | |
e9eee03e | 1030 | * has not set tolerant to an insane level, give up and die. |
3c079792 AK |
1031 | * |
1032 | * This is mainly used in the case when the system doesn't | |
1033 | * support MCE broadcasting or it has been disabled. | |
bd78432c TH |
1034 | */ |
1035 | if (no_way_out && tolerant < 3) | |
ac960375 | 1036 | mce_panic("Fatal machine check on current CPU", final, msg); |
bd78432c TH |
1037 | |
1038 | /* | |
1039 | * If the error seems to be unrecoverable, something should be | |
1040 | * done. Try to kill as little as possible. If we can kill just | |
1041 | * one task, do that. If the user has set the tolerance very | |
1042 | * high, don't try to do anything at all. | |
1043 | */ | |
bd78432c | 1044 | |
ed7290d0 AK |
1045 | if (kill_it && tolerant < 3) |
1046 | force_sig(SIGBUS, current); | |
1da177e4 | 1047 | |
e02e68d3 TH |
1048 | /* notify userspace ASAP */ |
1049 | set_thread_flag(TIF_MCE_NOTIFY); | |
1050 | ||
3c079792 AK |
1051 | if (worst > 0) |
1052 | mce_report_event(regs); | |
5f8c1a54 | 1053 | mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); |
32561696 | 1054 | out: |
553f265f | 1055 | atomic_dec(&mce_entry); |
88921be3 | 1056 | sync_core(); |
1da177e4 | 1057 | } |
ea149b36 | 1058 | EXPORT_SYMBOL_GPL(do_machine_check); |
1da177e4 | 1059 | |
9b1beaf2 AK |
1060 | /* dummy to break dependency. actual code is in mm/memory-failure.c */ |
1061 | void __attribute__((weak)) memory_failure(unsigned long pfn, int vector) | |
1062 | { | |
1063 | printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn); | |
1064 | } | |
1065 | ||
1066 | /* | |
1067 | * Called after mce notification in process context. This code | |
1068 | * is allowed to sleep. Call the high level VM handler to process | |
1069 | * any corrupted pages. | |
1070 | * Assume that the work queue code only calls this one at a time | |
1071 | * per CPU. | |
1072 | * Note we don't disable preemption, so this code might run on the wrong | |
1073 | * CPU. In this case the event is picked up by the scheduled work queue. | |
1074 | * This is merely a fast path to expedite processing in some common | |
1075 | * cases. | |
1076 | */ | |
1077 | void mce_notify_process(void) | |
1078 | { | |
1079 | unsigned long pfn; | |
1080 | mce_notify_irq(); | |
1081 | while (mce_ring_get(&pfn)) | |
1082 | memory_failure(pfn, MCE_VECTOR); | |
1083 | } | |
1084 | ||
1085 | static void mce_process_work(struct work_struct *dummy) | |
1086 | { | |
1087 | mce_notify_process(); | |
1088 | } | |
1089 | ||
15d5f839 DZ |
1090 | #ifdef CONFIG_X86_MCE_INTEL |
1091 | /*** | |
1092 | * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog | |
676b1855 | 1093 | * @cpu: The CPU on which the event occurred. |
15d5f839 DZ |
1094 | * @status: Event status information |
1095 | * | |
1096 | * This function should be called by the thermal interrupt after the | |
1097 | * event has been processed and the decision was made to log the event | |
1098 | * further. | |
1099 | * | |
1100 | * The status parameter will be saved to the 'status' field of 'struct mce' | |
1101 | * and historically has been the register value of the | |
1102 | * MSR_IA32_THERMAL_STATUS (Intel) msr. | |
1103 | */ | |
b5f2fa4e | 1104 | void mce_log_therm_throt_event(__u64 status) |
15d5f839 DZ |
1105 | { |
1106 | struct mce m; | |
1107 | ||
b5f2fa4e | 1108 | mce_setup(&m); |
15d5f839 DZ |
1109 | m.bank = MCE_THERMAL_BANK; |
1110 | m.status = status; | |
15d5f839 DZ |
1111 | mce_log(&m); |
1112 | } | |
1113 | #endif /* CONFIG_X86_MCE_INTEL */ | |
1114 | ||
1da177e4 | 1115 | /* |
8a336b0a TH |
1116 | * Periodic polling timer for "silent" machine check errors. If the |
1117 | * poller finds an MCE, poll 2x faster. When the poller finds no more | |
1118 | * errors, poll 2x slower (up to check_interval seconds). | |
1da177e4 | 1119 | */ |
1da177e4 | 1120 | static int check_interval = 5 * 60; /* 5 minutes */ |
e9eee03e | 1121 | |
245b2e70 | 1122 | static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */ |
52d168e2 | 1123 | static DEFINE_PER_CPU(struct timer_list, mce_timer); |
1da177e4 | 1124 | |
52d168e2 | 1125 | static void mcheck_timer(unsigned long data) |
1da177e4 | 1126 | { |
52d168e2 | 1127 | struct timer_list *t = &per_cpu(mce_timer, data); |
6298c512 | 1128 | int *n; |
52d168e2 AK |
1129 | |
1130 | WARN_ON(smp_processor_id() != data); | |
1131 | ||
e9eee03e | 1132 | if (mce_available(¤t_cpu_data)) { |
ee031c31 AK |
1133 | machine_check_poll(MCP_TIMESTAMP, |
1134 | &__get_cpu_var(mce_poll_banks)); | |
e9eee03e | 1135 | } |
1da177e4 LT |
1136 | |
1137 | /* | |
e02e68d3 TH |
1138 | * Alert userspace if needed. If we logged an MCE, reduce the |
1139 | * polling interval, otherwise increase the polling interval. | |
1da177e4 | 1140 | */ |
245b2e70 | 1141 | n = &__get_cpu_var(mce_next_interval); |
9ff36ee9 | 1142 | if (mce_notify_irq()) |
6298c512 | 1143 | *n = max(*n/2, HZ/100); |
14a02530 | 1144 | else |
6298c512 | 1145 | *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ)); |
e02e68d3 | 1146 | |
6298c512 | 1147 | t->expires = jiffies + *n; |
5be6066a | 1148 | add_timer_on(t, smp_processor_id()); |
e02e68d3 TH |
1149 | } |
1150 | ||
9bd98405 AK |
1151 | static void mce_do_trigger(struct work_struct *work) |
1152 | { | |
1020bcbc | 1153 | call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT); |
9bd98405 AK |
1154 | } |
1155 | ||
1156 | static DECLARE_WORK(mce_trigger_work, mce_do_trigger); | |
1157 | ||
e02e68d3 | 1158 | /* |
9bd98405 AK |
1159 | * Notify the user(s) about new machine check events. |
1160 | * Can be called from interrupt context, but not from machine check/NMI | |
1161 | * context. | |
e02e68d3 | 1162 | */ |
9ff36ee9 | 1163 | int mce_notify_irq(void) |
e02e68d3 | 1164 | { |
8457c84d AK |
1165 | /* Not more than two messages every minute */ |
1166 | static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); | |
1167 | ||
e02e68d3 | 1168 | clear_thread_flag(TIF_MCE_NOTIFY); |
e9eee03e | 1169 | |
1020bcbc | 1170 | if (test_and_clear_bit(0, &mce_need_notify)) { |
e02e68d3 | 1171 | wake_up_interruptible(&mce_wait); |
9bd98405 AK |
1172 | |
1173 | /* | |
1174 | * There is no risk of missing notifications because | |
1175 | * work_pending is always cleared before the function is | |
1176 | * executed. | |
1177 | */ | |
1020bcbc | 1178 | if (mce_helper[0] && !work_pending(&mce_trigger_work)) |
9bd98405 | 1179 | schedule_work(&mce_trigger_work); |
e02e68d3 | 1180 | |
8457c84d | 1181 | if (__ratelimit(&ratelimit)) |
8a336b0a | 1182 | printk(KERN_INFO "Machine check events logged\n"); |
e02e68d3 TH |
1183 | |
1184 | return 1; | |
1da177e4 | 1185 | } |
e02e68d3 TH |
1186 | return 0; |
1187 | } | |
9ff36ee9 | 1188 | EXPORT_SYMBOL_GPL(mce_notify_irq); |
8a336b0a | 1189 | |
cebe1820 AK |
1190 | static int mce_banks_init(void) |
1191 | { | |
1192 | int i; | |
1193 | ||
1194 | mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL); | |
1195 | if (!mce_banks) | |
1196 | return -ENOMEM; | |
1197 | for (i = 0; i < banks; i++) { | |
1198 | struct mce_bank *b = &mce_banks[i]; | |
11868a2d | 1199 | |
cebe1820 AK |
1200 | b->ctl = -1ULL; |
1201 | b->init = 1; | |
1202 | } | |
1203 | return 0; | |
1204 | } | |
1205 | ||
d88203d1 | 1206 | /* |
1da177e4 LT |
1207 | * Initialize Machine Checks for a CPU. |
1208 | */ | |
419d6162 | 1209 | static int __cpuinit mce_cap_init(void) |
1da177e4 | 1210 | { |
0d7482e3 | 1211 | unsigned b; |
e9eee03e | 1212 | u64 cap; |
1da177e4 LT |
1213 | |
1214 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
01c6680a TG |
1215 | |
1216 | b = cap & MCG_BANKCNT_MASK; | |
b659294b IM |
1217 | printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b); |
1218 | ||
0d7482e3 AK |
1219 | if (b > MAX_NR_BANKS) { |
1220 | printk(KERN_WARNING | |
1221 | "MCE: Using only %u machine check banks out of %u\n", | |
1222 | MAX_NR_BANKS, b); | |
1223 | b = MAX_NR_BANKS; | |
1224 | } | |
1225 | ||
1226 | /* Don't support asymmetric configurations today */ | |
1227 | WARN_ON(banks != 0 && b != banks); | |
1228 | banks = b; | |
cebe1820 AK |
1229 | if (!mce_banks) { |
1230 | int err = mce_banks_init(); | |
11868a2d | 1231 | |
cebe1820 AK |
1232 | if (err) |
1233 | return err; | |
1da177e4 | 1234 | } |
0d7482e3 | 1235 | |
94ad8474 | 1236 | /* Use accurate RIP reporting if available. */ |
01c6680a | 1237 | if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) |
94ad8474 | 1238 | rip_msr = MSR_IA32_MCG_EIP; |
1da177e4 | 1239 | |
ed7290d0 AK |
1240 | if (cap & MCG_SER_P) |
1241 | mce_ser = 1; | |
1242 | ||
0d7482e3 AK |
1243 | return 0; |
1244 | } | |
1245 | ||
8be91105 | 1246 | static void mce_init(void) |
0d7482e3 | 1247 | { |
e9eee03e | 1248 | mce_banks_t all_banks; |
0d7482e3 AK |
1249 | u64 cap; |
1250 | int i; | |
1251 | ||
b79109c3 AK |
1252 | /* |
1253 | * Log the machine checks left over from the previous reset. | |
1254 | */ | |
ee031c31 | 1255 | bitmap_fill(all_banks, MAX_NR_BANKS); |
5679af4c | 1256 | machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks); |
1da177e4 LT |
1257 | |
1258 | set_in_cr4(X86_CR4_MCE); | |
1259 | ||
0d7482e3 | 1260 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
1da177e4 LT |
1261 | if (cap & MCG_CTL_P) |
1262 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); | |
1263 | ||
1264 | for (i = 0; i < banks; i++) { | |
cebe1820 | 1265 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1266 | |
cebe1820 | 1267 | if (!b->init) |
06b7a7a5 | 1268 | continue; |
a2d32bcb AK |
1269 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
1270 | wrmsrl(MSR_IA32_MCx_STATUS(i), 0); | |
d88203d1 | 1271 | } |
1da177e4 LT |
1272 | } |
1273 | ||
1274 | /* Add per CPU specific workarounds here */ | |
df58bee2 | 1275 | static int __cpuinit mce_cpu_quirks(struct cpuinfo_x86 *c) |
d88203d1 | 1276 | { |
e412cd25 IM |
1277 | if (c->x86_vendor == X86_VENDOR_UNKNOWN) { |
1278 | pr_info("MCE: unknown CPU type - not enabling MCE support.\n"); | |
1279 | return -EOPNOTSUPP; | |
1280 | } | |
1281 | ||
1da177e4 | 1282 | /* This should be disabled by the BIOS, but isn't always */ |
911f6a7b | 1283 | if (c->x86_vendor == X86_VENDOR_AMD) { |
e9eee03e IM |
1284 | if (c->x86 == 15 && banks > 4) { |
1285 | /* | |
1286 | * disable GART TBL walk error reporting, which | |
1287 | * trips off incorrectly with the IOMMU & 3ware | |
1288 | * & Cerberus: | |
1289 | */ | |
cebe1820 | 1290 | clear_bit(10, (unsigned long *)&mce_banks[4].ctl); |
e9eee03e IM |
1291 | } |
1292 | if (c->x86 <= 17 && mce_bootlog < 0) { | |
1293 | /* | |
1294 | * Lots of broken BIOS around that don't clear them | |
1295 | * by default and leave crap in there. Don't log: | |
1296 | */ | |
911f6a7b | 1297 | mce_bootlog = 0; |
e9eee03e | 1298 | } |
2e6f694f AK |
1299 | /* |
1300 | * Various K7s with broken bank 0 around. Always disable | |
1301 | * by default. | |
1302 | */ | |
203abd67 | 1303 | if (c->x86 == 6 && banks > 0) |
cebe1820 | 1304 | mce_banks[0].ctl = 0; |
1da177e4 | 1305 | } |
e583538f | 1306 | |
06b7a7a5 AK |
1307 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
1308 | /* | |
1309 | * SDM documents that on family 6 bank 0 should not be written | |
1310 | * because it aliases to another special BIOS controlled | |
1311 | * register. | |
1312 | * But it's not aliased anymore on model 0x1a+ | |
1313 | * Don't ignore bank 0 completely because there could be a | |
1314 | * valid event later, merely don't write CTL0. | |
1315 | */ | |
1316 | ||
cebe1820 AK |
1317 | if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0) |
1318 | mce_banks[0].init = 0; | |
3c079792 AK |
1319 | |
1320 | /* | |
1321 | * All newer Intel systems support MCE broadcasting. Enable | |
1322 | * synchronization with a one second timeout. | |
1323 | */ | |
1324 | if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && | |
1325 | monarch_timeout < 0) | |
1326 | monarch_timeout = USEC_PER_SEC; | |
c7f6fa44 | 1327 | |
e412cd25 IM |
1328 | /* |
1329 | * There are also broken BIOSes on some Pentium M and | |
1330 | * earlier systems: | |
1331 | */ | |
1332 | if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0) | |
c7f6fa44 | 1333 | mce_bootlog = 0; |
06b7a7a5 | 1334 | } |
3c079792 AK |
1335 | if (monarch_timeout < 0) |
1336 | monarch_timeout = 0; | |
29b0f591 AK |
1337 | if (mce_bootlog != 0) |
1338 | mce_panic_timeout = 30; | |
e412cd25 IM |
1339 | |
1340 | return 0; | |
d88203d1 | 1341 | } |
1da177e4 | 1342 | |
4efc0670 AK |
1343 | static void __cpuinit mce_ancient_init(struct cpuinfo_x86 *c) |
1344 | { | |
1345 | if (c->x86 != 5) | |
1346 | return; | |
1347 | switch (c->x86_vendor) { | |
1348 | case X86_VENDOR_INTEL: | |
c6978369 | 1349 | intel_p5_mcheck_init(c); |
4efc0670 AK |
1350 | break; |
1351 | case X86_VENDOR_CENTAUR: | |
1352 | winchip_mcheck_init(c); | |
1353 | break; | |
1354 | } | |
1355 | } | |
1356 | ||
cc3ca220 | 1357 | static void mce_cpu_features(struct cpuinfo_x86 *c) |
1da177e4 LT |
1358 | { |
1359 | switch (c->x86_vendor) { | |
1360 | case X86_VENDOR_INTEL: | |
1361 | mce_intel_feature_init(c); | |
1362 | break; | |
89b831ef JS |
1363 | case X86_VENDOR_AMD: |
1364 | mce_amd_feature_init(c); | |
1365 | break; | |
1da177e4 LT |
1366 | default: |
1367 | break; | |
1368 | } | |
1369 | } | |
1370 | ||
52d168e2 AK |
1371 | static void mce_init_timer(void) |
1372 | { | |
1373 | struct timer_list *t = &__get_cpu_var(mce_timer); | |
245b2e70 | 1374 | int *n = &__get_cpu_var(mce_next_interval); |
52d168e2 | 1375 | |
62fdac59 HS |
1376 | if (mce_ignore_ce) |
1377 | return; | |
1378 | ||
6298c512 AK |
1379 | *n = check_interval * HZ; |
1380 | if (!*n) | |
52d168e2 AK |
1381 | return; |
1382 | setup_timer(t, mcheck_timer, smp_processor_id()); | |
6298c512 | 1383 | t->expires = round_jiffies(jiffies + *n); |
5be6066a | 1384 | add_timer_on(t, smp_processor_id()); |
52d168e2 AK |
1385 | } |
1386 | ||
9eda8cb3 AK |
1387 | /* Handle unconfigured int18 (should never happen) */ |
1388 | static void unexpected_machine_check(struct pt_regs *regs, long error_code) | |
1389 | { | |
1390 | printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n", | |
1391 | smp_processor_id()); | |
1392 | } | |
1393 | ||
1394 | /* Call the installed machine check handler for this CPU setup. */ | |
1395 | void (*machine_check_vector)(struct pt_regs *, long error_code) = | |
1396 | unexpected_machine_check; | |
1397 | ||
d88203d1 | 1398 | /* |
1da177e4 | 1399 | * Called for each booted CPU to set up machine checks. |
e9eee03e | 1400 | * Must be called with preempt off: |
1da177e4 | 1401 | */ |
e6982c67 | 1402 | void __cpuinit mcheck_init(struct cpuinfo_x86 *c) |
1da177e4 | 1403 | { |
4efc0670 AK |
1404 | if (mce_disabled) |
1405 | return; | |
1406 | ||
1407 | mce_ancient_init(c); | |
1408 | ||
5b4408fd | 1409 | if (!mce_available(c)) |
1da177e4 LT |
1410 | return; |
1411 | ||
e412cd25 | 1412 | if (mce_cap_init() < 0 || mce_cpu_quirks(c) < 0) { |
04b2b1a4 | 1413 | mce_disabled = 1; |
0d7482e3 AK |
1414 | return; |
1415 | } | |
0d7482e3 | 1416 | |
5d727926 AK |
1417 | machine_check_vector = do_machine_check; |
1418 | ||
8be91105 | 1419 | mce_init(); |
1da177e4 | 1420 | mce_cpu_features(c); |
52d168e2 | 1421 | mce_init_timer(); |
9b1beaf2 | 1422 | INIT_WORK(&__get_cpu_var(mce_work), mce_process_work); |
1da177e4 LT |
1423 | } |
1424 | ||
1425 | /* | |
1426 | * Character device to read and clear the MCE log. | |
1427 | */ | |
1428 | ||
f528e7ba | 1429 | static DEFINE_SPINLOCK(mce_state_lock); |
e9eee03e IM |
1430 | static int open_count; /* #times opened */ |
1431 | static int open_exclu; /* already open exclusive? */ | |
f528e7ba TH |
1432 | |
1433 | static int mce_open(struct inode *inode, struct file *file) | |
1434 | { | |
1435 | spin_lock(&mce_state_lock); | |
1436 | ||
1437 | if (open_exclu || (open_count && (file->f_flags & O_EXCL))) { | |
1438 | spin_unlock(&mce_state_lock); | |
e9eee03e | 1439 | |
f528e7ba TH |
1440 | return -EBUSY; |
1441 | } | |
1442 | ||
1443 | if (file->f_flags & O_EXCL) | |
1444 | open_exclu = 1; | |
1445 | open_count++; | |
1446 | ||
1447 | spin_unlock(&mce_state_lock); | |
1448 | ||
bd78432c | 1449 | return nonseekable_open(inode, file); |
f528e7ba TH |
1450 | } |
1451 | ||
1452 | static int mce_release(struct inode *inode, struct file *file) | |
1453 | { | |
1454 | spin_lock(&mce_state_lock); | |
1455 | ||
1456 | open_count--; | |
1457 | open_exclu = 0; | |
1458 | ||
1459 | spin_unlock(&mce_state_lock); | |
1460 | ||
1461 | return 0; | |
1462 | } | |
1463 | ||
d88203d1 TG |
1464 | static void collect_tscs(void *data) |
1465 | { | |
1da177e4 | 1466 | unsigned long *cpu_tsc = (unsigned long *)data; |
d88203d1 | 1467 | |
1da177e4 | 1468 | rdtscll(cpu_tsc[smp_processor_id()]); |
d88203d1 | 1469 | } |
1da177e4 | 1470 | |
e9eee03e IM |
1471 | static DEFINE_MUTEX(mce_read_mutex); |
1472 | ||
d88203d1 TG |
1473 | static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize, |
1474 | loff_t *off) | |
1da177e4 | 1475 | { |
e9eee03e | 1476 | char __user *buf = ubuf; |
f0de53bb | 1477 | unsigned long *cpu_tsc; |
ef41df43 | 1478 | unsigned prev, next; |
1da177e4 LT |
1479 | int i, err; |
1480 | ||
6bca67f9 | 1481 | cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL); |
f0de53bb AK |
1482 | if (!cpu_tsc) |
1483 | return -ENOMEM; | |
1484 | ||
8c8b8859 | 1485 | mutex_lock(&mce_read_mutex); |
1da177e4 LT |
1486 | next = rcu_dereference(mcelog.next); |
1487 | ||
1488 | /* Only supports full reads right now */ | |
d88203d1 | 1489 | if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) { |
8c8b8859 | 1490 | mutex_unlock(&mce_read_mutex); |
f0de53bb | 1491 | kfree(cpu_tsc); |
e9eee03e | 1492 | |
1da177e4 LT |
1493 | return -EINVAL; |
1494 | } | |
1495 | ||
1496 | err = 0; | |
ef41df43 HY |
1497 | prev = 0; |
1498 | do { | |
1499 | for (i = prev; i < next; i++) { | |
1500 | unsigned long start = jiffies; | |
1501 | ||
1502 | while (!mcelog.entry[i].finished) { | |
1503 | if (time_after_eq(jiffies, start + 2)) { | |
1504 | memset(mcelog.entry + i, 0, | |
1505 | sizeof(struct mce)); | |
1506 | goto timeout; | |
1507 | } | |
1508 | cpu_relax(); | |
673242c1 | 1509 | } |
ef41df43 HY |
1510 | smp_rmb(); |
1511 | err |= copy_to_user(buf, mcelog.entry + i, | |
1512 | sizeof(struct mce)); | |
1513 | buf += sizeof(struct mce); | |
1514 | timeout: | |
1515 | ; | |
673242c1 | 1516 | } |
1da177e4 | 1517 | |
ef41df43 HY |
1518 | memset(mcelog.entry + prev, 0, |
1519 | (next - prev) * sizeof(struct mce)); | |
1520 | prev = next; | |
1521 | next = cmpxchg(&mcelog.next, prev, 0); | |
1522 | } while (next != prev); | |
1da177e4 | 1523 | |
b2b18660 | 1524 | synchronize_sched(); |
1da177e4 | 1525 | |
d88203d1 TG |
1526 | /* |
1527 | * Collect entries that were still getting written before the | |
1528 | * synchronize. | |
1529 | */ | |
15c8b6c1 | 1530 | on_each_cpu(collect_tscs, cpu_tsc, 1); |
e9eee03e | 1531 | |
d88203d1 TG |
1532 | for (i = next; i < MCE_LOG_LEN; i++) { |
1533 | if (mcelog.entry[i].finished && | |
1534 | mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) { | |
1535 | err |= copy_to_user(buf, mcelog.entry+i, | |
1536 | sizeof(struct mce)); | |
1da177e4 LT |
1537 | smp_rmb(); |
1538 | buf += sizeof(struct mce); | |
1539 | memset(&mcelog.entry[i], 0, sizeof(struct mce)); | |
1540 | } | |
d88203d1 | 1541 | } |
8c8b8859 | 1542 | mutex_unlock(&mce_read_mutex); |
f0de53bb | 1543 | kfree(cpu_tsc); |
e9eee03e | 1544 | |
d88203d1 | 1545 | return err ? -EFAULT : buf - ubuf; |
1da177e4 LT |
1546 | } |
1547 | ||
e02e68d3 TH |
1548 | static unsigned int mce_poll(struct file *file, poll_table *wait) |
1549 | { | |
1550 | poll_wait(file, &mce_wait, wait); | |
1551 | if (rcu_dereference(mcelog.next)) | |
1552 | return POLLIN | POLLRDNORM; | |
1553 | return 0; | |
1554 | } | |
1555 | ||
c68461b6 | 1556 | static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg) |
1da177e4 LT |
1557 | { |
1558 | int __user *p = (int __user *)arg; | |
d88203d1 | 1559 | |
1da177e4 | 1560 | if (!capable(CAP_SYS_ADMIN)) |
d88203d1 | 1561 | return -EPERM; |
e9eee03e | 1562 | |
1da177e4 | 1563 | switch (cmd) { |
d88203d1 | 1564 | case MCE_GET_RECORD_LEN: |
1da177e4 LT |
1565 | return put_user(sizeof(struct mce), p); |
1566 | case MCE_GET_LOG_LEN: | |
d88203d1 | 1567 | return put_user(MCE_LOG_LEN, p); |
1da177e4 LT |
1568 | case MCE_GETCLEAR_FLAGS: { |
1569 | unsigned flags; | |
d88203d1 TG |
1570 | |
1571 | do { | |
1da177e4 | 1572 | flags = mcelog.flags; |
d88203d1 | 1573 | } while (cmpxchg(&mcelog.flags, flags, 0) != flags); |
e9eee03e | 1574 | |
d88203d1 | 1575 | return put_user(flags, p); |
1da177e4 LT |
1576 | } |
1577 | default: | |
d88203d1 TG |
1578 | return -ENOTTY; |
1579 | } | |
1da177e4 LT |
1580 | } |
1581 | ||
a1ff41bf | 1582 | /* Modified in mce-inject.c, so not static or const */ |
ea149b36 | 1583 | struct file_operations mce_chrdev_ops = { |
e9eee03e IM |
1584 | .open = mce_open, |
1585 | .release = mce_release, | |
1586 | .read = mce_read, | |
1587 | .poll = mce_poll, | |
1588 | .unlocked_ioctl = mce_ioctl, | |
1da177e4 | 1589 | }; |
ea149b36 | 1590 | EXPORT_SYMBOL_GPL(mce_chrdev_ops); |
1da177e4 LT |
1591 | |
1592 | static struct miscdevice mce_log_device = { | |
1593 | MISC_MCELOG_MINOR, | |
1594 | "mcelog", | |
1595 | &mce_chrdev_ops, | |
1596 | }; | |
1597 | ||
13503fa9 | 1598 | /* |
62fdac59 HS |
1599 | * mce=off Disables machine check |
1600 | * mce=no_cmci Disables CMCI | |
1601 | * mce=dont_log_ce Clears corrected events silently, no log created for CEs. | |
1602 | * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared. | |
3c079792 AK |
1603 | * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above) |
1604 | * monarchtimeout is how long to wait for other CPUs on machine | |
1605 | * check, or 0 to not wait | |
13503fa9 HS |
1606 | * mce=bootlog Log MCEs from before booting. Disabled by default on AMD. |
1607 | * mce=nobootlog Don't log MCEs from before booting. | |
1608 | */ | |
1da177e4 LT |
1609 | static int __init mcheck_enable(char *str) |
1610 | { | |
e3346fc4 | 1611 | if (*str == 0) { |
4efc0670 | 1612 | enable_p5_mce(); |
e3346fc4 BZ |
1613 | return 1; |
1614 | } | |
4efc0670 AK |
1615 | if (*str == '=') |
1616 | str++; | |
1da177e4 | 1617 | if (!strcmp(str, "off")) |
04b2b1a4 | 1618 | mce_disabled = 1; |
62fdac59 HS |
1619 | else if (!strcmp(str, "no_cmci")) |
1620 | mce_cmci_disabled = 1; | |
1621 | else if (!strcmp(str, "dont_log_ce")) | |
1622 | mce_dont_log_ce = 1; | |
1623 | else if (!strcmp(str, "ignore_ce")) | |
1624 | mce_ignore_ce = 1; | |
13503fa9 HS |
1625 | else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) |
1626 | mce_bootlog = (str[0] == 'b'); | |
3c079792 | 1627 | else if (isdigit(str[0])) { |
8c566ef5 | 1628 | get_option(&str, &tolerant); |
3c079792 AK |
1629 | if (*str == ',') { |
1630 | ++str; | |
1631 | get_option(&str, &monarch_timeout); | |
1632 | } | |
1633 | } else { | |
4efc0670 | 1634 | printk(KERN_INFO "mce argument %s ignored. Please use /sys\n", |
13503fa9 HS |
1635 | str); |
1636 | return 0; | |
1637 | } | |
9b41046c | 1638 | return 1; |
1da177e4 | 1639 | } |
4efc0670 | 1640 | __setup("mce", mcheck_enable); |
1da177e4 | 1641 | |
d88203d1 | 1642 | /* |
1da177e4 | 1643 | * Sysfs support |
d88203d1 | 1644 | */ |
1da177e4 | 1645 | |
973a2dd1 AK |
1646 | /* |
1647 | * Disable machine checks on suspend and shutdown. We can't really handle | |
1648 | * them later. | |
1649 | */ | |
1650 | static int mce_disable(void) | |
1651 | { | |
1652 | int i; | |
1653 | ||
06b7a7a5 | 1654 | for (i = 0; i < banks; i++) { |
cebe1820 | 1655 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1656 | |
cebe1820 | 1657 | if (b->init) |
a2d32bcb | 1658 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 1659 | } |
973a2dd1 AK |
1660 | return 0; |
1661 | } | |
1662 | ||
1663 | static int mce_suspend(struct sys_device *dev, pm_message_t state) | |
1664 | { | |
1665 | return mce_disable(); | |
1666 | } | |
1667 | ||
1668 | static int mce_shutdown(struct sys_device *dev) | |
1669 | { | |
1670 | return mce_disable(); | |
1671 | } | |
1672 | ||
e9eee03e IM |
1673 | /* |
1674 | * On resume clear all MCE state. Don't want to see leftovers from the BIOS. | |
1675 | * Only one CPU is active at this time, the others get re-added later using | |
1676 | * CPU hotplug: | |
1677 | */ | |
1da177e4 LT |
1678 | static int mce_resume(struct sys_device *dev) |
1679 | { | |
8be91105 | 1680 | mce_init(); |
6ec68bff | 1681 | mce_cpu_features(¤t_cpu_data); |
e9eee03e | 1682 | |
1da177e4 LT |
1683 | return 0; |
1684 | } | |
1685 | ||
52d168e2 AK |
1686 | static void mce_cpu_restart(void *data) |
1687 | { | |
1688 | del_timer_sync(&__get_cpu_var(mce_timer)); | |
33edbf02 HS |
1689 | if (!mce_available(¤t_cpu_data)) |
1690 | return; | |
1691 | mce_init(); | |
52d168e2 AK |
1692 | mce_init_timer(); |
1693 | } | |
1694 | ||
1da177e4 | 1695 | /* Reinit MCEs after user configuration changes */ |
d88203d1 TG |
1696 | static void mce_restart(void) |
1697 | { | |
52d168e2 | 1698 | on_each_cpu(mce_cpu_restart, NULL, 1); |
1da177e4 LT |
1699 | } |
1700 | ||
9af43b54 HS |
1701 | /* Toggle features for corrected errors */ |
1702 | static void mce_disable_ce(void *all) | |
1703 | { | |
1704 | if (!mce_available(¤t_cpu_data)) | |
1705 | return; | |
1706 | if (all) | |
1707 | del_timer_sync(&__get_cpu_var(mce_timer)); | |
1708 | cmci_clear(); | |
1709 | } | |
1710 | ||
1711 | static void mce_enable_ce(void *all) | |
1712 | { | |
1713 | if (!mce_available(¤t_cpu_data)) | |
1714 | return; | |
1715 | cmci_reenable(); | |
1716 | cmci_recheck(); | |
1717 | if (all) | |
1718 | mce_init_timer(); | |
1719 | } | |
1720 | ||
1da177e4 | 1721 | static struct sysdev_class mce_sysclass = { |
e9eee03e IM |
1722 | .suspend = mce_suspend, |
1723 | .shutdown = mce_shutdown, | |
1724 | .resume = mce_resume, | |
1725 | .name = "machinecheck", | |
1da177e4 LT |
1726 | }; |
1727 | ||
cb491fca | 1728 | DEFINE_PER_CPU(struct sys_device, mce_dev); |
e9eee03e IM |
1729 | |
1730 | __cpuinitdata | |
1731 | void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); | |
1da177e4 | 1732 | |
cebe1820 AK |
1733 | static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr) |
1734 | { | |
1735 | return container_of(attr, struct mce_bank, attr); | |
1736 | } | |
0d7482e3 AK |
1737 | |
1738 | static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
1739 | char *buf) | |
1740 | { | |
cebe1820 | 1741 | return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl); |
0d7482e3 AK |
1742 | } |
1743 | ||
1744 | static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
9319cec8 | 1745 | const char *buf, size_t size) |
0d7482e3 | 1746 | { |
9319cec8 | 1747 | u64 new; |
e9eee03e | 1748 | |
9319cec8 | 1749 | if (strict_strtoull(buf, 0, &new) < 0) |
0d7482e3 | 1750 | return -EINVAL; |
e9eee03e | 1751 | |
cebe1820 | 1752 | attr_to_bank(attr)->ctl = new; |
0d7482e3 | 1753 | mce_restart(); |
e9eee03e | 1754 | |
9319cec8 | 1755 | return size; |
0d7482e3 | 1756 | } |
a98f0dd3 | 1757 | |
e9eee03e IM |
1758 | static ssize_t |
1759 | show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf) | |
a98f0dd3 | 1760 | { |
1020bcbc | 1761 | strcpy(buf, mce_helper); |
a98f0dd3 | 1762 | strcat(buf, "\n"); |
1020bcbc | 1763 | return strlen(mce_helper) + 1; |
a98f0dd3 AK |
1764 | } |
1765 | ||
4a0b2b4d | 1766 | static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr, |
e9eee03e | 1767 | const char *buf, size_t siz) |
a98f0dd3 AK |
1768 | { |
1769 | char *p; | |
e9eee03e | 1770 | |
1020bcbc HS |
1771 | strncpy(mce_helper, buf, sizeof(mce_helper)); |
1772 | mce_helper[sizeof(mce_helper)-1] = 0; | |
1020bcbc | 1773 | p = strchr(mce_helper, '\n'); |
e9eee03e | 1774 | |
e9084ec9 | 1775 | if (p) |
e9eee03e IM |
1776 | *p = 0; |
1777 | ||
e9084ec9 | 1778 | return strlen(mce_helper) + !!p; |
a98f0dd3 AK |
1779 | } |
1780 | ||
9af43b54 HS |
1781 | static ssize_t set_ignore_ce(struct sys_device *s, |
1782 | struct sysdev_attribute *attr, | |
1783 | const char *buf, size_t size) | |
1784 | { | |
1785 | u64 new; | |
1786 | ||
1787 | if (strict_strtoull(buf, 0, &new) < 0) | |
1788 | return -EINVAL; | |
1789 | ||
1790 | if (mce_ignore_ce ^ !!new) { | |
1791 | if (new) { | |
1792 | /* disable ce features */ | |
1793 | on_each_cpu(mce_disable_ce, (void *)1, 1); | |
1794 | mce_ignore_ce = 1; | |
1795 | } else { | |
1796 | /* enable ce features */ | |
1797 | mce_ignore_ce = 0; | |
1798 | on_each_cpu(mce_enable_ce, (void *)1, 1); | |
1799 | } | |
1800 | } | |
1801 | return size; | |
1802 | } | |
1803 | ||
1804 | static ssize_t set_cmci_disabled(struct sys_device *s, | |
1805 | struct sysdev_attribute *attr, | |
1806 | const char *buf, size_t size) | |
1807 | { | |
1808 | u64 new; | |
1809 | ||
1810 | if (strict_strtoull(buf, 0, &new) < 0) | |
1811 | return -EINVAL; | |
1812 | ||
1813 | if (mce_cmci_disabled ^ !!new) { | |
1814 | if (new) { | |
1815 | /* disable cmci */ | |
1816 | on_each_cpu(mce_disable_ce, NULL, 1); | |
1817 | mce_cmci_disabled = 1; | |
1818 | } else { | |
1819 | /* enable cmci */ | |
1820 | mce_cmci_disabled = 0; | |
1821 | on_each_cpu(mce_enable_ce, NULL, 1); | |
1822 | } | |
1823 | } | |
1824 | return size; | |
1825 | } | |
1826 | ||
b56f642d AK |
1827 | static ssize_t store_int_with_restart(struct sys_device *s, |
1828 | struct sysdev_attribute *attr, | |
1829 | const char *buf, size_t size) | |
1830 | { | |
1831 | ssize_t ret = sysdev_store_int(s, attr, buf, size); | |
1832 | mce_restart(); | |
1833 | return ret; | |
1834 | } | |
1835 | ||
a98f0dd3 | 1836 | static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger); |
d95d62c0 | 1837 | static SYSDEV_INT_ATTR(tolerant, 0644, tolerant); |
3c079792 | 1838 | static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout); |
9af43b54 | 1839 | static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce); |
e9eee03e | 1840 | |
b56f642d AK |
1841 | static struct sysdev_ext_attribute attr_check_interval = { |
1842 | _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int, | |
1843 | store_int_with_restart), | |
1844 | &check_interval | |
1845 | }; | |
e9eee03e | 1846 | |
9af43b54 HS |
1847 | static struct sysdev_ext_attribute attr_ignore_ce = { |
1848 | _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce), | |
1849 | &mce_ignore_ce | |
1850 | }; | |
1851 | ||
1852 | static struct sysdev_ext_attribute attr_cmci_disabled = { | |
74b602c7 | 1853 | _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled), |
9af43b54 HS |
1854 | &mce_cmci_disabled |
1855 | }; | |
1856 | ||
cb491fca | 1857 | static struct sysdev_attribute *mce_attrs[] = { |
9af43b54 HS |
1858 | &attr_tolerant.attr, |
1859 | &attr_check_interval.attr, | |
1860 | &attr_trigger, | |
3c079792 | 1861 | &attr_monarch_timeout.attr, |
9af43b54 HS |
1862 | &attr_dont_log_ce.attr, |
1863 | &attr_ignore_ce.attr, | |
1864 | &attr_cmci_disabled.attr, | |
a98f0dd3 AK |
1865 | NULL |
1866 | }; | |
1da177e4 | 1867 | |
cb491fca | 1868 | static cpumask_var_t mce_dev_initialized; |
bae19fe0 | 1869 | |
e9eee03e | 1870 | /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */ |
91c6d400 | 1871 | static __cpuinit int mce_create_device(unsigned int cpu) |
1da177e4 LT |
1872 | { |
1873 | int err; | |
b1f49f95 | 1874 | int i, j; |
92cb7612 | 1875 | |
90367556 | 1876 | if (!mce_available(&boot_cpu_data)) |
91c6d400 AK |
1877 | return -EIO; |
1878 | ||
cb491fca IM |
1879 | memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject)); |
1880 | per_cpu(mce_dev, cpu).id = cpu; | |
1881 | per_cpu(mce_dev, cpu).cls = &mce_sysclass; | |
91c6d400 | 1882 | |
cb491fca | 1883 | err = sysdev_register(&per_cpu(mce_dev, cpu)); |
d435d862 AM |
1884 | if (err) |
1885 | return err; | |
1886 | ||
cb491fca IM |
1887 | for (i = 0; mce_attrs[i]; i++) { |
1888 | err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
d435d862 AM |
1889 | if (err) |
1890 | goto error; | |
1891 | } | |
b1f49f95 | 1892 | for (j = 0; j < banks; j++) { |
cb491fca | 1893 | err = sysdev_create_file(&per_cpu(mce_dev, cpu), |
cebe1820 | 1894 | &mce_banks[j].attr); |
0d7482e3 AK |
1895 | if (err) |
1896 | goto error2; | |
1897 | } | |
cb491fca | 1898 | cpumask_set_cpu(cpu, mce_dev_initialized); |
91c6d400 | 1899 | |
d435d862 | 1900 | return 0; |
0d7482e3 | 1901 | error2: |
b1f49f95 | 1902 | while (--j >= 0) |
cebe1820 | 1903 | sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[j].attr); |
d435d862 | 1904 | error: |
cb491fca | 1905 | while (--i >= 0) |
cebe1820 | 1906 | sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr); |
cb491fca IM |
1907 | |
1908 | sysdev_unregister(&per_cpu(mce_dev, cpu)); | |
d435d862 | 1909 | |
91c6d400 AK |
1910 | return err; |
1911 | } | |
1912 | ||
2d9cd6c2 | 1913 | static __cpuinit void mce_remove_device(unsigned int cpu) |
91c6d400 | 1914 | { |
73ca5358 SL |
1915 | int i; |
1916 | ||
cb491fca | 1917 | if (!cpumask_test_cpu(cpu, mce_dev_initialized)) |
bae19fe0 AH |
1918 | return; |
1919 | ||
cb491fca IM |
1920 | for (i = 0; mce_attrs[i]; i++) |
1921 | sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
1922 | ||
0d7482e3 | 1923 | for (i = 0; i < banks; i++) |
cebe1820 | 1924 | sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr); |
cb491fca IM |
1925 | |
1926 | sysdev_unregister(&per_cpu(mce_dev, cpu)); | |
1927 | cpumask_clear_cpu(cpu, mce_dev_initialized); | |
91c6d400 | 1928 | } |
91c6d400 | 1929 | |
d6b75584 | 1930 | /* Make sure there are no machine checks on offlined CPUs. */ |
ec5b3d32 | 1931 | static void mce_disable_cpu(void *h) |
d6b75584 | 1932 | { |
88ccbedd | 1933 | unsigned long action = *(unsigned long *)h; |
cb491fca | 1934 | int i; |
d6b75584 AK |
1935 | |
1936 | if (!mce_available(¤t_cpu_data)) | |
1937 | return; | |
88ccbedd AK |
1938 | if (!(action & CPU_TASKS_FROZEN)) |
1939 | cmci_clear(); | |
06b7a7a5 | 1940 | for (i = 0; i < banks; i++) { |
cebe1820 | 1941 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1942 | |
cebe1820 | 1943 | if (b->init) |
a2d32bcb | 1944 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 1945 | } |
d6b75584 AK |
1946 | } |
1947 | ||
ec5b3d32 | 1948 | static void mce_reenable_cpu(void *h) |
d6b75584 | 1949 | { |
88ccbedd | 1950 | unsigned long action = *(unsigned long *)h; |
e9eee03e | 1951 | int i; |
d6b75584 AK |
1952 | |
1953 | if (!mce_available(¤t_cpu_data)) | |
1954 | return; | |
e9eee03e | 1955 | |
88ccbedd AK |
1956 | if (!(action & CPU_TASKS_FROZEN)) |
1957 | cmci_reenable(); | |
06b7a7a5 | 1958 | for (i = 0; i < banks; i++) { |
cebe1820 | 1959 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1960 | |
cebe1820 | 1961 | if (b->init) |
a2d32bcb | 1962 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
06b7a7a5 | 1963 | } |
d6b75584 AK |
1964 | } |
1965 | ||
91c6d400 | 1966 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ |
e9eee03e IM |
1967 | static int __cpuinit |
1968 | mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) | |
91c6d400 AK |
1969 | { |
1970 | unsigned int cpu = (unsigned long)hcpu; | |
52d168e2 | 1971 | struct timer_list *t = &per_cpu(mce_timer, cpu); |
91c6d400 AK |
1972 | |
1973 | switch (action) { | |
bae19fe0 AH |
1974 | case CPU_ONLINE: |
1975 | case CPU_ONLINE_FROZEN: | |
1976 | mce_create_device(cpu); | |
8735728e RW |
1977 | if (threshold_cpu_callback) |
1978 | threshold_cpu_callback(action, cpu); | |
91c6d400 | 1979 | break; |
91c6d400 | 1980 | case CPU_DEAD: |
8bb78442 | 1981 | case CPU_DEAD_FROZEN: |
8735728e RW |
1982 | if (threshold_cpu_callback) |
1983 | threshold_cpu_callback(action, cpu); | |
91c6d400 AK |
1984 | mce_remove_device(cpu); |
1985 | break; | |
52d168e2 AK |
1986 | case CPU_DOWN_PREPARE: |
1987 | case CPU_DOWN_PREPARE_FROZEN: | |
1988 | del_timer_sync(t); | |
88ccbedd | 1989 | smp_call_function_single(cpu, mce_disable_cpu, &action, 1); |
52d168e2 AK |
1990 | break; |
1991 | case CPU_DOWN_FAILED: | |
1992 | case CPU_DOWN_FAILED_FROZEN: | |
6298c512 | 1993 | t->expires = round_jiffies(jiffies + |
245b2e70 | 1994 | __get_cpu_var(mce_next_interval)); |
52d168e2 | 1995 | add_timer_on(t, cpu); |
88ccbedd AK |
1996 | smp_call_function_single(cpu, mce_reenable_cpu, &action, 1); |
1997 | break; | |
1998 | case CPU_POST_DEAD: | |
1999 | /* intentionally ignoring frozen here */ | |
2000 | cmci_rediscover(cpu); | |
52d168e2 | 2001 | break; |
91c6d400 | 2002 | } |
bae19fe0 | 2003 | return NOTIFY_OK; |
91c6d400 AK |
2004 | } |
2005 | ||
1e35669d | 2006 | static struct notifier_block mce_cpu_notifier __cpuinitdata = { |
91c6d400 AK |
2007 | .notifier_call = mce_cpu_callback, |
2008 | }; | |
2009 | ||
cebe1820 | 2010 | static __init void mce_init_banks(void) |
0d7482e3 AK |
2011 | { |
2012 | int i; | |
2013 | ||
0d7482e3 | 2014 | for (i = 0; i < banks; i++) { |
cebe1820 AK |
2015 | struct mce_bank *b = &mce_banks[i]; |
2016 | struct sysdev_attribute *a = &b->attr; | |
e9eee03e | 2017 | |
cebe1820 AK |
2018 | a->attr.name = b->attrname; |
2019 | snprintf(b->attrname, ATTR_LEN, "bank%d", i); | |
e9eee03e IM |
2020 | |
2021 | a->attr.mode = 0644; | |
2022 | a->show = show_bank; | |
2023 | a->store = set_bank; | |
0d7482e3 | 2024 | } |
0d7482e3 AK |
2025 | } |
2026 | ||
91c6d400 AK |
2027 | static __init int mce_init_device(void) |
2028 | { | |
2029 | int err; | |
2030 | int i = 0; | |
2031 | ||
1da177e4 LT |
2032 | if (!mce_available(&boot_cpu_data)) |
2033 | return -EIO; | |
0d7482e3 | 2034 | |
e92fae06 | 2035 | zalloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL); |
996867d0 | 2036 | |
cebe1820 | 2037 | mce_init_banks(); |
0d7482e3 | 2038 | |
1da177e4 | 2039 | err = sysdev_class_register(&mce_sysclass); |
d435d862 AM |
2040 | if (err) |
2041 | return err; | |
91c6d400 AK |
2042 | |
2043 | for_each_online_cpu(i) { | |
d435d862 AM |
2044 | err = mce_create_device(i); |
2045 | if (err) | |
2046 | return err; | |
91c6d400 AK |
2047 | } |
2048 | ||
be6b5a35 | 2049 | register_hotcpu_notifier(&mce_cpu_notifier); |
1da177e4 | 2050 | misc_register(&mce_log_device); |
e9eee03e | 2051 | |
1da177e4 | 2052 | return err; |
1da177e4 | 2053 | } |
91c6d400 | 2054 | |
1da177e4 | 2055 | device_initcall(mce_init_device); |
a988d334 | 2056 | |
d7c3c9a6 AK |
2057 | /* |
2058 | * Old style boot options parsing. Only for compatibility. | |
2059 | */ | |
2060 | static int __init mcheck_disable(char *str) | |
2061 | { | |
2062 | mce_disabled = 1; | |
2063 | return 1; | |
2064 | } | |
2065 | __setup("nomce", mcheck_disable); | |
a988d334 | 2066 | |
5be9ed25 HY |
2067 | #ifdef CONFIG_DEBUG_FS |
2068 | struct dentry *mce_get_debugfs_dir(void) | |
a988d334 | 2069 | { |
5be9ed25 | 2070 | static struct dentry *dmce; |
a988d334 | 2071 | |
5be9ed25 HY |
2072 | if (!dmce) |
2073 | dmce = debugfs_create_dir("mce", NULL); | |
a988d334 | 2074 | |
5be9ed25 HY |
2075 | return dmce; |
2076 | } | |
a988d334 | 2077 | |
bf783f9f HY |
2078 | static void mce_reset(void) |
2079 | { | |
2080 | cpu_missing = 0; | |
2081 | atomic_set(&mce_fake_paniced, 0); | |
2082 | atomic_set(&mce_executing, 0); | |
2083 | atomic_set(&mce_callin, 0); | |
2084 | atomic_set(&global_nwo, 0); | |
2085 | } | |
a988d334 | 2086 | |
bf783f9f HY |
2087 | static int fake_panic_get(void *data, u64 *val) |
2088 | { | |
2089 | *val = fake_panic; | |
2090 | return 0; | |
a988d334 IM |
2091 | } |
2092 | ||
bf783f9f | 2093 | static int fake_panic_set(void *data, u64 val) |
a988d334 | 2094 | { |
bf783f9f HY |
2095 | mce_reset(); |
2096 | fake_panic = val; | |
2097 | return 0; | |
a988d334 | 2098 | } |
a988d334 | 2099 | |
bf783f9f HY |
2100 | DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get, |
2101 | fake_panic_set, "%llu\n"); | |
d7c3c9a6 | 2102 | |
bf783f9f | 2103 | static int __init mce_debugfs_init(void) |
d7c3c9a6 | 2104 | { |
bf783f9f HY |
2105 | struct dentry *dmce, *ffake_panic; |
2106 | ||
2107 | dmce = mce_get_debugfs_dir(); | |
2108 | if (!dmce) | |
2109 | return -ENOMEM; | |
2110 | ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL, | |
2111 | &fake_panic_fops); | |
2112 | if (!ffake_panic) | |
2113 | return -ENOMEM; | |
2114 | ||
2115 | return 0; | |
d7c3c9a6 | 2116 | } |
bf783f9f | 2117 | late_initcall(mce_debugfs_init); |
5be9ed25 | 2118 | #endif |