Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Machine check handler. | |
e9eee03e | 3 | * |
1da177e4 | 4 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. |
d88203d1 TG |
5 | * Rest from unknown author(s). |
6 | * 2004 Andi Kleen. Rewrote most of it. | |
b79109c3 AK |
7 | * Copyright 2008 Intel Corporation |
8 | * Author: Andi Kleen | |
1da177e4 | 9 | */ |
e9eee03e IM |
10 | #include <linux/thread_info.h> |
11 | #include <linux/capability.h> | |
12 | #include <linux/miscdevice.h> | |
ccc3c319 | 13 | #include <linux/interrupt.h> |
e9eee03e IM |
14 | #include <linux/ratelimit.h> |
15 | #include <linux/kallsyms.h> | |
16 | #include <linux/rcupdate.h> | |
e9eee03e | 17 | #include <linux/kobject.h> |
14a02530 | 18 | #include <linux/uaccess.h> |
e9eee03e IM |
19 | #include <linux/kdebug.h> |
20 | #include <linux/kernel.h> | |
21 | #include <linux/percpu.h> | |
1da177e4 | 22 | #include <linux/string.h> |
1da177e4 | 23 | #include <linux/sysdev.h> |
3c079792 | 24 | #include <linux/delay.h> |
8c566ef5 | 25 | #include <linux/ctype.h> |
e9eee03e | 26 | #include <linux/sched.h> |
0d7482e3 | 27 | #include <linux/sysfs.h> |
e9eee03e IM |
28 | #include <linux/types.h> |
29 | #include <linux/init.h> | |
30 | #include <linux/kmod.h> | |
31 | #include <linux/poll.h> | |
3c079792 | 32 | #include <linux/nmi.h> |
e9eee03e | 33 | #include <linux/cpu.h> |
14a02530 | 34 | #include <linux/smp.h> |
e9eee03e | 35 | #include <linux/fs.h> |
9b1beaf2 | 36 | #include <linux/mm.h> |
5be9ed25 | 37 | #include <linux/debugfs.h> |
e9eee03e | 38 | |
d88203d1 | 39 | #include <asm/processor.h> |
ccc3c319 AK |
40 | #include <asm/hw_irq.h> |
41 | #include <asm/apic.h> | |
e02e68d3 | 42 | #include <asm/idle.h> |
ccc3c319 | 43 | #include <asm/ipi.h> |
e9eee03e IM |
44 | #include <asm/mce.h> |
45 | #include <asm/msr.h> | |
1da177e4 | 46 | |
bd19a5e6 | 47 | #include "mce-internal.h" |
711c2e48 | 48 | |
2aa2b50d IM |
49 | static DEFINE_MUTEX(mce_read_mutex); |
50 | ||
f56e8a07 PM |
51 | #define rcu_dereference_check_mce(p) \ |
52 | rcu_dereference_check((p), \ | |
53 | rcu_read_lock_sched_held() || \ | |
54 | lockdep_is_held(&mce_read_mutex)) | |
55 | ||
8968f9d3 HS |
56 | #define CREATE_TRACE_POINTS |
57 | #include <trace/events/mce.h> | |
58 | ||
4e5b3e69 | 59 | int mce_disabled __read_mostly; |
04b2b1a4 | 60 | |
e9eee03e | 61 | #define MISC_MCELOG_MINOR 227 |
0d7482e3 | 62 | |
3c079792 AK |
63 | #define SPINUNIT 100 /* 100ns */ |
64 | ||
553f265f AK |
65 | atomic_t mce_entry; |
66 | ||
01ca79f1 AK |
67 | DEFINE_PER_CPU(unsigned, mce_exception_count); |
68 | ||
bd78432c TH |
69 | /* |
70 | * Tolerant levels: | |
71 | * 0: always panic on uncorrected errors, log corrected errors | |
72 | * 1: panic or SIGBUS on uncorrected errors, log corrected errors | |
73 | * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors | |
74 | * 3: never panic or SIGBUS, log all errors (for testing only) | |
75 | */ | |
4e5b3e69 HS |
76 | static int tolerant __read_mostly = 1; |
77 | static int banks __read_mostly; | |
4e5b3e69 HS |
78 | static int rip_msr __read_mostly; |
79 | static int mce_bootlog __read_mostly = -1; | |
80 | static int monarch_timeout __read_mostly = -1; | |
81 | static int mce_panic_timeout __read_mostly; | |
82 | static int mce_dont_log_ce __read_mostly; | |
83 | int mce_cmci_disabled __read_mostly; | |
84 | int mce_ignore_ce __read_mostly; | |
85 | int mce_ser __read_mostly; | |
a98f0dd3 | 86 | |
cebe1820 AK |
87 | struct mce_bank *mce_banks __read_mostly; |
88 | ||
1020bcbc HS |
89 | /* User mode helper program triggered by machine check event */ |
90 | static unsigned long mce_need_notify; | |
91 | static char mce_helper[128]; | |
92 | static char *mce_helper_argv[2] = { mce_helper, NULL }; | |
1da177e4 | 93 | |
e02e68d3 | 94 | static DECLARE_WAIT_QUEUE_HEAD(mce_wait); |
3c079792 AK |
95 | static DEFINE_PER_CPU(struct mce, mces_seen); |
96 | static int cpu_missing; | |
97 | ||
fb253195 BP |
98 | /* |
99 | * CPU/chipset specific EDAC code can register a notifier call here to print | |
100 | * MCE errors in a human-readable form. | |
101 | */ | |
102 | ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain); | |
103 | EXPORT_SYMBOL_GPL(x86_mce_decoder_chain); | |
104 | ||
105 | static int default_decode_mce(struct notifier_block *nb, unsigned long val, | |
106 | void *data) | |
f436f8bb IM |
107 | { |
108 | pr_emerg("No human readable MCE decoding support on this CPU type.\n"); | |
109 | pr_emerg("Run the message through 'mcelog --ascii' to decode.\n"); | |
fb253195 BP |
110 | |
111 | return NOTIFY_STOP; | |
f436f8bb IM |
112 | } |
113 | ||
fb253195 BP |
114 | static struct notifier_block mce_dec_nb = { |
115 | .notifier_call = default_decode_mce, | |
116 | .priority = -1, | |
117 | }; | |
e02e68d3 | 118 | |
ee031c31 AK |
119 | /* MCA banks polled by the period polling timer for corrected events */ |
120 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { | |
121 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL | |
122 | }; | |
123 | ||
9b1beaf2 AK |
124 | static DEFINE_PER_CPU(struct work_struct, mce_work); |
125 | ||
b5f2fa4e AK |
126 | /* Do initial initialization of a struct mce */ |
127 | void mce_setup(struct mce *m) | |
128 | { | |
129 | memset(m, 0, sizeof(struct mce)); | |
d620c67f | 130 | m->cpu = m->extcpu = smp_processor_id(); |
b5f2fa4e | 131 | rdtscll(m->tsc); |
8ee08347 AK |
132 | /* We hope get_seconds stays lockless */ |
133 | m->time = get_seconds(); | |
134 | m->cpuvendor = boot_cpu_data.x86_vendor; | |
135 | m->cpuid = cpuid_eax(1); | |
136 | #ifdef CONFIG_SMP | |
137 | m->socketid = cpu_data(m->extcpu).phys_proc_id; | |
138 | #endif | |
139 | m->apicid = cpu_data(m->extcpu).initial_apicid; | |
140 | rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap); | |
b5f2fa4e AK |
141 | } |
142 | ||
ea149b36 AK |
143 | DEFINE_PER_CPU(struct mce, injectm); |
144 | EXPORT_PER_CPU_SYMBOL_GPL(injectm); | |
145 | ||
1da177e4 LT |
146 | /* |
147 | * Lockless MCE logging infrastructure. | |
148 | * This avoids deadlocks on printk locks without having to break locks. Also | |
149 | * separate MCEs from kernel messages to avoid bogus bug reports. | |
150 | */ | |
151 | ||
231fd906 | 152 | static struct mce_log mcelog = { |
f6fb0ac0 AK |
153 | .signature = MCE_LOG_SIGNATURE, |
154 | .len = MCE_LOG_LEN, | |
155 | .recordlen = sizeof(struct mce), | |
d88203d1 | 156 | }; |
1da177e4 LT |
157 | |
158 | void mce_log(struct mce *mce) | |
159 | { | |
160 | unsigned next, entry; | |
e9eee03e | 161 | |
8968f9d3 HS |
162 | /* Emit the trace record: */ |
163 | trace_mce_record(mce); | |
164 | ||
1da177e4 | 165 | mce->finished = 0; |
7644143c | 166 | wmb(); |
1da177e4 | 167 | for (;;) { |
f56e8a07 | 168 | entry = rcu_dereference_check_mce(mcelog.next); |
673242c1 | 169 | for (;;) { |
e9eee03e IM |
170 | /* |
171 | * When the buffer fills up discard new entries. | |
172 | * Assume that the earlier errors are the more | |
173 | * interesting ones: | |
174 | */ | |
673242c1 | 175 | if (entry >= MCE_LOG_LEN) { |
14a02530 HS |
176 | set_bit(MCE_OVERFLOW, |
177 | (unsigned long *)&mcelog.flags); | |
673242c1 AK |
178 | return; |
179 | } | |
e9eee03e | 180 | /* Old left over entry. Skip: */ |
673242c1 AK |
181 | if (mcelog.entry[entry].finished) { |
182 | entry++; | |
183 | continue; | |
184 | } | |
7644143c | 185 | break; |
1da177e4 | 186 | } |
1da177e4 LT |
187 | smp_rmb(); |
188 | next = entry + 1; | |
189 | if (cmpxchg(&mcelog.next, entry, next) == entry) | |
190 | break; | |
191 | } | |
192 | memcpy(mcelog.entry + entry, mce, sizeof(struct mce)); | |
7644143c | 193 | wmb(); |
1da177e4 | 194 | mcelog.entry[entry].finished = 1; |
7644143c | 195 | wmb(); |
1da177e4 | 196 | |
a0189c70 | 197 | mce->finished = 1; |
1020bcbc | 198 | set_bit(0, &mce_need_notify); |
1da177e4 LT |
199 | } |
200 | ||
77e26cca | 201 | static void print_mce(struct mce *m) |
1da177e4 | 202 | { |
f436f8bb | 203 | pr_emerg("CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n", |
d620c67f | 204 | m->extcpu, m->mcgstatus, m->bank, m->status); |
f436f8bb | 205 | |
65ea5b03 | 206 | if (m->ip) { |
f436f8bb IM |
207 | pr_emerg("RIP%s %02x:<%016Lx> ", |
208 | !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", | |
209 | m->cs, m->ip); | |
210 | ||
1da177e4 | 211 | if (m->cs == __KERNEL_CS) |
65ea5b03 | 212 | print_symbol("{%s}", m->ip); |
f436f8bb | 213 | pr_cont("\n"); |
1da177e4 | 214 | } |
f436f8bb IM |
215 | |
216 | pr_emerg("TSC %llx ", m->tsc); | |
1da177e4 | 217 | if (m->addr) |
f436f8bb | 218 | pr_cont("ADDR %llx ", m->addr); |
1da177e4 | 219 | if (m->misc) |
f436f8bb | 220 | pr_cont("MISC %llx ", m->misc); |
549d042d | 221 | |
f436f8bb IM |
222 | pr_cont("\n"); |
223 | pr_emerg("PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n", | |
224 | m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid); | |
225 | ||
226 | /* | |
227 | * Print out human-readable details about the MCE error, | |
fb253195 | 228 | * (if the CPU has an implementation for that) |
f436f8bb | 229 | */ |
fb253195 | 230 | atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m); |
86503560 AK |
231 | } |
232 | ||
77e26cca HS |
233 | static void print_mce_head(void) |
234 | { | |
f436f8bb | 235 | pr_emerg("\nHARDWARE ERROR\n"); |
77e26cca HS |
236 | } |
237 | ||
86503560 AK |
238 | static void print_mce_tail(void) |
239 | { | |
f436f8bb | 240 | pr_emerg("This is not a software problem!\n"); |
1da177e4 LT |
241 | } |
242 | ||
f94b61c2 AK |
243 | #define PANIC_TIMEOUT 5 /* 5 seconds */ |
244 | ||
245 | static atomic_t mce_paniced; | |
246 | ||
bf783f9f HY |
247 | static int fake_panic; |
248 | static atomic_t mce_fake_paniced; | |
249 | ||
f94b61c2 AK |
250 | /* Panic in progress. Enable interrupts and wait for final IPI */ |
251 | static void wait_for_panic(void) | |
252 | { | |
253 | long timeout = PANIC_TIMEOUT*USEC_PER_SEC; | |
f436f8bb | 254 | |
f94b61c2 AK |
255 | preempt_disable(); |
256 | local_irq_enable(); | |
257 | while (timeout-- > 0) | |
258 | udelay(1); | |
29b0f591 AK |
259 | if (panic_timeout == 0) |
260 | panic_timeout = mce_panic_timeout; | |
f94b61c2 AK |
261 | panic("Panicing machine check CPU died"); |
262 | } | |
263 | ||
bd19a5e6 | 264 | static void mce_panic(char *msg, struct mce *final, char *exp) |
d88203d1 | 265 | { |
1da177e4 | 266 | int i; |
e02e68d3 | 267 | |
bf783f9f HY |
268 | if (!fake_panic) { |
269 | /* | |
270 | * Make sure only one CPU runs in machine check panic | |
271 | */ | |
272 | if (atomic_inc_return(&mce_paniced) > 1) | |
273 | wait_for_panic(); | |
274 | barrier(); | |
f94b61c2 | 275 | |
bf783f9f HY |
276 | bust_spinlocks(1); |
277 | console_verbose(); | |
278 | } else { | |
279 | /* Don't log too much for fake panic */ | |
280 | if (atomic_inc_return(&mce_fake_paniced) > 1) | |
281 | return; | |
282 | } | |
77e26cca | 283 | print_mce_head(); |
a0189c70 | 284 | /* First print corrected ones that are still unlogged */ |
1da177e4 | 285 | for (i = 0; i < MCE_LOG_LEN; i++) { |
a0189c70 | 286 | struct mce *m = &mcelog.entry[i]; |
77e26cca HS |
287 | if (!(m->status & MCI_STATUS_VAL)) |
288 | continue; | |
289 | if (!(m->status & MCI_STATUS_UC)) | |
290 | print_mce(m); | |
a0189c70 AK |
291 | } |
292 | /* Now print uncorrected but with the final one last */ | |
293 | for (i = 0; i < MCE_LOG_LEN; i++) { | |
294 | struct mce *m = &mcelog.entry[i]; | |
295 | if (!(m->status & MCI_STATUS_VAL)) | |
1da177e4 | 296 | continue; |
77e26cca HS |
297 | if (!(m->status & MCI_STATUS_UC)) |
298 | continue; | |
a0189c70 | 299 | if (!final || memcmp(m, final, sizeof(struct mce))) |
77e26cca | 300 | print_mce(m); |
1da177e4 | 301 | } |
a0189c70 | 302 | if (final) |
77e26cca | 303 | print_mce(final); |
3c079792 AK |
304 | if (cpu_missing) |
305 | printk(KERN_EMERG "Some CPUs didn't answer in synchronization\n"); | |
86503560 | 306 | print_mce_tail(); |
bd19a5e6 AK |
307 | if (exp) |
308 | printk(KERN_EMERG "Machine check: %s\n", exp); | |
bf783f9f HY |
309 | if (!fake_panic) { |
310 | if (panic_timeout == 0) | |
311 | panic_timeout = mce_panic_timeout; | |
312 | panic(msg); | |
313 | } else | |
314 | printk(KERN_EMERG "Fake kernel panic: %s\n", msg); | |
d88203d1 | 315 | } |
1da177e4 | 316 | |
ea149b36 AK |
317 | /* Support code for software error injection */ |
318 | ||
319 | static int msr_to_offset(u32 msr) | |
320 | { | |
321 | unsigned bank = __get_cpu_var(injectm.bank); | |
f436f8bb | 322 | |
ea149b36 AK |
323 | if (msr == rip_msr) |
324 | return offsetof(struct mce, ip); | |
a2d32bcb | 325 | if (msr == MSR_IA32_MCx_STATUS(bank)) |
ea149b36 | 326 | return offsetof(struct mce, status); |
a2d32bcb | 327 | if (msr == MSR_IA32_MCx_ADDR(bank)) |
ea149b36 | 328 | return offsetof(struct mce, addr); |
a2d32bcb | 329 | if (msr == MSR_IA32_MCx_MISC(bank)) |
ea149b36 AK |
330 | return offsetof(struct mce, misc); |
331 | if (msr == MSR_IA32_MCG_STATUS) | |
332 | return offsetof(struct mce, mcgstatus); | |
333 | return -1; | |
334 | } | |
335 | ||
5f8c1a54 AK |
336 | /* MSR access wrappers used for error injection */ |
337 | static u64 mce_rdmsrl(u32 msr) | |
338 | { | |
339 | u64 v; | |
11868a2d | 340 | |
ea149b36 AK |
341 | if (__get_cpu_var(injectm).finished) { |
342 | int offset = msr_to_offset(msr); | |
11868a2d | 343 | |
ea149b36 AK |
344 | if (offset < 0) |
345 | return 0; | |
346 | return *(u64 *)((char *)&__get_cpu_var(injectm) + offset); | |
347 | } | |
11868a2d IM |
348 | |
349 | if (rdmsrl_safe(msr, &v)) { | |
350 | WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr); | |
351 | /* | |
352 | * Return zero in case the access faulted. This should | |
353 | * not happen normally but can happen if the CPU does | |
354 | * something weird, or if the code is buggy. | |
355 | */ | |
356 | v = 0; | |
357 | } | |
358 | ||
5f8c1a54 AK |
359 | return v; |
360 | } | |
361 | ||
362 | static void mce_wrmsrl(u32 msr, u64 v) | |
363 | { | |
ea149b36 AK |
364 | if (__get_cpu_var(injectm).finished) { |
365 | int offset = msr_to_offset(msr); | |
11868a2d | 366 | |
ea149b36 AK |
367 | if (offset >= 0) |
368 | *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v; | |
369 | return; | |
370 | } | |
5f8c1a54 AK |
371 | wrmsrl(msr, v); |
372 | } | |
373 | ||
9b1beaf2 AK |
374 | /* |
375 | * Simple lockless ring to communicate PFNs from the exception handler with the | |
376 | * process context work function. This is vastly simplified because there's | |
377 | * only a single reader and a single writer. | |
378 | */ | |
379 | #define MCE_RING_SIZE 16 /* we use one entry less */ | |
380 | ||
381 | struct mce_ring { | |
382 | unsigned short start; | |
383 | unsigned short end; | |
384 | unsigned long ring[MCE_RING_SIZE]; | |
385 | }; | |
386 | static DEFINE_PER_CPU(struct mce_ring, mce_ring); | |
387 | ||
388 | /* Runs with CPU affinity in workqueue */ | |
389 | static int mce_ring_empty(void) | |
390 | { | |
391 | struct mce_ring *r = &__get_cpu_var(mce_ring); | |
392 | ||
393 | return r->start == r->end; | |
394 | } | |
395 | ||
396 | static int mce_ring_get(unsigned long *pfn) | |
397 | { | |
398 | struct mce_ring *r; | |
399 | int ret = 0; | |
400 | ||
401 | *pfn = 0; | |
402 | get_cpu(); | |
403 | r = &__get_cpu_var(mce_ring); | |
404 | if (r->start == r->end) | |
405 | goto out; | |
406 | *pfn = r->ring[r->start]; | |
407 | r->start = (r->start + 1) % MCE_RING_SIZE; | |
408 | ret = 1; | |
409 | out: | |
410 | put_cpu(); | |
411 | return ret; | |
412 | } | |
413 | ||
414 | /* Always runs in MCE context with preempt off */ | |
415 | static int mce_ring_add(unsigned long pfn) | |
416 | { | |
417 | struct mce_ring *r = &__get_cpu_var(mce_ring); | |
418 | unsigned next; | |
419 | ||
420 | next = (r->end + 1) % MCE_RING_SIZE; | |
421 | if (next == r->start) | |
422 | return -1; | |
423 | r->ring[r->end] = pfn; | |
424 | wmb(); | |
425 | r->end = next; | |
426 | return 0; | |
427 | } | |
428 | ||
88ccbedd | 429 | int mce_available(struct cpuinfo_x86 *c) |
1da177e4 | 430 | { |
04b2b1a4 | 431 | if (mce_disabled) |
5b4408fd | 432 | return 0; |
3d1712c9 | 433 | return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); |
1da177e4 LT |
434 | } |
435 | ||
9b1beaf2 AK |
436 | static void mce_schedule_work(void) |
437 | { | |
438 | if (!mce_ring_empty()) { | |
439 | struct work_struct *work = &__get_cpu_var(mce_work); | |
440 | if (!work_pending(work)) | |
441 | schedule_work(work); | |
442 | } | |
443 | } | |
444 | ||
1b2797dc HY |
445 | /* |
446 | * Get the address of the instruction at the time of the machine check | |
447 | * error. | |
448 | */ | |
94ad8474 AK |
449 | static inline void mce_get_rip(struct mce *m, struct pt_regs *regs) |
450 | { | |
1b2797dc HY |
451 | |
452 | if (regs && (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV))) { | |
65ea5b03 | 453 | m->ip = regs->ip; |
94ad8474 AK |
454 | m->cs = regs->cs; |
455 | } else { | |
65ea5b03 | 456 | m->ip = 0; |
94ad8474 AK |
457 | m->cs = 0; |
458 | } | |
1b2797dc | 459 | if (rip_msr) |
5f8c1a54 | 460 | m->ip = mce_rdmsrl(rip_msr); |
94ad8474 AK |
461 | } |
462 | ||
11868a2d | 463 | #ifdef CONFIG_X86_LOCAL_APIC |
ccc3c319 AK |
464 | /* |
465 | * Called after interrupts have been reenabled again | |
466 | * when a MCE happened during an interrupts off region | |
467 | * in the kernel. | |
468 | */ | |
469 | asmlinkage void smp_mce_self_interrupt(struct pt_regs *regs) | |
470 | { | |
471 | ack_APIC_irq(); | |
472 | exit_idle(); | |
473 | irq_enter(); | |
9ff36ee9 | 474 | mce_notify_irq(); |
9b1beaf2 | 475 | mce_schedule_work(); |
ccc3c319 AK |
476 | irq_exit(); |
477 | } | |
478 | #endif | |
479 | ||
480 | static void mce_report_event(struct pt_regs *regs) | |
481 | { | |
482 | if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) { | |
9ff36ee9 | 483 | mce_notify_irq(); |
9b1beaf2 AK |
484 | /* |
485 | * Triggering the work queue here is just an insurance | |
486 | * policy in case the syscall exit notify handler | |
487 | * doesn't run soon enough or ends up running on the | |
488 | * wrong CPU (can happen when audit sleeps) | |
489 | */ | |
490 | mce_schedule_work(); | |
ccc3c319 AK |
491 | return; |
492 | } | |
493 | ||
494 | #ifdef CONFIG_X86_LOCAL_APIC | |
495 | /* | |
496 | * Without APIC do not notify. The event will be picked | |
497 | * up eventually. | |
498 | */ | |
499 | if (!cpu_has_apic) | |
500 | return; | |
501 | ||
502 | /* | |
503 | * When interrupts are disabled we cannot use | |
504 | * kernel services safely. Trigger an self interrupt | |
505 | * through the APIC to instead do the notification | |
506 | * after interrupts are reenabled again. | |
507 | */ | |
508 | apic->send_IPI_self(MCE_SELF_VECTOR); | |
509 | ||
510 | /* | |
511 | * Wait for idle afterwards again so that we don't leave the | |
512 | * APIC in a non idle state because the normal APIC writes | |
513 | * cannot exclude us. | |
514 | */ | |
515 | apic_wait_icr_idle(); | |
516 | #endif | |
517 | } | |
518 | ||
ca84f696 AK |
519 | DEFINE_PER_CPU(unsigned, mce_poll_count); |
520 | ||
d88203d1 | 521 | /* |
b79109c3 AK |
522 | * Poll for corrected events or events that happened before reset. |
523 | * Those are just logged through /dev/mcelog. | |
524 | * | |
525 | * This is executed in standard interrupt context. | |
ed7290d0 AK |
526 | * |
527 | * Note: spec recommends to panic for fatal unsignalled | |
528 | * errors here. However this would be quite problematic -- | |
529 | * we would need to reimplement the Monarch handling and | |
530 | * it would mess up the exclusion between exception handler | |
531 | * and poll hander -- * so we skip this for now. | |
532 | * These cases should not happen anyways, or only when the CPU | |
533 | * is already totally * confused. In this case it's likely it will | |
534 | * not fully execute the machine check handler either. | |
b79109c3 | 535 | */ |
ee031c31 | 536 | void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) |
b79109c3 AK |
537 | { |
538 | struct mce m; | |
539 | int i; | |
540 | ||
ca84f696 AK |
541 | __get_cpu_var(mce_poll_count)++; |
542 | ||
b79109c3 AK |
543 | mce_setup(&m); |
544 | ||
5f8c1a54 | 545 | m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); |
b79109c3 | 546 | for (i = 0; i < banks; i++) { |
cebe1820 | 547 | if (!mce_banks[i].ctl || !test_bit(i, *b)) |
b79109c3 AK |
548 | continue; |
549 | ||
550 | m.misc = 0; | |
551 | m.addr = 0; | |
552 | m.bank = i; | |
553 | m.tsc = 0; | |
554 | ||
555 | barrier(); | |
a2d32bcb | 556 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
b79109c3 AK |
557 | if (!(m.status & MCI_STATUS_VAL)) |
558 | continue; | |
559 | ||
560 | /* | |
ed7290d0 AK |
561 | * Uncorrected or signalled events are handled by the exception |
562 | * handler when it is enabled, so don't process those here. | |
b79109c3 AK |
563 | * |
564 | * TBD do the same check for MCI_STATUS_EN here? | |
565 | */ | |
ed7290d0 AK |
566 | if (!(flags & MCP_UC) && |
567 | (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC))) | |
b79109c3 AK |
568 | continue; |
569 | ||
570 | if (m.status & MCI_STATUS_MISCV) | |
a2d32bcb | 571 | m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i)); |
b79109c3 | 572 | if (m.status & MCI_STATUS_ADDRV) |
a2d32bcb | 573 | m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i)); |
b79109c3 AK |
574 | |
575 | if (!(flags & MCP_TIMESTAMP)) | |
576 | m.tsc = 0; | |
577 | /* | |
578 | * Don't get the IP here because it's unlikely to | |
579 | * have anything to do with the actual error location. | |
580 | */ | |
62fdac59 | 581 | if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) { |
5679af4c AK |
582 | mce_log(&m); |
583 | add_taint(TAINT_MACHINE_CHECK); | |
584 | } | |
b79109c3 AK |
585 | |
586 | /* | |
587 | * Clear state for this bank. | |
588 | */ | |
a2d32bcb | 589 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
b79109c3 AK |
590 | } |
591 | ||
592 | /* | |
593 | * Don't clear MCG_STATUS here because it's only defined for | |
594 | * exceptions. | |
595 | */ | |
88921be3 AK |
596 | |
597 | sync_core(); | |
b79109c3 | 598 | } |
ea149b36 | 599 | EXPORT_SYMBOL_GPL(machine_check_poll); |
b79109c3 | 600 | |
bd19a5e6 AK |
601 | /* |
602 | * Do a quick check if any of the events requires a panic. | |
603 | * This decides if we keep the events around or clear them. | |
604 | */ | |
605 | static int mce_no_way_out(struct mce *m, char **msg) | |
606 | { | |
607 | int i; | |
608 | ||
609 | for (i = 0; i < banks; i++) { | |
a2d32bcb | 610 | m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
bd19a5e6 AK |
611 | if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY) |
612 | return 1; | |
613 | } | |
614 | return 0; | |
615 | } | |
616 | ||
3c079792 AK |
617 | /* |
618 | * Variable to establish order between CPUs while scanning. | |
619 | * Each CPU spins initially until executing is equal its number. | |
620 | */ | |
621 | static atomic_t mce_executing; | |
622 | ||
623 | /* | |
624 | * Defines order of CPUs on entry. First CPU becomes Monarch. | |
625 | */ | |
626 | static atomic_t mce_callin; | |
627 | ||
628 | /* | |
629 | * Check if a timeout waiting for other CPUs happened. | |
630 | */ | |
631 | static int mce_timed_out(u64 *t) | |
632 | { | |
633 | /* | |
634 | * The others already did panic for some reason. | |
635 | * Bail out like in a timeout. | |
636 | * rmb() to tell the compiler that system_state | |
637 | * might have been modified by someone else. | |
638 | */ | |
639 | rmb(); | |
640 | if (atomic_read(&mce_paniced)) | |
641 | wait_for_panic(); | |
642 | if (!monarch_timeout) | |
643 | goto out; | |
644 | if ((s64)*t < SPINUNIT) { | |
645 | /* CHECKME: Make panic default for 1 too? */ | |
646 | if (tolerant < 1) | |
647 | mce_panic("Timeout synchronizing machine check over CPUs", | |
648 | NULL, NULL); | |
649 | cpu_missing = 1; | |
650 | return 1; | |
651 | } | |
652 | *t -= SPINUNIT; | |
653 | out: | |
654 | touch_nmi_watchdog(); | |
655 | return 0; | |
656 | } | |
657 | ||
658 | /* | |
659 | * The Monarch's reign. The Monarch is the CPU who entered | |
660 | * the machine check handler first. It waits for the others to | |
661 | * raise the exception too and then grades them. When any | |
662 | * error is fatal panic. Only then let the others continue. | |
663 | * | |
664 | * The other CPUs entering the MCE handler will be controlled by the | |
665 | * Monarch. They are called Subjects. | |
666 | * | |
667 | * This way we prevent any potential data corruption in a unrecoverable case | |
668 | * and also makes sure always all CPU's errors are examined. | |
669 | * | |
680b6cfd | 670 | * Also this detects the case of a machine check event coming from outer |
3c079792 AK |
671 | * space (not detected by any CPUs) In this case some external agent wants |
672 | * us to shut down, so panic too. | |
673 | * | |
674 | * The other CPUs might still decide to panic if the handler happens | |
675 | * in a unrecoverable place, but in this case the system is in a semi-stable | |
676 | * state and won't corrupt anything by itself. It's ok to let the others | |
677 | * continue for a bit first. | |
678 | * | |
679 | * All the spin loops have timeouts; when a timeout happens a CPU | |
680 | * typically elects itself to be Monarch. | |
681 | */ | |
682 | static void mce_reign(void) | |
683 | { | |
684 | int cpu; | |
685 | struct mce *m = NULL; | |
686 | int global_worst = 0; | |
687 | char *msg = NULL; | |
688 | char *nmsg = NULL; | |
689 | ||
690 | /* | |
691 | * This CPU is the Monarch and the other CPUs have run | |
692 | * through their handlers. | |
693 | * Grade the severity of the errors of all the CPUs. | |
694 | */ | |
695 | for_each_possible_cpu(cpu) { | |
696 | int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant, | |
697 | &nmsg); | |
698 | if (severity > global_worst) { | |
699 | msg = nmsg; | |
700 | global_worst = severity; | |
701 | m = &per_cpu(mces_seen, cpu); | |
702 | } | |
703 | } | |
704 | ||
705 | /* | |
706 | * Cannot recover? Panic here then. | |
707 | * This dumps all the mces in the log buffer and stops the | |
708 | * other CPUs. | |
709 | */ | |
710 | if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3) | |
ac960375 | 711 | mce_panic("Fatal Machine check", m, msg); |
3c079792 AK |
712 | |
713 | /* | |
714 | * For UC somewhere we let the CPU who detects it handle it. | |
715 | * Also must let continue the others, otherwise the handling | |
716 | * CPU could deadlock on a lock. | |
717 | */ | |
718 | ||
719 | /* | |
720 | * No machine check event found. Must be some external | |
721 | * source or one CPU is hung. Panic. | |
722 | */ | |
680b6cfd | 723 | if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3) |
3c079792 AK |
724 | mce_panic("Machine check from unknown source", NULL, NULL); |
725 | ||
726 | /* | |
727 | * Now clear all the mces_seen so that they don't reappear on | |
728 | * the next mce. | |
729 | */ | |
730 | for_each_possible_cpu(cpu) | |
731 | memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce)); | |
732 | } | |
733 | ||
734 | static atomic_t global_nwo; | |
735 | ||
736 | /* | |
737 | * Start of Monarch synchronization. This waits until all CPUs have | |
738 | * entered the exception handler and then determines if any of them | |
739 | * saw a fatal event that requires panic. Then it executes them | |
740 | * in the entry order. | |
741 | * TBD double check parallel CPU hotunplug | |
742 | */ | |
7fb06fc9 | 743 | static int mce_start(int *no_way_out) |
3c079792 | 744 | { |
7fb06fc9 | 745 | int order; |
3c079792 AK |
746 | int cpus = num_online_cpus(); |
747 | u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC; | |
748 | ||
7fb06fc9 HS |
749 | if (!timeout) |
750 | return -1; | |
3c079792 | 751 | |
7fb06fc9 | 752 | atomic_add(*no_way_out, &global_nwo); |
184e1fdf HY |
753 | /* |
754 | * global_nwo should be updated before mce_callin | |
755 | */ | |
756 | smp_wmb(); | |
a95436e4 | 757 | order = atomic_inc_return(&mce_callin); |
3c079792 AK |
758 | |
759 | /* | |
760 | * Wait for everyone. | |
761 | */ | |
762 | while (atomic_read(&mce_callin) != cpus) { | |
763 | if (mce_timed_out(&timeout)) { | |
764 | atomic_set(&global_nwo, 0); | |
7fb06fc9 | 765 | return -1; |
3c079792 AK |
766 | } |
767 | ndelay(SPINUNIT); | |
768 | } | |
769 | ||
184e1fdf HY |
770 | /* |
771 | * mce_callin should be read before global_nwo | |
772 | */ | |
773 | smp_rmb(); | |
3c079792 | 774 | |
7fb06fc9 HS |
775 | if (order == 1) { |
776 | /* | |
777 | * Monarch: Starts executing now, the others wait. | |
778 | */ | |
3c079792 | 779 | atomic_set(&mce_executing, 1); |
7fb06fc9 HS |
780 | } else { |
781 | /* | |
782 | * Subject: Now start the scanning loop one by one in | |
783 | * the original callin order. | |
784 | * This way when there are any shared banks it will be | |
785 | * only seen by one CPU before cleared, avoiding duplicates. | |
786 | */ | |
787 | while (atomic_read(&mce_executing) < order) { | |
788 | if (mce_timed_out(&timeout)) { | |
789 | atomic_set(&global_nwo, 0); | |
790 | return -1; | |
791 | } | |
792 | ndelay(SPINUNIT); | |
793 | } | |
3c079792 AK |
794 | } |
795 | ||
796 | /* | |
7fb06fc9 | 797 | * Cache the global no_way_out state. |
3c079792 | 798 | */ |
7fb06fc9 HS |
799 | *no_way_out = atomic_read(&global_nwo); |
800 | ||
801 | return order; | |
3c079792 AK |
802 | } |
803 | ||
804 | /* | |
805 | * Synchronize between CPUs after main scanning loop. | |
806 | * This invokes the bulk of the Monarch processing. | |
807 | */ | |
808 | static int mce_end(int order) | |
809 | { | |
810 | int ret = -1; | |
811 | u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC; | |
812 | ||
813 | if (!timeout) | |
814 | goto reset; | |
815 | if (order < 0) | |
816 | goto reset; | |
817 | ||
818 | /* | |
819 | * Allow others to run. | |
820 | */ | |
821 | atomic_inc(&mce_executing); | |
822 | ||
823 | if (order == 1) { | |
824 | /* CHECKME: Can this race with a parallel hotplug? */ | |
825 | int cpus = num_online_cpus(); | |
826 | ||
827 | /* | |
828 | * Monarch: Wait for everyone to go through their scanning | |
829 | * loops. | |
830 | */ | |
831 | while (atomic_read(&mce_executing) <= cpus) { | |
832 | if (mce_timed_out(&timeout)) | |
833 | goto reset; | |
834 | ndelay(SPINUNIT); | |
835 | } | |
836 | ||
837 | mce_reign(); | |
838 | barrier(); | |
839 | ret = 0; | |
840 | } else { | |
841 | /* | |
842 | * Subject: Wait for Monarch to finish. | |
843 | */ | |
844 | while (atomic_read(&mce_executing) != 0) { | |
845 | if (mce_timed_out(&timeout)) | |
846 | goto reset; | |
847 | ndelay(SPINUNIT); | |
848 | } | |
849 | ||
850 | /* | |
851 | * Don't reset anything. That's done by the Monarch. | |
852 | */ | |
853 | return 0; | |
854 | } | |
855 | ||
856 | /* | |
857 | * Reset all global state. | |
858 | */ | |
859 | reset: | |
860 | atomic_set(&global_nwo, 0); | |
861 | atomic_set(&mce_callin, 0); | |
862 | barrier(); | |
863 | ||
864 | /* | |
865 | * Let others run again. | |
866 | */ | |
867 | atomic_set(&mce_executing, 0); | |
868 | return ret; | |
869 | } | |
870 | ||
9b1beaf2 AK |
871 | /* |
872 | * Check if the address reported by the CPU is in a format we can parse. | |
873 | * It would be possible to add code for most other cases, but all would | |
874 | * be somewhat complicated (e.g. segment offset would require an instruction | |
875 | * parser). So only support physical addresses upto page granuality for now. | |
876 | */ | |
877 | static int mce_usable_address(struct mce *m) | |
878 | { | |
879 | if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV)) | |
880 | return 0; | |
881 | if ((m->misc & 0x3f) > PAGE_SHIFT) | |
882 | return 0; | |
883 | if (((m->misc >> 6) & 7) != MCM_ADDR_PHYS) | |
884 | return 0; | |
885 | return 1; | |
886 | } | |
887 | ||
3c079792 AK |
888 | static void mce_clear_state(unsigned long *toclear) |
889 | { | |
890 | int i; | |
891 | ||
892 | for (i = 0; i < banks; i++) { | |
893 | if (test_bit(i, toclear)) | |
a2d32bcb | 894 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
3c079792 AK |
895 | } |
896 | } | |
897 | ||
b79109c3 AK |
898 | /* |
899 | * The actual machine check handler. This only handles real | |
900 | * exceptions when something got corrupted coming in through int 18. | |
901 | * | |
902 | * This is executed in NMI context not subject to normal locking rules. This | |
903 | * implies that most kernel services cannot be safely used. Don't even | |
904 | * think about putting a printk in there! | |
3c079792 AK |
905 | * |
906 | * On Intel systems this is entered on all CPUs in parallel through | |
907 | * MCE broadcast. However some CPUs might be broken beyond repair, | |
908 | * so be always careful when synchronizing with others. | |
1da177e4 | 909 | */ |
e9eee03e | 910 | void do_machine_check(struct pt_regs *regs, long error_code) |
1da177e4 | 911 | { |
3c079792 | 912 | struct mce m, *final; |
1da177e4 | 913 | int i; |
3c079792 AK |
914 | int worst = 0; |
915 | int severity; | |
916 | /* | |
917 | * Establish sequential order between the CPUs entering the machine | |
918 | * check handler. | |
919 | */ | |
7fb06fc9 | 920 | int order; |
bd78432c TH |
921 | /* |
922 | * If no_way_out gets set, there is no safe way to recover from this | |
923 | * MCE. If tolerant is cranked up, we'll try anyway. | |
924 | */ | |
925 | int no_way_out = 0; | |
926 | /* | |
927 | * If kill_it gets set, there might be a way to recover from this | |
928 | * error. | |
929 | */ | |
930 | int kill_it = 0; | |
b79109c3 | 931 | DECLARE_BITMAP(toclear, MAX_NR_BANKS); |
bd19a5e6 | 932 | char *msg = "Unknown"; |
1da177e4 | 933 | |
553f265f AK |
934 | atomic_inc(&mce_entry); |
935 | ||
01ca79f1 AK |
936 | __get_cpu_var(mce_exception_count)++; |
937 | ||
b79109c3 | 938 | if (notify_die(DIE_NMI, "machine check", regs, error_code, |
22f5991c | 939 | 18, SIGKILL) == NOTIFY_STOP) |
32561696 | 940 | goto out; |
b79109c3 | 941 | if (!banks) |
32561696 | 942 | goto out; |
1da177e4 | 943 | |
b5f2fa4e AK |
944 | mce_setup(&m); |
945 | ||
5f8c1a54 | 946 | m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); |
3c079792 AK |
947 | final = &__get_cpu_var(mces_seen); |
948 | *final = m; | |
949 | ||
680b6cfd HS |
950 | no_way_out = mce_no_way_out(&m, &msg); |
951 | ||
1da177e4 LT |
952 | barrier(); |
953 | ||
ed7290d0 AK |
954 | /* |
955 | * When no restart IP must always kill or panic. | |
956 | */ | |
957 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) | |
958 | kill_it = 1; | |
959 | ||
3c079792 AK |
960 | /* |
961 | * Go through all the banks in exclusion of the other CPUs. | |
962 | * This way we don't report duplicated events on shared banks | |
963 | * because the first one to see it will clear it. | |
964 | */ | |
7fb06fc9 | 965 | order = mce_start(&no_way_out); |
1da177e4 | 966 | for (i = 0; i < banks; i++) { |
b79109c3 | 967 | __clear_bit(i, toclear); |
cebe1820 | 968 | if (!mce_banks[i].ctl) |
1da177e4 | 969 | continue; |
d88203d1 TG |
970 | |
971 | m.misc = 0; | |
1da177e4 LT |
972 | m.addr = 0; |
973 | m.bank = i; | |
1da177e4 | 974 | |
a2d32bcb | 975 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
1da177e4 LT |
976 | if ((m.status & MCI_STATUS_VAL) == 0) |
977 | continue; | |
978 | ||
b79109c3 | 979 | /* |
ed7290d0 AK |
980 | * Non uncorrected or non signaled errors are handled by |
981 | * machine_check_poll. Leave them alone, unless this panics. | |
b79109c3 | 982 | */ |
ed7290d0 AK |
983 | if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) && |
984 | !no_way_out) | |
b79109c3 AK |
985 | continue; |
986 | ||
987 | /* | |
988 | * Set taint even when machine check was not enabled. | |
989 | */ | |
990 | add_taint(TAINT_MACHINE_CHECK); | |
991 | ||
ed7290d0 | 992 | severity = mce_severity(&m, tolerant, NULL); |
b79109c3 | 993 | |
ed7290d0 AK |
994 | /* |
995 | * When machine check was for corrected handler don't touch, | |
996 | * unless we're panicing. | |
997 | */ | |
998 | if (severity == MCE_KEEP_SEVERITY && !no_way_out) | |
999 | continue; | |
1000 | __set_bit(i, toclear); | |
1001 | if (severity == MCE_NO_SEVERITY) { | |
b79109c3 AK |
1002 | /* |
1003 | * Machine check event was not enabled. Clear, but | |
1004 | * ignore. | |
1005 | */ | |
1006 | continue; | |
1da177e4 LT |
1007 | } |
1008 | ||
ed7290d0 AK |
1009 | /* |
1010 | * Kill on action required. | |
1011 | */ | |
1012 | if (severity == MCE_AR_SEVERITY) | |
1013 | kill_it = 1; | |
1014 | ||
1da177e4 | 1015 | if (m.status & MCI_STATUS_MISCV) |
a2d32bcb | 1016 | m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i)); |
1da177e4 | 1017 | if (m.status & MCI_STATUS_ADDRV) |
a2d32bcb | 1018 | m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i)); |
1da177e4 | 1019 | |
9b1beaf2 AK |
1020 | /* |
1021 | * Action optional error. Queue address for later processing. | |
1022 | * When the ring overflows we just ignore the AO error. | |
1023 | * RED-PEN add some logging mechanism when | |
1024 | * usable_address or mce_add_ring fails. | |
1025 | * RED-PEN don't ignore overflow for tolerant == 0 | |
1026 | */ | |
1027 | if (severity == MCE_AO_SEVERITY && mce_usable_address(&m)) | |
1028 | mce_ring_add(m.addr >> PAGE_SHIFT); | |
1029 | ||
94ad8474 | 1030 | mce_get_rip(&m, regs); |
b79109c3 | 1031 | mce_log(&m); |
1da177e4 | 1032 | |
3c079792 AK |
1033 | if (severity > worst) { |
1034 | *final = m; | |
1035 | worst = severity; | |
1da177e4 | 1036 | } |
1da177e4 LT |
1037 | } |
1038 | ||
3c079792 AK |
1039 | if (!no_way_out) |
1040 | mce_clear_state(toclear); | |
1041 | ||
e9eee03e | 1042 | /* |
3c079792 AK |
1043 | * Do most of the synchronization with other CPUs. |
1044 | * When there's any problem use only local no_way_out state. | |
e9eee03e | 1045 | */ |
3c079792 AK |
1046 | if (mce_end(order) < 0) |
1047 | no_way_out = worst >= MCE_PANIC_SEVERITY; | |
bd78432c TH |
1048 | |
1049 | /* | |
1050 | * If we have decided that we just CAN'T continue, and the user | |
e9eee03e | 1051 | * has not set tolerant to an insane level, give up and die. |
3c079792 AK |
1052 | * |
1053 | * This is mainly used in the case when the system doesn't | |
1054 | * support MCE broadcasting or it has been disabled. | |
bd78432c TH |
1055 | */ |
1056 | if (no_way_out && tolerant < 3) | |
ac960375 | 1057 | mce_panic("Fatal machine check on current CPU", final, msg); |
bd78432c TH |
1058 | |
1059 | /* | |
1060 | * If the error seems to be unrecoverable, something should be | |
1061 | * done. Try to kill as little as possible. If we can kill just | |
1062 | * one task, do that. If the user has set the tolerance very | |
1063 | * high, don't try to do anything at all. | |
1064 | */ | |
bd78432c | 1065 | |
ed7290d0 AK |
1066 | if (kill_it && tolerant < 3) |
1067 | force_sig(SIGBUS, current); | |
1da177e4 | 1068 | |
e02e68d3 TH |
1069 | /* notify userspace ASAP */ |
1070 | set_thread_flag(TIF_MCE_NOTIFY); | |
1071 | ||
3c079792 AK |
1072 | if (worst > 0) |
1073 | mce_report_event(regs); | |
5f8c1a54 | 1074 | mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); |
32561696 | 1075 | out: |
553f265f | 1076 | atomic_dec(&mce_entry); |
88921be3 | 1077 | sync_core(); |
1da177e4 | 1078 | } |
ea149b36 | 1079 | EXPORT_SYMBOL_GPL(do_machine_check); |
1da177e4 | 1080 | |
9b1beaf2 AK |
1081 | /* dummy to break dependency. actual code is in mm/memory-failure.c */ |
1082 | void __attribute__((weak)) memory_failure(unsigned long pfn, int vector) | |
1083 | { | |
1084 | printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn); | |
1085 | } | |
1086 | ||
1087 | /* | |
1088 | * Called after mce notification in process context. This code | |
1089 | * is allowed to sleep. Call the high level VM handler to process | |
1090 | * any corrupted pages. | |
1091 | * Assume that the work queue code only calls this one at a time | |
1092 | * per CPU. | |
1093 | * Note we don't disable preemption, so this code might run on the wrong | |
1094 | * CPU. In this case the event is picked up by the scheduled work queue. | |
1095 | * This is merely a fast path to expedite processing in some common | |
1096 | * cases. | |
1097 | */ | |
1098 | void mce_notify_process(void) | |
1099 | { | |
1100 | unsigned long pfn; | |
1101 | mce_notify_irq(); | |
1102 | while (mce_ring_get(&pfn)) | |
1103 | memory_failure(pfn, MCE_VECTOR); | |
1104 | } | |
1105 | ||
1106 | static void mce_process_work(struct work_struct *dummy) | |
1107 | { | |
1108 | mce_notify_process(); | |
1109 | } | |
1110 | ||
15d5f839 DZ |
1111 | #ifdef CONFIG_X86_MCE_INTEL |
1112 | /*** | |
1113 | * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog | |
676b1855 | 1114 | * @cpu: The CPU on which the event occurred. |
15d5f839 DZ |
1115 | * @status: Event status information |
1116 | * | |
1117 | * This function should be called by the thermal interrupt after the | |
1118 | * event has been processed and the decision was made to log the event | |
1119 | * further. | |
1120 | * | |
1121 | * The status parameter will be saved to the 'status' field of 'struct mce' | |
1122 | * and historically has been the register value of the | |
1123 | * MSR_IA32_THERMAL_STATUS (Intel) msr. | |
1124 | */ | |
b5f2fa4e | 1125 | void mce_log_therm_throt_event(__u64 status) |
15d5f839 DZ |
1126 | { |
1127 | struct mce m; | |
1128 | ||
b5f2fa4e | 1129 | mce_setup(&m); |
15d5f839 DZ |
1130 | m.bank = MCE_THERMAL_BANK; |
1131 | m.status = status; | |
15d5f839 DZ |
1132 | mce_log(&m); |
1133 | } | |
1134 | #endif /* CONFIG_X86_MCE_INTEL */ | |
1135 | ||
1da177e4 | 1136 | /* |
8a336b0a TH |
1137 | * Periodic polling timer for "silent" machine check errors. If the |
1138 | * poller finds an MCE, poll 2x faster. When the poller finds no more | |
1139 | * errors, poll 2x slower (up to check_interval seconds). | |
1da177e4 | 1140 | */ |
1da177e4 | 1141 | static int check_interval = 5 * 60; /* 5 minutes */ |
e9eee03e | 1142 | |
245b2e70 | 1143 | static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */ |
52d168e2 | 1144 | static DEFINE_PER_CPU(struct timer_list, mce_timer); |
1da177e4 | 1145 | |
5e09954a | 1146 | static void mce_start_timer(unsigned long data) |
1da177e4 | 1147 | { |
52d168e2 | 1148 | struct timer_list *t = &per_cpu(mce_timer, data); |
6298c512 | 1149 | int *n; |
52d168e2 AK |
1150 | |
1151 | WARN_ON(smp_processor_id() != data); | |
1152 | ||
e9eee03e | 1153 | if (mce_available(¤t_cpu_data)) { |
ee031c31 AK |
1154 | machine_check_poll(MCP_TIMESTAMP, |
1155 | &__get_cpu_var(mce_poll_banks)); | |
e9eee03e | 1156 | } |
1da177e4 LT |
1157 | |
1158 | /* | |
e02e68d3 TH |
1159 | * Alert userspace if needed. If we logged an MCE, reduce the |
1160 | * polling interval, otherwise increase the polling interval. | |
1da177e4 | 1161 | */ |
245b2e70 | 1162 | n = &__get_cpu_var(mce_next_interval); |
9ff36ee9 | 1163 | if (mce_notify_irq()) |
6298c512 | 1164 | *n = max(*n/2, HZ/100); |
14a02530 | 1165 | else |
6298c512 | 1166 | *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ)); |
e02e68d3 | 1167 | |
6298c512 | 1168 | t->expires = jiffies + *n; |
5be6066a | 1169 | add_timer_on(t, smp_processor_id()); |
e02e68d3 TH |
1170 | } |
1171 | ||
9bd98405 AK |
1172 | static void mce_do_trigger(struct work_struct *work) |
1173 | { | |
1020bcbc | 1174 | call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT); |
9bd98405 AK |
1175 | } |
1176 | ||
1177 | static DECLARE_WORK(mce_trigger_work, mce_do_trigger); | |
1178 | ||
e02e68d3 | 1179 | /* |
9bd98405 AK |
1180 | * Notify the user(s) about new machine check events. |
1181 | * Can be called from interrupt context, but not from machine check/NMI | |
1182 | * context. | |
e02e68d3 | 1183 | */ |
9ff36ee9 | 1184 | int mce_notify_irq(void) |
e02e68d3 | 1185 | { |
8457c84d AK |
1186 | /* Not more than two messages every minute */ |
1187 | static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); | |
1188 | ||
e02e68d3 | 1189 | clear_thread_flag(TIF_MCE_NOTIFY); |
e9eee03e | 1190 | |
1020bcbc | 1191 | if (test_and_clear_bit(0, &mce_need_notify)) { |
e02e68d3 | 1192 | wake_up_interruptible(&mce_wait); |
9bd98405 AK |
1193 | |
1194 | /* | |
1195 | * There is no risk of missing notifications because | |
1196 | * work_pending is always cleared before the function is | |
1197 | * executed. | |
1198 | */ | |
1020bcbc | 1199 | if (mce_helper[0] && !work_pending(&mce_trigger_work)) |
9bd98405 | 1200 | schedule_work(&mce_trigger_work); |
e02e68d3 | 1201 | |
8457c84d | 1202 | if (__ratelimit(&ratelimit)) |
8a336b0a | 1203 | printk(KERN_INFO "Machine check events logged\n"); |
e02e68d3 TH |
1204 | |
1205 | return 1; | |
1da177e4 | 1206 | } |
e02e68d3 TH |
1207 | return 0; |
1208 | } | |
9ff36ee9 | 1209 | EXPORT_SYMBOL_GPL(mce_notify_irq); |
8a336b0a | 1210 | |
cffd377e | 1211 | static int __cpuinit __mcheck_cpu_mce_banks_init(void) |
cebe1820 AK |
1212 | { |
1213 | int i; | |
1214 | ||
1215 | mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL); | |
1216 | if (!mce_banks) | |
1217 | return -ENOMEM; | |
1218 | for (i = 0; i < banks; i++) { | |
1219 | struct mce_bank *b = &mce_banks[i]; | |
11868a2d | 1220 | |
cebe1820 AK |
1221 | b->ctl = -1ULL; |
1222 | b->init = 1; | |
1223 | } | |
1224 | return 0; | |
1225 | } | |
1226 | ||
d88203d1 | 1227 | /* |
1da177e4 LT |
1228 | * Initialize Machine Checks for a CPU. |
1229 | */ | |
5e09954a | 1230 | static int __cpuinit __mcheck_cpu_cap_init(void) |
1da177e4 | 1231 | { |
0d7482e3 | 1232 | unsigned b; |
e9eee03e | 1233 | u64 cap; |
1da177e4 LT |
1234 | |
1235 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
01c6680a TG |
1236 | |
1237 | b = cap & MCG_BANKCNT_MASK; | |
93ae5012 RD |
1238 | if (!banks) |
1239 | printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b); | |
b659294b | 1240 | |
0d7482e3 AK |
1241 | if (b > MAX_NR_BANKS) { |
1242 | printk(KERN_WARNING | |
1243 | "MCE: Using only %u machine check banks out of %u\n", | |
1244 | MAX_NR_BANKS, b); | |
1245 | b = MAX_NR_BANKS; | |
1246 | } | |
1247 | ||
1248 | /* Don't support asymmetric configurations today */ | |
1249 | WARN_ON(banks != 0 && b != banks); | |
1250 | banks = b; | |
cebe1820 | 1251 | if (!mce_banks) { |
cffd377e | 1252 | int err = __mcheck_cpu_mce_banks_init(); |
11868a2d | 1253 | |
cebe1820 AK |
1254 | if (err) |
1255 | return err; | |
1da177e4 | 1256 | } |
0d7482e3 | 1257 | |
94ad8474 | 1258 | /* Use accurate RIP reporting if available. */ |
01c6680a | 1259 | if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) |
94ad8474 | 1260 | rip_msr = MSR_IA32_MCG_EIP; |
1da177e4 | 1261 | |
ed7290d0 AK |
1262 | if (cap & MCG_SER_P) |
1263 | mce_ser = 1; | |
1264 | ||
0d7482e3 AK |
1265 | return 0; |
1266 | } | |
1267 | ||
5e09954a | 1268 | static void __mcheck_cpu_init_generic(void) |
0d7482e3 | 1269 | { |
e9eee03e | 1270 | mce_banks_t all_banks; |
0d7482e3 AK |
1271 | u64 cap; |
1272 | int i; | |
1273 | ||
b79109c3 AK |
1274 | /* |
1275 | * Log the machine checks left over from the previous reset. | |
1276 | */ | |
ee031c31 | 1277 | bitmap_fill(all_banks, MAX_NR_BANKS); |
5679af4c | 1278 | machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks); |
1da177e4 LT |
1279 | |
1280 | set_in_cr4(X86_CR4_MCE); | |
1281 | ||
0d7482e3 | 1282 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
1da177e4 LT |
1283 | if (cap & MCG_CTL_P) |
1284 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); | |
1285 | ||
1286 | for (i = 0; i < banks; i++) { | |
cebe1820 | 1287 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1288 | |
cebe1820 | 1289 | if (!b->init) |
06b7a7a5 | 1290 | continue; |
a2d32bcb AK |
1291 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
1292 | wrmsrl(MSR_IA32_MCx_STATUS(i), 0); | |
d88203d1 | 1293 | } |
1da177e4 LT |
1294 | } |
1295 | ||
1296 | /* Add per CPU specific workarounds here */ | |
5e09954a | 1297 | static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) |
d88203d1 | 1298 | { |
e412cd25 IM |
1299 | if (c->x86_vendor == X86_VENDOR_UNKNOWN) { |
1300 | pr_info("MCE: unknown CPU type - not enabling MCE support.\n"); | |
1301 | return -EOPNOTSUPP; | |
1302 | } | |
1303 | ||
1da177e4 | 1304 | /* This should be disabled by the BIOS, but isn't always */ |
911f6a7b | 1305 | if (c->x86_vendor == X86_VENDOR_AMD) { |
e9eee03e IM |
1306 | if (c->x86 == 15 && banks > 4) { |
1307 | /* | |
1308 | * disable GART TBL walk error reporting, which | |
1309 | * trips off incorrectly with the IOMMU & 3ware | |
1310 | * & Cerberus: | |
1311 | */ | |
cebe1820 | 1312 | clear_bit(10, (unsigned long *)&mce_banks[4].ctl); |
e9eee03e IM |
1313 | } |
1314 | if (c->x86 <= 17 && mce_bootlog < 0) { | |
1315 | /* | |
1316 | * Lots of broken BIOS around that don't clear them | |
1317 | * by default and leave crap in there. Don't log: | |
1318 | */ | |
911f6a7b | 1319 | mce_bootlog = 0; |
e9eee03e | 1320 | } |
2e6f694f AK |
1321 | /* |
1322 | * Various K7s with broken bank 0 around. Always disable | |
1323 | * by default. | |
1324 | */ | |
203abd67 | 1325 | if (c->x86 == 6 && banks > 0) |
cebe1820 | 1326 | mce_banks[0].ctl = 0; |
1da177e4 | 1327 | } |
e583538f | 1328 | |
06b7a7a5 AK |
1329 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
1330 | /* | |
1331 | * SDM documents that on family 6 bank 0 should not be written | |
1332 | * because it aliases to another special BIOS controlled | |
1333 | * register. | |
1334 | * But it's not aliased anymore on model 0x1a+ | |
1335 | * Don't ignore bank 0 completely because there could be a | |
1336 | * valid event later, merely don't write CTL0. | |
1337 | */ | |
1338 | ||
cebe1820 AK |
1339 | if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0) |
1340 | mce_banks[0].init = 0; | |
3c079792 AK |
1341 | |
1342 | /* | |
1343 | * All newer Intel systems support MCE broadcasting. Enable | |
1344 | * synchronization with a one second timeout. | |
1345 | */ | |
1346 | if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && | |
1347 | monarch_timeout < 0) | |
1348 | monarch_timeout = USEC_PER_SEC; | |
c7f6fa44 | 1349 | |
e412cd25 IM |
1350 | /* |
1351 | * There are also broken BIOSes on some Pentium M and | |
1352 | * earlier systems: | |
1353 | */ | |
1354 | if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0) | |
c7f6fa44 | 1355 | mce_bootlog = 0; |
06b7a7a5 | 1356 | } |
3c079792 AK |
1357 | if (monarch_timeout < 0) |
1358 | monarch_timeout = 0; | |
29b0f591 AK |
1359 | if (mce_bootlog != 0) |
1360 | mce_panic_timeout = 30; | |
e412cd25 IM |
1361 | |
1362 | return 0; | |
d88203d1 | 1363 | } |
1da177e4 | 1364 | |
5e09954a | 1365 | static void __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) |
4efc0670 AK |
1366 | { |
1367 | if (c->x86 != 5) | |
1368 | return; | |
1369 | switch (c->x86_vendor) { | |
1370 | case X86_VENDOR_INTEL: | |
c6978369 | 1371 | intel_p5_mcheck_init(c); |
4efc0670 AK |
1372 | break; |
1373 | case X86_VENDOR_CENTAUR: | |
1374 | winchip_mcheck_init(c); | |
1375 | break; | |
1376 | } | |
1377 | } | |
1378 | ||
5e09954a | 1379 | static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
1380 | { |
1381 | switch (c->x86_vendor) { | |
1382 | case X86_VENDOR_INTEL: | |
1383 | mce_intel_feature_init(c); | |
1384 | break; | |
89b831ef JS |
1385 | case X86_VENDOR_AMD: |
1386 | mce_amd_feature_init(c); | |
1387 | break; | |
1da177e4 LT |
1388 | default: |
1389 | break; | |
1390 | } | |
1391 | } | |
1392 | ||
5e09954a | 1393 | static void __mcheck_cpu_init_timer(void) |
52d168e2 AK |
1394 | { |
1395 | struct timer_list *t = &__get_cpu_var(mce_timer); | |
245b2e70 | 1396 | int *n = &__get_cpu_var(mce_next_interval); |
52d168e2 | 1397 | |
bc09effa JB |
1398 | setup_timer(t, mce_start_timer, smp_processor_id()); |
1399 | ||
62fdac59 HS |
1400 | if (mce_ignore_ce) |
1401 | return; | |
1402 | ||
6298c512 AK |
1403 | *n = check_interval * HZ; |
1404 | if (!*n) | |
52d168e2 | 1405 | return; |
6298c512 | 1406 | t->expires = round_jiffies(jiffies + *n); |
5be6066a | 1407 | add_timer_on(t, smp_processor_id()); |
52d168e2 AK |
1408 | } |
1409 | ||
9eda8cb3 AK |
1410 | /* Handle unconfigured int18 (should never happen) */ |
1411 | static void unexpected_machine_check(struct pt_regs *regs, long error_code) | |
1412 | { | |
1413 | printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n", | |
1414 | smp_processor_id()); | |
1415 | } | |
1416 | ||
1417 | /* Call the installed machine check handler for this CPU setup. */ | |
1418 | void (*machine_check_vector)(struct pt_regs *, long error_code) = | |
1419 | unexpected_machine_check; | |
1420 | ||
d88203d1 | 1421 | /* |
1da177e4 | 1422 | * Called for each booted CPU to set up machine checks. |
e9eee03e | 1423 | * Must be called with preempt off: |
1da177e4 | 1424 | */ |
5e09954a | 1425 | void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c) |
1da177e4 | 1426 | { |
4efc0670 AK |
1427 | if (mce_disabled) |
1428 | return; | |
1429 | ||
5e09954a | 1430 | __mcheck_cpu_ancient_init(c); |
4efc0670 | 1431 | |
5b4408fd | 1432 | if (!mce_available(c)) |
1da177e4 LT |
1433 | return; |
1434 | ||
5e09954a | 1435 | if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) { |
04b2b1a4 | 1436 | mce_disabled = 1; |
0d7482e3 AK |
1437 | return; |
1438 | } | |
0d7482e3 | 1439 | |
5d727926 AK |
1440 | machine_check_vector = do_machine_check; |
1441 | ||
5e09954a BP |
1442 | __mcheck_cpu_init_generic(); |
1443 | __mcheck_cpu_init_vendor(c); | |
1444 | __mcheck_cpu_init_timer(); | |
9b1beaf2 | 1445 | INIT_WORK(&__get_cpu_var(mce_work), mce_process_work); |
fb253195 | 1446 | |
1da177e4 LT |
1447 | } |
1448 | ||
1449 | /* | |
1450 | * Character device to read and clear the MCE log. | |
1451 | */ | |
1452 | ||
f528e7ba | 1453 | static DEFINE_SPINLOCK(mce_state_lock); |
e9eee03e IM |
1454 | static int open_count; /* #times opened */ |
1455 | static int open_exclu; /* already open exclusive? */ | |
f528e7ba TH |
1456 | |
1457 | static int mce_open(struct inode *inode, struct file *file) | |
1458 | { | |
1459 | spin_lock(&mce_state_lock); | |
1460 | ||
1461 | if (open_exclu || (open_count && (file->f_flags & O_EXCL))) { | |
1462 | spin_unlock(&mce_state_lock); | |
e9eee03e | 1463 | |
f528e7ba TH |
1464 | return -EBUSY; |
1465 | } | |
1466 | ||
1467 | if (file->f_flags & O_EXCL) | |
1468 | open_exclu = 1; | |
1469 | open_count++; | |
1470 | ||
1471 | spin_unlock(&mce_state_lock); | |
1472 | ||
bd78432c | 1473 | return nonseekable_open(inode, file); |
f528e7ba TH |
1474 | } |
1475 | ||
1476 | static int mce_release(struct inode *inode, struct file *file) | |
1477 | { | |
1478 | spin_lock(&mce_state_lock); | |
1479 | ||
1480 | open_count--; | |
1481 | open_exclu = 0; | |
1482 | ||
1483 | spin_unlock(&mce_state_lock); | |
1484 | ||
1485 | return 0; | |
1486 | } | |
1487 | ||
d88203d1 TG |
1488 | static void collect_tscs(void *data) |
1489 | { | |
1da177e4 | 1490 | unsigned long *cpu_tsc = (unsigned long *)data; |
d88203d1 | 1491 | |
1da177e4 | 1492 | rdtscll(cpu_tsc[smp_processor_id()]); |
d88203d1 | 1493 | } |
1da177e4 | 1494 | |
d88203d1 TG |
1495 | static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize, |
1496 | loff_t *off) | |
1da177e4 | 1497 | { |
e9eee03e | 1498 | char __user *buf = ubuf; |
f0de53bb | 1499 | unsigned long *cpu_tsc; |
ef41df43 | 1500 | unsigned prev, next; |
1da177e4 LT |
1501 | int i, err; |
1502 | ||
6bca67f9 | 1503 | cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL); |
f0de53bb AK |
1504 | if (!cpu_tsc) |
1505 | return -ENOMEM; | |
1506 | ||
8c8b8859 | 1507 | mutex_lock(&mce_read_mutex); |
f56e8a07 | 1508 | next = rcu_dereference_check_mce(mcelog.next); |
1da177e4 LT |
1509 | |
1510 | /* Only supports full reads right now */ | |
d88203d1 | 1511 | if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) { |
8c8b8859 | 1512 | mutex_unlock(&mce_read_mutex); |
f0de53bb | 1513 | kfree(cpu_tsc); |
e9eee03e | 1514 | |
1da177e4 LT |
1515 | return -EINVAL; |
1516 | } | |
1517 | ||
1518 | err = 0; | |
ef41df43 HY |
1519 | prev = 0; |
1520 | do { | |
1521 | for (i = prev; i < next; i++) { | |
1522 | unsigned long start = jiffies; | |
1523 | ||
1524 | while (!mcelog.entry[i].finished) { | |
1525 | if (time_after_eq(jiffies, start + 2)) { | |
1526 | memset(mcelog.entry + i, 0, | |
1527 | sizeof(struct mce)); | |
1528 | goto timeout; | |
1529 | } | |
1530 | cpu_relax(); | |
673242c1 | 1531 | } |
ef41df43 HY |
1532 | smp_rmb(); |
1533 | err |= copy_to_user(buf, mcelog.entry + i, | |
1534 | sizeof(struct mce)); | |
1535 | buf += sizeof(struct mce); | |
1536 | timeout: | |
1537 | ; | |
673242c1 | 1538 | } |
1da177e4 | 1539 | |
ef41df43 HY |
1540 | memset(mcelog.entry + prev, 0, |
1541 | (next - prev) * sizeof(struct mce)); | |
1542 | prev = next; | |
1543 | next = cmpxchg(&mcelog.next, prev, 0); | |
1544 | } while (next != prev); | |
1da177e4 | 1545 | |
b2b18660 | 1546 | synchronize_sched(); |
1da177e4 | 1547 | |
d88203d1 TG |
1548 | /* |
1549 | * Collect entries that were still getting written before the | |
1550 | * synchronize. | |
1551 | */ | |
15c8b6c1 | 1552 | on_each_cpu(collect_tscs, cpu_tsc, 1); |
e9eee03e | 1553 | |
d88203d1 TG |
1554 | for (i = next; i < MCE_LOG_LEN; i++) { |
1555 | if (mcelog.entry[i].finished && | |
1556 | mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) { | |
1557 | err |= copy_to_user(buf, mcelog.entry+i, | |
1558 | sizeof(struct mce)); | |
1da177e4 LT |
1559 | smp_rmb(); |
1560 | buf += sizeof(struct mce); | |
1561 | memset(&mcelog.entry[i], 0, sizeof(struct mce)); | |
1562 | } | |
d88203d1 | 1563 | } |
8c8b8859 | 1564 | mutex_unlock(&mce_read_mutex); |
f0de53bb | 1565 | kfree(cpu_tsc); |
e9eee03e | 1566 | |
d88203d1 | 1567 | return err ? -EFAULT : buf - ubuf; |
1da177e4 LT |
1568 | } |
1569 | ||
e02e68d3 TH |
1570 | static unsigned int mce_poll(struct file *file, poll_table *wait) |
1571 | { | |
1572 | poll_wait(file, &mce_wait, wait); | |
f56e8a07 | 1573 | if (rcu_dereference_check_mce(mcelog.next)) |
e02e68d3 TH |
1574 | return POLLIN | POLLRDNORM; |
1575 | return 0; | |
1576 | } | |
1577 | ||
c68461b6 | 1578 | static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg) |
1da177e4 LT |
1579 | { |
1580 | int __user *p = (int __user *)arg; | |
d88203d1 | 1581 | |
1da177e4 | 1582 | if (!capable(CAP_SYS_ADMIN)) |
d88203d1 | 1583 | return -EPERM; |
e9eee03e | 1584 | |
1da177e4 | 1585 | switch (cmd) { |
d88203d1 | 1586 | case MCE_GET_RECORD_LEN: |
1da177e4 LT |
1587 | return put_user(sizeof(struct mce), p); |
1588 | case MCE_GET_LOG_LEN: | |
d88203d1 | 1589 | return put_user(MCE_LOG_LEN, p); |
1da177e4 LT |
1590 | case MCE_GETCLEAR_FLAGS: { |
1591 | unsigned flags; | |
d88203d1 TG |
1592 | |
1593 | do { | |
1da177e4 | 1594 | flags = mcelog.flags; |
d88203d1 | 1595 | } while (cmpxchg(&mcelog.flags, flags, 0) != flags); |
e9eee03e | 1596 | |
d88203d1 | 1597 | return put_user(flags, p); |
1da177e4 LT |
1598 | } |
1599 | default: | |
d88203d1 TG |
1600 | return -ENOTTY; |
1601 | } | |
1da177e4 LT |
1602 | } |
1603 | ||
a1ff41bf | 1604 | /* Modified in mce-inject.c, so not static or const */ |
ea149b36 | 1605 | struct file_operations mce_chrdev_ops = { |
e9eee03e IM |
1606 | .open = mce_open, |
1607 | .release = mce_release, | |
1608 | .read = mce_read, | |
1609 | .poll = mce_poll, | |
1610 | .unlocked_ioctl = mce_ioctl, | |
1da177e4 | 1611 | }; |
ea149b36 | 1612 | EXPORT_SYMBOL_GPL(mce_chrdev_ops); |
1da177e4 LT |
1613 | |
1614 | static struct miscdevice mce_log_device = { | |
1615 | MISC_MCELOG_MINOR, | |
1616 | "mcelog", | |
1617 | &mce_chrdev_ops, | |
1618 | }; | |
1619 | ||
13503fa9 | 1620 | /* |
62fdac59 HS |
1621 | * mce=off Disables machine check |
1622 | * mce=no_cmci Disables CMCI | |
1623 | * mce=dont_log_ce Clears corrected events silently, no log created for CEs. | |
1624 | * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared. | |
3c079792 AK |
1625 | * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above) |
1626 | * monarchtimeout is how long to wait for other CPUs on machine | |
1627 | * check, or 0 to not wait | |
13503fa9 HS |
1628 | * mce=bootlog Log MCEs from before booting. Disabled by default on AMD. |
1629 | * mce=nobootlog Don't log MCEs from before booting. | |
1630 | */ | |
1da177e4 LT |
1631 | static int __init mcheck_enable(char *str) |
1632 | { | |
e3346fc4 | 1633 | if (*str == 0) { |
4efc0670 | 1634 | enable_p5_mce(); |
e3346fc4 BZ |
1635 | return 1; |
1636 | } | |
4efc0670 AK |
1637 | if (*str == '=') |
1638 | str++; | |
1da177e4 | 1639 | if (!strcmp(str, "off")) |
04b2b1a4 | 1640 | mce_disabled = 1; |
62fdac59 HS |
1641 | else if (!strcmp(str, "no_cmci")) |
1642 | mce_cmci_disabled = 1; | |
1643 | else if (!strcmp(str, "dont_log_ce")) | |
1644 | mce_dont_log_ce = 1; | |
1645 | else if (!strcmp(str, "ignore_ce")) | |
1646 | mce_ignore_ce = 1; | |
13503fa9 HS |
1647 | else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) |
1648 | mce_bootlog = (str[0] == 'b'); | |
3c079792 | 1649 | else if (isdigit(str[0])) { |
8c566ef5 | 1650 | get_option(&str, &tolerant); |
3c079792 AK |
1651 | if (*str == ',') { |
1652 | ++str; | |
1653 | get_option(&str, &monarch_timeout); | |
1654 | } | |
1655 | } else { | |
4efc0670 | 1656 | printk(KERN_INFO "mce argument %s ignored. Please use /sys\n", |
13503fa9 HS |
1657 | str); |
1658 | return 0; | |
1659 | } | |
9b41046c | 1660 | return 1; |
1da177e4 | 1661 | } |
4efc0670 | 1662 | __setup("mce", mcheck_enable); |
1da177e4 | 1663 | |
a2202aa2 | 1664 | int __init mcheck_init(void) |
b33a6363 BP |
1665 | { |
1666 | atomic_notifier_chain_register(&x86_mce_decoder_chain, &mce_dec_nb); | |
1667 | ||
a2202aa2 YW |
1668 | mcheck_intel_therm_init(); |
1669 | ||
b33a6363 BP |
1670 | return 0; |
1671 | } | |
b33a6363 | 1672 | |
d88203d1 | 1673 | /* |
1da177e4 | 1674 | * Sysfs support |
d88203d1 | 1675 | */ |
1da177e4 | 1676 | |
973a2dd1 AK |
1677 | /* |
1678 | * Disable machine checks on suspend and shutdown. We can't really handle | |
1679 | * them later. | |
1680 | */ | |
5e09954a | 1681 | static int mce_disable_error_reporting(void) |
973a2dd1 AK |
1682 | { |
1683 | int i; | |
1684 | ||
06b7a7a5 | 1685 | for (i = 0; i < banks; i++) { |
cebe1820 | 1686 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1687 | |
cebe1820 | 1688 | if (b->init) |
a2d32bcb | 1689 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 1690 | } |
973a2dd1 AK |
1691 | return 0; |
1692 | } | |
1693 | ||
1694 | static int mce_suspend(struct sys_device *dev, pm_message_t state) | |
1695 | { | |
5e09954a | 1696 | return mce_disable_error_reporting(); |
973a2dd1 AK |
1697 | } |
1698 | ||
1699 | static int mce_shutdown(struct sys_device *dev) | |
1700 | { | |
5e09954a | 1701 | return mce_disable_error_reporting(); |
973a2dd1 AK |
1702 | } |
1703 | ||
e9eee03e IM |
1704 | /* |
1705 | * On resume clear all MCE state. Don't want to see leftovers from the BIOS. | |
1706 | * Only one CPU is active at this time, the others get re-added later using | |
1707 | * CPU hotplug: | |
1708 | */ | |
1da177e4 LT |
1709 | static int mce_resume(struct sys_device *dev) |
1710 | { | |
5e09954a BP |
1711 | __mcheck_cpu_init_generic(); |
1712 | __mcheck_cpu_init_vendor(¤t_cpu_data); | |
e9eee03e | 1713 | |
1da177e4 LT |
1714 | return 0; |
1715 | } | |
1716 | ||
52d168e2 AK |
1717 | static void mce_cpu_restart(void *data) |
1718 | { | |
1719 | del_timer_sync(&__get_cpu_var(mce_timer)); | |
33edbf02 HS |
1720 | if (!mce_available(¤t_cpu_data)) |
1721 | return; | |
5e09954a BP |
1722 | __mcheck_cpu_init_generic(); |
1723 | __mcheck_cpu_init_timer(); | |
52d168e2 AK |
1724 | } |
1725 | ||
1da177e4 | 1726 | /* Reinit MCEs after user configuration changes */ |
d88203d1 TG |
1727 | static void mce_restart(void) |
1728 | { | |
52d168e2 | 1729 | on_each_cpu(mce_cpu_restart, NULL, 1); |
1da177e4 LT |
1730 | } |
1731 | ||
9af43b54 HS |
1732 | /* Toggle features for corrected errors */ |
1733 | static void mce_disable_ce(void *all) | |
1734 | { | |
1735 | if (!mce_available(¤t_cpu_data)) | |
1736 | return; | |
1737 | if (all) | |
1738 | del_timer_sync(&__get_cpu_var(mce_timer)); | |
1739 | cmci_clear(); | |
1740 | } | |
1741 | ||
1742 | static void mce_enable_ce(void *all) | |
1743 | { | |
1744 | if (!mce_available(¤t_cpu_data)) | |
1745 | return; | |
1746 | cmci_reenable(); | |
1747 | cmci_recheck(); | |
1748 | if (all) | |
5e09954a | 1749 | __mcheck_cpu_init_timer(); |
9af43b54 HS |
1750 | } |
1751 | ||
1da177e4 | 1752 | static struct sysdev_class mce_sysclass = { |
e9eee03e IM |
1753 | .suspend = mce_suspend, |
1754 | .shutdown = mce_shutdown, | |
1755 | .resume = mce_resume, | |
1756 | .name = "machinecheck", | |
1da177e4 LT |
1757 | }; |
1758 | ||
cb491fca | 1759 | DEFINE_PER_CPU(struct sys_device, mce_dev); |
e9eee03e IM |
1760 | |
1761 | __cpuinitdata | |
1762 | void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); | |
1da177e4 | 1763 | |
cebe1820 AK |
1764 | static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr) |
1765 | { | |
1766 | return container_of(attr, struct mce_bank, attr); | |
1767 | } | |
0d7482e3 AK |
1768 | |
1769 | static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
1770 | char *buf) | |
1771 | { | |
cebe1820 | 1772 | return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl); |
0d7482e3 AK |
1773 | } |
1774 | ||
1775 | static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
9319cec8 | 1776 | const char *buf, size_t size) |
0d7482e3 | 1777 | { |
9319cec8 | 1778 | u64 new; |
e9eee03e | 1779 | |
9319cec8 | 1780 | if (strict_strtoull(buf, 0, &new) < 0) |
0d7482e3 | 1781 | return -EINVAL; |
e9eee03e | 1782 | |
cebe1820 | 1783 | attr_to_bank(attr)->ctl = new; |
0d7482e3 | 1784 | mce_restart(); |
e9eee03e | 1785 | |
9319cec8 | 1786 | return size; |
0d7482e3 | 1787 | } |
a98f0dd3 | 1788 | |
e9eee03e IM |
1789 | static ssize_t |
1790 | show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf) | |
a98f0dd3 | 1791 | { |
1020bcbc | 1792 | strcpy(buf, mce_helper); |
a98f0dd3 | 1793 | strcat(buf, "\n"); |
1020bcbc | 1794 | return strlen(mce_helper) + 1; |
a98f0dd3 AK |
1795 | } |
1796 | ||
4a0b2b4d | 1797 | static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr, |
e9eee03e | 1798 | const char *buf, size_t siz) |
a98f0dd3 AK |
1799 | { |
1800 | char *p; | |
e9eee03e | 1801 | |
1020bcbc HS |
1802 | strncpy(mce_helper, buf, sizeof(mce_helper)); |
1803 | mce_helper[sizeof(mce_helper)-1] = 0; | |
1020bcbc | 1804 | p = strchr(mce_helper, '\n'); |
e9eee03e | 1805 | |
e9084ec9 | 1806 | if (p) |
e9eee03e IM |
1807 | *p = 0; |
1808 | ||
e9084ec9 | 1809 | return strlen(mce_helper) + !!p; |
a98f0dd3 AK |
1810 | } |
1811 | ||
9af43b54 HS |
1812 | static ssize_t set_ignore_ce(struct sys_device *s, |
1813 | struct sysdev_attribute *attr, | |
1814 | const char *buf, size_t size) | |
1815 | { | |
1816 | u64 new; | |
1817 | ||
1818 | if (strict_strtoull(buf, 0, &new) < 0) | |
1819 | return -EINVAL; | |
1820 | ||
1821 | if (mce_ignore_ce ^ !!new) { | |
1822 | if (new) { | |
1823 | /* disable ce features */ | |
1824 | on_each_cpu(mce_disable_ce, (void *)1, 1); | |
1825 | mce_ignore_ce = 1; | |
1826 | } else { | |
1827 | /* enable ce features */ | |
1828 | mce_ignore_ce = 0; | |
1829 | on_each_cpu(mce_enable_ce, (void *)1, 1); | |
1830 | } | |
1831 | } | |
1832 | return size; | |
1833 | } | |
1834 | ||
1835 | static ssize_t set_cmci_disabled(struct sys_device *s, | |
1836 | struct sysdev_attribute *attr, | |
1837 | const char *buf, size_t size) | |
1838 | { | |
1839 | u64 new; | |
1840 | ||
1841 | if (strict_strtoull(buf, 0, &new) < 0) | |
1842 | return -EINVAL; | |
1843 | ||
1844 | if (mce_cmci_disabled ^ !!new) { | |
1845 | if (new) { | |
1846 | /* disable cmci */ | |
1847 | on_each_cpu(mce_disable_ce, NULL, 1); | |
1848 | mce_cmci_disabled = 1; | |
1849 | } else { | |
1850 | /* enable cmci */ | |
1851 | mce_cmci_disabled = 0; | |
1852 | on_each_cpu(mce_enable_ce, NULL, 1); | |
1853 | } | |
1854 | } | |
1855 | return size; | |
1856 | } | |
1857 | ||
b56f642d AK |
1858 | static ssize_t store_int_with_restart(struct sys_device *s, |
1859 | struct sysdev_attribute *attr, | |
1860 | const char *buf, size_t size) | |
1861 | { | |
1862 | ssize_t ret = sysdev_store_int(s, attr, buf, size); | |
1863 | mce_restart(); | |
1864 | return ret; | |
1865 | } | |
1866 | ||
a98f0dd3 | 1867 | static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger); |
d95d62c0 | 1868 | static SYSDEV_INT_ATTR(tolerant, 0644, tolerant); |
3c079792 | 1869 | static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout); |
9af43b54 | 1870 | static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce); |
e9eee03e | 1871 | |
b56f642d AK |
1872 | static struct sysdev_ext_attribute attr_check_interval = { |
1873 | _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int, | |
1874 | store_int_with_restart), | |
1875 | &check_interval | |
1876 | }; | |
e9eee03e | 1877 | |
9af43b54 HS |
1878 | static struct sysdev_ext_attribute attr_ignore_ce = { |
1879 | _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce), | |
1880 | &mce_ignore_ce | |
1881 | }; | |
1882 | ||
1883 | static struct sysdev_ext_attribute attr_cmci_disabled = { | |
74b602c7 | 1884 | _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled), |
9af43b54 HS |
1885 | &mce_cmci_disabled |
1886 | }; | |
1887 | ||
cb491fca | 1888 | static struct sysdev_attribute *mce_attrs[] = { |
9af43b54 HS |
1889 | &attr_tolerant.attr, |
1890 | &attr_check_interval.attr, | |
1891 | &attr_trigger, | |
3c079792 | 1892 | &attr_monarch_timeout.attr, |
9af43b54 HS |
1893 | &attr_dont_log_ce.attr, |
1894 | &attr_ignore_ce.attr, | |
1895 | &attr_cmci_disabled.attr, | |
a98f0dd3 AK |
1896 | NULL |
1897 | }; | |
1da177e4 | 1898 | |
cb491fca | 1899 | static cpumask_var_t mce_dev_initialized; |
bae19fe0 | 1900 | |
e9eee03e | 1901 | /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */ |
91c6d400 | 1902 | static __cpuinit int mce_create_device(unsigned int cpu) |
1da177e4 LT |
1903 | { |
1904 | int err; | |
b1f49f95 | 1905 | int i, j; |
92cb7612 | 1906 | |
90367556 | 1907 | if (!mce_available(&boot_cpu_data)) |
91c6d400 AK |
1908 | return -EIO; |
1909 | ||
cb491fca IM |
1910 | memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject)); |
1911 | per_cpu(mce_dev, cpu).id = cpu; | |
1912 | per_cpu(mce_dev, cpu).cls = &mce_sysclass; | |
91c6d400 | 1913 | |
cb491fca | 1914 | err = sysdev_register(&per_cpu(mce_dev, cpu)); |
d435d862 AM |
1915 | if (err) |
1916 | return err; | |
1917 | ||
cb491fca IM |
1918 | for (i = 0; mce_attrs[i]; i++) { |
1919 | err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
d435d862 AM |
1920 | if (err) |
1921 | goto error; | |
1922 | } | |
b1f49f95 | 1923 | for (j = 0; j < banks; j++) { |
cb491fca | 1924 | err = sysdev_create_file(&per_cpu(mce_dev, cpu), |
cebe1820 | 1925 | &mce_banks[j].attr); |
0d7482e3 AK |
1926 | if (err) |
1927 | goto error2; | |
1928 | } | |
cb491fca | 1929 | cpumask_set_cpu(cpu, mce_dev_initialized); |
91c6d400 | 1930 | |
d435d862 | 1931 | return 0; |
0d7482e3 | 1932 | error2: |
b1f49f95 | 1933 | while (--j >= 0) |
cebe1820 | 1934 | sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[j].attr); |
d435d862 | 1935 | error: |
cb491fca | 1936 | while (--i >= 0) |
5c0e9f28 | 1937 | sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); |
cb491fca IM |
1938 | |
1939 | sysdev_unregister(&per_cpu(mce_dev, cpu)); | |
d435d862 | 1940 | |
91c6d400 AK |
1941 | return err; |
1942 | } | |
1943 | ||
2d9cd6c2 | 1944 | static __cpuinit void mce_remove_device(unsigned int cpu) |
91c6d400 | 1945 | { |
73ca5358 SL |
1946 | int i; |
1947 | ||
cb491fca | 1948 | if (!cpumask_test_cpu(cpu, mce_dev_initialized)) |
bae19fe0 AH |
1949 | return; |
1950 | ||
cb491fca IM |
1951 | for (i = 0; mce_attrs[i]; i++) |
1952 | sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
1953 | ||
0d7482e3 | 1954 | for (i = 0; i < banks; i++) |
cebe1820 | 1955 | sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr); |
cb491fca IM |
1956 | |
1957 | sysdev_unregister(&per_cpu(mce_dev, cpu)); | |
1958 | cpumask_clear_cpu(cpu, mce_dev_initialized); | |
91c6d400 | 1959 | } |
91c6d400 | 1960 | |
d6b75584 | 1961 | /* Make sure there are no machine checks on offlined CPUs. */ |
767df1bd | 1962 | static void __cpuinit mce_disable_cpu(void *h) |
d6b75584 | 1963 | { |
88ccbedd | 1964 | unsigned long action = *(unsigned long *)h; |
cb491fca | 1965 | int i; |
d6b75584 AK |
1966 | |
1967 | if (!mce_available(¤t_cpu_data)) | |
1968 | return; | |
767df1bd | 1969 | |
88ccbedd AK |
1970 | if (!(action & CPU_TASKS_FROZEN)) |
1971 | cmci_clear(); | |
06b7a7a5 | 1972 | for (i = 0; i < banks; i++) { |
cebe1820 | 1973 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1974 | |
cebe1820 | 1975 | if (b->init) |
a2d32bcb | 1976 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 1977 | } |
d6b75584 AK |
1978 | } |
1979 | ||
767df1bd | 1980 | static void __cpuinit mce_reenable_cpu(void *h) |
d6b75584 | 1981 | { |
88ccbedd | 1982 | unsigned long action = *(unsigned long *)h; |
e9eee03e | 1983 | int i; |
d6b75584 AK |
1984 | |
1985 | if (!mce_available(¤t_cpu_data)) | |
1986 | return; | |
e9eee03e | 1987 | |
88ccbedd AK |
1988 | if (!(action & CPU_TASKS_FROZEN)) |
1989 | cmci_reenable(); | |
06b7a7a5 | 1990 | for (i = 0; i < banks; i++) { |
cebe1820 | 1991 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1992 | |
cebe1820 | 1993 | if (b->init) |
a2d32bcb | 1994 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
06b7a7a5 | 1995 | } |
d6b75584 AK |
1996 | } |
1997 | ||
91c6d400 | 1998 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ |
e9eee03e IM |
1999 | static int __cpuinit |
2000 | mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) | |
91c6d400 AK |
2001 | { |
2002 | unsigned int cpu = (unsigned long)hcpu; | |
52d168e2 | 2003 | struct timer_list *t = &per_cpu(mce_timer, cpu); |
91c6d400 AK |
2004 | |
2005 | switch (action) { | |
bae19fe0 AH |
2006 | case CPU_ONLINE: |
2007 | case CPU_ONLINE_FROZEN: | |
2008 | mce_create_device(cpu); | |
8735728e RW |
2009 | if (threshold_cpu_callback) |
2010 | threshold_cpu_callback(action, cpu); | |
91c6d400 | 2011 | break; |
91c6d400 | 2012 | case CPU_DEAD: |
8bb78442 | 2013 | case CPU_DEAD_FROZEN: |
8735728e RW |
2014 | if (threshold_cpu_callback) |
2015 | threshold_cpu_callback(action, cpu); | |
91c6d400 AK |
2016 | mce_remove_device(cpu); |
2017 | break; | |
52d168e2 AK |
2018 | case CPU_DOWN_PREPARE: |
2019 | case CPU_DOWN_PREPARE_FROZEN: | |
2020 | del_timer_sync(t); | |
88ccbedd | 2021 | smp_call_function_single(cpu, mce_disable_cpu, &action, 1); |
52d168e2 AK |
2022 | break; |
2023 | case CPU_DOWN_FAILED: | |
2024 | case CPU_DOWN_FAILED_FROZEN: | |
fe5ed91d HS |
2025 | if (!mce_ignore_ce && check_interval) { |
2026 | t->expires = round_jiffies(jiffies + | |
245b2e70 | 2027 | __get_cpu_var(mce_next_interval)); |
fe5ed91d HS |
2028 | add_timer_on(t, cpu); |
2029 | } | |
88ccbedd AK |
2030 | smp_call_function_single(cpu, mce_reenable_cpu, &action, 1); |
2031 | break; | |
2032 | case CPU_POST_DEAD: | |
2033 | /* intentionally ignoring frozen here */ | |
2034 | cmci_rediscover(cpu); | |
52d168e2 | 2035 | break; |
91c6d400 | 2036 | } |
bae19fe0 | 2037 | return NOTIFY_OK; |
91c6d400 AK |
2038 | } |
2039 | ||
1e35669d | 2040 | static struct notifier_block mce_cpu_notifier __cpuinitdata = { |
91c6d400 AK |
2041 | .notifier_call = mce_cpu_callback, |
2042 | }; | |
2043 | ||
cebe1820 | 2044 | static __init void mce_init_banks(void) |
0d7482e3 AK |
2045 | { |
2046 | int i; | |
2047 | ||
0d7482e3 | 2048 | for (i = 0; i < banks; i++) { |
cebe1820 AK |
2049 | struct mce_bank *b = &mce_banks[i]; |
2050 | struct sysdev_attribute *a = &b->attr; | |
e9eee03e | 2051 | |
a07e4156 | 2052 | sysfs_attr_init(&a->attr); |
cebe1820 AK |
2053 | a->attr.name = b->attrname; |
2054 | snprintf(b->attrname, ATTR_LEN, "bank%d", i); | |
e9eee03e IM |
2055 | |
2056 | a->attr.mode = 0644; | |
2057 | a->show = show_bank; | |
2058 | a->store = set_bank; | |
0d7482e3 | 2059 | } |
0d7482e3 AK |
2060 | } |
2061 | ||
5e09954a | 2062 | static __init int mcheck_init_device(void) |
91c6d400 AK |
2063 | { |
2064 | int err; | |
2065 | int i = 0; | |
2066 | ||
1da177e4 LT |
2067 | if (!mce_available(&boot_cpu_data)) |
2068 | return -EIO; | |
0d7482e3 | 2069 | |
e92fae06 | 2070 | zalloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL); |
996867d0 | 2071 | |
cebe1820 | 2072 | mce_init_banks(); |
0d7482e3 | 2073 | |
1da177e4 | 2074 | err = sysdev_class_register(&mce_sysclass); |
d435d862 AM |
2075 | if (err) |
2076 | return err; | |
91c6d400 AK |
2077 | |
2078 | for_each_online_cpu(i) { | |
d435d862 AM |
2079 | err = mce_create_device(i); |
2080 | if (err) | |
2081 | return err; | |
91c6d400 AK |
2082 | } |
2083 | ||
be6b5a35 | 2084 | register_hotcpu_notifier(&mce_cpu_notifier); |
1da177e4 | 2085 | misc_register(&mce_log_device); |
e9eee03e | 2086 | |
1da177e4 | 2087 | return err; |
1da177e4 | 2088 | } |
91c6d400 | 2089 | |
5e09954a | 2090 | device_initcall(mcheck_init_device); |
a988d334 | 2091 | |
d7c3c9a6 AK |
2092 | /* |
2093 | * Old style boot options parsing. Only for compatibility. | |
2094 | */ | |
2095 | static int __init mcheck_disable(char *str) | |
2096 | { | |
2097 | mce_disabled = 1; | |
2098 | return 1; | |
2099 | } | |
2100 | __setup("nomce", mcheck_disable); | |
a988d334 | 2101 | |
5be9ed25 HY |
2102 | #ifdef CONFIG_DEBUG_FS |
2103 | struct dentry *mce_get_debugfs_dir(void) | |
a988d334 | 2104 | { |
5be9ed25 | 2105 | static struct dentry *dmce; |
a988d334 | 2106 | |
5be9ed25 HY |
2107 | if (!dmce) |
2108 | dmce = debugfs_create_dir("mce", NULL); | |
a988d334 | 2109 | |
5be9ed25 HY |
2110 | return dmce; |
2111 | } | |
a988d334 | 2112 | |
bf783f9f HY |
2113 | static void mce_reset(void) |
2114 | { | |
2115 | cpu_missing = 0; | |
2116 | atomic_set(&mce_fake_paniced, 0); | |
2117 | atomic_set(&mce_executing, 0); | |
2118 | atomic_set(&mce_callin, 0); | |
2119 | atomic_set(&global_nwo, 0); | |
2120 | } | |
a988d334 | 2121 | |
bf783f9f HY |
2122 | static int fake_panic_get(void *data, u64 *val) |
2123 | { | |
2124 | *val = fake_panic; | |
2125 | return 0; | |
a988d334 IM |
2126 | } |
2127 | ||
bf783f9f | 2128 | static int fake_panic_set(void *data, u64 val) |
a988d334 | 2129 | { |
bf783f9f HY |
2130 | mce_reset(); |
2131 | fake_panic = val; | |
2132 | return 0; | |
a988d334 | 2133 | } |
a988d334 | 2134 | |
bf783f9f HY |
2135 | DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get, |
2136 | fake_panic_set, "%llu\n"); | |
d7c3c9a6 | 2137 | |
5e09954a | 2138 | static int __init mcheck_debugfs_init(void) |
d7c3c9a6 | 2139 | { |
bf783f9f HY |
2140 | struct dentry *dmce, *ffake_panic; |
2141 | ||
2142 | dmce = mce_get_debugfs_dir(); | |
2143 | if (!dmce) | |
2144 | return -ENOMEM; | |
2145 | ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL, | |
2146 | &fake_panic_fops); | |
2147 | if (!ffake_panic) | |
2148 | return -ENOMEM; | |
2149 | ||
2150 | return 0; | |
d7c3c9a6 | 2151 | } |
5e09954a | 2152 | late_initcall(mcheck_debugfs_init); |
5be9ed25 | 2153 | #endif |