Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Machine check handler. | |
e9eee03e | 3 | * |
1da177e4 | 4 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. |
d88203d1 TG |
5 | * Rest from unknown author(s). |
6 | * 2004 Andi Kleen. Rewrote most of it. | |
b79109c3 AK |
7 | * Copyright 2008 Intel Corporation |
8 | * Author: Andi Kleen | |
1da177e4 | 9 | */ |
e9eee03e IM |
10 | #include <linux/thread_info.h> |
11 | #include <linux/capability.h> | |
12 | #include <linux/miscdevice.h> | |
13 | #include <linux/ratelimit.h> | |
14 | #include <linux/kallsyms.h> | |
15 | #include <linux/rcupdate.h> | |
e9eee03e | 16 | #include <linux/kobject.h> |
14a02530 | 17 | #include <linux/uaccess.h> |
e9eee03e IM |
18 | #include <linux/kdebug.h> |
19 | #include <linux/kernel.h> | |
20 | #include <linux/percpu.h> | |
1da177e4 | 21 | #include <linux/string.h> |
8a25a2fd | 22 | #include <linux/device.h> |
f3c6ea1b | 23 | #include <linux/syscore_ops.h> |
3c079792 | 24 | #include <linux/delay.h> |
8c566ef5 | 25 | #include <linux/ctype.h> |
e9eee03e | 26 | #include <linux/sched.h> |
0d7482e3 | 27 | #include <linux/sysfs.h> |
e9eee03e | 28 | #include <linux/types.h> |
5a0e3ad6 | 29 | #include <linux/slab.h> |
e9eee03e IM |
30 | #include <linux/init.h> |
31 | #include <linux/kmod.h> | |
32 | #include <linux/poll.h> | |
3c079792 | 33 | #include <linux/nmi.h> |
e9eee03e | 34 | #include <linux/cpu.h> |
14a02530 | 35 | #include <linux/smp.h> |
e9eee03e | 36 | #include <linux/fs.h> |
9b1beaf2 | 37 | #include <linux/mm.h> |
5be9ed25 | 38 | #include <linux/debugfs.h> |
b77e70bf | 39 | #include <linux/irq_work.h> |
69c60c88 | 40 | #include <linux/export.h> |
e9eee03e | 41 | |
d88203d1 | 42 | #include <asm/processor.h> |
e9eee03e IM |
43 | #include <asm/mce.h> |
44 | #include <asm/msr.h> | |
1da177e4 | 45 | |
bd19a5e6 | 46 | #include "mce-internal.h" |
711c2e48 | 47 | |
93b62c3c | 48 | static DEFINE_MUTEX(mce_chrdev_read_mutex); |
2aa2b50d | 49 | |
f56e8a07 | 50 | #define rcu_dereference_check_mce(p) \ |
ec8c27e0 | 51 | rcu_dereference_index_check((p), \ |
f56e8a07 | 52 | rcu_read_lock_sched_held() || \ |
93b62c3c | 53 | lockdep_is_held(&mce_chrdev_read_mutex)) |
f56e8a07 | 54 | |
8968f9d3 HS |
55 | #define CREATE_TRACE_POINTS |
56 | #include <trace/events/mce.h> | |
57 | ||
4e5b3e69 | 58 | int mce_disabled __read_mostly; |
04b2b1a4 | 59 | |
e9eee03e | 60 | #define MISC_MCELOG_MINOR 227 |
0d7482e3 | 61 | |
3c079792 AK |
62 | #define SPINUNIT 100 /* 100ns */ |
63 | ||
553f265f AK |
64 | atomic_t mce_entry; |
65 | ||
01ca79f1 AK |
66 | DEFINE_PER_CPU(unsigned, mce_exception_count); |
67 | ||
bd78432c TH |
68 | /* |
69 | * Tolerant levels: | |
70 | * 0: always panic on uncorrected errors, log corrected errors | |
71 | * 1: panic or SIGBUS on uncorrected errors, log corrected errors | |
72 | * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors | |
73 | * 3: never panic or SIGBUS, log all errors (for testing only) | |
74 | */ | |
4e5b3e69 HS |
75 | static int tolerant __read_mostly = 1; |
76 | static int banks __read_mostly; | |
4e5b3e69 HS |
77 | static int rip_msr __read_mostly; |
78 | static int mce_bootlog __read_mostly = -1; | |
79 | static int monarch_timeout __read_mostly = -1; | |
80 | static int mce_panic_timeout __read_mostly; | |
81 | static int mce_dont_log_ce __read_mostly; | |
82 | int mce_cmci_disabled __read_mostly; | |
83 | int mce_ignore_ce __read_mostly; | |
84 | int mce_ser __read_mostly; | |
a98f0dd3 | 85 | |
cebe1820 AK |
86 | struct mce_bank *mce_banks __read_mostly; |
87 | ||
1020bcbc HS |
88 | /* User mode helper program triggered by machine check event */ |
89 | static unsigned long mce_need_notify; | |
90 | static char mce_helper[128]; | |
91 | static char *mce_helper_argv[2] = { mce_helper, NULL }; | |
1da177e4 | 92 | |
93b62c3c HS |
93 | static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait); |
94 | ||
3c079792 AK |
95 | static DEFINE_PER_CPU(struct mce, mces_seen); |
96 | static int cpu_missing; | |
97 | ||
ee031c31 AK |
98 | /* MCA banks polled by the period polling timer for corrected events */ |
99 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { | |
100 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL | |
101 | }; | |
102 | ||
9b1beaf2 AK |
103 | static DEFINE_PER_CPU(struct work_struct, mce_work); |
104 | ||
3653ada5 BP |
105 | /* |
106 | * CPU/chipset specific EDAC code can register a notifier call here to print | |
107 | * MCE errors in a human-readable form. | |
108 | */ | |
109 | ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain); | |
110 | ||
b5f2fa4e AK |
111 | /* Do initial initialization of a struct mce */ |
112 | void mce_setup(struct mce *m) | |
113 | { | |
114 | memset(m, 0, sizeof(struct mce)); | |
d620c67f | 115 | m->cpu = m->extcpu = smp_processor_id(); |
b5f2fa4e | 116 | rdtscll(m->tsc); |
8ee08347 AK |
117 | /* We hope get_seconds stays lockless */ |
118 | m->time = get_seconds(); | |
119 | m->cpuvendor = boot_cpu_data.x86_vendor; | |
120 | m->cpuid = cpuid_eax(1); | |
8ee08347 | 121 | m->socketid = cpu_data(m->extcpu).phys_proc_id; |
8ee08347 AK |
122 | m->apicid = cpu_data(m->extcpu).initial_apicid; |
123 | rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap); | |
b5f2fa4e AK |
124 | } |
125 | ||
ea149b36 AK |
126 | DEFINE_PER_CPU(struct mce, injectm); |
127 | EXPORT_PER_CPU_SYMBOL_GPL(injectm); | |
128 | ||
1da177e4 LT |
129 | /* |
130 | * Lockless MCE logging infrastructure. | |
131 | * This avoids deadlocks on printk locks without having to break locks. Also | |
132 | * separate MCEs from kernel messages to avoid bogus bug reports. | |
133 | */ | |
134 | ||
231fd906 | 135 | static struct mce_log mcelog = { |
f6fb0ac0 AK |
136 | .signature = MCE_LOG_SIGNATURE, |
137 | .len = MCE_LOG_LEN, | |
138 | .recordlen = sizeof(struct mce), | |
d88203d1 | 139 | }; |
1da177e4 LT |
140 | |
141 | void mce_log(struct mce *mce) | |
142 | { | |
143 | unsigned next, entry; | |
f0cb5452 | 144 | int ret = 0; |
e9eee03e | 145 | |
8968f9d3 HS |
146 | /* Emit the trace record: */ |
147 | trace_mce_record(mce); | |
148 | ||
f0cb5452 BP |
149 | ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, mce); |
150 | if (ret == NOTIFY_STOP) | |
151 | return; | |
152 | ||
1da177e4 | 153 | mce->finished = 0; |
7644143c | 154 | wmb(); |
1da177e4 | 155 | for (;;) { |
f56e8a07 | 156 | entry = rcu_dereference_check_mce(mcelog.next); |
673242c1 | 157 | for (;;) { |
696e409d | 158 | |
e9eee03e IM |
159 | /* |
160 | * When the buffer fills up discard new entries. | |
161 | * Assume that the earlier errors are the more | |
162 | * interesting ones: | |
163 | */ | |
673242c1 | 164 | if (entry >= MCE_LOG_LEN) { |
14a02530 HS |
165 | set_bit(MCE_OVERFLOW, |
166 | (unsigned long *)&mcelog.flags); | |
673242c1 AK |
167 | return; |
168 | } | |
e9eee03e | 169 | /* Old left over entry. Skip: */ |
673242c1 AK |
170 | if (mcelog.entry[entry].finished) { |
171 | entry++; | |
172 | continue; | |
173 | } | |
7644143c | 174 | break; |
1da177e4 | 175 | } |
1da177e4 LT |
176 | smp_rmb(); |
177 | next = entry + 1; | |
178 | if (cmpxchg(&mcelog.next, entry, next) == entry) | |
179 | break; | |
180 | } | |
181 | memcpy(mcelog.entry + entry, mce, sizeof(struct mce)); | |
7644143c | 182 | wmb(); |
1da177e4 | 183 | mcelog.entry[entry].finished = 1; |
7644143c | 184 | wmb(); |
1da177e4 | 185 | |
a0189c70 | 186 | mce->finished = 1; |
1020bcbc | 187 | set_bit(0, &mce_need_notify); |
1da177e4 LT |
188 | } |
189 | ||
09371957 BP |
190 | static void drain_mcelog_buffer(void) |
191 | { | |
192 | unsigned int next, i, prev = 0; | |
193 | ||
b11e3d78 | 194 | next = ACCESS_ONCE(mcelog.next); |
09371957 BP |
195 | |
196 | do { | |
197 | struct mce *m; | |
198 | ||
199 | /* drain what was logged during boot */ | |
200 | for (i = prev; i < next; i++) { | |
201 | unsigned long start = jiffies; | |
202 | unsigned retries = 1; | |
203 | ||
204 | m = &mcelog.entry[i]; | |
205 | ||
206 | while (!m->finished) { | |
207 | if (time_after_eq(jiffies, start + 2*retries)) | |
208 | retries++; | |
209 | ||
210 | cpu_relax(); | |
211 | ||
212 | if (!m->finished && retries >= 4) { | |
213 | pr_err("MCE: skipping error being logged currently!\n"); | |
214 | break; | |
215 | } | |
216 | } | |
217 | smp_rmb(); | |
218 | atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m); | |
219 | } | |
220 | ||
221 | memset(mcelog.entry + prev, 0, (next - prev) * sizeof(*m)); | |
222 | prev = next; | |
223 | next = cmpxchg(&mcelog.next, prev, 0); | |
224 | } while (next != prev); | |
225 | } | |
226 | ||
227 | ||
3653ada5 BP |
228 | void mce_register_decode_chain(struct notifier_block *nb) |
229 | { | |
230 | atomic_notifier_chain_register(&x86_mce_decoder_chain, nb); | |
09371957 | 231 | drain_mcelog_buffer(); |
3653ada5 BP |
232 | } |
233 | EXPORT_SYMBOL_GPL(mce_register_decode_chain); | |
234 | ||
235 | void mce_unregister_decode_chain(struct notifier_block *nb) | |
236 | { | |
237 | atomic_notifier_chain_unregister(&x86_mce_decoder_chain, nb); | |
238 | } | |
239 | EXPORT_SYMBOL_GPL(mce_unregister_decode_chain); | |
240 | ||
77e26cca | 241 | static void print_mce(struct mce *m) |
1da177e4 | 242 | { |
dffa4b2f BP |
243 | int ret = 0; |
244 | ||
a2d7b0d4 | 245 | pr_emerg(HW_ERR "CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n", |
d620c67f | 246 | m->extcpu, m->mcgstatus, m->bank, m->status); |
f436f8bb | 247 | |
65ea5b03 | 248 | if (m->ip) { |
a2d7b0d4 | 249 | pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ", |
f436f8bb IM |
250 | !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", |
251 | m->cs, m->ip); | |
252 | ||
1da177e4 | 253 | if (m->cs == __KERNEL_CS) |
65ea5b03 | 254 | print_symbol("{%s}", m->ip); |
f436f8bb | 255 | pr_cont("\n"); |
1da177e4 | 256 | } |
f436f8bb | 257 | |
a2d7b0d4 | 258 | pr_emerg(HW_ERR "TSC %llx ", m->tsc); |
1da177e4 | 259 | if (m->addr) |
f436f8bb | 260 | pr_cont("ADDR %llx ", m->addr); |
1da177e4 | 261 | if (m->misc) |
f436f8bb | 262 | pr_cont("MISC %llx ", m->misc); |
549d042d | 263 | |
f436f8bb | 264 | pr_cont("\n"); |
506ed6b5 AK |
265 | /* |
266 | * Note this output is parsed by external tools and old fields | |
267 | * should not be changed. | |
268 | */ | |
881e23e5 | 269 | pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n", |
506ed6b5 AK |
270 | m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid, |
271 | cpu_data(m->extcpu).microcode); | |
f436f8bb IM |
272 | |
273 | /* | |
274 | * Print out human-readable details about the MCE error, | |
fb253195 | 275 | * (if the CPU has an implementation for that) |
f436f8bb | 276 | */ |
dffa4b2f BP |
277 | ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m); |
278 | if (ret == NOTIFY_STOP) | |
279 | return; | |
280 | ||
281 | pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n"); | |
86503560 AK |
282 | } |
283 | ||
f94b61c2 AK |
284 | #define PANIC_TIMEOUT 5 /* 5 seconds */ |
285 | ||
286 | static atomic_t mce_paniced; | |
287 | ||
bf783f9f HY |
288 | static int fake_panic; |
289 | static atomic_t mce_fake_paniced; | |
290 | ||
f94b61c2 AK |
291 | /* Panic in progress. Enable interrupts and wait for final IPI */ |
292 | static void wait_for_panic(void) | |
293 | { | |
294 | long timeout = PANIC_TIMEOUT*USEC_PER_SEC; | |
f436f8bb | 295 | |
f94b61c2 AK |
296 | preempt_disable(); |
297 | local_irq_enable(); | |
298 | while (timeout-- > 0) | |
299 | udelay(1); | |
29b0f591 AK |
300 | if (panic_timeout == 0) |
301 | panic_timeout = mce_panic_timeout; | |
f94b61c2 AK |
302 | panic("Panicing machine check CPU died"); |
303 | } | |
304 | ||
bd19a5e6 | 305 | static void mce_panic(char *msg, struct mce *final, char *exp) |
d88203d1 | 306 | { |
482908b4 | 307 | int i, apei_err = 0; |
e02e68d3 | 308 | |
bf783f9f HY |
309 | if (!fake_panic) { |
310 | /* | |
311 | * Make sure only one CPU runs in machine check panic | |
312 | */ | |
313 | if (atomic_inc_return(&mce_paniced) > 1) | |
314 | wait_for_panic(); | |
315 | barrier(); | |
f94b61c2 | 316 | |
bf783f9f HY |
317 | bust_spinlocks(1); |
318 | console_verbose(); | |
319 | } else { | |
320 | /* Don't log too much for fake panic */ | |
321 | if (atomic_inc_return(&mce_fake_paniced) > 1) | |
322 | return; | |
323 | } | |
a0189c70 | 324 | /* First print corrected ones that are still unlogged */ |
1da177e4 | 325 | for (i = 0; i < MCE_LOG_LEN; i++) { |
a0189c70 | 326 | struct mce *m = &mcelog.entry[i]; |
77e26cca HS |
327 | if (!(m->status & MCI_STATUS_VAL)) |
328 | continue; | |
482908b4 | 329 | if (!(m->status & MCI_STATUS_UC)) { |
77e26cca | 330 | print_mce(m); |
482908b4 HY |
331 | if (!apei_err) |
332 | apei_err = apei_write_mce(m); | |
333 | } | |
a0189c70 AK |
334 | } |
335 | /* Now print uncorrected but with the final one last */ | |
336 | for (i = 0; i < MCE_LOG_LEN; i++) { | |
337 | struct mce *m = &mcelog.entry[i]; | |
338 | if (!(m->status & MCI_STATUS_VAL)) | |
1da177e4 | 339 | continue; |
77e26cca HS |
340 | if (!(m->status & MCI_STATUS_UC)) |
341 | continue; | |
482908b4 | 342 | if (!final || memcmp(m, final, sizeof(struct mce))) { |
77e26cca | 343 | print_mce(m); |
482908b4 HY |
344 | if (!apei_err) |
345 | apei_err = apei_write_mce(m); | |
346 | } | |
1da177e4 | 347 | } |
482908b4 | 348 | if (final) { |
77e26cca | 349 | print_mce(final); |
482908b4 HY |
350 | if (!apei_err) |
351 | apei_err = apei_write_mce(final); | |
352 | } | |
3c079792 | 353 | if (cpu_missing) |
a2d7b0d4 | 354 | pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n"); |
bd19a5e6 | 355 | if (exp) |
a2d7b0d4 | 356 | pr_emerg(HW_ERR "Machine check: %s\n", exp); |
bf783f9f HY |
357 | if (!fake_panic) { |
358 | if (panic_timeout == 0) | |
359 | panic_timeout = mce_panic_timeout; | |
360 | panic(msg); | |
361 | } else | |
a2d7b0d4 | 362 | pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg); |
d88203d1 | 363 | } |
1da177e4 | 364 | |
ea149b36 AK |
365 | /* Support code for software error injection */ |
366 | ||
367 | static int msr_to_offset(u32 msr) | |
368 | { | |
0a3aee0d | 369 | unsigned bank = __this_cpu_read(injectm.bank); |
f436f8bb | 370 | |
ea149b36 AK |
371 | if (msr == rip_msr) |
372 | return offsetof(struct mce, ip); | |
a2d32bcb | 373 | if (msr == MSR_IA32_MCx_STATUS(bank)) |
ea149b36 | 374 | return offsetof(struct mce, status); |
a2d32bcb | 375 | if (msr == MSR_IA32_MCx_ADDR(bank)) |
ea149b36 | 376 | return offsetof(struct mce, addr); |
a2d32bcb | 377 | if (msr == MSR_IA32_MCx_MISC(bank)) |
ea149b36 AK |
378 | return offsetof(struct mce, misc); |
379 | if (msr == MSR_IA32_MCG_STATUS) | |
380 | return offsetof(struct mce, mcgstatus); | |
381 | return -1; | |
382 | } | |
383 | ||
5f8c1a54 AK |
384 | /* MSR access wrappers used for error injection */ |
385 | static u64 mce_rdmsrl(u32 msr) | |
386 | { | |
387 | u64 v; | |
11868a2d | 388 | |
0a3aee0d | 389 | if (__this_cpu_read(injectm.finished)) { |
ea149b36 | 390 | int offset = msr_to_offset(msr); |
11868a2d | 391 | |
ea149b36 AK |
392 | if (offset < 0) |
393 | return 0; | |
394 | return *(u64 *)((char *)&__get_cpu_var(injectm) + offset); | |
395 | } | |
11868a2d IM |
396 | |
397 | if (rdmsrl_safe(msr, &v)) { | |
398 | WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr); | |
399 | /* | |
400 | * Return zero in case the access faulted. This should | |
401 | * not happen normally but can happen if the CPU does | |
402 | * something weird, or if the code is buggy. | |
403 | */ | |
404 | v = 0; | |
405 | } | |
406 | ||
5f8c1a54 AK |
407 | return v; |
408 | } | |
409 | ||
410 | static void mce_wrmsrl(u32 msr, u64 v) | |
411 | { | |
0a3aee0d | 412 | if (__this_cpu_read(injectm.finished)) { |
ea149b36 | 413 | int offset = msr_to_offset(msr); |
11868a2d | 414 | |
ea149b36 AK |
415 | if (offset >= 0) |
416 | *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v; | |
417 | return; | |
418 | } | |
5f8c1a54 AK |
419 | wrmsrl(msr, v); |
420 | } | |
421 | ||
b8325c5b HS |
422 | /* |
423 | * Collect all global (w.r.t. this processor) status about this machine | |
424 | * check into our "mce" struct so that we can use it later to assess | |
425 | * the severity of the problem as we read per-bank specific details. | |
426 | */ | |
427 | static inline void mce_gather_info(struct mce *m, struct pt_regs *regs) | |
428 | { | |
429 | mce_setup(m); | |
430 | ||
431 | m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); | |
432 | if (regs) { | |
433 | /* | |
434 | * Get the address of the instruction at the time of | |
435 | * the machine check error. | |
436 | */ | |
437 | if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) { | |
438 | m->ip = regs->ip; | |
439 | m->cs = regs->cs; | |
a129a7c8 AK |
440 | |
441 | /* | |
442 | * When in VM86 mode make the cs look like ring 3 | |
443 | * always. This is a lie, but it's better than passing | |
444 | * the additional vm86 bit around everywhere. | |
445 | */ | |
446 | if (v8086_mode(regs)) | |
447 | m->cs |= 3; | |
b8325c5b HS |
448 | } |
449 | /* Use accurate RIP reporting if available. */ | |
450 | if (rip_msr) | |
451 | m->ip = mce_rdmsrl(rip_msr); | |
452 | } | |
453 | } | |
454 | ||
9b1beaf2 AK |
455 | /* |
456 | * Simple lockless ring to communicate PFNs from the exception handler with the | |
457 | * process context work function. This is vastly simplified because there's | |
458 | * only a single reader and a single writer. | |
459 | */ | |
460 | #define MCE_RING_SIZE 16 /* we use one entry less */ | |
461 | ||
462 | struct mce_ring { | |
463 | unsigned short start; | |
464 | unsigned short end; | |
465 | unsigned long ring[MCE_RING_SIZE]; | |
466 | }; | |
467 | static DEFINE_PER_CPU(struct mce_ring, mce_ring); | |
468 | ||
469 | /* Runs with CPU affinity in workqueue */ | |
470 | static int mce_ring_empty(void) | |
471 | { | |
472 | struct mce_ring *r = &__get_cpu_var(mce_ring); | |
473 | ||
474 | return r->start == r->end; | |
475 | } | |
476 | ||
477 | static int mce_ring_get(unsigned long *pfn) | |
478 | { | |
479 | struct mce_ring *r; | |
480 | int ret = 0; | |
481 | ||
482 | *pfn = 0; | |
483 | get_cpu(); | |
484 | r = &__get_cpu_var(mce_ring); | |
485 | if (r->start == r->end) | |
486 | goto out; | |
487 | *pfn = r->ring[r->start]; | |
488 | r->start = (r->start + 1) % MCE_RING_SIZE; | |
489 | ret = 1; | |
490 | out: | |
491 | put_cpu(); | |
492 | return ret; | |
493 | } | |
494 | ||
495 | /* Always runs in MCE context with preempt off */ | |
496 | static int mce_ring_add(unsigned long pfn) | |
497 | { | |
498 | struct mce_ring *r = &__get_cpu_var(mce_ring); | |
499 | unsigned next; | |
500 | ||
501 | next = (r->end + 1) % MCE_RING_SIZE; | |
502 | if (next == r->start) | |
503 | return -1; | |
504 | r->ring[r->end] = pfn; | |
505 | wmb(); | |
506 | r->end = next; | |
507 | return 0; | |
508 | } | |
509 | ||
88ccbedd | 510 | int mce_available(struct cpuinfo_x86 *c) |
1da177e4 | 511 | { |
04b2b1a4 | 512 | if (mce_disabled) |
5b4408fd | 513 | return 0; |
3d1712c9 | 514 | return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); |
1da177e4 LT |
515 | } |
516 | ||
9b1beaf2 AK |
517 | static void mce_schedule_work(void) |
518 | { | |
519 | if (!mce_ring_empty()) { | |
520 | struct work_struct *work = &__get_cpu_var(mce_work); | |
521 | if (!work_pending(work)) | |
522 | schedule_work(work); | |
523 | } | |
524 | } | |
525 | ||
b77e70bf HS |
526 | DEFINE_PER_CPU(struct irq_work, mce_irq_work); |
527 | ||
528 | static void mce_irq_work_cb(struct irq_work *entry) | |
ccc3c319 | 529 | { |
9ff36ee9 | 530 | mce_notify_irq(); |
9b1beaf2 | 531 | mce_schedule_work(); |
ccc3c319 | 532 | } |
ccc3c319 AK |
533 | |
534 | static void mce_report_event(struct pt_regs *regs) | |
535 | { | |
536 | if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) { | |
9ff36ee9 | 537 | mce_notify_irq(); |
9b1beaf2 AK |
538 | /* |
539 | * Triggering the work queue here is just an insurance | |
540 | * policy in case the syscall exit notify handler | |
541 | * doesn't run soon enough or ends up running on the | |
542 | * wrong CPU (can happen when audit sleeps) | |
543 | */ | |
544 | mce_schedule_work(); | |
ccc3c319 AK |
545 | return; |
546 | } | |
547 | ||
b77e70bf | 548 | irq_work_queue(&__get_cpu_var(mce_irq_work)); |
ccc3c319 AK |
549 | } |
550 | ||
85f92694 TL |
551 | /* |
552 | * Read ADDR and MISC registers. | |
553 | */ | |
554 | static void mce_read_aux(struct mce *m, int i) | |
555 | { | |
556 | if (m->status & MCI_STATUS_MISCV) | |
557 | m->misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i)); | |
558 | if (m->status & MCI_STATUS_ADDRV) { | |
559 | m->addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i)); | |
560 | ||
561 | /* | |
562 | * Mask the reported address by the reported granularity. | |
563 | */ | |
564 | if (mce_ser && (m->status & MCI_STATUS_MISCV)) { | |
565 | u8 shift = MCI_MISC_ADDR_LSB(m->misc); | |
566 | m->addr >>= shift; | |
567 | m->addr <<= shift; | |
568 | } | |
569 | } | |
570 | } | |
571 | ||
ca84f696 AK |
572 | DEFINE_PER_CPU(unsigned, mce_poll_count); |
573 | ||
d88203d1 | 574 | /* |
b79109c3 AK |
575 | * Poll for corrected events or events that happened before reset. |
576 | * Those are just logged through /dev/mcelog. | |
577 | * | |
578 | * This is executed in standard interrupt context. | |
ed7290d0 AK |
579 | * |
580 | * Note: spec recommends to panic for fatal unsignalled | |
581 | * errors here. However this would be quite problematic -- | |
582 | * we would need to reimplement the Monarch handling and | |
583 | * it would mess up the exclusion between exception handler | |
584 | * and poll hander -- * so we skip this for now. | |
585 | * These cases should not happen anyways, or only when the CPU | |
586 | * is already totally * confused. In this case it's likely it will | |
587 | * not fully execute the machine check handler either. | |
b79109c3 | 588 | */ |
ee031c31 | 589 | void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) |
b79109c3 AK |
590 | { |
591 | struct mce m; | |
592 | int i; | |
593 | ||
c6ae41e7 | 594 | this_cpu_inc(mce_poll_count); |
ca84f696 | 595 | |
b8325c5b | 596 | mce_gather_info(&m, NULL); |
b79109c3 | 597 | |
b79109c3 | 598 | for (i = 0; i < banks; i++) { |
cebe1820 | 599 | if (!mce_banks[i].ctl || !test_bit(i, *b)) |
b79109c3 AK |
600 | continue; |
601 | ||
602 | m.misc = 0; | |
603 | m.addr = 0; | |
604 | m.bank = i; | |
605 | m.tsc = 0; | |
606 | ||
607 | barrier(); | |
a2d32bcb | 608 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
b79109c3 AK |
609 | if (!(m.status & MCI_STATUS_VAL)) |
610 | continue; | |
611 | ||
612 | /* | |
ed7290d0 AK |
613 | * Uncorrected or signalled events are handled by the exception |
614 | * handler when it is enabled, so don't process those here. | |
b79109c3 AK |
615 | * |
616 | * TBD do the same check for MCI_STATUS_EN here? | |
617 | */ | |
ed7290d0 AK |
618 | if (!(flags & MCP_UC) && |
619 | (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC))) | |
b79109c3 AK |
620 | continue; |
621 | ||
85f92694 | 622 | mce_read_aux(&m, i); |
b79109c3 AK |
623 | |
624 | if (!(flags & MCP_TIMESTAMP)) | |
625 | m.tsc = 0; | |
626 | /* | |
627 | * Don't get the IP here because it's unlikely to | |
628 | * have anything to do with the actual error location. | |
629 | */ | |
f0cb5452 | 630 | if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) |
5679af4c | 631 | mce_log(&m); |
b79109c3 AK |
632 | |
633 | /* | |
634 | * Clear state for this bank. | |
635 | */ | |
a2d32bcb | 636 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
b79109c3 AK |
637 | } |
638 | ||
639 | /* | |
640 | * Don't clear MCG_STATUS here because it's only defined for | |
641 | * exceptions. | |
642 | */ | |
88921be3 AK |
643 | |
644 | sync_core(); | |
b79109c3 | 645 | } |
ea149b36 | 646 | EXPORT_SYMBOL_GPL(machine_check_poll); |
b79109c3 | 647 | |
bd19a5e6 AK |
648 | /* |
649 | * Do a quick check if any of the events requires a panic. | |
650 | * This decides if we keep the events around or clear them. | |
651 | */ | |
95022b8c | 652 | static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp) |
bd19a5e6 | 653 | { |
95022b8c | 654 | int i, ret = 0; |
bd19a5e6 AK |
655 | |
656 | for (i = 0; i < banks; i++) { | |
a2d32bcb | 657 | m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
95022b8c TL |
658 | if (m->status & MCI_STATUS_VAL) |
659 | __set_bit(i, validp); | |
bd19a5e6 | 660 | if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY) |
95022b8c | 661 | ret = 1; |
bd19a5e6 | 662 | } |
95022b8c | 663 | return ret; |
bd19a5e6 AK |
664 | } |
665 | ||
3c079792 AK |
666 | /* |
667 | * Variable to establish order between CPUs while scanning. | |
668 | * Each CPU spins initially until executing is equal its number. | |
669 | */ | |
670 | static atomic_t mce_executing; | |
671 | ||
672 | /* | |
673 | * Defines order of CPUs on entry. First CPU becomes Monarch. | |
674 | */ | |
675 | static atomic_t mce_callin; | |
676 | ||
677 | /* | |
678 | * Check if a timeout waiting for other CPUs happened. | |
679 | */ | |
680 | static int mce_timed_out(u64 *t) | |
681 | { | |
682 | /* | |
683 | * The others already did panic for some reason. | |
684 | * Bail out like in a timeout. | |
685 | * rmb() to tell the compiler that system_state | |
686 | * might have been modified by someone else. | |
687 | */ | |
688 | rmb(); | |
689 | if (atomic_read(&mce_paniced)) | |
690 | wait_for_panic(); | |
691 | if (!monarch_timeout) | |
692 | goto out; | |
693 | if ((s64)*t < SPINUNIT) { | |
694 | /* CHECKME: Make panic default for 1 too? */ | |
695 | if (tolerant < 1) | |
696 | mce_panic("Timeout synchronizing machine check over CPUs", | |
697 | NULL, NULL); | |
698 | cpu_missing = 1; | |
699 | return 1; | |
700 | } | |
701 | *t -= SPINUNIT; | |
702 | out: | |
703 | touch_nmi_watchdog(); | |
704 | return 0; | |
705 | } | |
706 | ||
707 | /* | |
708 | * The Monarch's reign. The Monarch is the CPU who entered | |
709 | * the machine check handler first. It waits for the others to | |
710 | * raise the exception too and then grades them. When any | |
711 | * error is fatal panic. Only then let the others continue. | |
712 | * | |
713 | * The other CPUs entering the MCE handler will be controlled by the | |
714 | * Monarch. They are called Subjects. | |
715 | * | |
716 | * This way we prevent any potential data corruption in a unrecoverable case | |
717 | * and also makes sure always all CPU's errors are examined. | |
718 | * | |
680b6cfd | 719 | * Also this detects the case of a machine check event coming from outer |
3c079792 AK |
720 | * space (not detected by any CPUs) In this case some external agent wants |
721 | * us to shut down, so panic too. | |
722 | * | |
723 | * The other CPUs might still decide to panic if the handler happens | |
724 | * in a unrecoverable place, but in this case the system is in a semi-stable | |
725 | * state and won't corrupt anything by itself. It's ok to let the others | |
726 | * continue for a bit first. | |
727 | * | |
728 | * All the spin loops have timeouts; when a timeout happens a CPU | |
729 | * typically elects itself to be Monarch. | |
730 | */ | |
731 | static void mce_reign(void) | |
732 | { | |
733 | int cpu; | |
734 | struct mce *m = NULL; | |
735 | int global_worst = 0; | |
736 | char *msg = NULL; | |
737 | char *nmsg = NULL; | |
738 | ||
739 | /* | |
740 | * This CPU is the Monarch and the other CPUs have run | |
741 | * through their handlers. | |
742 | * Grade the severity of the errors of all the CPUs. | |
743 | */ | |
744 | for_each_possible_cpu(cpu) { | |
745 | int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant, | |
746 | &nmsg); | |
747 | if (severity > global_worst) { | |
748 | msg = nmsg; | |
749 | global_worst = severity; | |
750 | m = &per_cpu(mces_seen, cpu); | |
751 | } | |
752 | } | |
753 | ||
754 | /* | |
755 | * Cannot recover? Panic here then. | |
756 | * This dumps all the mces in the log buffer and stops the | |
757 | * other CPUs. | |
758 | */ | |
759 | if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3) | |
ac960375 | 760 | mce_panic("Fatal Machine check", m, msg); |
3c079792 AK |
761 | |
762 | /* | |
763 | * For UC somewhere we let the CPU who detects it handle it. | |
764 | * Also must let continue the others, otherwise the handling | |
765 | * CPU could deadlock on a lock. | |
766 | */ | |
767 | ||
768 | /* | |
769 | * No machine check event found. Must be some external | |
770 | * source or one CPU is hung. Panic. | |
771 | */ | |
680b6cfd | 772 | if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3) |
3c079792 AK |
773 | mce_panic("Machine check from unknown source", NULL, NULL); |
774 | ||
775 | /* | |
776 | * Now clear all the mces_seen so that they don't reappear on | |
777 | * the next mce. | |
778 | */ | |
779 | for_each_possible_cpu(cpu) | |
780 | memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce)); | |
781 | } | |
782 | ||
783 | static atomic_t global_nwo; | |
784 | ||
785 | /* | |
786 | * Start of Monarch synchronization. This waits until all CPUs have | |
787 | * entered the exception handler and then determines if any of them | |
788 | * saw a fatal event that requires panic. Then it executes them | |
789 | * in the entry order. | |
790 | * TBD double check parallel CPU hotunplug | |
791 | */ | |
7fb06fc9 | 792 | static int mce_start(int *no_way_out) |
3c079792 | 793 | { |
7fb06fc9 | 794 | int order; |
3c079792 AK |
795 | int cpus = num_online_cpus(); |
796 | u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC; | |
797 | ||
7fb06fc9 HS |
798 | if (!timeout) |
799 | return -1; | |
3c079792 | 800 | |
7fb06fc9 | 801 | atomic_add(*no_way_out, &global_nwo); |
184e1fdf HY |
802 | /* |
803 | * global_nwo should be updated before mce_callin | |
804 | */ | |
805 | smp_wmb(); | |
a95436e4 | 806 | order = atomic_inc_return(&mce_callin); |
3c079792 AK |
807 | |
808 | /* | |
809 | * Wait for everyone. | |
810 | */ | |
811 | while (atomic_read(&mce_callin) != cpus) { | |
812 | if (mce_timed_out(&timeout)) { | |
813 | atomic_set(&global_nwo, 0); | |
7fb06fc9 | 814 | return -1; |
3c079792 AK |
815 | } |
816 | ndelay(SPINUNIT); | |
817 | } | |
818 | ||
184e1fdf HY |
819 | /* |
820 | * mce_callin should be read before global_nwo | |
821 | */ | |
822 | smp_rmb(); | |
3c079792 | 823 | |
7fb06fc9 HS |
824 | if (order == 1) { |
825 | /* | |
826 | * Monarch: Starts executing now, the others wait. | |
827 | */ | |
3c079792 | 828 | atomic_set(&mce_executing, 1); |
7fb06fc9 HS |
829 | } else { |
830 | /* | |
831 | * Subject: Now start the scanning loop one by one in | |
832 | * the original callin order. | |
833 | * This way when there are any shared banks it will be | |
834 | * only seen by one CPU before cleared, avoiding duplicates. | |
835 | */ | |
836 | while (atomic_read(&mce_executing) < order) { | |
837 | if (mce_timed_out(&timeout)) { | |
838 | atomic_set(&global_nwo, 0); | |
839 | return -1; | |
840 | } | |
841 | ndelay(SPINUNIT); | |
842 | } | |
3c079792 AK |
843 | } |
844 | ||
845 | /* | |
7fb06fc9 | 846 | * Cache the global no_way_out state. |
3c079792 | 847 | */ |
7fb06fc9 HS |
848 | *no_way_out = atomic_read(&global_nwo); |
849 | ||
850 | return order; | |
3c079792 AK |
851 | } |
852 | ||
853 | /* | |
854 | * Synchronize between CPUs after main scanning loop. | |
855 | * This invokes the bulk of the Monarch processing. | |
856 | */ | |
857 | static int mce_end(int order) | |
858 | { | |
859 | int ret = -1; | |
860 | u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC; | |
861 | ||
862 | if (!timeout) | |
863 | goto reset; | |
864 | if (order < 0) | |
865 | goto reset; | |
866 | ||
867 | /* | |
868 | * Allow others to run. | |
869 | */ | |
870 | atomic_inc(&mce_executing); | |
871 | ||
872 | if (order == 1) { | |
873 | /* CHECKME: Can this race with a parallel hotplug? */ | |
874 | int cpus = num_online_cpus(); | |
875 | ||
876 | /* | |
877 | * Monarch: Wait for everyone to go through their scanning | |
878 | * loops. | |
879 | */ | |
880 | while (atomic_read(&mce_executing) <= cpus) { | |
881 | if (mce_timed_out(&timeout)) | |
882 | goto reset; | |
883 | ndelay(SPINUNIT); | |
884 | } | |
885 | ||
886 | mce_reign(); | |
887 | barrier(); | |
888 | ret = 0; | |
889 | } else { | |
890 | /* | |
891 | * Subject: Wait for Monarch to finish. | |
892 | */ | |
893 | while (atomic_read(&mce_executing) != 0) { | |
894 | if (mce_timed_out(&timeout)) | |
895 | goto reset; | |
896 | ndelay(SPINUNIT); | |
897 | } | |
898 | ||
899 | /* | |
900 | * Don't reset anything. That's done by the Monarch. | |
901 | */ | |
902 | return 0; | |
903 | } | |
904 | ||
905 | /* | |
906 | * Reset all global state. | |
907 | */ | |
908 | reset: | |
909 | atomic_set(&global_nwo, 0); | |
910 | atomic_set(&mce_callin, 0); | |
911 | barrier(); | |
912 | ||
913 | /* | |
914 | * Let others run again. | |
915 | */ | |
916 | atomic_set(&mce_executing, 0); | |
917 | return ret; | |
918 | } | |
919 | ||
9b1beaf2 AK |
920 | /* |
921 | * Check if the address reported by the CPU is in a format we can parse. | |
922 | * It would be possible to add code for most other cases, but all would | |
923 | * be somewhat complicated (e.g. segment offset would require an instruction | |
0d2eb44f | 924 | * parser). So only support physical addresses up to page granuality for now. |
9b1beaf2 AK |
925 | */ |
926 | static int mce_usable_address(struct mce *m) | |
927 | { | |
928 | if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV)) | |
929 | return 0; | |
2b90e77e | 930 | if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT) |
9b1beaf2 | 931 | return 0; |
2b90e77e | 932 | if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS) |
9b1beaf2 AK |
933 | return 0; |
934 | return 1; | |
935 | } | |
936 | ||
3c079792 AK |
937 | static void mce_clear_state(unsigned long *toclear) |
938 | { | |
939 | int i; | |
940 | ||
941 | for (i = 0; i < banks; i++) { | |
942 | if (test_bit(i, toclear)) | |
a2d32bcb | 943 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
3c079792 AK |
944 | } |
945 | } | |
946 | ||
af104e39 TL |
947 | /* |
948 | * Need to save faulting physical address associated with a process | |
949 | * in the machine check handler some place where we can grab it back | |
950 | * later in mce_notify_process() | |
951 | */ | |
952 | #define MCE_INFO_MAX 16 | |
953 | ||
954 | struct mce_info { | |
955 | atomic_t inuse; | |
956 | struct task_struct *t; | |
957 | __u64 paddr; | |
dad1743e | 958 | int restartable; |
af104e39 TL |
959 | } mce_info[MCE_INFO_MAX]; |
960 | ||
dad1743e | 961 | static void mce_save_info(__u64 addr, int c) |
af104e39 TL |
962 | { |
963 | struct mce_info *mi; | |
964 | ||
965 | for (mi = mce_info; mi < &mce_info[MCE_INFO_MAX]; mi++) { | |
966 | if (atomic_cmpxchg(&mi->inuse, 0, 1) == 0) { | |
967 | mi->t = current; | |
968 | mi->paddr = addr; | |
dad1743e | 969 | mi->restartable = c; |
af104e39 TL |
970 | return; |
971 | } | |
972 | } | |
973 | ||
974 | mce_panic("Too many concurrent recoverable errors", NULL, NULL); | |
975 | } | |
976 | ||
977 | static struct mce_info *mce_find_info(void) | |
978 | { | |
979 | struct mce_info *mi; | |
980 | ||
981 | for (mi = mce_info; mi < &mce_info[MCE_INFO_MAX]; mi++) | |
982 | if (atomic_read(&mi->inuse) && mi->t == current) | |
983 | return mi; | |
984 | return NULL; | |
985 | } | |
986 | ||
987 | static void mce_clear_info(struct mce_info *mi) | |
988 | { | |
989 | atomic_set(&mi->inuse, 0); | |
990 | } | |
991 | ||
b79109c3 AK |
992 | /* |
993 | * The actual machine check handler. This only handles real | |
994 | * exceptions when something got corrupted coming in through int 18. | |
995 | * | |
996 | * This is executed in NMI context not subject to normal locking rules. This | |
997 | * implies that most kernel services cannot be safely used. Don't even | |
998 | * think about putting a printk in there! | |
3c079792 AK |
999 | * |
1000 | * On Intel systems this is entered on all CPUs in parallel through | |
1001 | * MCE broadcast. However some CPUs might be broken beyond repair, | |
1002 | * so be always careful when synchronizing with others. | |
1da177e4 | 1003 | */ |
e9eee03e | 1004 | void do_machine_check(struct pt_regs *regs, long error_code) |
1da177e4 | 1005 | { |
3c079792 | 1006 | struct mce m, *final; |
1da177e4 | 1007 | int i; |
3c079792 AK |
1008 | int worst = 0; |
1009 | int severity; | |
1010 | /* | |
1011 | * Establish sequential order between the CPUs entering the machine | |
1012 | * check handler. | |
1013 | */ | |
7fb06fc9 | 1014 | int order; |
bd78432c TH |
1015 | /* |
1016 | * If no_way_out gets set, there is no safe way to recover from this | |
1017 | * MCE. If tolerant is cranked up, we'll try anyway. | |
1018 | */ | |
1019 | int no_way_out = 0; | |
1020 | /* | |
1021 | * If kill_it gets set, there might be a way to recover from this | |
1022 | * error. | |
1023 | */ | |
1024 | int kill_it = 0; | |
b79109c3 | 1025 | DECLARE_BITMAP(toclear, MAX_NR_BANKS); |
95022b8c | 1026 | DECLARE_BITMAP(valid_banks, MAX_NR_BANKS); |
bd19a5e6 | 1027 | char *msg = "Unknown"; |
1da177e4 | 1028 | |
553f265f AK |
1029 | atomic_inc(&mce_entry); |
1030 | ||
c6ae41e7 | 1031 | this_cpu_inc(mce_exception_count); |
01ca79f1 | 1032 | |
b79109c3 | 1033 | if (!banks) |
32561696 | 1034 | goto out; |
1da177e4 | 1035 | |
b8325c5b | 1036 | mce_gather_info(&m, regs); |
b5f2fa4e | 1037 | |
3c079792 AK |
1038 | final = &__get_cpu_var(mces_seen); |
1039 | *final = m; | |
1040 | ||
95022b8c TL |
1041 | memset(valid_banks, 0, sizeof(valid_banks)); |
1042 | no_way_out = mce_no_way_out(&m, &msg, valid_banks); | |
680b6cfd | 1043 | |
1da177e4 LT |
1044 | barrier(); |
1045 | ||
ed7290d0 | 1046 | /* |
a8c321fb TL |
1047 | * When no restart IP might need to kill or panic. |
1048 | * Assume the worst for now, but if we find the | |
1049 | * severity is MCE_AR_SEVERITY we have other options. | |
ed7290d0 AK |
1050 | */ |
1051 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) | |
1052 | kill_it = 1; | |
1053 | ||
3c079792 AK |
1054 | /* |
1055 | * Go through all the banks in exclusion of the other CPUs. | |
1056 | * This way we don't report duplicated events on shared banks | |
1057 | * because the first one to see it will clear it. | |
1058 | */ | |
7fb06fc9 | 1059 | order = mce_start(&no_way_out); |
1da177e4 | 1060 | for (i = 0; i < banks; i++) { |
b79109c3 | 1061 | __clear_bit(i, toclear); |
95022b8c TL |
1062 | if (!test_bit(i, valid_banks)) |
1063 | continue; | |
cebe1820 | 1064 | if (!mce_banks[i].ctl) |
1da177e4 | 1065 | continue; |
d88203d1 TG |
1066 | |
1067 | m.misc = 0; | |
1da177e4 LT |
1068 | m.addr = 0; |
1069 | m.bank = i; | |
1da177e4 | 1070 | |
a2d32bcb | 1071 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
1da177e4 LT |
1072 | if ((m.status & MCI_STATUS_VAL) == 0) |
1073 | continue; | |
1074 | ||
b79109c3 | 1075 | /* |
ed7290d0 AK |
1076 | * Non uncorrected or non signaled errors are handled by |
1077 | * machine_check_poll. Leave them alone, unless this panics. | |
b79109c3 | 1078 | */ |
ed7290d0 AK |
1079 | if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) && |
1080 | !no_way_out) | |
b79109c3 AK |
1081 | continue; |
1082 | ||
1083 | /* | |
1084 | * Set taint even when machine check was not enabled. | |
1085 | */ | |
1086 | add_taint(TAINT_MACHINE_CHECK); | |
1087 | ||
ed7290d0 | 1088 | severity = mce_severity(&m, tolerant, NULL); |
b79109c3 | 1089 | |
ed7290d0 AK |
1090 | /* |
1091 | * When machine check was for corrected handler don't touch, | |
1092 | * unless we're panicing. | |
1093 | */ | |
1094 | if (severity == MCE_KEEP_SEVERITY && !no_way_out) | |
1095 | continue; | |
1096 | __set_bit(i, toclear); | |
1097 | if (severity == MCE_NO_SEVERITY) { | |
b79109c3 AK |
1098 | /* |
1099 | * Machine check event was not enabled. Clear, but | |
1100 | * ignore. | |
1101 | */ | |
1102 | continue; | |
1da177e4 LT |
1103 | } |
1104 | ||
85f92694 | 1105 | mce_read_aux(&m, i); |
1da177e4 | 1106 | |
9b1beaf2 AK |
1107 | /* |
1108 | * Action optional error. Queue address for later processing. | |
1109 | * When the ring overflows we just ignore the AO error. | |
1110 | * RED-PEN add some logging mechanism when | |
1111 | * usable_address or mce_add_ring fails. | |
1112 | * RED-PEN don't ignore overflow for tolerant == 0 | |
1113 | */ | |
1114 | if (severity == MCE_AO_SEVERITY && mce_usable_address(&m)) | |
1115 | mce_ring_add(m.addr >> PAGE_SHIFT); | |
1116 | ||
b79109c3 | 1117 | mce_log(&m); |
1da177e4 | 1118 | |
3c079792 AK |
1119 | if (severity > worst) { |
1120 | *final = m; | |
1121 | worst = severity; | |
1da177e4 | 1122 | } |
1da177e4 LT |
1123 | } |
1124 | ||
a8c321fb TL |
1125 | /* mce_clear_state will clear *final, save locally for use later */ |
1126 | m = *final; | |
1127 | ||
3c079792 AK |
1128 | if (!no_way_out) |
1129 | mce_clear_state(toclear); | |
1130 | ||
e9eee03e | 1131 | /* |
3c079792 AK |
1132 | * Do most of the synchronization with other CPUs. |
1133 | * When there's any problem use only local no_way_out state. | |
e9eee03e | 1134 | */ |
3c079792 AK |
1135 | if (mce_end(order) < 0) |
1136 | no_way_out = worst >= MCE_PANIC_SEVERITY; | |
bd78432c TH |
1137 | |
1138 | /* | |
a8c321fb TL |
1139 | * At insane "tolerant" levels we take no action. Otherwise |
1140 | * we only die if we have no other choice. For less serious | |
1141 | * issues we try to recover, or limit damage to the current | |
1142 | * process. | |
bd78432c | 1143 | */ |
a8c321fb TL |
1144 | if (tolerant < 3) { |
1145 | if (no_way_out) | |
1146 | mce_panic("Fatal machine check on current CPU", &m, msg); | |
1147 | if (worst == MCE_AR_SEVERITY) { | |
1148 | /* schedule action before return to userland */ | |
dad1743e | 1149 | mce_save_info(m.addr, m.mcgstatus & MCG_STATUS_RIPV); |
a8c321fb TL |
1150 | set_thread_flag(TIF_MCE_NOTIFY); |
1151 | } else if (kill_it) { | |
1152 | force_sig(SIGBUS, current); | |
1153 | } | |
1154 | } | |
e02e68d3 | 1155 | |
3c079792 AK |
1156 | if (worst > 0) |
1157 | mce_report_event(regs); | |
5f8c1a54 | 1158 | mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); |
32561696 | 1159 | out: |
553f265f | 1160 | atomic_dec(&mce_entry); |
88921be3 | 1161 | sync_core(); |
1da177e4 | 1162 | } |
ea149b36 | 1163 | EXPORT_SYMBOL_GPL(do_machine_check); |
1da177e4 | 1164 | |
cd42f4a3 TL |
1165 | #ifndef CONFIG_MEMORY_FAILURE |
1166 | int memory_failure(unsigned long pfn, int vector, int flags) | |
9b1beaf2 | 1167 | { |
a8c321fb TL |
1168 | /* mce_severity() should not hand us an ACTION_REQUIRED error */ |
1169 | BUG_ON(flags & MF_ACTION_REQUIRED); | |
cd42f4a3 TL |
1170 | printk(KERN_ERR "Uncorrected memory error in page 0x%lx ignored\n" |
1171 | "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n", pfn); | |
1172 | ||
1173 | return 0; | |
9b1beaf2 | 1174 | } |
cd42f4a3 | 1175 | #endif |
9b1beaf2 AK |
1176 | |
1177 | /* | |
a8c321fb TL |
1178 | * Called in process context that interrupted by MCE and marked with |
1179 | * TIF_MCE_NOTIFY, just before returning to erroneous userland. | |
1180 | * This code is allowed to sleep. | |
1181 | * Attempt possible recovery such as calling the high level VM handler to | |
1182 | * process any corrupted pages, and kill/signal current process if required. | |
1183 | * Action required errors are handled here. | |
9b1beaf2 AK |
1184 | */ |
1185 | void mce_notify_process(void) | |
1186 | { | |
1187 | unsigned long pfn; | |
a8c321fb TL |
1188 | struct mce_info *mi = mce_find_info(); |
1189 | ||
1190 | if (!mi) | |
1191 | mce_panic("Lost physical address for unconsumed uncorrectable error", NULL, NULL); | |
1192 | pfn = mi->paddr >> PAGE_SHIFT; | |
1193 | ||
1194 | clear_thread_flag(TIF_MCE_NOTIFY); | |
1195 | ||
1196 | pr_err("Uncorrected hardware memory error in user-access at %llx", | |
1197 | mi->paddr); | |
dad1743e TL |
1198 | /* |
1199 | * We must call memory_failure() here even if the current process is | |
1200 | * doomed. We still need to mark the page as poisoned and alert any | |
1201 | * other users of the page. | |
1202 | */ | |
1203 | if (memory_failure(pfn, MCE_VECTOR, MF_ACTION_REQUIRED) < 0 || | |
1204 | mi->restartable == 0) { | |
a8c321fb TL |
1205 | pr_err("Memory error not recovered"); |
1206 | force_sig(SIGBUS, current); | |
1207 | } | |
1208 | mce_clear_info(mi); | |
9b1beaf2 AK |
1209 | } |
1210 | ||
a8c321fb TL |
1211 | /* |
1212 | * Action optional processing happens here (picking up | |
1213 | * from the list of faulting pages that do_machine_check() | |
1214 | * placed into the "ring"). | |
1215 | */ | |
9b1beaf2 AK |
1216 | static void mce_process_work(struct work_struct *dummy) |
1217 | { | |
a8c321fb TL |
1218 | unsigned long pfn; |
1219 | ||
1220 | while (mce_ring_get(&pfn)) | |
1221 | memory_failure(pfn, MCE_VECTOR, 0); | |
9b1beaf2 AK |
1222 | } |
1223 | ||
15d5f839 DZ |
1224 | #ifdef CONFIG_X86_MCE_INTEL |
1225 | /*** | |
1226 | * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog | |
676b1855 | 1227 | * @cpu: The CPU on which the event occurred. |
15d5f839 DZ |
1228 | * @status: Event status information |
1229 | * | |
1230 | * This function should be called by the thermal interrupt after the | |
1231 | * event has been processed and the decision was made to log the event | |
1232 | * further. | |
1233 | * | |
1234 | * The status parameter will be saved to the 'status' field of 'struct mce' | |
1235 | * and historically has been the register value of the | |
1236 | * MSR_IA32_THERMAL_STATUS (Intel) msr. | |
1237 | */ | |
b5f2fa4e | 1238 | void mce_log_therm_throt_event(__u64 status) |
15d5f839 DZ |
1239 | { |
1240 | struct mce m; | |
1241 | ||
b5f2fa4e | 1242 | mce_setup(&m); |
15d5f839 DZ |
1243 | m.bank = MCE_THERMAL_BANK; |
1244 | m.status = status; | |
15d5f839 DZ |
1245 | mce_log(&m); |
1246 | } | |
1247 | #endif /* CONFIG_X86_MCE_INTEL */ | |
1248 | ||
1da177e4 | 1249 | /* |
8a336b0a TH |
1250 | * Periodic polling timer for "silent" machine check errors. If the |
1251 | * poller finds an MCE, poll 2x faster. When the poller finds no more | |
1252 | * errors, poll 2x slower (up to check_interval seconds). | |
1da177e4 | 1253 | */ |
82f7af09 | 1254 | static unsigned long check_interval = 5 * 60; /* 5 minutes */ |
e9eee03e | 1255 | |
82f7af09 | 1256 | static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */ |
52d168e2 | 1257 | static DEFINE_PER_CPU(struct timer_list, mce_timer); |
1da177e4 | 1258 | |
82f7af09 | 1259 | static void mce_timer_fn(unsigned long data) |
1da177e4 | 1260 | { |
82f7af09 TG |
1261 | struct timer_list *t = &__get_cpu_var(mce_timer); |
1262 | unsigned long iv; | |
52d168e2 AK |
1263 | |
1264 | WARN_ON(smp_processor_id() != data); | |
1265 | ||
7b543a53 | 1266 | if (mce_available(__this_cpu_ptr(&cpu_info))) { |
ee031c31 AK |
1267 | machine_check_poll(MCP_TIMESTAMP, |
1268 | &__get_cpu_var(mce_poll_banks)); | |
e9eee03e | 1269 | } |
1da177e4 LT |
1270 | |
1271 | /* | |
e02e68d3 TH |
1272 | * Alert userspace if needed. If we logged an MCE, reduce the |
1273 | * polling interval, otherwise increase the polling interval. | |
1da177e4 | 1274 | */ |
82f7af09 | 1275 | iv = __this_cpu_read(mce_next_interval); |
9ff36ee9 | 1276 | if (mce_notify_irq()) |
82f7af09 | 1277 | iv = max(iv, (unsigned long) HZ/100); |
14a02530 | 1278 | else |
82f7af09 TG |
1279 | iv = min(iv * 2, round_jiffies_relative(check_interval * HZ)); |
1280 | __this_cpu_write(mce_next_interval, iv); | |
e02e68d3 | 1281 | |
82f7af09 | 1282 | t->expires = jiffies + iv; |
5be6066a | 1283 | add_timer_on(t, smp_processor_id()); |
e02e68d3 TH |
1284 | } |
1285 | ||
9aaef96f HS |
1286 | /* Must not be called in IRQ context where del_timer_sync() can deadlock */ |
1287 | static void mce_timer_delete_all(void) | |
1288 | { | |
1289 | int cpu; | |
1290 | ||
1291 | for_each_online_cpu(cpu) | |
1292 | del_timer_sync(&per_cpu(mce_timer, cpu)); | |
1293 | } | |
1294 | ||
9bd98405 AK |
1295 | static void mce_do_trigger(struct work_struct *work) |
1296 | { | |
1020bcbc | 1297 | call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT); |
9bd98405 AK |
1298 | } |
1299 | ||
1300 | static DECLARE_WORK(mce_trigger_work, mce_do_trigger); | |
1301 | ||
e02e68d3 | 1302 | /* |
9bd98405 AK |
1303 | * Notify the user(s) about new machine check events. |
1304 | * Can be called from interrupt context, but not from machine check/NMI | |
1305 | * context. | |
e02e68d3 | 1306 | */ |
9ff36ee9 | 1307 | int mce_notify_irq(void) |
e02e68d3 | 1308 | { |
8457c84d AK |
1309 | /* Not more than two messages every minute */ |
1310 | static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); | |
1311 | ||
1020bcbc | 1312 | if (test_and_clear_bit(0, &mce_need_notify)) { |
93b62c3c HS |
1313 | /* wake processes polling /dev/mcelog */ |
1314 | wake_up_interruptible(&mce_chrdev_wait); | |
9bd98405 AK |
1315 | |
1316 | /* | |
1317 | * There is no risk of missing notifications because | |
1318 | * work_pending is always cleared before the function is | |
1319 | * executed. | |
1320 | */ | |
1020bcbc | 1321 | if (mce_helper[0] && !work_pending(&mce_trigger_work)) |
9bd98405 | 1322 | schedule_work(&mce_trigger_work); |
e02e68d3 | 1323 | |
8457c84d | 1324 | if (__ratelimit(&ratelimit)) |
a2d7b0d4 | 1325 | pr_info(HW_ERR "Machine check events logged\n"); |
e02e68d3 TH |
1326 | |
1327 | return 1; | |
1da177e4 | 1328 | } |
e02e68d3 TH |
1329 | return 0; |
1330 | } | |
9ff36ee9 | 1331 | EXPORT_SYMBOL_GPL(mce_notify_irq); |
8a336b0a | 1332 | |
cffd377e | 1333 | static int __cpuinit __mcheck_cpu_mce_banks_init(void) |
cebe1820 AK |
1334 | { |
1335 | int i; | |
1336 | ||
1337 | mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL); | |
1338 | if (!mce_banks) | |
1339 | return -ENOMEM; | |
1340 | for (i = 0; i < banks; i++) { | |
1341 | struct mce_bank *b = &mce_banks[i]; | |
11868a2d | 1342 | |
cebe1820 AK |
1343 | b->ctl = -1ULL; |
1344 | b->init = 1; | |
1345 | } | |
1346 | return 0; | |
1347 | } | |
1348 | ||
d88203d1 | 1349 | /* |
1da177e4 LT |
1350 | * Initialize Machine Checks for a CPU. |
1351 | */ | |
5e09954a | 1352 | static int __cpuinit __mcheck_cpu_cap_init(void) |
1da177e4 | 1353 | { |
0d7482e3 | 1354 | unsigned b; |
e9eee03e | 1355 | u64 cap; |
1da177e4 LT |
1356 | |
1357 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
01c6680a TG |
1358 | |
1359 | b = cap & MCG_BANKCNT_MASK; | |
93ae5012 RD |
1360 | if (!banks) |
1361 | printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b); | |
b659294b | 1362 | |
0d7482e3 AK |
1363 | if (b > MAX_NR_BANKS) { |
1364 | printk(KERN_WARNING | |
1365 | "MCE: Using only %u machine check banks out of %u\n", | |
1366 | MAX_NR_BANKS, b); | |
1367 | b = MAX_NR_BANKS; | |
1368 | } | |
1369 | ||
1370 | /* Don't support asymmetric configurations today */ | |
1371 | WARN_ON(banks != 0 && b != banks); | |
1372 | banks = b; | |
cebe1820 | 1373 | if (!mce_banks) { |
cffd377e | 1374 | int err = __mcheck_cpu_mce_banks_init(); |
11868a2d | 1375 | |
cebe1820 AK |
1376 | if (err) |
1377 | return err; | |
1da177e4 | 1378 | } |
0d7482e3 | 1379 | |
94ad8474 | 1380 | /* Use accurate RIP reporting if available. */ |
01c6680a | 1381 | if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) |
94ad8474 | 1382 | rip_msr = MSR_IA32_MCG_EIP; |
1da177e4 | 1383 | |
ed7290d0 AK |
1384 | if (cap & MCG_SER_P) |
1385 | mce_ser = 1; | |
1386 | ||
0d7482e3 AK |
1387 | return 0; |
1388 | } | |
1389 | ||
5e09954a | 1390 | static void __mcheck_cpu_init_generic(void) |
0d7482e3 | 1391 | { |
e9eee03e | 1392 | mce_banks_t all_banks; |
0d7482e3 AK |
1393 | u64 cap; |
1394 | int i; | |
1395 | ||
b79109c3 AK |
1396 | /* |
1397 | * Log the machine checks left over from the previous reset. | |
1398 | */ | |
ee031c31 | 1399 | bitmap_fill(all_banks, MAX_NR_BANKS); |
5679af4c | 1400 | machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks); |
1da177e4 LT |
1401 | |
1402 | set_in_cr4(X86_CR4_MCE); | |
1403 | ||
0d7482e3 | 1404 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
1da177e4 LT |
1405 | if (cap & MCG_CTL_P) |
1406 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); | |
1407 | ||
1408 | for (i = 0; i < banks; i++) { | |
cebe1820 | 1409 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1410 | |
cebe1820 | 1411 | if (!b->init) |
06b7a7a5 | 1412 | continue; |
a2d32bcb AK |
1413 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
1414 | wrmsrl(MSR_IA32_MCx_STATUS(i), 0); | |
d88203d1 | 1415 | } |
1da177e4 LT |
1416 | } |
1417 | ||
1418 | /* Add per CPU specific workarounds here */ | |
5e09954a | 1419 | static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) |
d88203d1 | 1420 | { |
e412cd25 IM |
1421 | if (c->x86_vendor == X86_VENDOR_UNKNOWN) { |
1422 | pr_info("MCE: unknown CPU type - not enabling MCE support.\n"); | |
1423 | return -EOPNOTSUPP; | |
1424 | } | |
1425 | ||
1da177e4 | 1426 | /* This should be disabled by the BIOS, but isn't always */ |
911f6a7b | 1427 | if (c->x86_vendor == X86_VENDOR_AMD) { |
e9eee03e IM |
1428 | if (c->x86 == 15 && banks > 4) { |
1429 | /* | |
1430 | * disable GART TBL walk error reporting, which | |
1431 | * trips off incorrectly with the IOMMU & 3ware | |
1432 | * & Cerberus: | |
1433 | */ | |
cebe1820 | 1434 | clear_bit(10, (unsigned long *)&mce_banks[4].ctl); |
e9eee03e IM |
1435 | } |
1436 | if (c->x86 <= 17 && mce_bootlog < 0) { | |
1437 | /* | |
1438 | * Lots of broken BIOS around that don't clear them | |
1439 | * by default and leave crap in there. Don't log: | |
1440 | */ | |
911f6a7b | 1441 | mce_bootlog = 0; |
e9eee03e | 1442 | } |
2e6f694f AK |
1443 | /* |
1444 | * Various K7s with broken bank 0 around. Always disable | |
1445 | * by default. | |
1446 | */ | |
203abd67 | 1447 | if (c->x86 == 6 && banks > 0) |
cebe1820 | 1448 | mce_banks[0].ctl = 0; |
575203b4 BP |
1449 | |
1450 | /* | |
1451 | * Turn off MC4_MISC thresholding banks on those models since | |
1452 | * they're not supported there. | |
1453 | */ | |
1454 | if (c->x86 == 0x15 && | |
1455 | (c->x86_model >= 0x10 && c->x86_model <= 0x1f)) { | |
1456 | int i; | |
1457 | u64 val, hwcr; | |
1458 | bool need_toggle; | |
1459 | u32 msrs[] = { | |
1460 | 0x00000413, /* MC4_MISC0 */ | |
1461 | 0xc0000408, /* MC4_MISC1 */ | |
1462 | }; | |
1463 | ||
1464 | rdmsrl(MSR_K7_HWCR, hwcr); | |
1465 | ||
1466 | /* McStatusWrEn has to be set */ | |
1467 | need_toggle = !(hwcr & BIT(18)); | |
1468 | ||
1469 | if (need_toggle) | |
1470 | wrmsrl(MSR_K7_HWCR, hwcr | BIT(18)); | |
1471 | ||
1472 | for (i = 0; i < ARRAY_SIZE(msrs); i++) { | |
1473 | rdmsrl(msrs[i], val); | |
1474 | ||
1475 | /* CntP bit set? */ | |
80f03361 BP |
1476 | if (val & BIT_64(62)) { |
1477 | val &= ~BIT_64(62); | |
1478 | wrmsrl(msrs[i], val); | |
575203b4 BP |
1479 | } |
1480 | } | |
1481 | ||
1482 | /* restore old settings */ | |
1483 | if (need_toggle) | |
1484 | wrmsrl(MSR_K7_HWCR, hwcr); | |
1485 | } | |
1da177e4 | 1486 | } |
e583538f | 1487 | |
06b7a7a5 AK |
1488 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
1489 | /* | |
1490 | * SDM documents that on family 6 bank 0 should not be written | |
1491 | * because it aliases to another special BIOS controlled | |
1492 | * register. | |
1493 | * But it's not aliased anymore on model 0x1a+ | |
1494 | * Don't ignore bank 0 completely because there could be a | |
1495 | * valid event later, merely don't write CTL0. | |
1496 | */ | |
1497 | ||
cebe1820 AK |
1498 | if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0) |
1499 | mce_banks[0].init = 0; | |
3c079792 AK |
1500 | |
1501 | /* | |
1502 | * All newer Intel systems support MCE broadcasting. Enable | |
1503 | * synchronization with a one second timeout. | |
1504 | */ | |
1505 | if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && | |
1506 | monarch_timeout < 0) | |
1507 | monarch_timeout = USEC_PER_SEC; | |
c7f6fa44 | 1508 | |
e412cd25 IM |
1509 | /* |
1510 | * There are also broken BIOSes on some Pentium M and | |
1511 | * earlier systems: | |
1512 | */ | |
1513 | if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0) | |
c7f6fa44 | 1514 | mce_bootlog = 0; |
06b7a7a5 | 1515 | } |
3c079792 AK |
1516 | if (monarch_timeout < 0) |
1517 | monarch_timeout = 0; | |
29b0f591 AK |
1518 | if (mce_bootlog != 0) |
1519 | mce_panic_timeout = 30; | |
e412cd25 IM |
1520 | |
1521 | return 0; | |
d88203d1 | 1522 | } |
1da177e4 | 1523 | |
3a97fc34 | 1524 | static int __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) |
4efc0670 AK |
1525 | { |
1526 | if (c->x86 != 5) | |
3a97fc34 HS |
1527 | return 0; |
1528 | ||
4efc0670 AK |
1529 | switch (c->x86_vendor) { |
1530 | case X86_VENDOR_INTEL: | |
c6978369 | 1531 | intel_p5_mcheck_init(c); |
3a97fc34 | 1532 | return 1; |
4efc0670 AK |
1533 | break; |
1534 | case X86_VENDOR_CENTAUR: | |
1535 | winchip_mcheck_init(c); | |
3a97fc34 | 1536 | return 1; |
4efc0670 AK |
1537 | break; |
1538 | } | |
3a97fc34 HS |
1539 | |
1540 | return 0; | |
4efc0670 AK |
1541 | } |
1542 | ||
5e09954a | 1543 | static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
1544 | { |
1545 | switch (c->x86_vendor) { | |
1546 | case X86_VENDOR_INTEL: | |
1547 | mce_intel_feature_init(c); | |
1548 | break; | |
89b831ef JS |
1549 | case X86_VENDOR_AMD: |
1550 | mce_amd_feature_init(c); | |
1551 | break; | |
1da177e4 LT |
1552 | default: |
1553 | break; | |
1554 | } | |
1555 | } | |
1556 | ||
5e09954a | 1557 | static void __mcheck_cpu_init_timer(void) |
52d168e2 AK |
1558 | { |
1559 | struct timer_list *t = &__get_cpu_var(mce_timer); | |
82f7af09 | 1560 | unsigned long iv = __this_cpu_read(mce_next_interval); |
52d168e2 | 1561 | |
82f7af09 | 1562 | setup_timer(t, mce_timer_fn, smp_processor_id()); |
bc09effa | 1563 | |
62fdac59 HS |
1564 | if (mce_ignore_ce) |
1565 | return; | |
1566 | ||
82f7af09 TG |
1567 | __this_cpu_write(mce_next_interval, iv); |
1568 | if (!iv) | |
52d168e2 | 1569 | return; |
82f7af09 | 1570 | t->expires = round_jiffies(jiffies + iv); |
5be6066a | 1571 | add_timer_on(t, smp_processor_id()); |
52d168e2 AK |
1572 | } |
1573 | ||
9eda8cb3 AK |
1574 | /* Handle unconfigured int18 (should never happen) */ |
1575 | static void unexpected_machine_check(struct pt_regs *regs, long error_code) | |
1576 | { | |
1577 | printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n", | |
1578 | smp_processor_id()); | |
1579 | } | |
1580 | ||
1581 | /* Call the installed machine check handler for this CPU setup. */ | |
1582 | void (*machine_check_vector)(struct pt_regs *, long error_code) = | |
1583 | unexpected_machine_check; | |
1584 | ||
d88203d1 | 1585 | /* |
1da177e4 | 1586 | * Called for each booted CPU to set up machine checks. |
e9eee03e | 1587 | * Must be called with preempt off: |
1da177e4 | 1588 | */ |
5e09954a | 1589 | void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c) |
1da177e4 | 1590 | { |
4efc0670 AK |
1591 | if (mce_disabled) |
1592 | return; | |
1593 | ||
3a97fc34 HS |
1594 | if (__mcheck_cpu_ancient_init(c)) |
1595 | return; | |
4efc0670 | 1596 | |
5b4408fd | 1597 | if (!mce_available(c)) |
1da177e4 LT |
1598 | return; |
1599 | ||
5e09954a | 1600 | if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) { |
04b2b1a4 | 1601 | mce_disabled = 1; |
0d7482e3 AK |
1602 | return; |
1603 | } | |
0d7482e3 | 1604 | |
5d727926 AK |
1605 | machine_check_vector = do_machine_check; |
1606 | ||
5e09954a BP |
1607 | __mcheck_cpu_init_generic(); |
1608 | __mcheck_cpu_init_vendor(c); | |
1609 | __mcheck_cpu_init_timer(); | |
9b1beaf2 | 1610 | INIT_WORK(&__get_cpu_var(mce_work), mce_process_work); |
b77e70bf | 1611 | init_irq_work(&__get_cpu_var(mce_irq_work), &mce_irq_work_cb); |
1da177e4 LT |
1612 | } |
1613 | ||
1614 | /* | |
93b62c3c | 1615 | * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log. |
1da177e4 LT |
1616 | */ |
1617 | ||
93b62c3c HS |
1618 | static DEFINE_SPINLOCK(mce_chrdev_state_lock); |
1619 | static int mce_chrdev_open_count; /* #times opened */ | |
1620 | static int mce_chrdev_open_exclu; /* already open exclusive? */ | |
f528e7ba | 1621 | |
93b62c3c | 1622 | static int mce_chrdev_open(struct inode *inode, struct file *file) |
f528e7ba | 1623 | { |
93b62c3c | 1624 | spin_lock(&mce_chrdev_state_lock); |
f528e7ba | 1625 | |
93b62c3c HS |
1626 | if (mce_chrdev_open_exclu || |
1627 | (mce_chrdev_open_count && (file->f_flags & O_EXCL))) { | |
1628 | spin_unlock(&mce_chrdev_state_lock); | |
e9eee03e | 1629 | |
f528e7ba TH |
1630 | return -EBUSY; |
1631 | } | |
1632 | ||
1633 | if (file->f_flags & O_EXCL) | |
93b62c3c HS |
1634 | mce_chrdev_open_exclu = 1; |
1635 | mce_chrdev_open_count++; | |
f528e7ba | 1636 | |
93b62c3c | 1637 | spin_unlock(&mce_chrdev_state_lock); |
f528e7ba | 1638 | |
bd78432c | 1639 | return nonseekable_open(inode, file); |
f528e7ba TH |
1640 | } |
1641 | ||
93b62c3c | 1642 | static int mce_chrdev_release(struct inode *inode, struct file *file) |
f528e7ba | 1643 | { |
93b62c3c | 1644 | spin_lock(&mce_chrdev_state_lock); |
f528e7ba | 1645 | |
93b62c3c HS |
1646 | mce_chrdev_open_count--; |
1647 | mce_chrdev_open_exclu = 0; | |
f528e7ba | 1648 | |
93b62c3c | 1649 | spin_unlock(&mce_chrdev_state_lock); |
f528e7ba TH |
1650 | |
1651 | return 0; | |
1652 | } | |
1653 | ||
d88203d1 TG |
1654 | static void collect_tscs(void *data) |
1655 | { | |
1da177e4 | 1656 | unsigned long *cpu_tsc = (unsigned long *)data; |
d88203d1 | 1657 | |
1da177e4 | 1658 | rdtscll(cpu_tsc[smp_processor_id()]); |
d88203d1 | 1659 | } |
1da177e4 | 1660 | |
482908b4 HY |
1661 | static int mce_apei_read_done; |
1662 | ||
1663 | /* Collect MCE record of previous boot in persistent storage via APEI ERST. */ | |
1664 | static int __mce_read_apei(char __user **ubuf, size_t usize) | |
1665 | { | |
1666 | int rc; | |
1667 | u64 record_id; | |
1668 | struct mce m; | |
1669 | ||
1670 | if (usize < sizeof(struct mce)) | |
1671 | return -EINVAL; | |
1672 | ||
1673 | rc = apei_read_mce(&m, &record_id); | |
1674 | /* Error or no more MCE record */ | |
1675 | if (rc <= 0) { | |
1676 | mce_apei_read_done = 1; | |
fadd85f1 NH |
1677 | /* |
1678 | * When ERST is disabled, mce_chrdev_read() should return | |
1679 | * "no record" instead of "no device." | |
1680 | */ | |
1681 | if (rc == -ENODEV) | |
1682 | return 0; | |
482908b4 HY |
1683 | return rc; |
1684 | } | |
1685 | rc = -EFAULT; | |
1686 | if (copy_to_user(*ubuf, &m, sizeof(struct mce))) | |
1687 | return rc; | |
1688 | /* | |
1689 | * In fact, we should have cleared the record after that has | |
1690 | * been flushed to the disk or sent to network in | |
1691 | * /sbin/mcelog, but we have no interface to support that now, | |
1692 | * so just clear it to avoid duplication. | |
1693 | */ | |
1694 | rc = apei_clear_mce(record_id); | |
1695 | if (rc) { | |
1696 | mce_apei_read_done = 1; | |
1697 | return rc; | |
1698 | } | |
1699 | *ubuf += sizeof(struct mce); | |
1700 | ||
1701 | return 0; | |
1702 | } | |
1703 | ||
93b62c3c HS |
1704 | static ssize_t mce_chrdev_read(struct file *filp, char __user *ubuf, |
1705 | size_t usize, loff_t *off) | |
1da177e4 | 1706 | { |
e9eee03e | 1707 | char __user *buf = ubuf; |
f0de53bb | 1708 | unsigned long *cpu_tsc; |
ef41df43 | 1709 | unsigned prev, next; |
1da177e4 LT |
1710 | int i, err; |
1711 | ||
6bca67f9 | 1712 | cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL); |
f0de53bb AK |
1713 | if (!cpu_tsc) |
1714 | return -ENOMEM; | |
1715 | ||
93b62c3c | 1716 | mutex_lock(&mce_chrdev_read_mutex); |
482908b4 HY |
1717 | |
1718 | if (!mce_apei_read_done) { | |
1719 | err = __mce_read_apei(&buf, usize); | |
1720 | if (err || buf != ubuf) | |
1721 | goto out; | |
1722 | } | |
1723 | ||
f56e8a07 | 1724 | next = rcu_dereference_check_mce(mcelog.next); |
1da177e4 LT |
1725 | |
1726 | /* Only supports full reads right now */ | |
482908b4 HY |
1727 | err = -EINVAL; |
1728 | if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) | |
1729 | goto out; | |
1da177e4 LT |
1730 | |
1731 | err = 0; | |
ef41df43 HY |
1732 | prev = 0; |
1733 | do { | |
1734 | for (i = prev; i < next; i++) { | |
1735 | unsigned long start = jiffies; | |
559faa6b | 1736 | struct mce *m = &mcelog.entry[i]; |
ef41df43 | 1737 | |
559faa6b | 1738 | while (!m->finished) { |
ef41df43 | 1739 | if (time_after_eq(jiffies, start + 2)) { |
559faa6b | 1740 | memset(m, 0, sizeof(*m)); |
ef41df43 HY |
1741 | goto timeout; |
1742 | } | |
1743 | cpu_relax(); | |
673242c1 | 1744 | } |
ef41df43 | 1745 | smp_rmb(); |
559faa6b HS |
1746 | err |= copy_to_user(buf, m, sizeof(*m)); |
1747 | buf += sizeof(*m); | |
ef41df43 HY |
1748 | timeout: |
1749 | ; | |
673242c1 | 1750 | } |
1da177e4 | 1751 | |
ef41df43 HY |
1752 | memset(mcelog.entry + prev, 0, |
1753 | (next - prev) * sizeof(struct mce)); | |
1754 | prev = next; | |
1755 | next = cmpxchg(&mcelog.next, prev, 0); | |
1756 | } while (next != prev); | |
1da177e4 | 1757 | |
b2b18660 | 1758 | synchronize_sched(); |
1da177e4 | 1759 | |
d88203d1 TG |
1760 | /* |
1761 | * Collect entries that were still getting written before the | |
1762 | * synchronize. | |
1763 | */ | |
15c8b6c1 | 1764 | on_each_cpu(collect_tscs, cpu_tsc, 1); |
e9eee03e | 1765 | |
d88203d1 | 1766 | for (i = next; i < MCE_LOG_LEN; i++) { |
559faa6b HS |
1767 | struct mce *m = &mcelog.entry[i]; |
1768 | ||
1769 | if (m->finished && m->tsc < cpu_tsc[m->cpu]) { | |
1770 | err |= copy_to_user(buf, m, sizeof(*m)); | |
1da177e4 | 1771 | smp_rmb(); |
559faa6b HS |
1772 | buf += sizeof(*m); |
1773 | memset(m, 0, sizeof(*m)); | |
1da177e4 | 1774 | } |
d88203d1 | 1775 | } |
482908b4 HY |
1776 | |
1777 | if (err) | |
1778 | err = -EFAULT; | |
1779 | ||
1780 | out: | |
93b62c3c | 1781 | mutex_unlock(&mce_chrdev_read_mutex); |
f0de53bb | 1782 | kfree(cpu_tsc); |
e9eee03e | 1783 | |
482908b4 | 1784 | return err ? err : buf - ubuf; |
1da177e4 LT |
1785 | } |
1786 | ||
93b62c3c | 1787 | static unsigned int mce_chrdev_poll(struct file *file, poll_table *wait) |
e02e68d3 | 1788 | { |
93b62c3c | 1789 | poll_wait(file, &mce_chrdev_wait, wait); |
a4dd9925 | 1790 | if (rcu_access_index(mcelog.next)) |
e02e68d3 | 1791 | return POLLIN | POLLRDNORM; |
482908b4 HY |
1792 | if (!mce_apei_read_done && apei_check_mce()) |
1793 | return POLLIN | POLLRDNORM; | |
e02e68d3 TH |
1794 | return 0; |
1795 | } | |
1796 | ||
93b62c3c HS |
1797 | static long mce_chrdev_ioctl(struct file *f, unsigned int cmd, |
1798 | unsigned long arg) | |
1da177e4 LT |
1799 | { |
1800 | int __user *p = (int __user *)arg; | |
d88203d1 | 1801 | |
1da177e4 | 1802 | if (!capable(CAP_SYS_ADMIN)) |
d88203d1 | 1803 | return -EPERM; |
e9eee03e | 1804 | |
1da177e4 | 1805 | switch (cmd) { |
d88203d1 | 1806 | case MCE_GET_RECORD_LEN: |
1da177e4 LT |
1807 | return put_user(sizeof(struct mce), p); |
1808 | case MCE_GET_LOG_LEN: | |
d88203d1 | 1809 | return put_user(MCE_LOG_LEN, p); |
1da177e4 LT |
1810 | case MCE_GETCLEAR_FLAGS: { |
1811 | unsigned flags; | |
d88203d1 TG |
1812 | |
1813 | do { | |
1da177e4 | 1814 | flags = mcelog.flags; |
d88203d1 | 1815 | } while (cmpxchg(&mcelog.flags, flags, 0) != flags); |
e9eee03e | 1816 | |
d88203d1 | 1817 | return put_user(flags, p); |
1da177e4 LT |
1818 | } |
1819 | default: | |
d88203d1 TG |
1820 | return -ENOTTY; |
1821 | } | |
1da177e4 LT |
1822 | } |
1823 | ||
66f5ddf3 LT |
1824 | static ssize_t (*mce_write)(struct file *filp, const char __user *ubuf, |
1825 | size_t usize, loff_t *off); | |
1826 | ||
1827 | void register_mce_write_callback(ssize_t (*fn)(struct file *filp, | |
1828 | const char __user *ubuf, | |
1829 | size_t usize, loff_t *off)) | |
1830 | { | |
1831 | mce_write = fn; | |
1832 | } | |
1833 | EXPORT_SYMBOL_GPL(register_mce_write_callback); | |
1834 | ||
1835 | ssize_t mce_chrdev_write(struct file *filp, const char __user *ubuf, | |
1836 | size_t usize, loff_t *off) | |
1837 | { | |
1838 | if (mce_write) | |
1839 | return mce_write(filp, ubuf, usize, off); | |
1840 | else | |
1841 | return -EINVAL; | |
1842 | } | |
1843 | ||
1844 | static const struct file_operations mce_chrdev_ops = { | |
93b62c3c HS |
1845 | .open = mce_chrdev_open, |
1846 | .release = mce_chrdev_release, | |
1847 | .read = mce_chrdev_read, | |
66f5ddf3 | 1848 | .write = mce_chrdev_write, |
93b62c3c HS |
1849 | .poll = mce_chrdev_poll, |
1850 | .unlocked_ioctl = mce_chrdev_ioctl, | |
1851 | .llseek = no_llseek, | |
1da177e4 LT |
1852 | }; |
1853 | ||
93b62c3c | 1854 | static struct miscdevice mce_chrdev_device = { |
1da177e4 LT |
1855 | MISC_MCELOG_MINOR, |
1856 | "mcelog", | |
1857 | &mce_chrdev_ops, | |
1858 | }; | |
1859 | ||
13503fa9 | 1860 | /* |
62fdac59 HS |
1861 | * mce=off Disables machine check |
1862 | * mce=no_cmci Disables CMCI | |
1863 | * mce=dont_log_ce Clears corrected events silently, no log created for CEs. | |
1864 | * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared. | |
3c079792 AK |
1865 | * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above) |
1866 | * monarchtimeout is how long to wait for other CPUs on machine | |
1867 | * check, or 0 to not wait | |
13503fa9 HS |
1868 | * mce=bootlog Log MCEs from before booting. Disabled by default on AMD. |
1869 | * mce=nobootlog Don't log MCEs from before booting. | |
1870 | */ | |
1da177e4 LT |
1871 | static int __init mcheck_enable(char *str) |
1872 | { | |
e3346fc4 | 1873 | if (*str == 0) { |
4efc0670 | 1874 | enable_p5_mce(); |
e3346fc4 BZ |
1875 | return 1; |
1876 | } | |
4efc0670 AK |
1877 | if (*str == '=') |
1878 | str++; | |
1da177e4 | 1879 | if (!strcmp(str, "off")) |
04b2b1a4 | 1880 | mce_disabled = 1; |
62fdac59 HS |
1881 | else if (!strcmp(str, "no_cmci")) |
1882 | mce_cmci_disabled = 1; | |
1883 | else if (!strcmp(str, "dont_log_ce")) | |
1884 | mce_dont_log_ce = 1; | |
1885 | else if (!strcmp(str, "ignore_ce")) | |
1886 | mce_ignore_ce = 1; | |
13503fa9 HS |
1887 | else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) |
1888 | mce_bootlog = (str[0] == 'b'); | |
3c079792 | 1889 | else if (isdigit(str[0])) { |
8c566ef5 | 1890 | get_option(&str, &tolerant); |
3c079792 AK |
1891 | if (*str == ',') { |
1892 | ++str; | |
1893 | get_option(&str, &monarch_timeout); | |
1894 | } | |
1895 | } else { | |
4efc0670 | 1896 | printk(KERN_INFO "mce argument %s ignored. Please use /sys\n", |
13503fa9 HS |
1897 | str); |
1898 | return 0; | |
1899 | } | |
9b41046c | 1900 | return 1; |
1da177e4 | 1901 | } |
4efc0670 | 1902 | __setup("mce", mcheck_enable); |
1da177e4 | 1903 | |
a2202aa2 | 1904 | int __init mcheck_init(void) |
b33a6363 | 1905 | { |
a2202aa2 YW |
1906 | mcheck_intel_therm_init(); |
1907 | ||
b33a6363 BP |
1908 | return 0; |
1909 | } | |
b33a6363 | 1910 | |
d88203d1 | 1911 | /* |
c7cece89 | 1912 | * mce_syscore: PM support |
d88203d1 | 1913 | */ |
1da177e4 | 1914 | |
973a2dd1 AK |
1915 | /* |
1916 | * Disable machine checks on suspend and shutdown. We can't really handle | |
1917 | * them later. | |
1918 | */ | |
5e09954a | 1919 | static int mce_disable_error_reporting(void) |
973a2dd1 AK |
1920 | { |
1921 | int i; | |
1922 | ||
06b7a7a5 | 1923 | for (i = 0; i < banks; i++) { |
cebe1820 | 1924 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1925 | |
cebe1820 | 1926 | if (b->init) |
a2d32bcb | 1927 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 1928 | } |
973a2dd1 AK |
1929 | return 0; |
1930 | } | |
1931 | ||
c7cece89 | 1932 | static int mce_syscore_suspend(void) |
973a2dd1 | 1933 | { |
5e09954a | 1934 | return mce_disable_error_reporting(); |
973a2dd1 AK |
1935 | } |
1936 | ||
c7cece89 | 1937 | static void mce_syscore_shutdown(void) |
973a2dd1 | 1938 | { |
f3c6ea1b | 1939 | mce_disable_error_reporting(); |
973a2dd1 AK |
1940 | } |
1941 | ||
e9eee03e IM |
1942 | /* |
1943 | * On resume clear all MCE state. Don't want to see leftovers from the BIOS. | |
1944 | * Only one CPU is active at this time, the others get re-added later using | |
1945 | * CPU hotplug: | |
1946 | */ | |
c7cece89 | 1947 | static void mce_syscore_resume(void) |
1da177e4 | 1948 | { |
5e09954a | 1949 | __mcheck_cpu_init_generic(); |
7b543a53 | 1950 | __mcheck_cpu_init_vendor(__this_cpu_ptr(&cpu_info)); |
1da177e4 LT |
1951 | } |
1952 | ||
f3c6ea1b | 1953 | static struct syscore_ops mce_syscore_ops = { |
c7cece89 HS |
1954 | .suspend = mce_syscore_suspend, |
1955 | .shutdown = mce_syscore_shutdown, | |
1956 | .resume = mce_syscore_resume, | |
f3c6ea1b RW |
1957 | }; |
1958 | ||
c7cece89 | 1959 | /* |
8a25a2fd | 1960 | * mce_device: Sysfs support |
c7cece89 HS |
1961 | */ |
1962 | ||
52d168e2 AK |
1963 | static void mce_cpu_restart(void *data) |
1964 | { | |
7b543a53 | 1965 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
33edbf02 | 1966 | return; |
5e09954a BP |
1967 | __mcheck_cpu_init_generic(); |
1968 | __mcheck_cpu_init_timer(); | |
52d168e2 AK |
1969 | } |
1970 | ||
1da177e4 | 1971 | /* Reinit MCEs after user configuration changes */ |
d88203d1 TG |
1972 | static void mce_restart(void) |
1973 | { | |
9aaef96f | 1974 | mce_timer_delete_all(); |
52d168e2 | 1975 | on_each_cpu(mce_cpu_restart, NULL, 1); |
1da177e4 LT |
1976 | } |
1977 | ||
9af43b54 | 1978 | /* Toggle features for corrected errors */ |
9aaef96f | 1979 | static void mce_disable_cmci(void *data) |
9af43b54 | 1980 | { |
7b543a53 | 1981 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
9af43b54 | 1982 | return; |
9af43b54 HS |
1983 | cmci_clear(); |
1984 | } | |
1985 | ||
1986 | static void mce_enable_ce(void *all) | |
1987 | { | |
7b543a53 | 1988 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
9af43b54 HS |
1989 | return; |
1990 | cmci_reenable(); | |
1991 | cmci_recheck(); | |
1992 | if (all) | |
5e09954a | 1993 | __mcheck_cpu_init_timer(); |
9af43b54 HS |
1994 | } |
1995 | ||
8a25a2fd | 1996 | static struct bus_type mce_subsys = { |
e9eee03e | 1997 | .name = "machinecheck", |
8a25a2fd | 1998 | .dev_name = "machinecheck", |
1da177e4 LT |
1999 | }; |
2000 | ||
d6126ef5 | 2001 | DEFINE_PER_CPU(struct device *, mce_device); |
e9eee03e IM |
2002 | |
2003 | __cpuinitdata | |
2004 | void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); | |
1da177e4 | 2005 | |
8a25a2fd | 2006 | static inline struct mce_bank *attr_to_bank(struct device_attribute *attr) |
cebe1820 AK |
2007 | { |
2008 | return container_of(attr, struct mce_bank, attr); | |
2009 | } | |
0d7482e3 | 2010 | |
8a25a2fd | 2011 | static ssize_t show_bank(struct device *s, struct device_attribute *attr, |
0d7482e3 AK |
2012 | char *buf) |
2013 | { | |
cebe1820 | 2014 | return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl); |
0d7482e3 AK |
2015 | } |
2016 | ||
8a25a2fd | 2017 | static ssize_t set_bank(struct device *s, struct device_attribute *attr, |
9319cec8 | 2018 | const char *buf, size_t size) |
0d7482e3 | 2019 | { |
9319cec8 | 2020 | u64 new; |
e9eee03e | 2021 | |
9319cec8 | 2022 | if (strict_strtoull(buf, 0, &new) < 0) |
0d7482e3 | 2023 | return -EINVAL; |
e9eee03e | 2024 | |
cebe1820 | 2025 | attr_to_bank(attr)->ctl = new; |
0d7482e3 | 2026 | mce_restart(); |
e9eee03e | 2027 | |
9319cec8 | 2028 | return size; |
0d7482e3 | 2029 | } |
a98f0dd3 | 2030 | |
e9eee03e | 2031 | static ssize_t |
8a25a2fd | 2032 | show_trigger(struct device *s, struct device_attribute *attr, char *buf) |
a98f0dd3 | 2033 | { |
1020bcbc | 2034 | strcpy(buf, mce_helper); |
a98f0dd3 | 2035 | strcat(buf, "\n"); |
1020bcbc | 2036 | return strlen(mce_helper) + 1; |
a98f0dd3 AK |
2037 | } |
2038 | ||
8a25a2fd | 2039 | static ssize_t set_trigger(struct device *s, struct device_attribute *attr, |
e9eee03e | 2040 | const char *buf, size_t siz) |
a98f0dd3 AK |
2041 | { |
2042 | char *p; | |
e9eee03e | 2043 | |
1020bcbc HS |
2044 | strncpy(mce_helper, buf, sizeof(mce_helper)); |
2045 | mce_helper[sizeof(mce_helper)-1] = 0; | |
1020bcbc | 2046 | p = strchr(mce_helper, '\n'); |
e9eee03e | 2047 | |
e9084ec9 | 2048 | if (p) |
e9eee03e IM |
2049 | *p = 0; |
2050 | ||
e9084ec9 | 2051 | return strlen(mce_helper) + !!p; |
a98f0dd3 AK |
2052 | } |
2053 | ||
8a25a2fd KS |
2054 | static ssize_t set_ignore_ce(struct device *s, |
2055 | struct device_attribute *attr, | |
9af43b54 HS |
2056 | const char *buf, size_t size) |
2057 | { | |
2058 | u64 new; | |
2059 | ||
2060 | if (strict_strtoull(buf, 0, &new) < 0) | |
2061 | return -EINVAL; | |
2062 | ||
2063 | if (mce_ignore_ce ^ !!new) { | |
2064 | if (new) { | |
2065 | /* disable ce features */ | |
9aaef96f HS |
2066 | mce_timer_delete_all(); |
2067 | on_each_cpu(mce_disable_cmci, NULL, 1); | |
9af43b54 HS |
2068 | mce_ignore_ce = 1; |
2069 | } else { | |
2070 | /* enable ce features */ | |
2071 | mce_ignore_ce = 0; | |
2072 | on_each_cpu(mce_enable_ce, (void *)1, 1); | |
2073 | } | |
2074 | } | |
2075 | return size; | |
2076 | } | |
2077 | ||
8a25a2fd KS |
2078 | static ssize_t set_cmci_disabled(struct device *s, |
2079 | struct device_attribute *attr, | |
9af43b54 HS |
2080 | const char *buf, size_t size) |
2081 | { | |
2082 | u64 new; | |
2083 | ||
2084 | if (strict_strtoull(buf, 0, &new) < 0) | |
2085 | return -EINVAL; | |
2086 | ||
2087 | if (mce_cmci_disabled ^ !!new) { | |
2088 | if (new) { | |
2089 | /* disable cmci */ | |
9aaef96f | 2090 | on_each_cpu(mce_disable_cmci, NULL, 1); |
9af43b54 HS |
2091 | mce_cmci_disabled = 1; |
2092 | } else { | |
2093 | /* enable cmci */ | |
2094 | mce_cmci_disabled = 0; | |
2095 | on_each_cpu(mce_enable_ce, NULL, 1); | |
2096 | } | |
2097 | } | |
2098 | return size; | |
2099 | } | |
2100 | ||
8a25a2fd KS |
2101 | static ssize_t store_int_with_restart(struct device *s, |
2102 | struct device_attribute *attr, | |
b56f642d AK |
2103 | const char *buf, size_t size) |
2104 | { | |
8a25a2fd | 2105 | ssize_t ret = device_store_int(s, attr, buf, size); |
b56f642d AK |
2106 | mce_restart(); |
2107 | return ret; | |
2108 | } | |
2109 | ||
8a25a2fd KS |
2110 | static DEVICE_ATTR(trigger, 0644, show_trigger, set_trigger); |
2111 | static DEVICE_INT_ATTR(tolerant, 0644, tolerant); | |
2112 | static DEVICE_INT_ATTR(monarch_timeout, 0644, monarch_timeout); | |
2113 | static DEVICE_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce); | |
e9eee03e | 2114 | |
8a25a2fd KS |
2115 | static struct dev_ext_attribute dev_attr_check_interval = { |
2116 | __ATTR(check_interval, 0644, device_show_int, store_int_with_restart), | |
b56f642d AK |
2117 | &check_interval |
2118 | }; | |
e9eee03e | 2119 | |
8a25a2fd KS |
2120 | static struct dev_ext_attribute dev_attr_ignore_ce = { |
2121 | __ATTR(ignore_ce, 0644, device_show_int, set_ignore_ce), | |
9af43b54 HS |
2122 | &mce_ignore_ce |
2123 | }; | |
2124 | ||
8a25a2fd KS |
2125 | static struct dev_ext_attribute dev_attr_cmci_disabled = { |
2126 | __ATTR(cmci_disabled, 0644, device_show_int, set_cmci_disabled), | |
9af43b54 HS |
2127 | &mce_cmci_disabled |
2128 | }; | |
2129 | ||
8a25a2fd KS |
2130 | static struct device_attribute *mce_device_attrs[] = { |
2131 | &dev_attr_tolerant.attr, | |
2132 | &dev_attr_check_interval.attr, | |
2133 | &dev_attr_trigger, | |
2134 | &dev_attr_monarch_timeout.attr, | |
2135 | &dev_attr_dont_log_ce.attr, | |
2136 | &dev_attr_ignore_ce.attr, | |
2137 | &dev_attr_cmci_disabled.attr, | |
a98f0dd3 AK |
2138 | NULL |
2139 | }; | |
1da177e4 | 2140 | |
8a25a2fd | 2141 | static cpumask_var_t mce_device_initialized; |
bae19fe0 | 2142 | |
e032d807 GKH |
2143 | static void mce_device_release(struct device *dev) |
2144 | { | |
2145 | kfree(dev); | |
2146 | } | |
2147 | ||
8a25a2fd KS |
2148 | /* Per cpu device init. All of the cpus still share the same ctrl bank: */ |
2149 | static __cpuinit int mce_device_create(unsigned int cpu) | |
1da177e4 | 2150 | { |
e032d807 | 2151 | struct device *dev; |
1da177e4 | 2152 | int err; |
b1f49f95 | 2153 | int i, j; |
92cb7612 | 2154 | |
90367556 | 2155 | if (!mce_available(&boot_cpu_data)) |
91c6d400 AK |
2156 | return -EIO; |
2157 | ||
e032d807 GKH |
2158 | dev = kzalloc(sizeof *dev, GFP_KERNEL); |
2159 | if (!dev) | |
2160 | return -ENOMEM; | |
8a25a2fd KS |
2161 | dev->id = cpu; |
2162 | dev->bus = &mce_subsys; | |
e032d807 | 2163 | dev->release = &mce_device_release; |
91c6d400 | 2164 | |
8a25a2fd | 2165 | err = device_register(dev); |
d435d862 AM |
2166 | if (err) |
2167 | return err; | |
2168 | ||
8a25a2fd KS |
2169 | for (i = 0; mce_device_attrs[i]; i++) { |
2170 | err = device_create_file(dev, mce_device_attrs[i]); | |
d435d862 AM |
2171 | if (err) |
2172 | goto error; | |
2173 | } | |
b1f49f95 | 2174 | for (j = 0; j < banks; j++) { |
8a25a2fd | 2175 | err = device_create_file(dev, &mce_banks[j].attr); |
0d7482e3 AK |
2176 | if (err) |
2177 | goto error2; | |
2178 | } | |
8a25a2fd | 2179 | cpumask_set_cpu(cpu, mce_device_initialized); |
d6126ef5 | 2180 | per_cpu(mce_device, cpu) = dev; |
91c6d400 | 2181 | |
d435d862 | 2182 | return 0; |
0d7482e3 | 2183 | error2: |
b1f49f95 | 2184 | while (--j >= 0) |
8a25a2fd | 2185 | device_remove_file(dev, &mce_banks[j].attr); |
d435d862 | 2186 | error: |
cb491fca | 2187 | while (--i >= 0) |
8a25a2fd | 2188 | device_remove_file(dev, mce_device_attrs[i]); |
cb491fca | 2189 | |
8a25a2fd | 2190 | device_unregister(dev); |
d435d862 | 2191 | |
91c6d400 AK |
2192 | return err; |
2193 | } | |
2194 | ||
8a25a2fd | 2195 | static __cpuinit void mce_device_remove(unsigned int cpu) |
91c6d400 | 2196 | { |
d6126ef5 | 2197 | struct device *dev = per_cpu(mce_device, cpu); |
73ca5358 SL |
2198 | int i; |
2199 | ||
8a25a2fd | 2200 | if (!cpumask_test_cpu(cpu, mce_device_initialized)) |
bae19fe0 AH |
2201 | return; |
2202 | ||
8a25a2fd KS |
2203 | for (i = 0; mce_device_attrs[i]; i++) |
2204 | device_remove_file(dev, mce_device_attrs[i]); | |
cb491fca | 2205 | |
0d7482e3 | 2206 | for (i = 0; i < banks; i++) |
8a25a2fd | 2207 | device_remove_file(dev, &mce_banks[i].attr); |
cb491fca | 2208 | |
8a25a2fd KS |
2209 | device_unregister(dev); |
2210 | cpumask_clear_cpu(cpu, mce_device_initialized); | |
d6126ef5 | 2211 | per_cpu(mce_device, cpu) = NULL; |
91c6d400 | 2212 | } |
91c6d400 | 2213 | |
d6b75584 | 2214 | /* Make sure there are no machine checks on offlined CPUs. */ |
767df1bd | 2215 | static void __cpuinit mce_disable_cpu(void *h) |
d6b75584 | 2216 | { |
88ccbedd | 2217 | unsigned long action = *(unsigned long *)h; |
cb491fca | 2218 | int i; |
d6b75584 | 2219 | |
7b543a53 | 2220 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
d6b75584 | 2221 | return; |
767df1bd | 2222 | |
88ccbedd AK |
2223 | if (!(action & CPU_TASKS_FROZEN)) |
2224 | cmci_clear(); | |
06b7a7a5 | 2225 | for (i = 0; i < banks; i++) { |
cebe1820 | 2226 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2227 | |
cebe1820 | 2228 | if (b->init) |
a2d32bcb | 2229 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 2230 | } |
d6b75584 AK |
2231 | } |
2232 | ||
767df1bd | 2233 | static void __cpuinit mce_reenable_cpu(void *h) |
d6b75584 | 2234 | { |
88ccbedd | 2235 | unsigned long action = *(unsigned long *)h; |
e9eee03e | 2236 | int i; |
d6b75584 | 2237 | |
7b543a53 | 2238 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
d6b75584 | 2239 | return; |
e9eee03e | 2240 | |
88ccbedd AK |
2241 | if (!(action & CPU_TASKS_FROZEN)) |
2242 | cmci_reenable(); | |
06b7a7a5 | 2243 | for (i = 0; i < banks; i++) { |
cebe1820 | 2244 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2245 | |
cebe1820 | 2246 | if (b->init) |
a2d32bcb | 2247 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
06b7a7a5 | 2248 | } |
d6b75584 AK |
2249 | } |
2250 | ||
91c6d400 | 2251 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ |
e9eee03e IM |
2252 | static int __cpuinit |
2253 | mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) | |
91c6d400 AK |
2254 | { |
2255 | unsigned int cpu = (unsigned long)hcpu; | |
52d168e2 | 2256 | struct timer_list *t = &per_cpu(mce_timer, cpu); |
91c6d400 AK |
2257 | |
2258 | switch (action) { | |
bae19fe0 AH |
2259 | case CPU_ONLINE: |
2260 | case CPU_ONLINE_FROZEN: | |
8a25a2fd | 2261 | mce_device_create(cpu); |
8735728e RW |
2262 | if (threshold_cpu_callback) |
2263 | threshold_cpu_callback(action, cpu); | |
91c6d400 | 2264 | break; |
91c6d400 | 2265 | case CPU_DEAD: |
8bb78442 | 2266 | case CPU_DEAD_FROZEN: |
8735728e RW |
2267 | if (threshold_cpu_callback) |
2268 | threshold_cpu_callback(action, cpu); | |
8a25a2fd | 2269 | mce_device_remove(cpu); |
91c6d400 | 2270 | break; |
52d168e2 AK |
2271 | case CPU_DOWN_PREPARE: |
2272 | case CPU_DOWN_PREPARE_FROZEN: | |
2273 | del_timer_sync(t); | |
88ccbedd | 2274 | smp_call_function_single(cpu, mce_disable_cpu, &action, 1); |
52d168e2 AK |
2275 | break; |
2276 | case CPU_DOWN_FAILED: | |
2277 | case CPU_DOWN_FAILED_FROZEN: | |
fe5ed91d HS |
2278 | if (!mce_ignore_ce && check_interval) { |
2279 | t->expires = round_jiffies(jiffies + | |
82f7af09 | 2280 | per_cpu(mce_next_interval, cpu)); |
fe5ed91d HS |
2281 | add_timer_on(t, cpu); |
2282 | } | |
88ccbedd AK |
2283 | smp_call_function_single(cpu, mce_reenable_cpu, &action, 1); |
2284 | break; | |
2285 | case CPU_POST_DEAD: | |
2286 | /* intentionally ignoring frozen here */ | |
2287 | cmci_rediscover(cpu); | |
52d168e2 | 2288 | break; |
91c6d400 | 2289 | } |
bae19fe0 | 2290 | return NOTIFY_OK; |
91c6d400 AK |
2291 | } |
2292 | ||
1e35669d | 2293 | static struct notifier_block mce_cpu_notifier __cpuinitdata = { |
91c6d400 AK |
2294 | .notifier_call = mce_cpu_callback, |
2295 | }; | |
2296 | ||
cebe1820 | 2297 | static __init void mce_init_banks(void) |
0d7482e3 AK |
2298 | { |
2299 | int i; | |
2300 | ||
0d7482e3 | 2301 | for (i = 0; i < banks; i++) { |
cebe1820 | 2302 | struct mce_bank *b = &mce_banks[i]; |
8a25a2fd | 2303 | struct device_attribute *a = &b->attr; |
e9eee03e | 2304 | |
a07e4156 | 2305 | sysfs_attr_init(&a->attr); |
cebe1820 AK |
2306 | a->attr.name = b->attrname; |
2307 | snprintf(b->attrname, ATTR_LEN, "bank%d", i); | |
e9eee03e IM |
2308 | |
2309 | a->attr.mode = 0644; | |
2310 | a->show = show_bank; | |
2311 | a->store = set_bank; | |
0d7482e3 | 2312 | } |
0d7482e3 AK |
2313 | } |
2314 | ||
5e09954a | 2315 | static __init int mcheck_init_device(void) |
91c6d400 AK |
2316 | { |
2317 | int err; | |
2318 | int i = 0; | |
2319 | ||
1da177e4 LT |
2320 | if (!mce_available(&boot_cpu_data)) |
2321 | return -EIO; | |
0d7482e3 | 2322 | |
8a25a2fd | 2323 | zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL); |
996867d0 | 2324 | |
cebe1820 | 2325 | mce_init_banks(); |
0d7482e3 | 2326 | |
8a25a2fd | 2327 | err = subsys_system_register(&mce_subsys, NULL); |
d435d862 AM |
2328 | if (err) |
2329 | return err; | |
91c6d400 AK |
2330 | |
2331 | for_each_online_cpu(i) { | |
8a25a2fd | 2332 | err = mce_device_create(i); |
d435d862 AM |
2333 | if (err) |
2334 | return err; | |
91c6d400 AK |
2335 | } |
2336 | ||
f3c6ea1b | 2337 | register_syscore_ops(&mce_syscore_ops); |
be6b5a35 | 2338 | register_hotcpu_notifier(&mce_cpu_notifier); |
93b62c3c HS |
2339 | |
2340 | /* register character device /dev/mcelog */ | |
2341 | misc_register(&mce_chrdev_device); | |
e9eee03e | 2342 | |
1da177e4 | 2343 | return err; |
1da177e4 | 2344 | } |
5e09954a | 2345 | device_initcall(mcheck_init_device); |
a988d334 | 2346 | |
d7c3c9a6 AK |
2347 | /* |
2348 | * Old style boot options parsing. Only for compatibility. | |
2349 | */ | |
2350 | static int __init mcheck_disable(char *str) | |
2351 | { | |
2352 | mce_disabled = 1; | |
2353 | return 1; | |
2354 | } | |
2355 | __setup("nomce", mcheck_disable); | |
a988d334 | 2356 | |
5be9ed25 HY |
2357 | #ifdef CONFIG_DEBUG_FS |
2358 | struct dentry *mce_get_debugfs_dir(void) | |
a988d334 | 2359 | { |
5be9ed25 | 2360 | static struct dentry *dmce; |
a988d334 | 2361 | |
5be9ed25 HY |
2362 | if (!dmce) |
2363 | dmce = debugfs_create_dir("mce", NULL); | |
a988d334 | 2364 | |
5be9ed25 HY |
2365 | return dmce; |
2366 | } | |
a988d334 | 2367 | |
bf783f9f HY |
2368 | static void mce_reset(void) |
2369 | { | |
2370 | cpu_missing = 0; | |
2371 | atomic_set(&mce_fake_paniced, 0); | |
2372 | atomic_set(&mce_executing, 0); | |
2373 | atomic_set(&mce_callin, 0); | |
2374 | atomic_set(&global_nwo, 0); | |
2375 | } | |
a988d334 | 2376 | |
bf783f9f HY |
2377 | static int fake_panic_get(void *data, u64 *val) |
2378 | { | |
2379 | *val = fake_panic; | |
2380 | return 0; | |
a988d334 IM |
2381 | } |
2382 | ||
bf783f9f | 2383 | static int fake_panic_set(void *data, u64 val) |
a988d334 | 2384 | { |
bf783f9f HY |
2385 | mce_reset(); |
2386 | fake_panic = val; | |
2387 | return 0; | |
a988d334 | 2388 | } |
a988d334 | 2389 | |
bf783f9f HY |
2390 | DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get, |
2391 | fake_panic_set, "%llu\n"); | |
d7c3c9a6 | 2392 | |
5e09954a | 2393 | static int __init mcheck_debugfs_init(void) |
d7c3c9a6 | 2394 | { |
bf783f9f HY |
2395 | struct dentry *dmce, *ffake_panic; |
2396 | ||
2397 | dmce = mce_get_debugfs_dir(); | |
2398 | if (!dmce) | |
2399 | return -ENOMEM; | |
2400 | ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL, | |
2401 | &fake_panic_fops); | |
2402 | if (!ffake_panic) | |
2403 | return -ENOMEM; | |
2404 | ||
2405 | return 0; | |
d7c3c9a6 | 2406 | } |
5e09954a | 2407 | late_initcall(mcheck_debugfs_init); |
5be9ed25 | 2408 | #endif |