Commit | Line | Data |
---|---|---|
15d5f839 | 1 | /* |
3222b36f DZ |
2 | * Thermal throttle event support code (such as syslog messaging and rate |
3 | * limiting) that was factored out from x86_64 (mce_intel.c) and i386 (p4.c). | |
cb6f3c15 | 4 | * |
3222b36f DZ |
5 | * This allows consistent reporting of CPU thermal throttle events. |
6 | * | |
7 | * Maintains a counter in /sys that keeps track of the number of thermal | |
8 | * events, such that the user knows how bad the thermal problem might be | |
9 | * (since the logging to syslog and mcelog is rate limited). | |
15d5f839 DZ |
10 | * |
11 | * Author: Dmitriy Zavin (dmitriyz@google.com) | |
12 | * | |
13 | * Credits: Adapted from Zwane Mwaikambo's original code in mce_intel.c. | |
3222b36f | 14 | * Inspired by Ross Biro's and Al Borchers' counter code. |
15d5f839 | 15 | */ |
a65c88dd | 16 | #include <linux/interrupt.h> |
cb6f3c15 IM |
17 | #include <linux/notifier.h> |
18 | #include <linux/jiffies.h> | |
895287c0 | 19 | #include <linux/kernel.h> |
15d5f839 | 20 | #include <linux/percpu.h> |
69c60c88 | 21 | #include <linux/export.h> |
895287c0 HS |
22 | #include <linux/types.h> |
23 | #include <linux/init.h> | |
24 | #include <linux/smp.h> | |
15d5f839 | 25 | #include <linux/cpu.h> |
cb6f3c15 | 26 | |
895287c0 | 27 | #include <asm/processor.h> |
895287c0 | 28 | #include <asm/apic.h> |
a65c88dd HS |
29 | #include <asm/idle.h> |
30 | #include <asm/mce.h> | |
895287c0 | 31 | #include <asm/msr.h> |
cf910e83 | 32 | #include <asm/trace/irq_vectors.h> |
15d5f839 DZ |
33 | |
34 | /* How long to wait between reporting thermal events */ | |
cb6f3c15 | 35 | #define CHECK_INTERVAL (300 * HZ) |
15d5f839 | 36 | |
0199114c FY |
37 | #define THERMAL_THROTTLING_EVENT 0 |
38 | #define POWER_LIMIT_EVENT 1 | |
39 | ||
39676840 | 40 | /* |
0199114c | 41 | * Current thermal event state: |
39676840 | 42 | */ |
55d435a2 | 43 | struct _thermal_state { |
0199114c FY |
44 | bool new_event; |
45 | int event; | |
39676840 | 46 | u64 next_check; |
0199114c FY |
47 | unsigned long count; |
48 | unsigned long last_count; | |
39676840 | 49 | }; |
cb6f3c15 | 50 | |
55d435a2 | 51 | struct thermal_state { |
0199114c FY |
52 | struct _thermal_state core_throttle; |
53 | struct _thermal_state core_power_limit; | |
54 | struct _thermal_state package_throttle; | |
55 | struct _thermal_state package_power_limit; | |
9e76a97e D |
56 | struct _thermal_state core_thresh0; |
57 | struct _thermal_state core_thresh1; | |
55d435a2 FY |
58 | }; |
59 | ||
9e76a97e D |
60 | /* Callback to handle core threshold interrupts */ |
61 | int (*platform_thermal_notify)(__u64 msr_val); | |
f21bbec9 | 62 | EXPORT_SYMBOL(platform_thermal_notify); |
9e76a97e | 63 | |
39676840 IM |
64 | static DEFINE_PER_CPU(struct thermal_state, thermal_state); |
65 | ||
66 | static atomic_t therm_throt_en = ATOMIC_INIT(0); | |
3222b36f | 67 | |
a2202aa2 YW |
68 | static u32 lvtthmr_init __read_mostly; |
69 | ||
3222b36f | 70 | #ifdef CONFIG_SYSFS |
8a25a2fd KS |
71 | #define define_therm_throt_device_one_ro(_name) \ |
72 | static DEVICE_ATTR(_name, 0444, \ | |
73 | therm_throt_device_show_##_name, \ | |
55d435a2 | 74 | NULL) \ |
cb6f3c15 | 75 | |
8a25a2fd | 76 | #define define_therm_throt_device_show_func(event, name) \ |
39676840 | 77 | \ |
8a25a2fd KS |
78 | static ssize_t therm_throt_device_show_##event##_##name( \ |
79 | struct device *dev, \ | |
80 | struct device_attribute *attr, \ | |
39676840 | 81 | char *buf) \ |
cb6f3c15 IM |
82 | { \ |
83 | unsigned int cpu = dev->id; \ | |
84 | ssize_t ret; \ | |
85 | \ | |
86 | preempt_disable(); /* CPU hotplug */ \ | |
55d435a2 | 87 | if (cpu_online(cpu)) { \ |
cb6f3c15 | 88 | ret = sprintf(buf, "%lu\n", \ |
0199114c | 89 | per_cpu(thermal_state, cpu).event.name); \ |
55d435a2 | 90 | } else \ |
cb6f3c15 IM |
91 | ret = 0; \ |
92 | preempt_enable(); \ | |
93 | \ | |
94 | return ret; \ | |
3222b36f DZ |
95 | } |
96 | ||
8a25a2fd KS |
97 | define_therm_throt_device_show_func(core_throttle, count); |
98 | define_therm_throt_device_one_ro(core_throttle_count); | |
55d435a2 | 99 | |
8a25a2fd KS |
100 | define_therm_throt_device_show_func(core_power_limit, count); |
101 | define_therm_throt_device_one_ro(core_power_limit_count); | |
0199114c | 102 | |
8a25a2fd KS |
103 | define_therm_throt_device_show_func(package_throttle, count); |
104 | define_therm_throt_device_one_ro(package_throttle_count); | |
3222b36f | 105 | |
8a25a2fd KS |
106 | define_therm_throt_device_show_func(package_power_limit, count); |
107 | define_therm_throt_device_one_ro(package_power_limit_count); | |
0199114c | 108 | |
3222b36f | 109 | static struct attribute *thermal_throttle_attrs[] = { |
8a25a2fd | 110 | &dev_attr_core_throttle_count.attr, |
3222b36f DZ |
111 | NULL |
112 | }; | |
113 | ||
0199114c | 114 | static struct attribute_group thermal_attr_group = { |
cb6f3c15 IM |
115 | .attrs = thermal_throttle_attrs, |
116 | .name = "thermal_throttle" | |
3222b36f DZ |
117 | }; |
118 | #endif /* CONFIG_SYSFS */ | |
15d5f839 | 119 | |
0199114c FY |
120 | #define CORE_LEVEL 0 |
121 | #define PACKAGE_LEVEL 1 | |
122 | ||
15d5f839 | 123 | /*** |
3222b36f | 124 | * therm_throt_process - Process thermal throttling event from interrupt |
15d5f839 DZ |
125 | * @curr: Whether the condition is current or not (boolean), since the |
126 | * thermal interrupt normally gets called both when the thermal | |
127 | * event begins and once the event has ended. | |
128 | * | |
3222b36f | 129 | * This function is called by the thermal interrupt after the |
15d5f839 DZ |
130 | * IRQ has been acknowledged. |
131 | * | |
132 | * It will take care of rate limiting and printing messages to the syslog. | |
133 | * | |
134 | * Returns: 0 : Event should NOT be further logged, i.e. still in | |
135 | * "timeout" from previous log message. | |
136 | * 1 : Event should be logged further, and a message has been | |
137 | * printed to the syslog. | |
138 | */ | |
0199114c | 139 | static int therm_throt_process(bool new_event, int event, int level) |
15d5f839 | 140 | { |
55d435a2 | 141 | struct _thermal_state *state; |
0199114c FY |
142 | unsigned int this_cpu = smp_processor_id(); |
143 | bool old_event; | |
39676840 | 144 | u64 now; |
0199114c | 145 | struct thermal_state *pstate = &per_cpu(thermal_state, this_cpu); |
39676840 | 146 | |
39676840 | 147 | now = get_jiffies_64(); |
0199114c FY |
148 | if (level == CORE_LEVEL) { |
149 | if (event == THERMAL_THROTTLING_EVENT) | |
150 | state = &pstate->core_throttle; | |
151 | else if (event == POWER_LIMIT_EVENT) | |
152 | state = &pstate->core_power_limit; | |
153 | else | |
154 | return 0; | |
155 | } else if (level == PACKAGE_LEVEL) { | |
156 | if (event == THERMAL_THROTTLING_EVENT) | |
157 | state = &pstate->package_throttle; | |
158 | else if (event == POWER_LIMIT_EVENT) | |
159 | state = &pstate->package_power_limit; | |
160 | else | |
161 | return 0; | |
162 | } else | |
163 | return 0; | |
39676840 | 164 | |
0199114c FY |
165 | old_event = state->new_event; |
166 | state->new_event = new_event; | |
15d5f839 | 167 | |
0199114c FY |
168 | if (new_event) |
169 | state->count++; | |
3222b36f | 170 | |
b417c9fd | 171 | if (time_before64(now, state->next_check) && |
0199114c | 172 | state->count != state->last_count) |
15d5f839 DZ |
173 | return 0; |
174 | ||
39676840 | 175 | state->next_check = now + CHECK_INTERVAL; |
0199114c | 176 | state->last_count = state->count; |
15d5f839 DZ |
177 | |
178 | /* if we just entered the thermal event */ | |
0199114c FY |
179 | if (new_event) { |
180 | if (event == THERMAL_THROTTLING_EVENT) | |
181 | printk(KERN_CRIT "CPU%d: %s temperature above threshold, cpu clock throttled (total events = %lu)\n", | |
182 | this_cpu, | |
183 | level == CORE_LEVEL ? "Core" : "Package", | |
184 | state->count); | |
185 | else | |
186 | printk(KERN_CRIT "CPU%d: %s power limit notification (total events = %lu)\n", | |
187 | this_cpu, | |
188 | level == CORE_LEVEL ? "Core" : "Package", | |
189 | state->count); | |
4e5c25d4 HD |
190 | return 1; |
191 | } | |
0199114c FY |
192 | if (old_event) { |
193 | if (event == THERMAL_THROTTLING_EVENT) | |
194 | printk(KERN_INFO "CPU%d: %s temperature/speed normal\n", | |
195 | this_cpu, | |
196 | level == CORE_LEVEL ? "Core" : "Package"); | |
197 | else | |
198 | printk(KERN_INFO "CPU%d: %s power limit normal\n", | |
199 | this_cpu, | |
200 | level == CORE_LEVEL ? "Core" : "Package"); | |
4e5c25d4 | 201 | return 1; |
15d5f839 DZ |
202 | } |
203 | ||
4e5c25d4 | 204 | return 0; |
15d5f839 | 205 | } |
3222b36f | 206 | |
9e76a97e D |
207 | static int thresh_event_valid(int event) |
208 | { | |
209 | struct _thermal_state *state; | |
210 | unsigned int this_cpu = smp_processor_id(); | |
211 | struct thermal_state *pstate = &per_cpu(thermal_state, this_cpu); | |
212 | u64 now = get_jiffies_64(); | |
213 | ||
214 | state = (event == 0) ? &pstate->core_thresh0 : &pstate->core_thresh1; | |
215 | ||
216 | if (time_before64(now, state->next_check)) | |
217 | return 0; | |
218 | ||
219 | state->next_check = now + CHECK_INTERVAL; | |
220 | return 1; | |
221 | } | |
222 | ||
3222b36f | 223 | #ifdef CONFIG_SYSFS |
cb6f3c15 | 224 | /* Add/Remove thermal_throttle interface for CPU device: */ |
8a25a2fd | 225 | static __cpuinit int thermal_throttle_add_dev(struct device *dev, |
51e3c1b5 | 226 | unsigned int cpu) |
3222b36f | 227 | { |
55d435a2 | 228 | int err; |
51e3c1b5 | 229 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
55d435a2 | 230 | |
8a25a2fd | 231 | err = sysfs_create_group(&dev->kobj, &thermal_attr_group); |
55d435a2 FY |
232 | if (err) |
233 | return err; | |
234 | ||
0199114c | 235 | if (cpu_has(c, X86_FEATURE_PLN)) |
8a25a2fd KS |
236 | err = sysfs_add_file_to_group(&dev->kobj, |
237 | &dev_attr_core_power_limit_count.attr, | |
0199114c | 238 | thermal_attr_group.name); |
b62be8ea | 239 | if (cpu_has(c, X86_FEATURE_PTS)) { |
8a25a2fd KS |
240 | err = sysfs_add_file_to_group(&dev->kobj, |
241 | &dev_attr_package_throttle_count.attr, | |
0199114c FY |
242 | thermal_attr_group.name); |
243 | if (cpu_has(c, X86_FEATURE_PLN)) | |
8a25a2fd KS |
244 | err = sysfs_add_file_to_group(&dev->kobj, |
245 | &dev_attr_package_power_limit_count.attr, | |
0199114c | 246 | thermal_attr_group.name); |
b62be8ea | 247 | } |
55d435a2 FY |
248 | |
249 | return err; | |
3222b36f DZ |
250 | } |
251 | ||
8a25a2fd | 252 | static __cpuinit void thermal_throttle_remove_dev(struct device *dev) |
3222b36f | 253 | { |
8a25a2fd | 254 | sysfs_remove_group(&dev->kobj, &thermal_attr_group); |
3222b36f DZ |
255 | } |
256 | ||
cb6f3c15 | 257 | /* Mutex protecting device creation against CPU hotplug: */ |
3222b36f DZ |
258 | static DEFINE_MUTEX(therm_cpu_lock); |
259 | ||
260 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ | |
cb6f3c15 IM |
261 | static __cpuinit int |
262 | thermal_throttle_cpu_callback(struct notifier_block *nfb, | |
263 | unsigned long action, | |
264 | void *hcpu) | |
3222b36f DZ |
265 | { |
266 | unsigned int cpu = (unsigned long)hcpu; | |
8a25a2fd | 267 | struct device *dev; |
c7e38a9c | 268 | int err = 0; |
3222b36f | 269 | |
8a25a2fd | 270 | dev = get_cpu_device(cpu); |
cb6f3c15 | 271 | |
3222b36f | 272 | switch (action) { |
c7e38a9c AM |
273 | case CPU_UP_PREPARE: |
274 | case CPU_UP_PREPARE_FROZEN: | |
38ef6d19 | 275 | mutex_lock(&therm_cpu_lock); |
8a25a2fd | 276 | err = thermal_throttle_add_dev(dev, cpu); |
38ef6d19 | 277 | mutex_unlock(&therm_cpu_lock); |
6569345a | 278 | WARN_ON(err); |
3222b36f | 279 | break; |
c7e38a9c AM |
280 | case CPU_UP_CANCELED: |
281 | case CPU_UP_CANCELED_FROZEN: | |
3222b36f | 282 | case CPU_DEAD: |
8bb78442 | 283 | case CPU_DEAD_FROZEN: |
38ef6d19 | 284 | mutex_lock(&therm_cpu_lock); |
8a25a2fd | 285 | thermal_throttle_remove_dev(dev); |
38ef6d19 | 286 | mutex_unlock(&therm_cpu_lock); |
3222b36f DZ |
287 | break; |
288 | } | |
a94247e7 | 289 | return notifier_from_errno(err); |
3222b36f DZ |
290 | } |
291 | ||
25d1b516 | 292 | static struct notifier_block thermal_throttle_cpu_notifier __cpuinitdata = |
3222b36f DZ |
293 | { |
294 | .notifier_call = thermal_throttle_cpu_callback, | |
295 | }; | |
3222b36f DZ |
296 | |
297 | static __init int thermal_throttle_init_device(void) | |
298 | { | |
299 | unsigned int cpu = 0; | |
6569345a | 300 | int err; |
3222b36f DZ |
301 | |
302 | if (!atomic_read(&therm_throt_en)) | |
303 | return 0; | |
304 | ||
305 | register_hotcpu_notifier(&thermal_throttle_cpu_notifier); | |
306 | ||
307 | #ifdef CONFIG_HOTPLUG_CPU | |
308 | mutex_lock(&therm_cpu_lock); | |
309 | #endif | |
310 | /* connect live CPUs to sysfs */ | |
6569345a | 311 | for_each_online_cpu(cpu) { |
8a25a2fd | 312 | err = thermal_throttle_add_dev(get_cpu_device(cpu), cpu); |
6569345a SH |
313 | WARN_ON(err); |
314 | } | |
3222b36f DZ |
315 | #ifdef CONFIG_HOTPLUG_CPU |
316 | mutex_unlock(&therm_cpu_lock); | |
317 | #endif | |
318 | ||
319 | return 0; | |
320 | } | |
3222b36f | 321 | device_initcall(thermal_throttle_init_device); |
a65c88dd | 322 | |
3222b36f | 323 | #endif /* CONFIG_SYSFS */ |
a65c88dd | 324 | |
9e76a97e D |
325 | static void notify_thresholds(__u64 msr_val) |
326 | { | |
327 | /* check whether the interrupt handler is defined; | |
328 | * otherwise simply return | |
329 | */ | |
330 | if (!platform_thermal_notify) | |
331 | return; | |
332 | ||
333 | /* lower threshold reached */ | |
334 | if ((msr_val & THERM_LOG_THRESHOLD0) && thresh_event_valid(0)) | |
335 | platform_thermal_notify(msr_val); | |
336 | /* higher threshold reached */ | |
337 | if ((msr_val & THERM_LOG_THRESHOLD1) && thresh_event_valid(1)) | |
338 | platform_thermal_notify(msr_val); | |
339 | } | |
340 | ||
a65c88dd | 341 | /* Thermal transition interrupt handler */ |
8363fc82 | 342 | static void intel_thermal_interrupt(void) |
a65c88dd HS |
343 | { |
344 | __u64 msr_val; | |
345 | ||
346 | rdmsrl(MSR_IA32_THERM_STATUS, msr_val); | |
0199114c | 347 | |
9e76a97e D |
348 | /* Check for violation of core thermal thresholds*/ |
349 | notify_thresholds(msr_val); | |
350 | ||
55d435a2 | 351 | if (therm_throt_process(msr_val & THERM_STATUS_PROCHOT, |
0199114c | 352 | THERMAL_THROTTLING_EVENT, |
55d435a2 | 353 | CORE_LEVEL) != 0) |
29e9bf18 | 354 | mce_log_therm_throt_event(msr_val); |
0199114c | 355 | |
fe504213 | 356 | if (this_cpu_has(X86_FEATURE_PLN)) |
29e9bf18 | 357 | therm_throt_process(msr_val & THERM_STATUS_POWER_LIMIT, |
0199114c | 358 | POWER_LIMIT_EVENT, |
29e9bf18 | 359 | CORE_LEVEL); |
55d435a2 | 360 | |
fe504213 | 361 | if (this_cpu_has(X86_FEATURE_PTS)) { |
55d435a2 | 362 | rdmsrl(MSR_IA32_PACKAGE_THERM_STATUS, msr_val); |
29e9bf18 | 363 | therm_throt_process(msr_val & PACKAGE_THERM_STATUS_PROCHOT, |
0199114c | 364 | THERMAL_THROTTLING_EVENT, |
29e9bf18 | 365 | PACKAGE_LEVEL); |
fe504213 | 366 | if (this_cpu_has(X86_FEATURE_PLN)) |
29e9bf18 | 367 | therm_throt_process(msr_val & |
0199114c FY |
368 | PACKAGE_THERM_STATUS_POWER_LIMIT, |
369 | POWER_LIMIT_EVENT, | |
29e9bf18 | 370 | PACKAGE_LEVEL); |
55d435a2 | 371 | } |
a65c88dd HS |
372 | } |
373 | ||
374 | static void unexpected_thermal_interrupt(void) | |
375 | { | |
592091c0 | 376 | printk(KERN_ERR "CPU%d: Unexpected LVT thermal interrupt!\n", |
a65c88dd | 377 | smp_processor_id()); |
a65c88dd HS |
378 | } |
379 | ||
380 | static void (*smp_thermal_vector)(void) = unexpected_thermal_interrupt; | |
381 | ||
eddc0e92 | 382 | static inline void __smp_thermal_interrupt(void) |
a65c88dd | 383 | { |
a65c88dd HS |
384 | inc_irq_stat(irq_thermal_count); |
385 | smp_thermal_vector(); | |
eddc0e92 SA |
386 | } |
387 | ||
388 | asmlinkage void smp_thermal_interrupt(struct pt_regs *regs) | |
389 | { | |
390 | entering_irq(); | |
391 | __smp_thermal_interrupt(); | |
392 | exiting_ack_irq(); | |
a65c88dd HS |
393 | } |
394 | ||
cf910e83 SA |
395 | asmlinkage void smp_trace_thermal_interrupt(struct pt_regs *regs) |
396 | { | |
397 | entering_irq(); | |
398 | trace_thermal_apic_entry(THERMAL_APIC_VECTOR); | |
399 | __smp_thermal_interrupt(); | |
400 | trace_thermal_apic_exit(THERMAL_APIC_VECTOR); | |
401 | exiting_ack_irq(); | |
402 | } | |
403 | ||
70fe4407 HS |
404 | /* Thermal monitoring depends on APIC, ACPI and clock modulation */ |
405 | static int intel_thermal_supported(struct cpuinfo_x86 *c) | |
406 | { | |
407 | if (!cpu_has_apic) | |
408 | return 0; | |
409 | if (!cpu_has(c, X86_FEATURE_ACPI) || !cpu_has(c, X86_FEATURE_ACC)) | |
410 | return 0; | |
411 | return 1; | |
412 | } | |
413 | ||
ce6b5d76 | 414 | void __init mcheck_intel_therm_init(void) |
a2202aa2 YW |
415 | { |
416 | /* | |
417 | * This function is only called on boot CPU. Save the init thermal | |
418 | * LVT value on BSP and use that value to restore APs' thermal LVT | |
419 | * entry BIOS programmed later | |
420 | */ | |
70fe4407 | 421 | if (intel_thermal_supported(&boot_cpu_data)) |
a2202aa2 YW |
422 | lvtthmr_init = apic_read(APIC_LVTTHMR); |
423 | } | |
424 | ||
cffd377e | 425 | void intel_init_thermal(struct cpuinfo_x86 *c) |
895287c0 HS |
426 | { |
427 | unsigned int cpu = smp_processor_id(); | |
428 | int tm2 = 0; | |
429 | u32 l, h; | |
430 | ||
70fe4407 | 431 | if (!intel_thermal_supported(c)) |
895287c0 HS |
432 | return; |
433 | ||
434 | /* | |
435 | * First check if its enabled already, in which case there might | |
436 | * be some SMM goo which handles it, so we can't even put a handler | |
437 | * since it might be delivered via SMI already: | |
438 | */ | |
439 | rdmsr(MSR_IA32_MISC_ENABLE, l, h); | |
a2202aa2 | 440 | |
e503f9e4 | 441 | h = lvtthmr_init; |
a2202aa2 YW |
442 | /* |
443 | * The initial value of thermal LVT entries on all APs always reads | |
444 | * 0x10000 because APs are woken up by BSP issuing INIT-SIPI-SIPI | |
445 | * sequence to them and LVT registers are reset to 0s except for | |
446 | * the mask bits which are set to 1s when APs receive INIT IPI. | |
e503f9e4 YS |
447 | * If BIOS takes over the thermal interrupt and sets its interrupt |
448 | * delivery mode to SMI (not fixed), it restores the value that the | |
449 | * BIOS has programmed on AP based on BSP's info we saved since BIOS | |
450 | * is always setting the same value for all threads/cores. | |
a2202aa2 | 451 | */ |
e503f9e4 YS |
452 | if ((h & APIC_DM_FIXED_MASK) != APIC_DM_FIXED) |
453 | apic_write(APIC_LVTTHMR, lvtthmr_init); | |
a2202aa2 | 454 | |
a2202aa2 | 455 | |
895287c0 HS |
456 | if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) { |
457 | printk(KERN_DEBUG | |
458 | "CPU%d: Thermal monitoring handled by SMI\n", cpu); | |
459 | return; | |
460 | } | |
461 | ||
895287c0 HS |
462 | /* Check whether a vector already exists */ |
463 | if (h & APIC_VECTOR_MASK) { | |
464 | printk(KERN_DEBUG | |
465 | "CPU%d: Thermal LVT vector (%#x) already installed\n", | |
466 | cpu, (h & APIC_VECTOR_MASK)); | |
467 | return; | |
468 | } | |
469 | ||
f3a0867b BZ |
470 | /* early Pentium M models use different method for enabling TM2 */ |
471 | if (cpu_has(c, X86_FEATURE_TM2)) { | |
472 | if (c->x86 == 6 && (c->x86_model == 9 || c->x86_model == 13)) { | |
473 | rdmsr(MSR_THERM2_CTL, l, h); | |
474 | if (l & MSR_THERM2_CTL_TM_SELECT) | |
475 | tm2 = 1; | |
476 | } else if (l & MSR_IA32_MISC_ENABLE_TM2) | |
477 | tm2 = 1; | |
478 | } | |
479 | ||
895287c0 HS |
480 | /* We'll mask the thermal vector in the lapic till we're ready: */ |
481 | h = THERMAL_APIC_VECTOR | APIC_DM_FIXED | APIC_LVT_MASKED; | |
482 | apic_write(APIC_LVTTHMR, h); | |
483 | ||
484 | rdmsr(MSR_IA32_THERM_INTERRUPT, l, h); | |
0199114c FY |
485 | if (cpu_has(c, X86_FEATURE_PLN)) |
486 | wrmsr(MSR_IA32_THERM_INTERRUPT, | |
487 | l | (THERM_INT_LOW_ENABLE | |
488 | | THERM_INT_HIGH_ENABLE | THERM_INT_PLN_ENABLE), h); | |
489 | else | |
490 | wrmsr(MSR_IA32_THERM_INTERRUPT, | |
491 | l | (THERM_INT_LOW_ENABLE | THERM_INT_HIGH_ENABLE), h); | |
895287c0 | 492 | |
55d435a2 FY |
493 | if (cpu_has(c, X86_FEATURE_PTS)) { |
494 | rdmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h); | |
0199114c FY |
495 | if (cpu_has(c, X86_FEATURE_PLN)) |
496 | wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, | |
497 | l | (PACKAGE_THERM_INT_LOW_ENABLE | |
498 | | PACKAGE_THERM_INT_HIGH_ENABLE | |
499 | | PACKAGE_THERM_INT_PLN_ENABLE), h); | |
500 | else | |
501 | wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, | |
502 | l | (PACKAGE_THERM_INT_LOW_ENABLE | |
503 | | PACKAGE_THERM_INT_HIGH_ENABLE), h); | |
55d435a2 FY |
504 | } |
505 | ||
8363fc82 | 506 | smp_thermal_vector = intel_thermal_interrupt; |
895287c0 HS |
507 | |
508 | rdmsr(MSR_IA32_MISC_ENABLE, l, h); | |
509 | wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h); | |
510 | ||
511 | /* Unmask the thermal vector: */ | |
512 | l = apic_read(APIC_LVTTHMR); | |
513 | apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED); | |
514 | ||
2eaad1fd MT |
515 | printk_once(KERN_INFO "CPU0: Thermal monitoring enabled (%s)\n", |
516 | tm2 ? "TM2" : "TM1"); | |
895287c0 HS |
517 | |
518 | /* enable thermal throttle processing */ | |
519 | atomic_set(&therm_throt_en, 1); | |
520 | } |