Commit | Line | Data |
---|---|---|
15d5f839 | 1 | /* |
3222b36f DZ |
2 | * Thermal throttle event support code (such as syslog messaging and rate |
3 | * limiting) that was factored out from x86_64 (mce_intel.c) and i386 (p4.c). | |
cb6f3c15 | 4 | * |
3222b36f DZ |
5 | * This allows consistent reporting of CPU thermal throttle events. |
6 | * | |
7 | * Maintains a counter in /sys that keeps track of the number of thermal | |
8 | * events, such that the user knows how bad the thermal problem might be | |
9 | * (since the logging to syslog and mcelog is rate limited). | |
15d5f839 DZ |
10 | * |
11 | * Author: Dmitriy Zavin (dmitriyz@google.com) | |
12 | * | |
13 | * Credits: Adapted from Zwane Mwaikambo's original code in mce_intel.c. | |
3222b36f | 14 | * Inspired by Ross Biro's and Al Borchers' counter code. |
15d5f839 | 15 | */ |
a65c88dd | 16 | #include <linux/interrupt.h> |
cb6f3c15 IM |
17 | #include <linux/notifier.h> |
18 | #include <linux/jiffies.h> | |
895287c0 | 19 | #include <linux/kernel.h> |
15d5f839 | 20 | #include <linux/percpu.h> |
3222b36f | 21 | #include <linux/sysdev.h> |
895287c0 HS |
22 | #include <linux/types.h> |
23 | #include <linux/init.h> | |
24 | #include <linux/smp.h> | |
15d5f839 | 25 | #include <linux/cpu.h> |
cb6f3c15 | 26 | |
895287c0 HS |
27 | #include <asm/processor.h> |
28 | #include <asm/system.h> | |
29 | #include <asm/apic.h> | |
a65c88dd HS |
30 | #include <asm/idle.h> |
31 | #include <asm/mce.h> | |
895287c0 | 32 | #include <asm/msr.h> |
15d5f839 DZ |
33 | |
34 | /* How long to wait between reporting thermal events */ | |
cb6f3c15 | 35 | #define CHECK_INTERVAL (300 * HZ) |
15d5f839 | 36 | |
0199114c FY |
37 | #define THERMAL_THROTTLING_EVENT 0 |
38 | #define POWER_LIMIT_EVENT 1 | |
39 | ||
39676840 | 40 | /* |
0199114c | 41 | * Current thermal event state: |
39676840 | 42 | */ |
55d435a2 | 43 | struct _thermal_state { |
0199114c FY |
44 | bool new_event; |
45 | int event; | |
39676840 | 46 | u64 next_check; |
0199114c FY |
47 | unsigned long count; |
48 | unsigned long last_count; | |
39676840 | 49 | }; |
cb6f3c15 | 50 | |
55d435a2 | 51 | struct thermal_state { |
0199114c FY |
52 | struct _thermal_state core_throttle; |
53 | struct _thermal_state core_power_limit; | |
54 | struct _thermal_state package_throttle; | |
55 | struct _thermal_state package_power_limit; | |
9e76a97e D |
56 | struct _thermal_state core_thresh0; |
57 | struct _thermal_state core_thresh1; | |
55d435a2 FY |
58 | }; |
59 | ||
9e76a97e D |
60 | /* Callback to handle core threshold interrupts */ |
61 | int (*platform_thermal_notify)(__u64 msr_val); | |
f21bbec9 | 62 | EXPORT_SYMBOL(platform_thermal_notify); |
9e76a97e | 63 | |
39676840 IM |
64 | static DEFINE_PER_CPU(struct thermal_state, thermal_state); |
65 | ||
66 | static atomic_t therm_throt_en = ATOMIC_INIT(0); | |
3222b36f | 67 | |
a2202aa2 YW |
68 | static u32 lvtthmr_init __read_mostly; |
69 | ||
3222b36f | 70 | #ifdef CONFIG_SYSFS |
cb6f3c15 | 71 | #define define_therm_throt_sysdev_one_ro(_name) \ |
55d435a2 FY |
72 | static SYSDEV_ATTR(_name, 0444, \ |
73 | therm_throt_sysdev_show_##_name, \ | |
74 | NULL) \ | |
cb6f3c15 | 75 | |
0199114c | 76 | #define define_therm_throt_sysdev_show_func(event, name) \ |
39676840 | 77 | \ |
0199114c | 78 | static ssize_t therm_throt_sysdev_show_##event##_##name( \ |
39676840 IM |
79 | struct sys_device *dev, \ |
80 | struct sysdev_attribute *attr, \ | |
81 | char *buf) \ | |
cb6f3c15 IM |
82 | { \ |
83 | unsigned int cpu = dev->id; \ | |
84 | ssize_t ret; \ | |
85 | \ | |
86 | preempt_disable(); /* CPU hotplug */ \ | |
55d435a2 | 87 | if (cpu_online(cpu)) { \ |
cb6f3c15 | 88 | ret = sprintf(buf, "%lu\n", \ |
0199114c | 89 | per_cpu(thermal_state, cpu).event.name); \ |
55d435a2 | 90 | } else \ |
cb6f3c15 IM |
91 | ret = 0; \ |
92 | preempt_enable(); \ | |
93 | \ | |
94 | return ret; \ | |
3222b36f DZ |
95 | } |
96 | ||
0199114c | 97 | define_therm_throt_sysdev_show_func(core_throttle, count); |
55d435a2 FY |
98 | define_therm_throt_sysdev_one_ro(core_throttle_count); |
99 | ||
0199114c FY |
100 | define_therm_throt_sysdev_show_func(core_power_limit, count); |
101 | define_therm_throt_sysdev_one_ro(core_power_limit_count); | |
102 | ||
103 | define_therm_throt_sysdev_show_func(package_throttle, count); | |
55d435a2 | 104 | define_therm_throt_sysdev_one_ro(package_throttle_count); |
3222b36f | 105 | |
0199114c FY |
106 | define_therm_throt_sysdev_show_func(package_power_limit, count); |
107 | define_therm_throt_sysdev_one_ro(package_power_limit_count); | |
108 | ||
3222b36f | 109 | static struct attribute *thermal_throttle_attrs[] = { |
55d435a2 | 110 | &attr_core_throttle_count.attr, |
3222b36f DZ |
111 | NULL |
112 | }; | |
113 | ||
0199114c | 114 | static struct attribute_group thermal_attr_group = { |
cb6f3c15 IM |
115 | .attrs = thermal_throttle_attrs, |
116 | .name = "thermal_throttle" | |
3222b36f DZ |
117 | }; |
118 | #endif /* CONFIG_SYSFS */ | |
15d5f839 | 119 | |
0199114c FY |
120 | #define CORE_LEVEL 0 |
121 | #define PACKAGE_LEVEL 1 | |
122 | ||
15d5f839 | 123 | /*** |
3222b36f | 124 | * therm_throt_process - Process thermal throttling event from interrupt |
15d5f839 DZ |
125 | * @curr: Whether the condition is current or not (boolean), since the |
126 | * thermal interrupt normally gets called both when the thermal | |
127 | * event begins and once the event has ended. | |
128 | * | |
3222b36f | 129 | * This function is called by the thermal interrupt after the |
15d5f839 DZ |
130 | * IRQ has been acknowledged. |
131 | * | |
132 | * It will take care of rate limiting and printing messages to the syslog. | |
133 | * | |
134 | * Returns: 0 : Event should NOT be further logged, i.e. still in | |
135 | * "timeout" from previous log message. | |
136 | * 1 : Event should be logged further, and a message has been | |
137 | * printed to the syslog. | |
138 | */ | |
0199114c | 139 | static int therm_throt_process(bool new_event, int event, int level) |
15d5f839 | 140 | { |
55d435a2 | 141 | struct _thermal_state *state; |
0199114c FY |
142 | unsigned int this_cpu = smp_processor_id(); |
143 | bool old_event; | |
39676840 | 144 | u64 now; |
0199114c | 145 | struct thermal_state *pstate = &per_cpu(thermal_state, this_cpu); |
39676840 | 146 | |
39676840 | 147 | now = get_jiffies_64(); |
0199114c FY |
148 | if (level == CORE_LEVEL) { |
149 | if (event == THERMAL_THROTTLING_EVENT) | |
150 | state = &pstate->core_throttle; | |
151 | else if (event == POWER_LIMIT_EVENT) | |
152 | state = &pstate->core_power_limit; | |
153 | else | |
154 | return 0; | |
155 | } else if (level == PACKAGE_LEVEL) { | |
156 | if (event == THERMAL_THROTTLING_EVENT) | |
157 | state = &pstate->package_throttle; | |
158 | else if (event == POWER_LIMIT_EVENT) | |
159 | state = &pstate->package_power_limit; | |
160 | else | |
161 | return 0; | |
162 | } else | |
163 | return 0; | |
39676840 | 164 | |
0199114c FY |
165 | old_event = state->new_event; |
166 | state->new_event = new_event; | |
15d5f839 | 167 | |
0199114c FY |
168 | if (new_event) |
169 | state->count++; | |
3222b36f | 170 | |
b417c9fd | 171 | if (time_before64(now, state->next_check) && |
0199114c | 172 | state->count != state->last_count) |
15d5f839 DZ |
173 | return 0; |
174 | ||
39676840 | 175 | state->next_check = now + CHECK_INTERVAL; |
0199114c | 176 | state->last_count = state->count; |
15d5f839 DZ |
177 | |
178 | /* if we just entered the thermal event */ | |
0199114c FY |
179 | if (new_event) { |
180 | if (event == THERMAL_THROTTLING_EVENT) | |
181 | printk(KERN_CRIT "CPU%d: %s temperature above threshold, cpu clock throttled (total events = %lu)\n", | |
182 | this_cpu, | |
183 | level == CORE_LEVEL ? "Core" : "Package", | |
184 | state->count); | |
185 | else | |
186 | printk(KERN_CRIT "CPU%d: %s power limit notification (total events = %lu)\n", | |
187 | this_cpu, | |
188 | level == CORE_LEVEL ? "Core" : "Package", | |
189 | state->count); | |
3222b36f | 190 | |
15d5f839 | 191 | add_taint(TAINT_MACHINE_CHECK); |
4e5c25d4 HD |
192 | return 1; |
193 | } | |
0199114c FY |
194 | if (old_event) { |
195 | if (event == THERMAL_THROTTLING_EVENT) | |
196 | printk(KERN_INFO "CPU%d: %s temperature/speed normal\n", | |
197 | this_cpu, | |
198 | level == CORE_LEVEL ? "Core" : "Package"); | |
199 | else | |
200 | printk(KERN_INFO "CPU%d: %s power limit normal\n", | |
201 | this_cpu, | |
202 | level == CORE_LEVEL ? "Core" : "Package"); | |
4e5c25d4 | 203 | return 1; |
15d5f839 DZ |
204 | } |
205 | ||
4e5c25d4 | 206 | return 0; |
15d5f839 | 207 | } |
3222b36f | 208 | |
9e76a97e D |
209 | static int thresh_event_valid(int event) |
210 | { | |
211 | struct _thermal_state *state; | |
212 | unsigned int this_cpu = smp_processor_id(); | |
213 | struct thermal_state *pstate = &per_cpu(thermal_state, this_cpu); | |
214 | u64 now = get_jiffies_64(); | |
215 | ||
216 | state = (event == 0) ? &pstate->core_thresh0 : &pstate->core_thresh1; | |
217 | ||
218 | if (time_before64(now, state->next_check)) | |
219 | return 0; | |
220 | ||
221 | state->next_check = now + CHECK_INTERVAL; | |
222 | return 1; | |
223 | } | |
224 | ||
3222b36f | 225 | #ifdef CONFIG_SYSFS |
cb6f3c15 | 226 | /* Add/Remove thermal_throttle interface for CPU device: */ |
51e3c1b5 SS |
227 | static __cpuinit int thermal_throttle_add_dev(struct sys_device *sys_dev, |
228 | unsigned int cpu) | |
3222b36f | 229 | { |
55d435a2 | 230 | int err; |
51e3c1b5 | 231 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
55d435a2 | 232 | |
0199114c | 233 | err = sysfs_create_group(&sys_dev->kobj, &thermal_attr_group); |
55d435a2 FY |
234 | if (err) |
235 | return err; | |
236 | ||
0199114c FY |
237 | if (cpu_has(c, X86_FEATURE_PLN)) |
238 | err = sysfs_add_file_to_group(&sys_dev->kobj, | |
239 | &attr_core_power_limit_count.attr, | |
240 | thermal_attr_group.name); | |
b62be8ea | 241 | if (cpu_has(c, X86_FEATURE_PTS)) { |
55d435a2 FY |
242 | err = sysfs_add_file_to_group(&sys_dev->kobj, |
243 | &attr_package_throttle_count.attr, | |
0199114c FY |
244 | thermal_attr_group.name); |
245 | if (cpu_has(c, X86_FEATURE_PLN)) | |
246 | err = sysfs_add_file_to_group(&sys_dev->kobj, | |
247 | &attr_package_power_limit_count.attr, | |
248 | thermal_attr_group.name); | |
b62be8ea | 249 | } |
55d435a2 FY |
250 | |
251 | return err; | |
3222b36f DZ |
252 | } |
253 | ||
6569345a | 254 | static __cpuinit void thermal_throttle_remove_dev(struct sys_device *sys_dev) |
3222b36f | 255 | { |
0199114c | 256 | sysfs_remove_group(&sys_dev->kobj, &thermal_attr_group); |
3222b36f DZ |
257 | } |
258 | ||
cb6f3c15 | 259 | /* Mutex protecting device creation against CPU hotplug: */ |
3222b36f DZ |
260 | static DEFINE_MUTEX(therm_cpu_lock); |
261 | ||
262 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ | |
cb6f3c15 IM |
263 | static __cpuinit int |
264 | thermal_throttle_cpu_callback(struct notifier_block *nfb, | |
265 | unsigned long action, | |
266 | void *hcpu) | |
3222b36f DZ |
267 | { |
268 | unsigned int cpu = (unsigned long)hcpu; | |
269 | struct sys_device *sys_dev; | |
c7e38a9c | 270 | int err = 0; |
3222b36f DZ |
271 | |
272 | sys_dev = get_cpu_sysdev(cpu); | |
cb6f3c15 | 273 | |
3222b36f | 274 | switch (action) { |
c7e38a9c AM |
275 | case CPU_UP_PREPARE: |
276 | case CPU_UP_PREPARE_FROZEN: | |
38ef6d19 | 277 | mutex_lock(&therm_cpu_lock); |
51e3c1b5 | 278 | err = thermal_throttle_add_dev(sys_dev, cpu); |
38ef6d19 | 279 | mutex_unlock(&therm_cpu_lock); |
6569345a | 280 | WARN_ON(err); |
3222b36f | 281 | break; |
c7e38a9c AM |
282 | case CPU_UP_CANCELED: |
283 | case CPU_UP_CANCELED_FROZEN: | |
3222b36f | 284 | case CPU_DEAD: |
8bb78442 | 285 | case CPU_DEAD_FROZEN: |
38ef6d19 | 286 | mutex_lock(&therm_cpu_lock); |
3222b36f | 287 | thermal_throttle_remove_dev(sys_dev); |
38ef6d19 | 288 | mutex_unlock(&therm_cpu_lock); |
3222b36f DZ |
289 | break; |
290 | } | |
a94247e7 | 291 | return notifier_from_errno(err); |
3222b36f DZ |
292 | } |
293 | ||
25d1b516 | 294 | static struct notifier_block thermal_throttle_cpu_notifier __cpuinitdata = |
3222b36f DZ |
295 | { |
296 | .notifier_call = thermal_throttle_cpu_callback, | |
297 | }; | |
3222b36f DZ |
298 | |
299 | static __init int thermal_throttle_init_device(void) | |
300 | { | |
301 | unsigned int cpu = 0; | |
6569345a | 302 | int err; |
3222b36f DZ |
303 | |
304 | if (!atomic_read(&therm_throt_en)) | |
305 | return 0; | |
306 | ||
307 | register_hotcpu_notifier(&thermal_throttle_cpu_notifier); | |
308 | ||
309 | #ifdef CONFIG_HOTPLUG_CPU | |
310 | mutex_lock(&therm_cpu_lock); | |
311 | #endif | |
312 | /* connect live CPUs to sysfs */ | |
6569345a | 313 | for_each_online_cpu(cpu) { |
51e3c1b5 | 314 | err = thermal_throttle_add_dev(get_cpu_sysdev(cpu), cpu); |
6569345a SH |
315 | WARN_ON(err); |
316 | } | |
3222b36f DZ |
317 | #ifdef CONFIG_HOTPLUG_CPU |
318 | mutex_unlock(&therm_cpu_lock); | |
319 | #endif | |
320 | ||
321 | return 0; | |
322 | } | |
3222b36f | 323 | device_initcall(thermal_throttle_init_device); |
a65c88dd | 324 | |
3222b36f | 325 | #endif /* CONFIG_SYSFS */ |
a65c88dd | 326 | |
0199114c FY |
327 | /* |
328 | * Set up the most two significant bit to notify mce log that this thermal | |
329 | * event type. | |
330 | * This is a temp solution. May be changed in the future with mce log | |
331 | * infrasture. | |
332 | */ | |
333 | #define CORE_THROTTLED (0) | |
334 | #define CORE_POWER_LIMIT ((__u64)1 << 62) | |
335 | #define PACKAGE_THROTTLED ((__u64)2 << 62) | |
336 | #define PACKAGE_POWER_LIMIT ((__u64)3 << 62) | |
337 | ||
9e76a97e D |
338 | static void notify_thresholds(__u64 msr_val) |
339 | { | |
340 | /* check whether the interrupt handler is defined; | |
341 | * otherwise simply return | |
342 | */ | |
343 | if (!platform_thermal_notify) | |
344 | return; | |
345 | ||
346 | /* lower threshold reached */ | |
347 | if ((msr_val & THERM_LOG_THRESHOLD0) && thresh_event_valid(0)) | |
348 | platform_thermal_notify(msr_val); | |
349 | /* higher threshold reached */ | |
350 | if ((msr_val & THERM_LOG_THRESHOLD1) && thresh_event_valid(1)) | |
351 | platform_thermal_notify(msr_val); | |
352 | } | |
353 | ||
a65c88dd | 354 | /* Thermal transition interrupt handler */ |
8363fc82 | 355 | static void intel_thermal_interrupt(void) |
a65c88dd HS |
356 | { |
357 | __u64 msr_val; | |
358 | ||
359 | rdmsrl(MSR_IA32_THERM_STATUS, msr_val); | |
0199114c | 360 | |
9e76a97e D |
361 | /* Check for violation of core thermal thresholds*/ |
362 | notify_thresholds(msr_val); | |
363 | ||
55d435a2 | 364 | if (therm_throt_process(msr_val & THERM_STATUS_PROCHOT, |
0199114c | 365 | THERMAL_THROTTLING_EVENT, |
55d435a2 | 366 | CORE_LEVEL) != 0) |
0199114c FY |
367 | mce_log_therm_throt_event(CORE_THROTTLED | msr_val); |
368 | ||
fe504213 | 369 | if (this_cpu_has(X86_FEATURE_PLN)) |
0199114c FY |
370 | if (therm_throt_process(msr_val & THERM_STATUS_POWER_LIMIT, |
371 | POWER_LIMIT_EVENT, | |
372 | CORE_LEVEL) != 0) | |
373 | mce_log_therm_throt_event(CORE_POWER_LIMIT | msr_val); | |
55d435a2 | 374 | |
fe504213 | 375 | if (this_cpu_has(X86_FEATURE_PTS)) { |
55d435a2 FY |
376 | rdmsrl(MSR_IA32_PACKAGE_THERM_STATUS, msr_val); |
377 | if (therm_throt_process(msr_val & PACKAGE_THERM_STATUS_PROCHOT, | |
0199114c | 378 | THERMAL_THROTTLING_EVENT, |
55d435a2 | 379 | PACKAGE_LEVEL) != 0) |
0199114c | 380 | mce_log_therm_throt_event(PACKAGE_THROTTLED | msr_val); |
fe504213 | 381 | if (this_cpu_has(X86_FEATURE_PLN)) |
0199114c FY |
382 | if (therm_throt_process(msr_val & |
383 | PACKAGE_THERM_STATUS_POWER_LIMIT, | |
384 | POWER_LIMIT_EVENT, | |
385 | PACKAGE_LEVEL) != 0) | |
386 | mce_log_therm_throt_event(PACKAGE_POWER_LIMIT | |
387 | | msr_val); | |
55d435a2 | 388 | } |
a65c88dd HS |
389 | } |
390 | ||
391 | static void unexpected_thermal_interrupt(void) | |
392 | { | |
592091c0 | 393 | printk(KERN_ERR "CPU%d: Unexpected LVT thermal interrupt!\n", |
a65c88dd HS |
394 | smp_processor_id()); |
395 | add_taint(TAINT_MACHINE_CHECK); | |
396 | } | |
397 | ||
398 | static void (*smp_thermal_vector)(void) = unexpected_thermal_interrupt; | |
399 | ||
400 | asmlinkage void smp_thermal_interrupt(struct pt_regs *regs) | |
401 | { | |
402 | exit_idle(); | |
403 | irq_enter(); | |
404 | inc_irq_stat(irq_thermal_count); | |
405 | smp_thermal_vector(); | |
406 | irq_exit(); | |
407 | /* Ack only at the end to avoid potential reentry */ | |
408 | ack_APIC_irq(); | |
409 | } | |
410 | ||
70fe4407 HS |
411 | /* Thermal monitoring depends on APIC, ACPI and clock modulation */ |
412 | static int intel_thermal_supported(struct cpuinfo_x86 *c) | |
413 | { | |
414 | if (!cpu_has_apic) | |
415 | return 0; | |
416 | if (!cpu_has(c, X86_FEATURE_ACPI) || !cpu_has(c, X86_FEATURE_ACC)) | |
417 | return 0; | |
418 | return 1; | |
419 | } | |
420 | ||
ce6b5d76 | 421 | void __init mcheck_intel_therm_init(void) |
a2202aa2 YW |
422 | { |
423 | /* | |
424 | * This function is only called on boot CPU. Save the init thermal | |
425 | * LVT value on BSP and use that value to restore APs' thermal LVT | |
426 | * entry BIOS programmed later | |
427 | */ | |
70fe4407 | 428 | if (intel_thermal_supported(&boot_cpu_data)) |
a2202aa2 YW |
429 | lvtthmr_init = apic_read(APIC_LVTTHMR); |
430 | } | |
431 | ||
cffd377e | 432 | void intel_init_thermal(struct cpuinfo_x86 *c) |
895287c0 HS |
433 | { |
434 | unsigned int cpu = smp_processor_id(); | |
435 | int tm2 = 0; | |
436 | u32 l, h; | |
437 | ||
70fe4407 | 438 | if (!intel_thermal_supported(c)) |
895287c0 HS |
439 | return; |
440 | ||
441 | /* | |
442 | * First check if its enabled already, in which case there might | |
443 | * be some SMM goo which handles it, so we can't even put a handler | |
444 | * since it might be delivered via SMI already: | |
445 | */ | |
446 | rdmsr(MSR_IA32_MISC_ENABLE, l, h); | |
a2202aa2 YW |
447 | |
448 | /* | |
449 | * The initial value of thermal LVT entries on all APs always reads | |
450 | * 0x10000 because APs are woken up by BSP issuing INIT-SIPI-SIPI | |
451 | * sequence to them and LVT registers are reset to 0s except for | |
452 | * the mask bits which are set to 1s when APs receive INIT IPI. | |
453 | * Always restore the value that BIOS has programmed on AP based on | |
454 | * BSP's info we saved since BIOS is always setting the same value | |
455 | * for all threads/cores | |
456 | */ | |
457 | apic_write(APIC_LVTTHMR, lvtthmr_init); | |
458 | ||
459 | h = lvtthmr_init; | |
460 | ||
895287c0 HS |
461 | if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) { |
462 | printk(KERN_DEBUG | |
463 | "CPU%d: Thermal monitoring handled by SMI\n", cpu); | |
464 | return; | |
465 | } | |
466 | ||
895287c0 HS |
467 | /* Check whether a vector already exists */ |
468 | if (h & APIC_VECTOR_MASK) { | |
469 | printk(KERN_DEBUG | |
470 | "CPU%d: Thermal LVT vector (%#x) already installed\n", | |
471 | cpu, (h & APIC_VECTOR_MASK)); | |
472 | return; | |
473 | } | |
474 | ||
f3a0867b BZ |
475 | /* early Pentium M models use different method for enabling TM2 */ |
476 | if (cpu_has(c, X86_FEATURE_TM2)) { | |
477 | if (c->x86 == 6 && (c->x86_model == 9 || c->x86_model == 13)) { | |
478 | rdmsr(MSR_THERM2_CTL, l, h); | |
479 | if (l & MSR_THERM2_CTL_TM_SELECT) | |
480 | tm2 = 1; | |
481 | } else if (l & MSR_IA32_MISC_ENABLE_TM2) | |
482 | tm2 = 1; | |
483 | } | |
484 | ||
895287c0 HS |
485 | /* We'll mask the thermal vector in the lapic till we're ready: */ |
486 | h = THERMAL_APIC_VECTOR | APIC_DM_FIXED | APIC_LVT_MASKED; | |
487 | apic_write(APIC_LVTTHMR, h); | |
488 | ||
489 | rdmsr(MSR_IA32_THERM_INTERRUPT, l, h); | |
0199114c FY |
490 | if (cpu_has(c, X86_FEATURE_PLN)) |
491 | wrmsr(MSR_IA32_THERM_INTERRUPT, | |
492 | l | (THERM_INT_LOW_ENABLE | |
493 | | THERM_INT_HIGH_ENABLE | THERM_INT_PLN_ENABLE), h); | |
494 | else | |
495 | wrmsr(MSR_IA32_THERM_INTERRUPT, | |
496 | l | (THERM_INT_LOW_ENABLE | THERM_INT_HIGH_ENABLE), h); | |
895287c0 | 497 | |
55d435a2 FY |
498 | if (cpu_has(c, X86_FEATURE_PTS)) { |
499 | rdmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h); | |
0199114c FY |
500 | if (cpu_has(c, X86_FEATURE_PLN)) |
501 | wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, | |
502 | l | (PACKAGE_THERM_INT_LOW_ENABLE | |
503 | | PACKAGE_THERM_INT_HIGH_ENABLE | |
504 | | PACKAGE_THERM_INT_PLN_ENABLE), h); | |
505 | else | |
506 | wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, | |
507 | l | (PACKAGE_THERM_INT_LOW_ENABLE | |
508 | | PACKAGE_THERM_INT_HIGH_ENABLE), h); | |
55d435a2 FY |
509 | } |
510 | ||
8363fc82 | 511 | smp_thermal_vector = intel_thermal_interrupt; |
895287c0 HS |
512 | |
513 | rdmsr(MSR_IA32_MISC_ENABLE, l, h); | |
514 | wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h); | |
515 | ||
516 | /* Unmask the thermal vector: */ | |
517 | l = apic_read(APIC_LVTTHMR); | |
518 | apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED); | |
519 | ||
2eaad1fd MT |
520 | printk_once(KERN_INFO "CPU0: Thermal monitoring enabled (%s)\n", |
521 | tm2 ? "TM2" : "TM1"); | |
895287c0 HS |
522 | |
523 | /* enable thermal throttle processing */ | |
524 | atomic_set(&therm_throt_en, 1); | |
525 | } |