Commit | Line | Data |
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757885e9 JS |
1 | /* |
2 | * Copyright (C) 2013 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Author: Jacob Shin <jacob.shin@amd.com> | |
5335ba5c | 5 | * Fixes: Borislav Petkov <bp@suse.de> |
757885e9 JS |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/earlycpio.h> | |
275bbe2e | 13 | #include <linux/initrd.h> |
757885e9 JS |
14 | |
15 | #include <asm/cpu.h> | |
16 | #include <asm/setup.h> | |
17 | #include <asm/microcode_amd.h> | |
18 | ||
5335ba5c BP |
19 | /* |
20 | * This points to the current valid container of microcode patches which we will | |
21 | * save from the initrd before jettisoning its contents. | |
22 | */ | |
23 | static u8 *container; | |
24 | static size_t container_size; | |
25 | ||
757885e9 | 26 | static u32 ucode_new_rev; |
5335ba5c BP |
27 | u8 amd_ucode_patch[PATCH_MAX_SIZE]; |
28 | static u16 this_equiv_id; | |
29 | ||
1d2ce978 | 30 | static struct cpio_data ucode_cpio; |
757885e9 JS |
31 | |
32 | /* | |
33 | * Microcode patch container file is prepended to the initrd in cpio format. | |
34 | * See Documentation/x86/early-microcode.txt | |
35 | */ | |
275bbe2e | 36 | static __initdata char ucode_path[] = "kernel/x86/microcode/AuthenticAMD.bin"; |
757885e9 | 37 | |
275bbe2e | 38 | static struct cpio_data __init find_ucode_in_initrd(void) |
757885e9 JS |
39 | { |
40 | long offset = 0; | |
275bbe2e JS |
41 | char *path; |
42 | void *start; | |
43 | size_t size; | |
757885e9 JS |
44 | |
45 | #ifdef CONFIG_X86_32 | |
275bbe2e JS |
46 | struct boot_params *p; |
47 | ||
757885e9 JS |
48 | /* |
49 | * On 32-bit, early load occurs before paging is turned on so we need | |
50 | * to use physical addresses. | |
51 | */ | |
275bbe2e JS |
52 | p = (struct boot_params *)__pa_nodebug(&boot_params); |
53 | path = (char *)__pa_nodebug(ucode_path); | |
54 | start = (void *)p->hdr.ramdisk_image; | |
55 | size = p->hdr.ramdisk_size; | |
275bbe2e JS |
56 | #else |
57 | path = ucode_path; | |
58 | start = (void *)(boot_params.hdr.ramdisk_image + PAGE_OFFSET); | |
59 | size = boot_params.hdr.ramdisk_size; | |
757885e9 | 60 | #endif |
275bbe2e | 61 | |
5335ba5c BP |
62 | return find_cpio_data(path, start, size, &offset); |
63 | } | |
757885e9 | 64 | |
5335ba5c BP |
65 | static size_t compute_container_size(u8 *data, u32 total_size) |
66 | { | |
67 | size_t size = 0; | |
68 | u32 *header = (u32 *)data; | |
757885e9 | 69 | |
5335ba5c BP |
70 | if (header[0] != UCODE_MAGIC || |
71 | header[1] != UCODE_EQUIV_CPU_TABLE_TYPE || /* type */ | |
72 | header[2] == 0) /* size */ | |
73 | return size; | |
275bbe2e | 74 | |
5335ba5c BP |
75 | size = header[2] + CONTAINER_HDR_SZ; |
76 | total_size -= size; | |
77 | data += size; | |
78 | ||
79 | while (total_size) { | |
80 | u16 patch_size; | |
81 | ||
82 | header = (u32 *)data; | |
83 | ||
84 | if (header[0] != UCODE_UCODE_TYPE) | |
85 | break; | |
86 | ||
87 | /* | |
88 | * Sanity-check patch size. | |
89 | */ | |
90 | patch_size = header[1]; | |
91 | if (patch_size > PATCH_MAX_SIZE) | |
92 | break; | |
93 | ||
94 | size += patch_size + SECTION_HDR_SIZE; | |
95 | data += patch_size + SECTION_HDR_SIZE; | |
96 | total_size -= patch_size + SECTION_HDR_SIZE; | |
97 | } | |
98 | ||
99 | return size; | |
757885e9 JS |
100 | } |
101 | ||
102 | /* | |
103 | * Early load occurs before we can vmalloc(). So we look for the microcode | |
104 | * patch container file in initrd, traverse equivalent cpu table, look for a | |
105 | * matching microcode patch, and update, all in initrd memory in place. | |
106 | * When vmalloc() is available for use later -- on 64-bit during first AP load, | |
107 | * and on 32-bit during save_microcode_in_initrd_amd() -- we can call | |
108 | * load_microcode_amd() to save equivalent cpu table and microcode patches in | |
109 | * kernel heap memory. | |
110 | */ | |
c0a717f2 | 111 | static void apply_ucode_in_initrd(void *ucode, size_t size, bool save_patch) |
757885e9 | 112 | { |
757885e9 | 113 | struct equiv_cpu_entry *eq; |
5335ba5c | 114 | size_t *cont_sz; |
757885e9 | 115 | u32 *header; |
5335ba5c | 116 | u8 *data, **cont; |
c0a717f2 | 117 | u8 (*patch)[PATCH_MAX_SIZE]; |
cd1c32ca | 118 | u16 eq_id = 0; |
757885e9 | 119 | int offset, left; |
5335ba5c | 120 | u32 rev, eax, ebx, ecx, edx; |
757885e9 JS |
121 | u32 *new_rev; |
122 | ||
123 | #ifdef CONFIG_X86_32 | |
124 | new_rev = (u32 *)__pa_nodebug(&ucode_new_rev); | |
5335ba5c BP |
125 | cont_sz = (size_t *)__pa_nodebug(&container_size); |
126 | cont = (u8 **)__pa_nodebug(&container); | |
c0a717f2 | 127 | patch = (u8 (*)[PATCH_MAX_SIZE])__pa_nodebug(&amd_ucode_patch); |
757885e9 JS |
128 | #else |
129 | new_rev = &ucode_new_rev; | |
5335ba5c BP |
130 | cont_sz = &container_size; |
131 | cont = &container; | |
c0a717f2 | 132 | patch = &amd_ucode_patch; |
757885e9 | 133 | #endif |
757885e9 | 134 | |
275bbe2e JS |
135 | data = ucode; |
136 | left = size; | |
757885e9 JS |
137 | header = (u32 *)data; |
138 | ||
139 | /* find equiv cpu table */ | |
5335ba5c BP |
140 | if (header[0] != UCODE_MAGIC || |
141 | header[1] != UCODE_EQUIV_CPU_TABLE_TYPE || /* type */ | |
757885e9 JS |
142 | header[2] == 0) /* size */ |
143 | return; | |
144 | ||
5335ba5c BP |
145 | eax = 0x00000001; |
146 | ecx = 0; | |
147 | native_cpuid(&eax, &ebx, &ecx, &edx); | |
cd1c32ca JS |
148 | |
149 | while (left > 0) { | |
150 | eq = (struct equiv_cpu_entry *)(data + CONTAINER_HDR_SZ); | |
151 | ||
5335ba5c BP |
152 | *cont = data; |
153 | ||
154 | /* Advance past the container header */ | |
cd1c32ca JS |
155 | offset = header[2] + CONTAINER_HDR_SZ; |
156 | data += offset; | |
157 | left -= offset; | |
158 | ||
159 | eq_id = find_equiv_id(eq, eax); | |
5335ba5c BP |
160 | if (eq_id) { |
161 | this_equiv_id = eq_id; | |
162 | *cont_sz = compute_container_size(*cont, left + offset); | |
163 | ||
164 | /* | |
165 | * truncate how much we need to iterate over in the | |
166 | * ucode update loop below | |
167 | */ | |
168 | left = *cont_sz - offset; | |
cd1c32ca | 169 | break; |
5335ba5c | 170 | } |
cd1c32ca JS |
171 | |
172 | /* | |
173 | * support multiple container files appended together. if this | |
174 | * one does not have a matching equivalent cpu entry, we fast | |
175 | * forward to the next container file. | |
176 | */ | |
177 | while (left > 0) { | |
178 | header = (u32 *)data; | |
179 | if (header[0] == UCODE_MAGIC && | |
180 | header[1] == UCODE_EQUIV_CPU_TABLE_TYPE) | |
181 | break; | |
182 | ||
183 | offset = header[1] + SECTION_HDR_SIZE; | |
184 | data += offset; | |
185 | left -= offset; | |
186 | } | |
187 | ||
9608d33b JS |
188 | /* mark where the next microcode container file starts */ |
189 | offset = data - (u8 *)ucode; | |
9608d33b | 190 | ucode = data; |
cd1c32ca | 191 | } |
757885e9 | 192 | |
9608d33b | 193 | if (!eq_id) { |
5335ba5c BP |
194 | *cont = NULL; |
195 | *cont_sz = 0; | |
757885e9 | 196 | return; |
9608d33b | 197 | } |
757885e9 | 198 | |
2eff73c0 BP |
199 | if (check_current_patch_level(&rev)) |
200 | return; | |
757885e9 JS |
201 | |
202 | while (left > 0) { | |
203 | struct microcode_amd *mc; | |
204 | ||
205 | header = (u32 *)data; | |
206 | if (header[0] != UCODE_UCODE_TYPE || /* type */ | |
207 | header[1] == 0) /* size */ | |
208 | break; | |
209 | ||
210 | mc = (struct microcode_amd *)(data + SECTION_HDR_SIZE); | |
5335ba5c BP |
211 | |
212 | if (eq_id == mc->hdr.processor_rev_id && rev < mc->hdr.patch_id) { | |
213 | ||
214 | if (!__apply_microcode_amd(mc)) { | |
9608d33b JS |
215 | rev = mc->hdr.patch_id; |
216 | *new_rev = rev; | |
5335ba5c | 217 | |
c0a717f2 BP |
218 | if (save_patch) |
219 | memcpy(patch, mc, | |
220 | min_t(u32, header[1], PATCH_MAX_SIZE)); | |
757885e9 | 221 | } |
5335ba5c | 222 | } |
757885e9 JS |
223 | |
224 | offset = header[1] + SECTION_HDR_SIZE; | |
225 | data += offset; | |
226 | left -= offset; | |
227 | } | |
228 | } | |
229 | ||
7b179b8f AS |
230 | static bool __init load_builtin_amd_microcode(struct cpio_data *cp, |
231 | unsigned int family) | |
760d765b | 232 | { |
ee38a907 | 233 | #ifdef CONFIG_X86_64 |
760d765b BP |
234 | char fw_name[36] = "amd-ucode/microcode_amd.bin"; |
235 | ||
236 | if (family >= 0x15) | |
237 | snprintf(fw_name, sizeof(fw_name), | |
238 | "amd-ucode/microcode_amd_fam%.2xh.bin", family); | |
239 | ||
240 | return get_builtin_firmware(cp, fw_name); | |
ee38a907 BP |
241 | #else |
242 | return false; | |
243 | #endif | |
760d765b BP |
244 | } |
245 | ||
7b179b8f | 246 | void __init load_ucode_amd_bsp(unsigned int family) |
757885e9 | 247 | { |
5335ba5c BP |
248 | struct cpio_data cp; |
249 | void **data; | |
250 | size_t *size; | |
251 | ||
252 | #ifdef CONFIG_X86_32 | |
253 | data = (void **)__pa_nodebug(&ucode_cpio.data); | |
254 | size = (size_t *)__pa_nodebug(&ucode_cpio.size); | |
255 | #else | |
256 | data = &ucode_cpio.data; | |
257 | size = &ucode_cpio.size; | |
258 | #endif | |
259 | ||
260 | cp = find_ucode_in_initrd(); | |
760d765b BP |
261 | if (!cp.data) { |
262 | if (!load_builtin_amd_microcode(&cp, family)) | |
263 | return; | |
264 | } | |
275bbe2e | 265 | |
5335ba5c BP |
266 | *data = cp.data; |
267 | *size = cp.size; | |
268 | ||
c0a717f2 | 269 | apply_ucode_in_initrd(cp.data, cp.size, true); |
757885e9 JS |
270 | } |
271 | ||
272 | #ifdef CONFIG_X86_32 | |
757885e9 JS |
273 | /* |
274 | * On 32-bit, since AP's early load occurs before paging is turned on, we | |
275 | * cannot traverse cpu_equiv_table and pcache in kernel heap memory. So during | |
276 | * cold boot, AP will apply_ucode_in_initrd() just like the BSP. During | |
5335ba5c BP |
277 | * save_microcode_in_initrd_amd() BSP's patch is copied to amd_ucode_patch, |
278 | * which is used upon resume from suspend. | |
757885e9 | 279 | */ |
148f9bb8 | 280 | void load_ucode_amd_ap(void) |
757885e9 JS |
281 | { |
282 | struct microcode_amd *mc; | |
275bbe2e | 283 | size_t *usize; |
5335ba5c | 284 | void **ucode; |
757885e9 | 285 | |
c0a717f2 | 286 | mc = (struct microcode_amd *)__pa_nodebug(amd_ucode_patch); |
275bbe2e | 287 | if (mc->hdr.patch_id && mc->hdr.processor_rev_id) { |
757885e9 | 288 | __apply_microcode_amd(mc); |
275bbe2e JS |
289 | return; |
290 | } | |
291 | ||
5335ba5c BP |
292 | ucode = (void *)__pa_nodebug(&container); |
293 | usize = (size_t *)__pa_nodebug(&container_size); | |
9608d33b | 294 | |
5335ba5c | 295 | if (!*ucode || !*usize) |
275bbe2e JS |
296 | return; |
297 | ||
c0a717f2 | 298 | apply_ucode_in_initrd(*ucode, *usize, false); |
757885e9 JS |
299 | } |
300 | ||
301 | static void __init collect_cpu_sig_on_bsp(void *arg) | |
302 | { | |
303 | unsigned int cpu = smp_processor_id(); | |
304 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; | |
5335ba5c | 305 | |
757885e9 JS |
306 | uci->cpu_sig.sig = cpuid_eax(0x00000001); |
307 | } | |
75a1ba5b BP |
308 | |
309 | static void __init get_bsp_sig(void) | |
310 | { | |
311 | unsigned int bsp = boot_cpu_data.cpu_index; | |
312 | struct ucode_cpu_info *uci = ucode_cpu_info + bsp; | |
313 | ||
314 | if (!uci->cpu_sig.sig) | |
315 | smp_call_function_single(bsp, collect_cpu_sig_on_bsp, NULL, 1); | |
316 | } | |
757885e9 | 317 | #else |
84516098 | 318 | void load_ucode_amd_ap(void) |
757885e9 | 319 | { |
84516098 | 320 | unsigned int cpu = smp_processor_id(); |
5335ba5c BP |
321 | struct equiv_cpu_entry *eq; |
322 | struct microcode_amd *mc; | |
757885e9 | 323 | u32 rev, eax; |
5335ba5c BP |
324 | u16 eq_id; |
325 | ||
326 | /* Exit if called on the BSP. */ | |
327 | if (!cpu) | |
328 | return; | |
329 | ||
330 | if (!container) | |
331 | return; | |
757885e9 | 332 | |
2eff73c0 BP |
333 | if (check_current_patch_level(&rev)) |
334 | return; | |
757885e9 | 335 | |
5335ba5c BP |
336 | eax = cpuid_eax(0x00000001); |
337 | eq = (struct equiv_cpu_entry *)(container + CONTAINER_HDR_SZ); | |
275bbe2e | 338 | |
5335ba5c BP |
339 | eq_id = find_equiv_id(eq, eax); |
340 | if (!eq_id) | |
341 | return; | |
342 | ||
343 | if (eq_id == this_equiv_id) { | |
344 | mc = (struct microcode_amd *)amd_ucode_patch; | |
275bbe2e | 345 | |
5335ba5c BP |
346 | if (mc && rev < mc->hdr.patch_id) { |
347 | if (!__apply_microcode_amd(mc)) | |
348 | ucode_new_rev = mc->hdr.patch_id; | |
349 | } | |
350 | ||
351 | } else { | |
352 | if (!ucode_cpio.data) | |
757885e9 | 353 | return; |
84516098 | 354 | |
5335ba5c BP |
355 | /* |
356 | * AP has a different equivalence ID than BSP, looks like | |
357 | * mixed-steppings silicon so go through the ucode blob anew. | |
358 | */ | |
c0a717f2 | 359 | apply_ucode_in_initrd(ucode_cpio.data, ucode_cpio.size, false); |
757885e9 | 360 | } |
757885e9 JS |
361 | } |
362 | #endif | |
363 | ||
364 | int __init save_microcode_in_initrd_amd(void) | |
365 | { | |
75a1ba5b | 366 | unsigned long cont; |
c0a717f2 | 367 | int retval = 0; |
757885e9 | 368 | enum ucode_state ret; |
4750a0d1 | 369 | u8 *cont_va; |
84516098 TK |
370 | u32 eax; |
371 | ||
75a1ba5b BP |
372 | if (!container) |
373 | return -EINVAL; | |
5335ba5c | 374 | |
75a1ba5b BP |
375 | #ifdef CONFIG_X86_32 |
376 | get_bsp_sig(); | |
4750a0d1 BP |
377 | cont = (unsigned long)container; |
378 | cont_va = __va(container); | |
75a1ba5b | 379 | #else |
5335ba5c | 380 | /* |
75a1ba5b BP |
381 | * We need the physical address of the container for both bitness since |
382 | * boot_params.hdr.ramdisk_image is a physical address. | |
5335ba5c | 383 | */ |
4750a0d1 BP |
384 | cont = __pa(container); |
385 | cont_va = container; | |
757885e9 | 386 | #endif |
75a1ba5b BP |
387 | |
388 | /* | |
389 | * Take into account the fact that the ramdisk might get relocated and | |
390 | * therefore we need to recompute the container's position in virtual | |
391 | * memory space. | |
392 | */ | |
393 | if (relocated_ramdisk) | |
394 | container = (u8 *)(__va(relocated_ramdisk) + | |
395 | (cont - boot_params.hdr.ramdisk_image)); | |
4750a0d1 BP |
396 | else |
397 | container = cont_va; | |
75a1ba5b | 398 | |
757885e9 JS |
399 | if (ucode_new_rev) |
400 | pr_info("microcode: updated early to new patch_level=0x%08x\n", | |
401 | ucode_new_rev); | |
402 | ||
84516098 TK |
403 | eax = cpuid_eax(0x00000001); |
404 | eax = ((eax >> 8) & 0xf) + ((eax >> 20) & 0xff); | |
405 | ||
2ef84b3b | 406 | ret = load_microcode_amd(smp_processor_id(), eax, container, container_size); |
757885e9 | 407 | if (ret != UCODE_OK) |
c0a717f2 | 408 | retval = -EINVAL; |
757885e9 | 409 | |
5335ba5c BP |
410 | /* |
411 | * This will be freed any msec now, stash patches for the current | |
412 | * family and switch to patch cache for cpu hotplug, etc later. | |
413 | */ | |
414 | container = NULL; | |
415 | container_size = 0; | |
416 | ||
c0a717f2 | 417 | return retval; |
757885e9 | 418 | } |
fbae4ba8 BP |
419 | |
420 | void reload_ucode_amd(void) | |
421 | { | |
422 | struct microcode_amd *mc; | |
2eff73c0 | 423 | u32 rev; |
fbae4ba8 | 424 | |
2eff73c0 BP |
425 | if (check_current_patch_level(&rev)) |
426 | return; | |
fbae4ba8 BP |
427 | |
428 | mc = (struct microcode_amd *)amd_ucode_patch; | |
429 | ||
430 | if (mc && rev < mc->hdr.patch_id) { | |
431 | if (!__apply_microcode_amd(mc)) { | |
432 | ucode_new_rev = mc->hdr.patch_id; | |
433 | pr_info("microcode: reload patch_level=0x%08x\n", | |
434 | ucode_new_rev); | |
435 | } | |
436 | } | |
437 | } |