[deliverable/linux.git] / arch / x86 / kernel / cpu / microcode / amd_early.c

/*
 * Copyright (C) 2013 Advanced Micro Devices, Inc.
 *
 * Author: Jacob Shin <jacob.shin@amd.com>
 * Fixes: Borislav Petkov <bp@suse.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/earlycpio.h>
#include <linux/initrd.h>

#include <asm/cpu.h>
#include <asm/setup.h>
#include <asm/microcode_amd.h>

/*
 * This points to the current valid container of microcode patches which we will
 * save from the initrd before jettisoning its contents.
 */
static u8 *container;
static size_t container_size;

static u32 ucode_new_rev;
u8 amd_ucode_patch[PATCH_MAX_SIZE];
static u16 this_equiv_id;

static struct cpio_data ucode_cpio;

/*
 * Microcode patch container file is prepended to the initrd in cpio format.
 * See Documentation/x86/early-microcode.txt
 */
static __initdata char ucode_path[] = "kernel/x86/microcode/AuthenticAMD.bin";

static struct cpio_data __init find_ucode_in_initrd(void)
{
	long offset = 0;
	char *path;
	void *start;
	size_t size;

#ifdef CONFIG_X86_32
	struct boot_params *p;

	/*
	 * On 32-bit, early load occurs before paging is turned on so we need
	 * to use physical addresses.
	 */
	p       = (struct boot_params *)__pa_nodebug(&boot_params);
	path    = (char *)__pa_nodebug(ucode_path);
	start   = (void *)p->hdr.ramdisk_image;
	size    = p->hdr.ramdisk_size;
#else
	path    = ucode_path;
	start   = (void *)(boot_params.hdr.ramdisk_image + PAGE_OFFSET);
	size    = boot_params.hdr.ramdisk_size;
#endif

	return find_cpio_data(path, start, size, &offset);
}

static size_t compute_container_size(u8 *data, u32 total_size)
{
	size_t size = 0;
	u32 *header = (u32 *)data;

	if (header[0] != UCODE_MAGIC ||
	    header[1] != UCODE_EQUIV_CPU_TABLE_TYPE || /* type */
	    header[2] == 0)                            /* size */
		return size;

	size = header[2] + CONTAINER_HDR_SZ;
	total_size -= size;
	data += size;

	while (total_size) {
		u16 patch_size;

		header = (u32 *)data;

		if (header[0] != UCODE_UCODE_TYPE)
			break;

		/*
		 * Sanity-check patch size.
		 */
		patch_size = header[1];
		if (patch_size > PATCH_MAX_SIZE)
			break;

		size	   += patch_size + SECTION_HDR_SIZE;
		data	   += patch_size + SECTION_HDR_SIZE;
		total_size -= patch_size + SECTION_HDR_SIZE;
	}

	return size;
}

/*
 * Early load occurs before we can vmalloc(). So we look for the microcode
 * patch container file in initrd, traverse equivalent cpu table, look for a
 * matching microcode patch, and update, all in initrd memory in place.
 * When vmalloc() is available for use later -- on 64-bit during first AP load,
 * and on 32-bit during save_microcode_in_initrd_amd() -- we can call
 * load_microcode_amd() to save equivalent cpu table and microcode patches in
 * kernel heap memory.
 */
static void apply_ucode_in_initrd(void *ucode, size_t size, bool save_patch)
{
	struct equiv_cpu_entry *eq;
	size_t *cont_sz;
	u32 *header;
	u8  *data, **cont;
	u8 (*patch)[PATCH_MAX_SIZE];
	u16 eq_id = 0;
	int offset, left;
	u32 rev, eax, ebx, ecx, edx;
	u32 *new_rev;

#ifdef CONFIG_X86_32
	new_rev = (u32 *)__pa_nodebug(&ucode_new_rev);
	cont_sz = (size_t *)__pa_nodebug(&container_size);
	cont	= (u8 **)__pa_nodebug(&container);
	patch	= (u8 (*)[PATCH_MAX_SIZE])__pa_nodebug(&amd_ucode_patch);
#else
	new_rev = &ucode_new_rev;
	cont_sz = &container_size;
	cont	= &container;
	patch	= &amd_ucode_patch;
#endif

	data   = ucode;
	left   = size;
	header = (u32 *)data;

	/* find equiv cpu table */
	if (header[0] != UCODE_MAGIC ||
	    header[1] != UCODE_EQUIV_CPU_TABLE_TYPE || /* type */
	    header[2] == 0)                            /* size */
		return;

	eax = 0x00000001;
	ecx = 0;
	native_cpuid(&eax, &ebx, &ecx, &edx);

	while (left > 0) {
		eq = (struct equiv_cpu_entry *)(data + CONTAINER_HDR_SZ);

		*cont = data;

		/* Advance past the container header */
		offset = header[2] + CONTAINER_HDR_SZ;
		data  += offset;
		left  -= offset;

		eq_id = find_equiv_id(eq, eax);
		if (eq_id) {
			this_equiv_id = eq_id;
			*cont_sz = compute_container_size(*cont, left + offset);

			/*
			 * truncate how much we need to iterate over in the
			 * ucode update loop below
			 */
			left = *cont_sz - offset;
			break;
		}

		/*
		 * support multiple container files appended together. if this
		 * one does not have a matching equivalent cpu entry, we fast
		 * forward to the next container file.
		 */
		while (left > 0) {
			header = (u32 *)data;
			if (header[0] == UCODE_MAGIC &&
			    header[1] == UCODE_EQUIV_CPU_TABLE_TYPE)
				break;

			offset = header[1] + SECTION_HDR_SIZE;
			data  += offset;
			left  -= offset;
		}

		/* mark where the next microcode container file starts */
		offset    = data - (u8 *)ucode;
		ucode     = data;
	}

	if (!eq_id) {
		*cont = NULL;
		*cont_sz = 0;
		return;
	}

	/* find ucode and update if needed */

	native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, eax);

	while (left > 0) {
		struct microcode_amd *mc;

		header = (u32 *)data;
		if (header[0] != UCODE_UCODE_TYPE || /* type */
		    header[1] == 0)                  /* size */
			break;

		mc = (struct microcode_amd *)(data + SECTION_HDR_SIZE);

		if (eq_id == mc->hdr.processor_rev_id && rev < mc->hdr.patch_id) {

			if (!__apply_microcode_amd(mc)) {
				rev = mc->hdr.patch_id;
				*new_rev = rev;

				if (save_patch)
					memcpy(patch, mc,
					       min_t(u32, header[1], PATCH_MAX_SIZE));
			}
		}

		offset  = header[1] + SECTION_HDR_SIZE;
		data   += offset;
		left   -= offset;
	}
}

void __init load_ucode_amd_bsp(void)
{
	struct cpio_data cp;
	void **data;
	size_t *size;

#ifdef CONFIG_X86_32
	data =  (void **)__pa_nodebug(&ucode_cpio.data);
	size = (size_t *)__pa_nodebug(&ucode_cpio.size);
#else
	data = &ucode_cpio.data;
	size = &ucode_cpio.size;
#endif

	cp = find_ucode_in_initrd();
	if (!cp.data)
		return;

	*data = cp.data;
	*size = cp.size;

	apply_ucode_in_initrd(cp.data, cp.size, true);
}

#ifdef CONFIG_X86_32
/*
 * On 32-bit, since AP's early load occurs before paging is turned on, we
 * cannot traverse cpu_equiv_table and pcache in kernel heap memory. So during
 * cold boot, AP will apply_ucode_in_initrd() just like the BSP. During
 * save_microcode_in_initrd_amd() BSP's patch is copied to amd_ucode_patch,
 * which is used upon resume from suspend.
 */
void load_ucode_amd_ap(void)
{
	struct microcode_amd *mc;
	size_t *usize;
	void **ucode;

	mc = (struct microcode_amd *)__pa_nodebug(amd_ucode_patch);
	if (mc->hdr.patch_id && mc->hdr.processor_rev_id) {
		__apply_microcode_amd(mc);
		return;
	}

	ucode = (void *)__pa_nodebug(&container);
	usize = (size_t *)__pa_nodebug(&container_size);

	if (!*ucode || !*usize)
		return;

	apply_ucode_in_initrd(*ucode, *usize, false);
}

static void __init collect_cpu_sig_on_bsp(void *arg)
{
	unsigned int cpu = smp_processor_id();
	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;

	uci->cpu_sig.sig = cpuid_eax(0x00000001);
}

static void __init get_bsp_sig(void)
{
	unsigned int bsp = boot_cpu_data.cpu_index;
	struct ucode_cpu_info *uci = ucode_cpu_info + bsp;

	if (!uci->cpu_sig.sig)
		smp_call_function_single(bsp, collect_cpu_sig_on_bsp, NULL, 1);
}
#else
void load_ucode_amd_ap(void)
{
	unsigned int cpu = smp_processor_id();
	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
	struct equiv_cpu_entry *eq;
	struct microcode_amd *mc;
	u32 rev, eax;
	u16 eq_id;

	/* Exit if called on the BSP. */
	if (!cpu)
		return;

	if (!container)
		return;

	rdmsr(MSR_AMD64_PATCH_LEVEL, rev, eax);

	uci->cpu_sig.rev = rev;
	uci->cpu_sig.sig = eax;

	eax = cpuid_eax(0x00000001);
	eq  = (struct equiv_cpu_entry *)(container + CONTAINER_HDR_SZ);

	eq_id = find_equiv_id(eq, eax);
	if (!eq_id)
		return;

	if (eq_id == this_equiv_id) {
		mc = (struct microcode_amd *)amd_ucode_patch;

		if (mc && rev < mc->hdr.patch_id) {
			if (!__apply_microcode_amd(mc))
				ucode_new_rev = mc->hdr.patch_id;
		}

	} else {
		if (!ucode_cpio.data)
			return;

		/*
		 * AP has a different equivalence ID than BSP, looks like
		 * mixed-steppings silicon so go through the ucode blob anew.
		 */
		apply_ucode_in_initrd(ucode_cpio.data, ucode_cpio.size, false);
	}
}
#endif

int __init save_microcode_in_initrd_amd(void)
{
	unsigned long cont;
	int retval = 0;
	enum ucode_state ret;
	u8 *cont_va;
	u32 eax;

	if (!container)
		return -EINVAL;

#ifdef CONFIG_X86_32
	get_bsp_sig();
	cont	= (unsigned long)container;
	cont_va = __va(container);
#else
	/*
	 * We need the physical address of the container for both bitness since
	 * boot_params.hdr.ramdisk_image is a physical address.
	 */
	cont    = __pa(container);
	cont_va = container;
#endif

	/*
	 * Take into account the fact that the ramdisk might get relocated and
	 * therefore we need to recompute the container's position in virtual
	 * memory space.
	 */
	if (relocated_ramdisk)
		container = (u8 *)(__va(relocated_ramdisk) +
			     (cont - boot_params.hdr.ramdisk_image));
	else
		container = cont_va;

	if (ucode_new_rev)
		pr_info("microcode: updated early to new patch_level=0x%08x\n",
			ucode_new_rev);

	eax   = cpuid_eax(0x00000001);
	eax   = ((eax >> 8) & 0xf) + ((eax >> 20) & 0xff);

	ret = load_microcode_amd(eax, container, container_size);
	if (ret != UCODE_OK)
		retval = -EINVAL;

	/*
	 * This will be freed any msec now, stash patches for the current
	 * family and switch to patch cache for cpu hotplug, etc later.
	 */
	container = NULL;
	container_size = 0;

	return retval;
}
Commit	Line	Data
757885e9 JS	1	/*
	2	* Copyright (C) 2013 Advanced Micro Devices, Inc.
	3	*
	4	* Author: Jacob Shin <jacob.shin@amd.com>
5335ba5c	5	* Fixes: Borislav Petkov <bp@suse.de>
757885e9 JS	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/earlycpio.h>
275bbe2e	13	#include <linux/initrd.h>
757885e9 JS	14
	15	#include <asm/cpu.h>
	16	#include <asm/setup.h>
	17	#include <asm/microcode_amd.h>
	18
5335ba5c BP	19	/*
	20	* This points to the current valid container of microcode patches which we will
	21	* save from the initrd before jettisoning its contents.
	22	*/
	23	static u8 *container;
	24	static size_t container_size;
	25
757885e9	26	static u32 ucode_new_rev;
5335ba5c BP	27	u8 amd_ucode_patch[PATCH_MAX_SIZE];
	28	static u16 this_equiv_id;
	29
1d2ce978	30	static struct cpio_data ucode_cpio;
757885e9 JS	31
	32	/*
	33	* Microcode patch container file is prepended to the initrd in cpio format.
	34	* See Documentation/x86/early-microcode.txt
	35	*/
275bbe2e	36	static __initdata char ucode_path[] = "kernel/x86/microcode/AuthenticAMD.bin";
757885e9	37
275bbe2e	38	static struct cpio_data __init find_ucode_in_initrd(void)
757885e9 JS	39	{
757885e9 JS	40	long offset = 0;
275bbe2e JS	41	char *path;
	42	void *start;
	43	size_t size;
757885e9 JS	44
757885e9 JS	45	#ifdef CONFIG_X86_32
275bbe2e JS	46	struct boot_params *p;
275bbe2e JS	47
757885e9 JS	48	/*
	49	* On 32-bit, early load occurs before paging is turned on so we need
	50	* to use physical addresses.
	51	*/
275bbe2e JS	52	p = (struct boot_params *)__pa_nodebug(&boot_params);
	53	path = (char *)__pa_nodebug(ucode_path);
	54	start = (void *)p->hdr.ramdisk_image;
	55	size = p->hdr.ramdisk_size;
275bbe2e JS	56	#else
	57	path = ucode_path;
	58	start = (void *)(boot_params.hdr.ramdisk_image + PAGE_OFFSET);
	59	size = boot_params.hdr.ramdisk_size;
757885e9	60	#endif
275bbe2e	61
5335ba5c BP	62	return find_cpio_data(path, start, size, &offset);
5335ba5c BP	63	}
757885e9	64
5335ba5c BP	65	static size_t compute_container_size(u8 *data, u32 total_size)
	66	{
	67	size_t size = 0;
	68	u32 header = (u32 )data;
757885e9	69
5335ba5c BP	70	if (header[0] != UCODE_MAGIC \|\|
	71	header[1] != UCODE_EQUIV_CPU_TABLE_TYPE \|\| /* type */
	72	header[2] == 0) /* size */
	73	return size;
275bbe2e	74
5335ba5c BP	75	size = header[2] + CONTAINER_HDR_SZ;
	76	total_size -= size;
	77	data += size;
	78
	79	while (total_size) {
	80	u16 patch_size;
	81
	82	header = (u32 *)data;
	83
	84	if (header[0] != UCODE_UCODE_TYPE)
	85	break;
	86
	87	/*
	88	* Sanity-check patch size.
	89	*/
	90	patch_size = header[1];
	91	if (patch_size > PATCH_MAX_SIZE)
	92	break;
	93
	94	size += patch_size + SECTION_HDR_SIZE;
	95	data += patch_size + SECTION_HDR_SIZE;
	96	total_size -= patch_size + SECTION_HDR_SIZE;
	97	}
	98
	99	return size;
757885e9 JS	100	}
	101
	102	/*
	103	* Early load occurs before we can vmalloc(). So we look for the microcode
	104	* patch container file in initrd, traverse equivalent cpu table, look for a
	105	* matching microcode patch, and update, all in initrd memory in place.
	106	* When vmalloc() is available for use later -- on 64-bit during first AP load,
	107	* and on 32-bit during save_microcode_in_initrd_amd() -- we can call
	108	* load_microcode_amd() to save equivalent cpu table and microcode patches in
	109	* kernel heap memory.
	110	*/
c0a717f2	111	static void apply_ucode_in_initrd(void *ucode, size_t size, bool save_patch)
757885e9	112	{
757885e9	113	struct equiv_cpu_entry *eq;
5335ba5c	114	size_t *cont_sz;
757885e9	115	u32 *header;
5335ba5c	116	u8 data, *cont;
c0a717f2	117	u8 (*patch)[PATCH_MAX_SIZE];
cd1c32ca	118	u16 eq_id = 0;
757885e9	119	int offset, left;
5335ba5c	120	u32 rev, eax, ebx, ecx, edx;
757885e9 JS	121	u32 *new_rev;
	122
	123	#ifdef CONFIG_X86_32
	124	new_rev = (u32 *)__pa_nodebug(&ucode_new_rev);
5335ba5c BP	125	cont_sz = (size_t *)__pa_nodebug(&container_size);
5335ba5c BP	126	cont = (u8 **)__pa_nodebug(&container);
c0a717f2	127	patch = (u8 (*)[PATCH_MAX_SIZE])__pa_nodebug(&amd_ucode_patch);
757885e9 JS	128	#else
757885e9 JS	129	new_rev = &ucode_new_rev;
5335ba5c BP	130	cont_sz = &container_size;
5335ba5c BP	131	cont = &container;
c0a717f2	132	patch = &amd_ucode_patch;
757885e9	133	#endif
757885e9	134
275bbe2e JS	135	data = ucode;
275bbe2e JS	136	left = size;
757885e9 JS	137	header = (u32 *)data;
	138
	139	/* find equiv cpu table */
5335ba5c BP	140	if (header[0] != UCODE_MAGIC \|\|
5335ba5c BP	141	header[1] != UCODE_EQUIV_CPU_TABLE_TYPE \|\| /* type */
757885e9 JS	142	header[2] == 0) /* size */
	143	return;
	144
5335ba5c BP	145	eax = 0x00000001;
	146	ecx = 0;
	147	native_cpuid(&eax, &ebx, &ecx, &edx);
cd1c32ca JS	148
	149	while (left > 0) {
	150	eq = (struct equiv_cpu_entry *)(data + CONTAINER_HDR_SZ);
	151
5335ba5c BP	152	*cont = data;
	153
	154	/* Advance past the container header */
cd1c32ca JS	155	offset = header[2] + CONTAINER_HDR_SZ;
	156	data += offset;
	157	left -= offset;
	158
	159	eq_id = find_equiv_id(eq, eax);
5335ba5c BP	160	if (eq_id) {
	161	this_equiv_id = eq_id;
	162	cont_sz = compute_container_size(cont, left + offset);
	163
	164	/*
	165	* truncate how much we need to iterate over in the
	166	* ucode update loop below
	167	*/
	168	left = *cont_sz - offset;
cd1c32ca	169	break;
5335ba5c	170	}
cd1c32ca JS	171
	172	/*
	173	* support multiple container files appended together. if this
	174	* one does not have a matching equivalent cpu entry, we fast
	175	* forward to the next container file.
	176	*/
	177	while (left > 0) {
	178	header = (u32 *)data;
	179	if (header[0] == UCODE_MAGIC &&
	180	header[1] == UCODE_EQUIV_CPU_TABLE_TYPE)
	181	break;
	182
	183	offset = header[1] + SECTION_HDR_SIZE;
	184	data += offset;
	185	left -= offset;
	186	}
	187
9608d33b JS	188	/* mark where the next microcode container file starts */
9608d33b JS	189	offset = data - (u8 *)ucode;
9608d33b	190	ucode = data;
cd1c32ca	191	}
757885e9	192
9608d33b	193	if (!eq_id) {
5335ba5c BP	194	*cont = NULL;
5335ba5c BP	195	*cont_sz = 0;
757885e9	196	return;
9608d33b	197	}
757885e9 JS	198
	199	/* find ucode and update if needed */
	200
5335ba5c	201	native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, eax);
757885e9 JS	202
	203	while (left > 0) {
	204	struct microcode_amd *mc;
	205
	206	header = (u32 *)data;
	207	if (header[0] != UCODE_UCODE_TYPE \|\| /* type */
	208	header[1] == 0) /* size */
	209	break;
	210
	211	mc = (struct microcode_amd *)(data + SECTION_HDR_SIZE);
5335ba5c BP	212
	213	if (eq_id == mc->hdr.processor_rev_id && rev < mc->hdr.patch_id) {
	214
	215	if (!__apply_microcode_amd(mc)) {
9608d33b JS	216	rev = mc->hdr.patch_id;
9608d33b JS	217	*new_rev = rev;
5335ba5c	218
c0a717f2 BP	219	if (save_patch)
	220	memcpy(patch, mc,
	221	min_t(u32, header[1], PATCH_MAX_SIZE));
757885e9	222	}
5335ba5c	223	}
757885e9 JS	224
	225	offset = header[1] + SECTION_HDR_SIZE;
	226	data += offset;
	227	left -= offset;
	228	}
	229	}
	230
	231	void __init load_ucode_amd_bsp(void)
	232	{
5335ba5c BP	233	struct cpio_data cp;
	234	void **data;
	235	size_t *size;
	236
	237	#ifdef CONFIG_X86_32
	238	data = (void **)__pa_nodebug(&ucode_cpio.data);
	239	size = (size_t *)__pa_nodebug(&ucode_cpio.size);
	240	#else
	241	data = &ucode_cpio.data;
	242	size = &ucode_cpio.size;
	243	#endif
	244
	245	cp = find_ucode_in_initrd();
	246	if (!cp.data)
275bbe2e JS	247	return;
275bbe2e JS	248
5335ba5c BP	249	*data = cp.data;
	250	*size = cp.size;
	251
c0a717f2	252	apply_ucode_in_initrd(cp.data, cp.size, true);
757885e9 JS	253	}
	254
	255	#ifdef CONFIG_X86_32
757885e9 JS	256	/*
	257	* On 32-bit, since AP's early load occurs before paging is turned on, we
	258	* cannot traverse cpu_equiv_table and pcache in kernel heap memory. So during
	259	* cold boot, AP will apply_ucode_in_initrd() just like the BSP. During
5335ba5c BP	260	* save_microcode_in_initrd_amd() BSP's patch is copied to amd_ucode_patch,
5335ba5c BP	261	* which is used upon resume from suspend.
757885e9	262	*/
148f9bb8	263	void load_ucode_amd_ap(void)
757885e9 JS	264	{
757885e9 JS	265	struct microcode_amd *mc;
275bbe2e	266	size_t *usize;
5335ba5c	267	void **ucode;
757885e9	268
c0a717f2	269	mc = (struct microcode_amd *)__pa_nodebug(amd_ucode_patch);
275bbe2e	270	if (mc->hdr.patch_id && mc->hdr.processor_rev_id) {
757885e9	271	__apply_microcode_amd(mc);
275bbe2e JS	272	return;
	273	}
	274
5335ba5c BP	275	ucode = (void *)__pa_nodebug(&container);
5335ba5c BP	276	usize = (size_t *)__pa_nodebug(&container_size);
9608d33b	277
5335ba5c	278	if (!ucode \|\| !usize)
275bbe2e JS	279	return;
275bbe2e JS	280
c0a717f2	281	apply_ucode_in_initrd(ucode, usize, false);
757885e9 JS	282	}
	283
	284	static void __init collect_cpu_sig_on_bsp(void *arg)
	285	{
	286	unsigned int cpu = smp_processor_id();
	287	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
5335ba5c	288
757885e9 JS	289	uci->cpu_sig.sig = cpuid_eax(0x00000001);
757885e9 JS	290	}
75a1ba5b BP	291
	292	static void __init get_bsp_sig(void)
	293	{
	294	unsigned int bsp = boot_cpu_data.cpu_index;
	295	struct ucode_cpu_info *uci = ucode_cpu_info + bsp;
	296
	297	if (!uci->cpu_sig.sig)
	298	smp_call_function_single(bsp, collect_cpu_sig_on_bsp, NULL, 1);
	299	}
757885e9	300	#else
84516098	301	void load_ucode_amd_ap(void)
757885e9	302	{
84516098 TK	303	unsigned int cpu = smp_processor_id();
84516098 TK	304	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
5335ba5c BP	305	struct equiv_cpu_entry *eq;
5335ba5c BP	306	struct microcode_amd *mc;
757885e9	307	u32 rev, eax;
5335ba5c BP	308	u16 eq_id;
	309
	310	/* Exit if called on the BSP. */
	311	if (!cpu)
	312	return;
	313
	314	if (!container)
	315	return;
757885e9 JS	316
757885e9 JS	317	rdmsr(MSR_AMD64_PATCH_LEVEL, rev, eax);
757885e9	318
757885e9	319	uci->cpu_sig.rev = rev;
84516098	320	uci->cpu_sig.sig = eax;
757885e9	321
5335ba5c BP	322	eax = cpuid_eax(0x00000001);
5335ba5c BP	323	eq = (struct equiv_cpu_entry *)(container + CONTAINER_HDR_SZ);
275bbe2e	324
5335ba5c BP	325	eq_id = find_equiv_id(eq, eax);
	326	if (!eq_id)
	327	return;
	328
	329	if (eq_id == this_equiv_id) {
	330	mc = (struct microcode_amd *)amd_ucode_patch;
275bbe2e	331
5335ba5c BP	332	if (mc && rev < mc->hdr.patch_id) {
	333	if (!__apply_microcode_amd(mc))
	334	ucode_new_rev = mc->hdr.patch_id;
	335	}
	336
	337	} else {
	338	if (!ucode_cpio.data)
757885e9	339	return;
84516098	340
5335ba5c BP	341	/*
	342	* AP has a different equivalence ID than BSP, looks like
	343	* mixed-steppings silicon so go through the ucode blob anew.
	344	*/
c0a717f2	345	apply_ucode_in_initrd(ucode_cpio.data, ucode_cpio.size, false);
757885e9	346	}
757885e9 JS	347	}
	348	#endif
	349
	350	int __init save_microcode_in_initrd_amd(void)
	351	{
75a1ba5b	352	unsigned long cont;
c0a717f2	353	int retval = 0;
757885e9	354	enum ucode_state ret;
4750a0d1	355	u8 *cont_va;
84516098 TK	356	u32 eax;
84516098 TK	357
75a1ba5b BP	358	if (!container)
75a1ba5b BP	359	return -EINVAL;
5335ba5c	360
75a1ba5b BP	361	#ifdef CONFIG_X86_32
75a1ba5b BP	362	get_bsp_sig();
4750a0d1 BP	363	cont = (unsigned long)container;
4750a0d1 BP	364	cont_va = __va(container);
75a1ba5b	365	#else
5335ba5c	366	/*
75a1ba5b BP	367	* We need the physical address of the container for both bitness since
75a1ba5b BP	368	* boot_params.hdr.ramdisk_image is a physical address.
5335ba5c	369	*/
4750a0d1 BP	370	cont = __pa(container);
4750a0d1 BP	371	cont_va = container;
757885e9	372	#endif
75a1ba5b BP	373
	374	/*
	375	* Take into account the fact that the ramdisk might get relocated and
	376	* therefore we need to recompute the container's position in virtual
	377	* memory space.
	378	*/
	379	if (relocated_ramdisk)
	380	container = (u8 *)(__va(relocated_ramdisk) +
	381	(cont - boot_params.hdr.ramdisk_image));
4750a0d1 BP	382	else
4750a0d1 BP	383	container = cont_va;
75a1ba5b	384
757885e9 JS	385	if (ucode_new_rev)
	386	pr_info("microcode: updated early to new patch_level=0x%08x\n",
	387	ucode_new_rev);
	388
84516098 TK	389	eax = cpuid_eax(0x00000001);
	390	eax = ((eax >> 8) & 0xf) + ((eax >> 20) & 0xff);
	391
5335ba5c	392	ret = load_microcode_amd(eax, container, container_size);
757885e9	393	if (ret != UCODE_OK)
c0a717f2	394	retval = -EINVAL;
757885e9	395
5335ba5c BP	396	/*
	397	* This will be freed any msec now, stash patches for the current
	398	* family and switch to patch cache for cpu hotplug, etc later.
	399	*/
	400	container = NULL;
	401	container_size = 0;
	402
c0a717f2	403	return retval;
757885e9	404	}