Commit | Line | Data |
---|---|---|
3e135d88 | 1 | /* |
6b44e72a | 2 | * CPU Microcode Update Driver for Linux |
3e135d88 | 3 | * |
6b44e72a BP |
4 | * Copyright (C) 2000-2006 Tigran Aivazian <tigran@aivazian.fsnet.co.uk> |
5 | * 2006 Shaohua Li <shaohua.li@intel.com> | |
6 | * 2013-2015 Borislav Petkov <bp@alien8.de> | |
3e135d88 | 7 | * |
fe055896 BP |
8 | * X86 CPU microcode early update for Linux: |
9 | * | |
10 | * Copyright (C) 2012 Fenghua Yu <fenghua.yu@intel.com> | |
11 | * H Peter Anvin" <hpa@zytor.com> | |
12 | * (C) 2015 Borislav Petkov <bp@alien8.de> | |
13 | * | |
6b44e72a | 14 | * This driver allows to upgrade microcode on x86 processors. |
3e135d88 | 15 | * |
6b44e72a BP |
16 | * This program is free software; you can redistribute it and/or |
17 | * modify it under the terms of the GNU General Public License | |
18 | * as published by the Free Software Foundation; either version | |
19 | * 2 of the License, or (at your option) any later version. | |
3e135d88 | 20 | */ |
f58e1f53 | 21 | |
6b26e1bf | 22 | #define pr_fmt(fmt) "microcode: " fmt |
f58e1f53 | 23 | |
4bae1967 | 24 | #include <linux/platform_device.h> |
fe055896 | 25 | #include <linux/syscore_ops.h> |
4bae1967 | 26 | #include <linux/miscdevice.h> |
871b72dd | 27 | #include <linux/capability.h> |
fe055896 | 28 | #include <linux/firmware.h> |
4bae1967 | 29 | #include <linux/kernel.h> |
3e135d88 PO |
30 | #include <linux/mutex.h> |
31 | #include <linux/cpu.h> | |
4bae1967 IM |
32 | #include <linux/fs.h> |
33 | #include <linux/mm.h> | |
3e135d88 | 34 | |
fe055896 | 35 | #include <asm/microcode_intel.h> |
78ff123b | 36 | #include <asm/cpu_device_id.h> |
fe055896 | 37 | #include <asm/microcode_amd.h> |
c93dc84c | 38 | #include <asm/perf_event.h> |
fe055896 BP |
39 | #include <asm/microcode.h> |
40 | #include <asm/processor.h> | |
41 | #include <asm/cmdline.h> | |
3e135d88 | 42 | |
6b26e1bf | 43 | #define MICROCODE_VERSION "2.01" |
3e135d88 | 44 | |
4bae1967 | 45 | static struct microcode_ops *microcode_ops; |
6b26e1bf BP |
46 | static bool dis_ucode_ldr; |
47 | ||
871b72dd DA |
48 | /* |
49 | * Synchronization. | |
50 | * | |
51 | * All non cpu-hotplug-callback call sites use: | |
52 | * | |
53 | * - microcode_mutex to synchronize with each other; | |
54 | * - get/put_online_cpus() to synchronize with | |
55 | * the cpu-hotplug-callback call sites. | |
56 | * | |
57 | * We guarantee that only a single cpu is being | |
58 | * updated at any particular moment of time. | |
59 | */ | |
d45de409 | 60 | static DEFINE_MUTEX(microcode_mutex); |
3e135d88 | 61 | |
4bae1967 | 62 | struct ucode_cpu_info ucode_cpu_info[NR_CPUS]; |
3e135d88 | 63 | |
871b72dd DA |
64 | /* |
65 | * Operations that are run on a target cpu: | |
66 | */ | |
67 | ||
68 | struct cpu_info_ctx { | |
69 | struct cpu_signature *cpu_sig; | |
70 | int err; | |
71 | }; | |
72 | ||
fe055896 BP |
73 | static bool __init check_loader_disabled_bsp(void) |
74 | { | |
e8c8165e BP |
75 | static const char *__dis_opt_str = "dis_ucode_ldr"; |
76 | ||
fe055896 BP |
77 | #ifdef CONFIG_X86_32 |
78 | const char *cmdline = (const char *)__pa_nodebug(boot_command_line); | |
e8c8165e | 79 | const char *option = (const char *)__pa_nodebug(__dis_opt_str); |
fe055896 BP |
80 | bool *res = (bool *)__pa_nodebug(&dis_ucode_ldr); |
81 | ||
82 | #else /* CONFIG_X86_64 */ | |
83 | const char *cmdline = boot_command_line; | |
e8c8165e | 84 | const char *option = __dis_opt_str; |
fe055896 BP |
85 | bool *res = &dis_ucode_ldr; |
86 | #endif | |
87 | ||
88 | if (cmdline_find_option_bool(cmdline, option)) | |
89 | *res = true; | |
90 | ||
91 | return *res; | |
92 | } | |
93 | ||
94 | extern struct builtin_fw __start_builtin_fw[]; | |
95 | extern struct builtin_fw __end_builtin_fw[]; | |
96 | ||
97 | bool get_builtin_firmware(struct cpio_data *cd, const char *name) | |
98 | { | |
99 | #ifdef CONFIG_FW_LOADER | |
100 | struct builtin_fw *b_fw; | |
101 | ||
102 | for (b_fw = __start_builtin_fw; b_fw != __end_builtin_fw; b_fw++) { | |
103 | if (!strcmp(name, b_fw->name)) { | |
104 | cd->size = b_fw->size; | |
105 | cd->data = b_fw->data; | |
106 | return true; | |
107 | } | |
108 | } | |
109 | #endif | |
110 | return false; | |
111 | } | |
112 | ||
113 | void __init load_ucode_bsp(void) | |
114 | { | |
115 | int vendor; | |
116 | unsigned int family; | |
117 | ||
118 | if (check_loader_disabled_bsp()) | |
119 | return; | |
120 | ||
121 | if (!have_cpuid_p()) | |
122 | return; | |
123 | ||
99f925ce BP |
124 | vendor = x86_cpuid_vendor(); |
125 | family = x86_cpuid_family(); | |
fe055896 BP |
126 | |
127 | switch (vendor) { | |
128 | case X86_VENDOR_INTEL: | |
129 | if (family >= 6) | |
130 | load_ucode_intel_bsp(); | |
131 | break; | |
132 | case X86_VENDOR_AMD: | |
133 | if (family >= 0x10) | |
134 | load_ucode_amd_bsp(family); | |
135 | break; | |
136 | default: | |
137 | break; | |
138 | } | |
139 | } | |
140 | ||
141 | static bool check_loader_disabled_ap(void) | |
142 | { | |
143 | #ifdef CONFIG_X86_32 | |
144 | return *((bool *)__pa_nodebug(&dis_ucode_ldr)); | |
145 | #else | |
146 | return dis_ucode_ldr; | |
147 | #endif | |
148 | } | |
149 | ||
150 | void load_ucode_ap(void) | |
151 | { | |
152 | int vendor, family; | |
153 | ||
154 | if (check_loader_disabled_ap()) | |
155 | return; | |
156 | ||
157 | if (!have_cpuid_p()) | |
158 | return; | |
159 | ||
99f925ce BP |
160 | vendor = x86_cpuid_vendor(); |
161 | family = x86_cpuid_family(); | |
fe055896 BP |
162 | |
163 | switch (vendor) { | |
164 | case X86_VENDOR_INTEL: | |
165 | if (family >= 6) | |
166 | load_ucode_intel_ap(); | |
167 | break; | |
168 | case X86_VENDOR_AMD: | |
169 | if (family >= 0x10) | |
170 | load_ucode_amd_ap(); | |
171 | break; | |
172 | default: | |
173 | break; | |
174 | } | |
175 | } | |
176 | ||
4b703305 | 177 | static int __init save_microcode_in_initrd(void) |
fe055896 BP |
178 | { |
179 | struct cpuinfo_x86 *c = &boot_cpu_data; | |
180 | ||
181 | switch (c->x86_vendor) { | |
182 | case X86_VENDOR_INTEL: | |
183 | if (c->x86 >= 6) | |
fa6788b8 | 184 | return save_microcode_in_initrd_intel(); |
fe055896 BP |
185 | break; |
186 | case X86_VENDOR_AMD: | |
187 | if (c->x86 >= 0x10) | |
fa6788b8 | 188 | return save_microcode_in_initrd_amd(); |
fe055896 BP |
189 | break; |
190 | default: | |
191 | break; | |
192 | } | |
193 | ||
fa6788b8 | 194 | return -EINVAL; |
fe055896 BP |
195 | } |
196 | ||
197 | void reload_early_microcode(void) | |
198 | { | |
199 | int vendor, family; | |
200 | ||
99f925ce BP |
201 | vendor = x86_cpuid_vendor(); |
202 | family = x86_cpuid_family(); | |
fe055896 BP |
203 | |
204 | switch (vendor) { | |
205 | case X86_VENDOR_INTEL: | |
206 | if (family >= 6) | |
207 | reload_ucode_intel(); | |
208 | break; | |
209 | case X86_VENDOR_AMD: | |
210 | if (family >= 0x10) | |
211 | reload_ucode_amd(); | |
212 | break; | |
213 | default: | |
214 | break; | |
215 | } | |
216 | } | |
217 | ||
871b72dd DA |
218 | static void collect_cpu_info_local(void *arg) |
219 | { | |
220 | struct cpu_info_ctx *ctx = arg; | |
221 | ||
222 | ctx->err = microcode_ops->collect_cpu_info(smp_processor_id(), | |
223 | ctx->cpu_sig); | |
224 | } | |
225 | ||
226 | static int collect_cpu_info_on_target(int cpu, struct cpu_signature *cpu_sig) | |
227 | { | |
228 | struct cpu_info_ctx ctx = { .cpu_sig = cpu_sig, .err = 0 }; | |
229 | int ret; | |
230 | ||
231 | ret = smp_call_function_single(cpu, collect_cpu_info_local, &ctx, 1); | |
232 | if (!ret) | |
233 | ret = ctx.err; | |
234 | ||
235 | return ret; | |
236 | } | |
237 | ||
238 | static int collect_cpu_info(int cpu) | |
239 | { | |
240 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; | |
241 | int ret; | |
242 | ||
243 | memset(uci, 0, sizeof(*uci)); | |
244 | ||
245 | ret = collect_cpu_info_on_target(cpu, &uci->cpu_sig); | |
246 | if (!ret) | |
247 | uci->valid = 1; | |
248 | ||
249 | return ret; | |
250 | } | |
251 | ||
252 | struct apply_microcode_ctx { | |
253 | int err; | |
254 | }; | |
255 | ||
256 | static void apply_microcode_local(void *arg) | |
257 | { | |
258 | struct apply_microcode_ctx *ctx = arg; | |
259 | ||
260 | ctx->err = microcode_ops->apply_microcode(smp_processor_id()); | |
261 | } | |
262 | ||
263 | static int apply_microcode_on_target(int cpu) | |
264 | { | |
265 | struct apply_microcode_ctx ctx = { .err = 0 }; | |
266 | int ret; | |
267 | ||
268 | ret = smp_call_function_single(cpu, apply_microcode_local, &ctx, 1); | |
269 | if (!ret) | |
270 | ret = ctx.err; | |
271 | ||
272 | return ret; | |
273 | } | |
274 | ||
3e135d88 | 275 | #ifdef CONFIG_MICROCODE_OLD_INTERFACE |
a0a29b62 | 276 | static int do_microcode_update(const void __user *buf, size_t size) |
3e135d88 | 277 | { |
3e135d88 | 278 | int error = 0; |
3e135d88 | 279 | int cpu; |
6f66cbc6 | 280 | |
a0a29b62 DA |
281 | for_each_online_cpu(cpu) { |
282 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; | |
871b72dd | 283 | enum ucode_state ustate; |
a0a29b62 DA |
284 | |
285 | if (!uci->valid) | |
286 | continue; | |
6f66cbc6 | 287 | |
871b72dd DA |
288 | ustate = microcode_ops->request_microcode_user(cpu, buf, size); |
289 | if (ustate == UCODE_ERROR) { | |
290 | error = -1; | |
291 | break; | |
292 | } else if (ustate == UCODE_OK) | |
293 | apply_microcode_on_target(cpu); | |
3e135d88 | 294 | } |
871b72dd | 295 | |
3e135d88 PO |
296 | return error; |
297 | } | |
298 | ||
3f10940e | 299 | static int microcode_open(struct inode *inode, struct file *file) |
3e135d88 | 300 | { |
3f10940e | 301 | return capable(CAP_SYS_RAWIO) ? nonseekable_open(inode, file) : -EPERM; |
3e135d88 PO |
302 | } |
303 | ||
d33dcb9e PO |
304 | static ssize_t microcode_write(struct file *file, const char __user *buf, |
305 | size_t len, loff_t *ppos) | |
3e135d88 | 306 | { |
871b72dd | 307 | ssize_t ret = -EINVAL; |
3e135d88 | 308 | |
4481374c | 309 | if ((len >> PAGE_SHIFT) > totalram_pages) { |
f58e1f53 | 310 | pr_err("too much data (max %ld pages)\n", totalram_pages); |
871b72dd | 311 | return ret; |
3e135d88 PO |
312 | } |
313 | ||
314 | get_online_cpus(); | |
315 | mutex_lock(µcode_mutex); | |
316 | ||
871b72dd | 317 | if (do_microcode_update(buf, len) == 0) |
3e135d88 PO |
318 | ret = (ssize_t)len; |
319 | ||
e3e45c01 SE |
320 | if (ret > 0) |
321 | perf_check_microcode(); | |
322 | ||
3e135d88 PO |
323 | mutex_unlock(µcode_mutex); |
324 | put_online_cpus(); | |
325 | ||
326 | return ret; | |
327 | } | |
328 | ||
329 | static const struct file_operations microcode_fops = { | |
871b72dd DA |
330 | .owner = THIS_MODULE, |
331 | .write = microcode_write, | |
332 | .open = microcode_open, | |
6038f373 | 333 | .llseek = no_llseek, |
3e135d88 PO |
334 | }; |
335 | ||
336 | static struct miscdevice microcode_dev = { | |
871b72dd DA |
337 | .minor = MICROCODE_MINOR, |
338 | .name = "microcode", | |
e454cea2 | 339 | .nodename = "cpu/microcode", |
871b72dd | 340 | .fops = µcode_fops, |
3e135d88 PO |
341 | }; |
342 | ||
d33dcb9e | 343 | static int __init microcode_dev_init(void) |
3e135d88 PO |
344 | { |
345 | int error; | |
346 | ||
347 | error = misc_register(µcode_dev); | |
348 | if (error) { | |
f58e1f53 | 349 | pr_err("can't misc_register on minor=%d\n", MICROCODE_MINOR); |
3e135d88 PO |
350 | return error; |
351 | } | |
352 | ||
353 | return 0; | |
354 | } | |
355 | ||
bd399063 | 356 | static void __exit microcode_dev_exit(void) |
3e135d88 PO |
357 | { |
358 | misc_deregister(µcode_dev); | |
359 | } | |
3e135d88 | 360 | #else |
4bae1967 IM |
361 | #define microcode_dev_init() 0 |
362 | #define microcode_dev_exit() do { } while (0) | |
3e135d88 PO |
363 | #endif |
364 | ||
365 | /* fake device for request_firmware */ | |
4bae1967 | 366 | static struct platform_device *microcode_pdev; |
3e135d88 | 367 | |
871b72dd | 368 | static int reload_for_cpu(int cpu) |
af5c820a | 369 | { |
871b72dd | 370 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; |
4dbf32c3 | 371 | enum ucode_state ustate; |
af5c820a RR |
372 | int err = 0; |
373 | ||
4dbf32c3 BP |
374 | if (!uci->valid) |
375 | return err; | |
871b72dd | 376 | |
48e30685 | 377 | ustate = microcode_ops->request_microcode_fw(cpu, µcode_pdev->dev, true); |
4dbf32c3 BP |
378 | if (ustate == UCODE_OK) |
379 | apply_microcode_on_target(cpu); | |
380 | else | |
381 | if (ustate == UCODE_ERROR) | |
382 | err = -EINVAL; | |
af5c820a RR |
383 | return err; |
384 | } | |
385 | ||
8a25a2fd KS |
386 | static ssize_t reload_store(struct device *dev, |
387 | struct device_attribute *attr, | |
871b72dd | 388 | const char *buf, size_t size) |
3e135d88 | 389 | { |
871b72dd | 390 | unsigned long val; |
c9fc3f77 BP |
391 | int cpu; |
392 | ssize_t ret = 0, tmp_ret; | |
393 | ||
e826abd5 SK |
394 | ret = kstrtoul(buf, 0, &val); |
395 | if (ret) | |
396 | return ret; | |
871b72dd | 397 | |
c9fc3f77 BP |
398 | if (val != 1) |
399 | return size; | |
400 | ||
401 | get_online_cpus(); | |
c93dc84c | 402 | mutex_lock(µcode_mutex); |
c9fc3f77 BP |
403 | for_each_online_cpu(cpu) { |
404 | tmp_ret = reload_for_cpu(cpu); | |
405 | if (tmp_ret != 0) | |
406 | pr_warn("Error reloading microcode on CPU %d\n", cpu); | |
407 | ||
408 | /* save retval of the first encountered reload error */ | |
409 | if (!ret) | |
410 | ret = tmp_ret; | |
3e135d88 | 411 | } |
c93dc84c PZ |
412 | if (!ret) |
413 | perf_check_microcode(); | |
414 | mutex_unlock(µcode_mutex); | |
c9fc3f77 | 415 | put_online_cpus(); |
871b72dd DA |
416 | |
417 | if (!ret) | |
418 | ret = size; | |
419 | ||
420 | return ret; | |
3e135d88 PO |
421 | } |
422 | ||
8a25a2fd KS |
423 | static ssize_t version_show(struct device *dev, |
424 | struct device_attribute *attr, char *buf) | |
3e135d88 PO |
425 | { |
426 | struct ucode_cpu_info *uci = ucode_cpu_info + dev->id; | |
427 | ||
d45de409 | 428 | return sprintf(buf, "0x%x\n", uci->cpu_sig.rev); |
3e135d88 PO |
429 | } |
430 | ||
8a25a2fd KS |
431 | static ssize_t pf_show(struct device *dev, |
432 | struct device_attribute *attr, char *buf) | |
3e135d88 PO |
433 | { |
434 | struct ucode_cpu_info *uci = ucode_cpu_info + dev->id; | |
435 | ||
d45de409 | 436 | return sprintf(buf, "0x%x\n", uci->cpu_sig.pf); |
3e135d88 PO |
437 | } |
438 | ||
8a25a2fd KS |
439 | static DEVICE_ATTR(reload, 0200, NULL, reload_store); |
440 | static DEVICE_ATTR(version, 0400, version_show, NULL); | |
441 | static DEVICE_ATTR(processor_flags, 0400, pf_show, NULL); | |
3e135d88 PO |
442 | |
443 | static struct attribute *mc_default_attrs[] = { | |
8a25a2fd KS |
444 | &dev_attr_version.attr, |
445 | &dev_attr_processor_flags.attr, | |
3e135d88 PO |
446 | NULL |
447 | }; | |
448 | ||
449 | static struct attribute_group mc_attr_group = { | |
871b72dd DA |
450 | .attrs = mc_default_attrs, |
451 | .name = "microcode", | |
3e135d88 PO |
452 | }; |
453 | ||
871b72dd | 454 | static void microcode_fini_cpu(int cpu) |
d45de409 | 455 | { |
d45de409 | 456 | microcode_ops->microcode_fini_cpu(cpu); |
280a9ca5 DA |
457 | } |
458 | ||
871b72dd | 459 | static enum ucode_state microcode_resume_cpu(int cpu) |
d45de409 | 460 | { |
f58e1f53 | 461 | pr_debug("CPU%d updated upon resume\n", cpu); |
bb9d3e47 BP |
462 | |
463 | if (apply_microcode_on_target(cpu)) | |
464 | return UCODE_ERROR; | |
871b72dd DA |
465 | |
466 | return UCODE_OK; | |
d45de409 DA |
467 | } |
468 | ||
48e30685 | 469 | static enum ucode_state microcode_init_cpu(int cpu, bool refresh_fw) |
d45de409 | 470 | { |
871b72dd | 471 | enum ucode_state ustate; |
9cd4d78e FY |
472 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; |
473 | ||
43858f57 | 474 | if (uci->valid) |
9cd4d78e | 475 | return UCODE_OK; |
d45de409 | 476 | |
871b72dd DA |
477 | if (collect_cpu_info(cpu)) |
478 | return UCODE_ERROR; | |
d45de409 | 479 | |
871b72dd DA |
480 | /* --dimm. Trigger a delayed update? */ |
481 | if (system_state != SYSTEM_RUNNING) | |
482 | return UCODE_NFOUND; | |
d45de409 | 483 | |
48e30685 BP |
484 | ustate = microcode_ops->request_microcode_fw(cpu, µcode_pdev->dev, |
485 | refresh_fw); | |
d45de409 | 486 | |
871b72dd | 487 | if (ustate == UCODE_OK) { |
f58e1f53 | 488 | pr_debug("CPU%d updated upon init\n", cpu); |
871b72dd | 489 | apply_microcode_on_target(cpu); |
d45de409 DA |
490 | } |
491 | ||
871b72dd | 492 | return ustate; |
d45de409 DA |
493 | } |
494 | ||
871b72dd | 495 | static enum ucode_state microcode_update_cpu(int cpu) |
d45de409 | 496 | { |
871b72dd | 497 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; |
d45de409 | 498 | |
2f99f5c8 | 499 | if (uci->valid) |
bb9d3e47 | 500 | return microcode_resume_cpu(cpu); |
d45de409 | 501 | |
48e30685 | 502 | return microcode_init_cpu(cpu, false); |
d45de409 DA |
503 | } |
504 | ||
8a25a2fd | 505 | static int mc_device_add(struct device *dev, struct subsys_interface *sif) |
3e135d88 | 506 | { |
8a25a2fd | 507 | int err, cpu = dev->id; |
3e135d88 PO |
508 | |
509 | if (!cpu_online(cpu)) | |
510 | return 0; | |
511 | ||
f58e1f53 | 512 | pr_debug("CPU%d added\n", cpu); |
3e135d88 | 513 | |
8a25a2fd | 514 | err = sysfs_create_group(&dev->kobj, &mc_attr_group); |
3e135d88 PO |
515 | if (err) |
516 | return err; | |
517 | ||
48e30685 | 518 | if (microcode_init_cpu(cpu, true) == UCODE_ERROR) |
6c53cbfc | 519 | return -EINVAL; |
af5c820a RR |
520 | |
521 | return err; | |
3e135d88 PO |
522 | } |
523 | ||
71db87ba | 524 | static void mc_device_remove(struct device *dev, struct subsys_interface *sif) |
3e135d88 | 525 | { |
8a25a2fd | 526 | int cpu = dev->id; |
3e135d88 PO |
527 | |
528 | if (!cpu_online(cpu)) | |
71db87ba | 529 | return; |
3e135d88 | 530 | |
f58e1f53 | 531 | pr_debug("CPU%d removed\n", cpu); |
d45de409 | 532 | microcode_fini_cpu(cpu); |
8a25a2fd | 533 | sysfs_remove_group(&dev->kobj, &mc_attr_group); |
3e135d88 PO |
534 | } |
535 | ||
8a25a2fd KS |
536 | static struct subsys_interface mc_cpu_interface = { |
537 | .name = "microcode", | |
538 | .subsys = &cpu_subsys, | |
539 | .add_dev = mc_device_add, | |
540 | .remove_dev = mc_device_remove, | |
f3c6ea1b RW |
541 | }; |
542 | ||
543 | /** | |
544 | * mc_bp_resume - Update boot CPU microcode during resume. | |
545 | */ | |
546 | static void mc_bp_resume(void) | |
3e135d88 | 547 | { |
f3c6ea1b | 548 | int cpu = smp_processor_id(); |
871b72dd | 549 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; |
3e135d88 | 550 | |
871b72dd DA |
551 | if (uci->valid && uci->mc) |
552 | microcode_ops->apply_microcode(cpu); | |
fb86b973 | 553 | else if (!uci->mc) |
fbae4ba8 | 554 | reload_early_microcode(); |
3e135d88 PO |
555 | } |
556 | ||
f3c6ea1b RW |
557 | static struct syscore_ops mc_syscore_ops = { |
558 | .resume = mc_bp_resume, | |
3e135d88 PO |
559 | }; |
560 | ||
148f9bb8 | 561 | static int |
3e135d88 PO |
562 | mc_cpu_callback(struct notifier_block *nb, unsigned long action, void *hcpu) |
563 | { | |
564 | unsigned int cpu = (unsigned long)hcpu; | |
8a25a2fd | 565 | struct device *dev; |
3e135d88 | 566 | |
8a25a2fd | 567 | dev = get_cpu_device(cpu); |
09c3f0d8 BP |
568 | |
569 | switch (action & ~CPU_TASKS_FROZEN) { | |
3e135d88 | 570 | case CPU_ONLINE: |
871b72dd | 571 | microcode_update_cpu(cpu); |
f58e1f53 | 572 | pr_debug("CPU%d added\n", cpu); |
09c3f0d8 BP |
573 | /* |
574 | * "break" is missing on purpose here because we want to fall | |
575 | * through in order to create the sysfs group. | |
576 | */ | |
577 | ||
578 | case CPU_DOWN_FAILED: | |
8a25a2fd | 579 | if (sysfs_create_group(&dev->kobj, &mc_attr_group)) |
f58e1f53 | 580 | pr_err("Failed to create group for CPU%d\n", cpu); |
3e135d88 | 581 | break; |
09c3f0d8 | 582 | |
3e135d88 | 583 | case CPU_DOWN_PREPARE: |
3e135d88 | 584 | /* Suspend is in progress, only remove the interface */ |
8a25a2fd | 585 | sysfs_remove_group(&dev->kobj, &mc_attr_group); |
f58e1f53 | 586 | pr_debug("CPU%d removed\n", cpu); |
d45de409 | 587 | break; |
70989449 SB |
588 | |
589 | /* | |
09c3f0d8 BP |
590 | * case CPU_DEAD: |
591 | * | |
70989449 SB |
592 | * When a CPU goes offline, don't free up or invalidate the copy of |
593 | * the microcode in kernel memory, so that we can reuse it when the | |
594 | * CPU comes back online without unnecessarily requesting the userspace | |
595 | * for it again. | |
596 | */ | |
3e135d88 | 597 | } |
09c3f0d8 BP |
598 | |
599 | /* The CPU refused to come up during a system resume */ | |
600 | if (action == CPU_UP_CANCELED_FROZEN) | |
601 | microcode_fini_cpu(cpu); | |
602 | ||
3e135d88 PO |
603 | return NOTIFY_OK; |
604 | } | |
605 | ||
4daa832d | 606 | static struct notifier_block mc_cpu_notifier = { |
4bae1967 | 607 | .notifier_call = mc_cpu_callback, |
3e135d88 PO |
608 | }; |
609 | ||
3d8986bc BP |
610 | static struct attribute *cpu_root_microcode_attrs[] = { |
611 | &dev_attr_reload.attr, | |
612 | NULL | |
613 | }; | |
614 | ||
615 | static struct attribute_group cpu_root_microcode_group = { | |
616 | .name = "microcode", | |
617 | .attrs = cpu_root_microcode_attrs, | |
618 | }; | |
619 | ||
9a2bc335 | 620 | int __init microcode_init(void) |
3e135d88 | 621 | { |
9a2bc335 | 622 | struct cpuinfo_x86 *c = &boot_cpu_data; |
3e135d88 PO |
623 | int error; |
624 | ||
84aba677 | 625 | if (dis_ucode_ldr) |
da63865a | 626 | return -EINVAL; |
65cef131 | 627 | |
18dbc916 DA |
628 | if (c->x86_vendor == X86_VENDOR_INTEL) |
629 | microcode_ops = init_intel_microcode(); | |
82b07865 | 630 | else if (c->x86_vendor == X86_VENDOR_AMD) |
18dbc916 | 631 | microcode_ops = init_amd_microcode(); |
283c1f25 | 632 | else |
f58e1f53 | 633 | pr_err("no support for this CPU vendor\n"); |
283c1f25 AH |
634 | |
635 | if (!microcode_ops) | |
18dbc916 | 636 | return -ENODEV; |
3e135d88 | 637 | |
3e135d88 PO |
638 | microcode_pdev = platform_device_register_simple("microcode", -1, |
639 | NULL, 0); | |
bd399063 | 640 | if (IS_ERR(microcode_pdev)) |
3e135d88 | 641 | return PTR_ERR(microcode_pdev); |
3e135d88 PO |
642 | |
643 | get_online_cpus(); | |
871b72dd DA |
644 | mutex_lock(µcode_mutex); |
645 | ||
8a25a2fd | 646 | error = subsys_interface_register(&mc_cpu_interface); |
c93dc84c PZ |
647 | if (!error) |
648 | perf_check_microcode(); | |
871b72dd | 649 | mutex_unlock(µcode_mutex); |
3e135d88 | 650 | put_online_cpus(); |
871b72dd | 651 | |
bd399063 SB |
652 | if (error) |
653 | goto out_pdev; | |
3e135d88 | 654 | |
3d8986bc BP |
655 | error = sysfs_create_group(&cpu_subsys.dev_root->kobj, |
656 | &cpu_root_microcode_group); | |
657 | ||
658 | if (error) { | |
659 | pr_err("Error creating microcode group!\n"); | |
660 | goto out_driver; | |
661 | } | |
662 | ||
871b72dd DA |
663 | error = microcode_dev_init(); |
664 | if (error) | |
3d8986bc | 665 | goto out_ucode_group; |
871b72dd | 666 | |
f3c6ea1b | 667 | register_syscore_ops(&mc_syscore_ops); |
3e135d88 | 668 | register_hotcpu_notifier(&mc_cpu_notifier); |
8d86f390 | 669 | |
871b72dd | 670 | pr_info("Microcode Update Driver: v" MICROCODE_VERSION |
f58e1f53 | 671 | " <tigran@aivazian.fsnet.co.uk>, Peter Oruba\n"); |
8d86f390 | 672 | |
3e135d88 | 673 | return 0; |
bd399063 | 674 | |
3d8986bc BP |
675 | out_ucode_group: |
676 | sysfs_remove_group(&cpu_subsys.dev_root->kobj, | |
677 | &cpu_root_microcode_group); | |
678 | ||
679 | out_driver: | |
bd399063 SB |
680 | get_online_cpus(); |
681 | mutex_lock(µcode_mutex); | |
682 | ||
ff4b8a57 | 683 | subsys_interface_unregister(&mc_cpu_interface); |
bd399063 SB |
684 | |
685 | mutex_unlock(µcode_mutex); | |
686 | put_online_cpus(); | |
687 | ||
3d8986bc | 688 | out_pdev: |
bd399063 SB |
689 | platform_device_unregister(microcode_pdev); |
690 | return error; | |
691 | ||
3e135d88 | 692 | } |
4b703305 | 693 | fs_initcall(save_microcode_in_initrd); |
2d5be37d | 694 | late_initcall(microcode_init); |