x86/microcode/intel: Use *wrmsrl variants
[deliverable/linux.git] / arch / x86 / kernel / cpu / microcode / intel.c
CommitLineData
1da177e4 1/*
6b44e72a 2 * Intel CPU Microcode Update Driver for Linux
1da177e4 3 *
6b44e72a
BP
4 * Copyright (C) 2000-2006 Tigran Aivazian <tigran@aivazian.fsnet.co.uk>
5 * 2006 Shaohua Li <shaohua.li@intel.com>
1da177e4 6 *
fe055896
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7 * Intel CPU microcode early update for Linux
8 *
9 * Copyright (C) 2012 Fenghua Yu <fenghua.yu@intel.com>
10 * H Peter Anvin" <hpa@zytor.com>
11 *
6b44e72a
BP
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version
15 * 2 of the License, or (at your option) any later version.
1da177e4 16 */
f58e1f53 17
fe055896
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18/*
19 * This needs to be before all headers so that pr_debug in printk.h doesn't turn
20 * printk calls into no_printk().
21 *
22 *#define DEBUG
23 */
6b26e1bf 24#define pr_fmt(fmt) "microcode: " fmt
f58e1f53 25
fe055896 26#include <linux/earlycpio.h>
4bae1967 27#include <linux/firmware.h>
4bae1967 28#include <linux/uaccess.h>
fe055896
BP
29#include <linux/vmalloc.h>
30#include <linux/initrd.h>
4bae1967 31#include <linux/kernel.h>
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32#include <linux/slab.h>
33#include <linux/cpu.h>
34#include <linux/mm.h>
1da177e4 35
9cd4d78e 36#include <asm/microcode_intel.h>
4bae1967 37#include <asm/processor.h>
fe055896
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38#include <asm/tlbflush.h>
39#include <asm/setup.h>
4bae1967 40#include <asm/msr.h>
1da177e4 41
fe055896
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42static unsigned long mc_saved_in_initrd[MAX_UCODE_COUNT];
43static struct mc_saved_data {
4fe9349f 44 unsigned int num_saved;
fe055896
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45 struct microcode_intel **mc_saved;
46} mc_saved_data;
47
48static enum ucode_state
49load_microcode_early(struct microcode_intel **saved,
50 unsigned int num_saved, struct ucode_cpu_info *uci)
51{
52 struct microcode_intel *ucode_ptr, *new_mc = NULL;
53 struct microcode_header_intel *mc_hdr;
54 int new_rev, ret, i;
55
56 new_rev = uci->cpu_sig.rev;
57
58 for (i = 0; i < num_saved; i++) {
59 ucode_ptr = saved[i];
60 mc_hdr = (struct microcode_header_intel *)ucode_ptr;
61
62 ret = has_newer_microcode(ucode_ptr,
63 uci->cpu_sig.sig,
64 uci->cpu_sig.pf,
65 new_rev);
66 if (!ret)
67 continue;
68
69 new_rev = mc_hdr->rev;
70 new_mc = ucode_ptr;
71 }
72
73 if (!new_mc)
74 return UCODE_NFOUND;
75
76 uci->mc = (struct microcode_intel *)new_mc;
77 return UCODE_OK;
78}
79
80static inline void
81copy_initrd_ptrs(struct microcode_intel **mc_saved, unsigned long *initrd,
82 unsigned long off, int num_saved)
83{
84 int i;
85
86 for (i = 0; i < num_saved; i++)
87 mc_saved[i] = (struct microcode_intel *)(initrd[i] + off);
88}
89
90#ifdef CONFIG_X86_32
91static void
bd6fe58d 92microcode_phys(struct microcode_intel **mc_saved_tmp, struct mc_saved_data *mcs)
fe055896
BP
93{
94 int i;
95 struct microcode_intel ***mc_saved;
96
bd6fe58d
BP
97 mc_saved = (struct microcode_intel ***)__pa_nodebug(&mcs->mc_saved);
98
4fe9349f 99 for (i = 0; i < mcs->num_saved; i++) {
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100 struct microcode_intel *p;
101
bd6fe58d 102 p = *(struct microcode_intel **)__pa_nodebug(mcs->mc_saved + i);
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103 mc_saved_tmp[i] = (struct microcode_intel *)__pa_nodebug(p);
104 }
105}
106#endif
107
108static enum ucode_state
bd6fe58d 109load_microcode(struct mc_saved_data *mcs, unsigned long *initrd,
fe055896
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110 unsigned long initrd_start, struct ucode_cpu_info *uci)
111{
112 struct microcode_intel *mc_saved_tmp[MAX_UCODE_COUNT];
4fe9349f 113 unsigned int count = mcs->num_saved;
fe055896 114
bd6fe58d 115 if (!mcs->mc_saved) {
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116 copy_initrd_ptrs(mc_saved_tmp, initrd, initrd_start, count);
117
118 return load_microcode_early(mc_saved_tmp, count, uci);
119 } else {
120#ifdef CONFIG_X86_32
bd6fe58d 121 microcode_phys(mc_saved_tmp, mcs);
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122 return load_microcode_early(mc_saved_tmp, count, uci);
123#else
bd6fe58d 124 return load_microcode_early(mcs->mc_saved, count, uci);
fe055896
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125#endif
126 }
127}
128
129/*
130 * Given CPU signature and a microcode patch, this function finds if the
131 * microcode patch has matching family and model with the CPU.
132 */
133static enum ucode_state
134matching_model_microcode(struct microcode_header_intel *mc_header,
135 unsigned long sig)
136{
137 unsigned int fam, model;
138 unsigned int fam_ucode, model_ucode;
139 struct extended_sigtable *ext_header;
140 unsigned long total_size = get_totalsize(mc_header);
141 unsigned long data_size = get_datasize(mc_header);
142 int ext_sigcount, i;
143 struct extended_signature *ext_sig;
144
99f925ce 145 fam = x86_family(sig);
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146 model = x86_model(sig);
147
99f925ce 148 fam_ucode = x86_family(mc_header->sig);
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149 model_ucode = x86_model(mc_header->sig);
150
151 if (fam == fam_ucode && model == model_ucode)
152 return UCODE_OK;
153
154 /* Look for ext. headers: */
155 if (total_size <= data_size + MC_HEADER_SIZE)
156 return UCODE_NFOUND;
157
158 ext_header = (void *) mc_header + data_size + MC_HEADER_SIZE;
159 ext_sig = (void *)ext_header + EXT_HEADER_SIZE;
160 ext_sigcount = ext_header->count;
161
162 for (i = 0; i < ext_sigcount; i++) {
99f925ce 163 fam_ucode = x86_family(ext_sig->sig);
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164 model_ucode = x86_model(ext_sig->sig);
165
166 if (fam == fam_ucode && model == model_ucode)
167 return UCODE_OK;
168
169 ext_sig++;
170 }
171 return UCODE_NFOUND;
172}
173
174static int
bd6fe58d 175save_microcode(struct mc_saved_data *mcs,
fe055896 176 struct microcode_intel **mc_saved_src,
4fe9349f 177 unsigned int num_saved)
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178{
179 int i, j;
180 struct microcode_intel **saved_ptr;
181 int ret;
182
4fe9349f 183 if (!num_saved)
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184 return -EINVAL;
185
186 /*
187 * Copy new microcode data.
188 */
4fe9349f 189 saved_ptr = kcalloc(num_saved, sizeof(struct microcode_intel *), GFP_KERNEL);
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190 if (!saved_ptr)
191 return -ENOMEM;
192
4fe9349f 193 for (i = 0; i < num_saved; i++) {
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194 struct microcode_header_intel *mc_hdr;
195 struct microcode_intel *mc;
196 unsigned long size;
197
198 if (!mc_saved_src[i]) {
199 ret = -EINVAL;
200 goto err;
201 }
202
203 mc = mc_saved_src[i];
204 mc_hdr = &mc->hdr;
205 size = get_totalsize(mc_hdr);
206
207 saved_ptr[i] = kmalloc(size, GFP_KERNEL);
208 if (!saved_ptr[i]) {
209 ret = -ENOMEM;
210 goto err;
211 }
212
213 memcpy(saved_ptr[i], mc, size);
214 }
215
216 /*
217 * Point to newly saved microcode.
218 */
4fe9349f
BP
219 mcs->mc_saved = saved_ptr;
220 mcs->num_saved = num_saved;
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221
222 return 0;
223
224err:
225 for (j = 0; j <= i; j++)
226 kfree(saved_ptr[j]);
227 kfree(saved_ptr);
228
229 return ret;
230}
231
232/*
233 * A microcode patch in ucode_ptr is saved into mc_saved
234 * - if it has matching signature and newer revision compared to an existing
235 * patch mc_saved.
236 * - or if it is a newly discovered microcode patch.
237 *
238 * The microcode patch should have matching model with CPU.
239 *
240 * Returns: The updated number @num_saved of saved microcode patches.
241 */
242static unsigned int _save_mc(struct microcode_intel **mc_saved,
243 u8 *ucode_ptr, unsigned int num_saved)
244{
245 struct microcode_header_intel *mc_hdr, *mc_saved_hdr;
246 unsigned int sig, pf;
247 int found = 0, i;
248
249 mc_hdr = (struct microcode_header_intel *)ucode_ptr;
250
251 for (i = 0; i < num_saved; i++) {
252 mc_saved_hdr = (struct microcode_header_intel *)mc_saved[i];
253 sig = mc_saved_hdr->sig;
254 pf = mc_saved_hdr->pf;
255
256 if (!find_matching_signature(ucode_ptr, sig, pf))
257 continue;
258
259 found = 1;
260
261 if (mc_hdr->rev <= mc_saved_hdr->rev)
262 continue;
263
264 /*
265 * Found an older ucode saved earlier. Replace it with
266 * this newer one.
267 */
268 mc_saved[i] = (struct microcode_intel *)ucode_ptr;
269 break;
270 }
271
272 /* Newly detected microcode, save it to memory. */
273 if (i >= num_saved && !found)
274 mc_saved[num_saved++] = (struct microcode_intel *)ucode_ptr;
275
276 return num_saved;
277}
278
279/*
280 * Get microcode matching with BSP's model. Only CPUs with the same model as
281 * BSP can stay in the platform.
282 */
283static enum ucode_state __init
284get_matching_model_microcode(int cpu, unsigned long start,
285 void *data, size_t size,
bd6fe58d 286 struct mc_saved_data *mcs,
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287 unsigned long *mc_saved_in_initrd,
288 struct ucode_cpu_info *uci)
289{
290 u8 *ucode_ptr = data;
291 unsigned int leftover = size;
292 enum ucode_state state = UCODE_OK;
293 unsigned int mc_size;
294 struct microcode_header_intel *mc_header;
295 struct microcode_intel *mc_saved_tmp[MAX_UCODE_COUNT];
4fe9349f 296 unsigned int num_saved = mcs->num_saved;
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297 int i;
298
4fe9349f 299 while (leftover && num_saved < ARRAY_SIZE(mc_saved_tmp)) {
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300
301 if (leftover < sizeof(mc_header))
302 break;
303
304 mc_header = (struct microcode_header_intel *)ucode_ptr;
305
306 mc_size = get_totalsize(mc_header);
307 if (!mc_size || mc_size > leftover ||
308 microcode_sanity_check(ucode_ptr, 0) < 0)
309 break;
310
311 leftover -= mc_size;
312
313 /*
314 * Since APs with same family and model as the BSP may boot in
315 * the platform, we need to find and save microcode patches
316 * with the same family and model as the BSP.
317 */
318 if (matching_model_microcode(mc_header, uci->cpu_sig.sig) !=
319 UCODE_OK) {
320 ucode_ptr += mc_size;
321 continue;
322 }
323
4fe9349f 324 num_saved = _save_mc(mc_saved_tmp, ucode_ptr, num_saved);
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325
326 ucode_ptr += mc_size;
327 }
328
329 if (leftover) {
330 state = UCODE_ERROR;
331 goto out;
332 }
333
4fe9349f 334 if (!num_saved) {
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335 state = UCODE_NFOUND;
336 goto out;
337 }
338
4fe9349f 339 for (i = 0; i < num_saved; i++)
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340 mc_saved_in_initrd[i] = (unsigned long)mc_saved_tmp[i] - start;
341
4fe9349f 342 mcs->num_saved = num_saved;
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343out:
344 return state;
345}
346
347static int collect_cpu_info_early(struct ucode_cpu_info *uci)
348{
349 unsigned int val[2];
350 unsigned int family, model;
351 struct cpu_signature csig;
352 unsigned int eax, ebx, ecx, edx;
353
354 csig.sig = 0;
355 csig.pf = 0;
356 csig.rev = 0;
357
358 memset(uci, 0, sizeof(*uci));
359
360 eax = 0x00000001;
361 ecx = 0;
362 native_cpuid(&eax, &ebx, &ecx, &edx);
363 csig.sig = eax;
364
99f925ce 365 family = x86_family(csig.sig);
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366 model = x86_model(csig.sig);
367
368 if ((model >= 5) || (family > 6)) {
369 /* get processor flags from MSR 0x17 */
370 native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
371 csig.pf = 1 << ((val[1] >> 18) & 7);
372 }
c416e611 373 native_wrmsrl(MSR_IA32_UCODE_REV, 0);
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374
375 /* As documented in the SDM: Do a CPUID 1 here */
376 sync_core();
377
378 /* get the current revision from MSR 0x8B */
379 native_rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]);
380
381 csig.rev = val[1];
382
383 uci->cpu_sig = csig;
384 uci->valid = 1;
385
386 return 0;
387}
388
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389static void show_saved_mc(void)
390{
c595ac2b 391#ifdef DEBUG
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392 int i, j;
393 unsigned int sig, pf, rev, total_size, data_size, date;
394 struct ucode_cpu_info uci;
395
4fe9349f 396 if (!mc_saved_data.num_saved) {
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397 pr_debug("no microcode data saved.\n");
398 return;
399 }
4fe9349f 400 pr_debug("Total microcode saved: %d\n", mc_saved_data.num_saved);
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401
402 collect_cpu_info_early(&uci);
403
404 sig = uci.cpu_sig.sig;
405 pf = uci.cpu_sig.pf;
406 rev = uci.cpu_sig.rev;
407 pr_debug("CPU: sig=0x%x, pf=0x%x, rev=0x%x\n", sig, pf, rev);
408
4fe9349f 409 for (i = 0; i < mc_saved_data.num_saved; i++) {
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410 struct microcode_header_intel *mc_saved_header;
411 struct extended_sigtable *ext_header;
412 int ext_sigcount;
413 struct extended_signature *ext_sig;
414
415 mc_saved_header = (struct microcode_header_intel *)
416 mc_saved_data.mc_saved[i];
417 sig = mc_saved_header->sig;
418 pf = mc_saved_header->pf;
419 rev = mc_saved_header->rev;
420 total_size = get_totalsize(mc_saved_header);
421 data_size = get_datasize(mc_saved_header);
422 date = mc_saved_header->date;
423
424 pr_debug("mc_saved[%d]: sig=0x%x, pf=0x%x, rev=0x%x, toal size=0x%x, date = %04x-%02x-%02x\n",
425 i, sig, pf, rev, total_size,
426 date & 0xffff,
427 date >> 24,
428 (date >> 16) & 0xff);
429
430 /* Look for ext. headers: */
431 if (total_size <= data_size + MC_HEADER_SIZE)
432 continue;
433
434 ext_header = (void *) mc_saved_header + data_size + MC_HEADER_SIZE;
435 ext_sigcount = ext_header->count;
436 ext_sig = (void *)ext_header + EXT_HEADER_SIZE;
437
438 for (j = 0; j < ext_sigcount; j++) {
439 sig = ext_sig->sig;
440 pf = ext_sig->pf;
441
442 pr_debug("\tExtended[%d]: sig=0x%x, pf=0x%x\n",
443 j, sig, pf);
444
445 ext_sig++;
446 }
447
448 }
fe055896 449#endif
c595ac2b 450}
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451
452#ifdef CONFIG_HOTPLUG_CPU
453static DEFINE_MUTEX(x86_cpu_microcode_mutex);
454/*
455 * Save this mc into mc_saved_data. So it will be loaded early when a CPU is
456 * hot added or resumes.
457 *
458 * Please make sure this mc should be a valid microcode patch before calling
459 * this function.
460 */
461int save_mc_for_early(u8 *mc)
462{
463 struct microcode_intel *mc_saved_tmp[MAX_UCODE_COUNT];
464 unsigned int mc_saved_count_init;
4fe9349f 465 unsigned int num_saved;
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466 struct microcode_intel **mc_saved;
467 int ret = 0;
468 int i;
469
470 /*
471 * Hold hotplug lock so mc_saved_data is not accessed by a CPU in
472 * hotplug.
473 */
474 mutex_lock(&x86_cpu_microcode_mutex);
475
4fe9349f
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476 mc_saved_count_init = mc_saved_data.num_saved;
477 num_saved = mc_saved_data.num_saved;
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478 mc_saved = mc_saved_data.mc_saved;
479
4fe9349f 480 if (mc_saved && num_saved)
fe055896 481 memcpy(mc_saved_tmp, mc_saved,
4fe9349f 482 num_saved * sizeof(struct microcode_intel *));
fe055896
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483 /*
484 * Save the microcode patch mc in mc_save_tmp structure if it's a newer
485 * version.
486 */
4fe9349f 487 num_saved = _save_mc(mc_saved_tmp, mc, num_saved);
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488
489 /*
490 * Save the mc_save_tmp in global mc_saved_data.
491 */
4fe9349f 492 ret = save_microcode(&mc_saved_data, mc_saved_tmp, num_saved);
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493 if (ret) {
494 pr_err("Cannot save microcode patch.\n");
495 goto out;
496 }
497
498 show_saved_mc();
499
500 /*
501 * Free old saved microcode data.
502 */
503 if (mc_saved) {
504 for (i = 0; i < mc_saved_count_init; i++)
505 kfree(mc_saved[i]);
506 kfree(mc_saved);
507 }
508
509out:
510 mutex_unlock(&x86_cpu_microcode_mutex);
511
512 return ret;
513}
514EXPORT_SYMBOL_GPL(save_mc_for_early);
515#endif
516
517static bool __init load_builtin_intel_microcode(struct cpio_data *cp)
518{
519#ifdef CONFIG_X86_64
520 unsigned int eax = 0x00000001, ebx, ecx = 0, edx;
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521 char name[30];
522
523 native_cpuid(&eax, &ebx, &ecx, &edx);
524
99f925ce
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525 sprintf(name, "intel-ucode/%02x-%02x-%02x",
526 x86_family(eax), x86_model(eax), x86_stepping(eax));
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527
528 return get_builtin_firmware(cp, name);
529#else
530 return false;
531#endif
532}
533
534static __initdata char ucode_name[] = "kernel/x86/microcode/GenuineIntel.bin";
535static __init enum ucode_state
bd6fe58d 536scan_microcode(struct mc_saved_data *mcs, unsigned long *initrd,
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537 unsigned long start, unsigned long size,
538 struct ucode_cpu_info *uci)
539{
540 struct cpio_data cd;
541 long offset = 0;
542#ifdef CONFIG_X86_32
543 char *p = (char *)__pa_nodebug(ucode_name);
544#else
545 char *p = ucode_name;
546#endif
547
548 cd.data = NULL;
549 cd.size = 0;
550
264285ac
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551 /* try built-in microcode if no initrd */
552 if (!size) {
fe055896
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553 if (!load_builtin_intel_microcode(&cd))
554 return UCODE_ERROR;
264285ac
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555 } else {
556 cd = find_cpio_data(p, (void *)start, size, &offset);
557 if (!cd.data)
558 return UCODE_ERROR;
fe055896
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559 }
560
561 return get_matching_model_microcode(0, start, cd.data, cd.size,
bd6fe58d 562 mcs, initrd, uci);
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563}
564
565/*
566 * Print ucode update info.
567 */
568static void
569print_ucode_info(struct ucode_cpu_info *uci, unsigned int date)
570{
b7f500ae
BP
571 pr_info_once("microcode updated early to revision 0x%x, date = %04x-%02x-%02x\n",
572 uci->cpu_sig.rev,
573 date & 0xffff,
574 date >> 24,
575 (date >> 16) & 0xff);
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576}
577
578#ifdef CONFIG_X86_32
579
580static int delay_ucode_info;
581static int current_mc_date;
582
583/*
584 * Print early updated ucode info after printk works. This is delayed info dump.
585 */
586void show_ucode_info_early(void)
587{
588 struct ucode_cpu_info uci;
589
590 if (delay_ucode_info) {
591 collect_cpu_info_early(&uci);
592 print_ucode_info(&uci, current_mc_date);
593 delay_ucode_info = 0;
594 }
595}
596
597/*
598 * At this point, we can not call printk() yet. Keep microcode patch number in
599 * mc_saved_data.mc_saved and delay printing microcode info in
600 * show_ucode_info_early() until printk() works.
601 */
602static void print_ucode(struct ucode_cpu_info *uci)
603{
de778275 604 struct microcode_intel *mc;
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605 int *delay_ucode_info_p;
606 int *current_mc_date_p;
607
de778275
BP
608 mc = uci->mc;
609 if (!mc)
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610 return;
611
612 delay_ucode_info_p = (int *)__pa_nodebug(&delay_ucode_info);
613 current_mc_date_p = (int *)__pa_nodebug(&current_mc_date);
614
615 *delay_ucode_info_p = 1;
de778275 616 *current_mc_date_p = mc->hdr.date;
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617}
618#else
619
620/*
621 * Flush global tlb. We only do this in x86_64 where paging has been enabled
622 * already and PGE should be enabled as well.
623 */
624static inline void flush_tlb_early(void)
625{
626 __native_flush_tlb_global_irq_disabled();
627}
628
629static inline void print_ucode(struct ucode_cpu_info *uci)
630{
de778275 631 struct microcode_intel *mc;
fe055896 632
de778275
BP
633 mc = uci->mc;
634 if (!mc)
fe055896
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635 return;
636
de778275 637 print_ucode_info(uci, mc->hdr.date);
fe055896
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638}
639#endif
640
641static int apply_microcode_early(struct ucode_cpu_info *uci, bool early)
642{
de778275 643 struct microcode_intel *mc;
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644 unsigned int val[2];
645
de778275
BP
646 mc = uci->mc;
647 if (!mc)
fe055896
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648 return 0;
649
650 /* write microcode via MSR 0x79 */
c416e611
BP
651 native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
652 native_wrmsrl(MSR_IA32_UCODE_REV, 0);
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653
654 /* As documented in the SDM: Do a CPUID 1 here */
655 sync_core();
656
657 /* get the current revision from MSR 0x8B */
658 native_rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]);
de778275 659 if (val[1] != mc->hdr.rev)
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660 return -1;
661
662#ifdef CONFIG_X86_64
663 /* Flush global tlb. This is precaution. */
664 flush_tlb_early();
665#endif
666 uci->cpu_sig.rev = val[1];
667
668 if (early)
669 print_ucode(uci);
670 else
de778275 671 print_ucode_info(uci, mc->hdr.date);
fe055896
BP
672
673 return 0;
674}
675
676/*
677 * This function converts microcode patch offsets previously stored in
678 * mc_saved_in_initrd to pointers and stores the pointers in mc_saved_data.
679 */
680int __init save_microcode_in_initrd_intel(void)
681{
4fe9349f 682 unsigned int count = mc_saved_data.num_saved;
fe055896
BP
683 struct microcode_intel *mc_saved[MAX_UCODE_COUNT];
684 int ret = 0;
685
4fe9349f 686 if (!count)
fe055896
BP
687 return ret;
688
5f9c01aa 689 copy_initrd_ptrs(mc_saved, mc_saved_in_initrd, get_initrd_start(), count);
4fe9349f 690
fe055896
BP
691 ret = save_microcode(&mc_saved_data, mc_saved, count);
692 if (ret)
693 pr_err("Cannot save microcode patches from initrd.\n");
694
695 show_saved_mc();
696
697 return ret;
698}
699
700static void __init
bd6fe58d 701_load_ucode_intel_bsp(struct mc_saved_data *mcs, unsigned long *initrd,
fe055896
BP
702 unsigned long start, unsigned long size)
703{
704 struct ucode_cpu_info uci;
705 enum ucode_state ret;
706
707 collect_cpu_info_early(&uci);
708
bd6fe58d 709 ret = scan_microcode(mcs, initrd, start, size, &uci);
fe055896
BP
710 if (ret != UCODE_OK)
711 return;
712
bd6fe58d 713 ret = load_microcode(mcs, initrd, start, &uci);
fe055896
BP
714 if (ret != UCODE_OK)
715 return;
716
717 apply_microcode_early(&uci, true);
718}
719
720void __init load_ucode_intel_bsp(void)
721{
722 u64 start, size;
723#ifdef CONFIG_X86_32
724 struct boot_params *p;
725
726 p = (struct boot_params *)__pa_nodebug(&boot_params);
fe055896
BP
727 size = p->hdr.ramdisk_size;
728
264285ac
BP
729 /*
730 * Set start only if we have an initrd image. We cannot use initrd_start
731 * because it is not set that early yet.
732 */
733 start = (size ? p->hdr.ramdisk_image : 0);
734
735 _load_ucode_intel_bsp((struct mc_saved_data *)__pa_nodebug(&mc_saved_data),
736 (unsigned long *)__pa_nodebug(&mc_saved_in_initrd),
737 start, size);
fe055896 738#else
fe055896 739 size = boot_params.hdr.ramdisk_size;
264285ac 740 start = (size ? boot_params.hdr.ramdisk_image + PAGE_OFFSET : 0);
fe055896
BP
741
742 _load_ucode_intel_bsp(&mc_saved_data, mc_saved_in_initrd, start, size);
743#endif
744}
745
746void load_ucode_intel_ap(void)
747{
fe055896 748 unsigned long *mc_saved_in_initrd_p;
bd6fe58d
BP
749 struct mc_saved_data *mcs_p;
750 struct ucode_cpu_info uci;
fe055896
BP
751 enum ucode_state ret;
752#ifdef CONFIG_X86_32
fe055896 753
5f9c01aa 754 mc_saved_in_initrd_p = (unsigned long *)__pa_nodebug(mc_saved_in_initrd);
bd6fe58d 755 mcs_p = (struct mc_saved_data *)__pa_nodebug(&mc_saved_data);
fe055896 756#else
fe055896 757 mc_saved_in_initrd_p = mc_saved_in_initrd;
bd6fe58d 758 mcs_p = &mc_saved_data;
fe055896
BP
759#endif
760
761 /*
762 * If there is no valid ucode previously saved in memory, no need to
763 * update ucode on this AP.
764 */
4fe9349f 765 if (!mcs_p->num_saved)
fe055896
BP
766 return;
767
768 collect_cpu_info_early(&uci);
bd6fe58d 769 ret = load_microcode(mcs_p, mc_saved_in_initrd_p,
5f9c01aa 770 get_initrd_start_addr(), &uci);
fe055896
BP
771
772 if (ret != UCODE_OK)
773 return;
774
775 apply_microcode_early(&uci, true);
776}
777
778void reload_ucode_intel(void)
779{
780 struct ucode_cpu_info uci;
781 enum ucode_state ret;
782
4fe9349f 783 if (!mc_saved_data.num_saved)
fe055896
BP
784 return;
785
786 collect_cpu_info_early(&uci);
787
788 ret = load_microcode_early(mc_saved_data.mc_saved,
4fe9349f 789 mc_saved_data.num_saved, &uci);
fe055896
BP
790 if (ret != UCODE_OK)
791 return;
792
793 apply_microcode_early(&uci, false);
794}
795
d45de409 796static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
1da177e4 797{
92cb7612 798 struct cpuinfo_x86 *c = &cpu_data(cpu_num);
1da177e4
LT
799 unsigned int val[2];
800
d45de409 801 memset(csig, 0, sizeof(*csig));
1da177e4 802
d45de409 803 csig->sig = cpuid_eax(0x00000001);
9a3110bf
SL
804
805 if ((c->x86_model >= 5) || (c->x86 > 6)) {
806 /* get processor flags from MSR 0x17 */
807 rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
d45de409 808 csig->pf = 1 << ((val[1] >> 18) & 7);
1da177e4
LT
809 }
810
506ed6b5 811 csig->rev = c->microcode;
f58e1f53
JP
812 pr_info("CPU%d sig=0x%x, pf=0x%x, revision=0x%x\n",
813 cpu_num, csig->sig, csig->pf, csig->rev);
d45de409
DA
814
815 return 0;
1da177e4
LT
816}
817
9a3110bf
SL
818/*
819 * return 0 - no update found
820 * return 1 - found update
9a3110bf 821 */
de778275 822static int get_matching_mc(struct microcode_intel *mc, int cpu)
9a3110bf 823{
9cd4d78e
FY
824 struct cpu_signature cpu_sig;
825 unsigned int csig, cpf, crev;
9a3110bf 826
9cd4d78e 827 collect_cpu_info(cpu, &cpu_sig);
a0a29b62 828
9cd4d78e
FY
829 csig = cpu_sig.sig;
830 cpf = cpu_sig.pf;
831 crev = cpu_sig.rev;
9a3110bf 832
de778275 833 return has_newer_microcode(mc, csig, cpf, crev);
1da177e4
LT
834}
835
532ed374 836static int apply_microcode_intel(int cpu)
1da177e4 837{
de778275 838 struct microcode_intel *mc;
4bae1967 839 struct ucode_cpu_info *uci;
26cbaa4d 840 struct cpuinfo_x86 *c;
1da177e4 841 unsigned int val[2];
4bae1967 842
9a3110bf 843 /* We should bind the task to the CPU */
26cbaa4d 844 if (WARN_ON(raw_smp_processor_id() != cpu))
58b5f2cc 845 return -1;
9a3110bf 846
58b5f2cc
BP
847 uci = ucode_cpu_info + cpu;
848 mc = uci->mc;
de778275 849 if (!mc)
871b72dd 850 return 0;
1da177e4 851
9cd4d78e
FY
852 /*
853 * Microcode on this CPU could be updated earlier. Only apply the
de778275 854 * microcode patch in mc when it is newer than the one on this
9cd4d78e
FY
855 * CPU.
856 */
de778275 857 if (!get_matching_mc(mc, cpu))
9cd4d78e
FY
858 return 0;
859
1da177e4 860 /* write microcode via MSR 0x79 */
c416e611
BP
861 wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
862 wrmsrl(MSR_IA32_UCODE_REV, 0);
1da177e4 863
506ed6b5 864 /* As documented in the SDM: Do a CPUID 1 here */
487472bc 865 sync_core();
245067d1 866
1da177e4
LT
867 /* get the current revision from MSR 0x8B */
868 rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]);
869
de778275 870 if (val[1] != mc->hdr.rev) {
f58e1f53 871 pr_err("CPU%d update to revision 0x%x failed\n",
26cbaa4d 872 cpu, mc->hdr.rev);
871b72dd 873 return -1;
9a3110bf 874 }
26cbaa4d 875
3235dc3f 876 pr_info("CPU%d updated to revision 0x%x, date = %04x-%02x-%02x\n",
26cbaa4d 877 cpu, val[1],
de778275
BP
878 mc->hdr.date & 0xffff,
879 mc->hdr.date >> 24,
880 (mc->hdr.date >> 16) & 0xff);
4bae1967 881
26cbaa4d
BP
882 c = &cpu_data(cpu);
883
d45de409 884 uci->cpu_sig.rev = val[1];
506ed6b5 885 c->microcode = val[1];
871b72dd
DA
886
887 return 0;
1da177e4
LT
888}
889
871b72dd
DA
890static enum ucode_state generic_load_microcode(int cpu, void *data, size_t size,
891 int (*get_ucode_data)(void *, const void *, size_t))
9a3110bf 892{
a0a29b62 893 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
938179b4 894 u8 *ucode_ptr = data, *new_mc = NULL, *mc = NULL;
a0a29b62
DA
895 int new_rev = uci->cpu_sig.rev;
896 unsigned int leftover = size;
871b72dd 897 enum ucode_state state = UCODE_OK;
938179b4 898 unsigned int curr_mc_size = 0;
9cd4d78e 899 unsigned int csig, cpf;
9a3110bf 900
a0a29b62
DA
901 while (leftover) {
902 struct microcode_header_intel mc_header;
903 unsigned int mc_size;
9a3110bf 904
35a9ff4e
QC
905 if (leftover < sizeof(mc_header)) {
906 pr_err("error! Truncated header in microcode data file\n");
907 break;
908 }
909
a0a29b62
DA
910 if (get_ucode_data(&mc_header, ucode_ptr, sizeof(mc_header)))
911 break;
a30a6a2c 912
a0a29b62
DA
913 mc_size = get_totalsize(&mc_header);
914 if (!mc_size || mc_size > leftover) {
f58e1f53 915 pr_err("error! Bad data in microcode data file\n");
a0a29b62
DA
916 break;
917 }
a30a6a2c 918
938179b4
DS
919 /* For performance reasons, reuse mc area when possible */
920 if (!mc || mc_size > curr_mc_size) {
5cdd2de0 921 vfree(mc);
938179b4
DS
922 mc = vmalloc(mc_size);
923 if (!mc)
924 break;
925 curr_mc_size = mc_size;
926 }
a0a29b62
DA
927
928 if (get_ucode_data(mc, ucode_ptr, mc_size) ||
9cd4d78e 929 microcode_sanity_check(mc, 1) < 0) {
a0a29b62
DA
930 break;
931 }
932
9cd4d78e
FY
933 csig = uci->cpu_sig.sig;
934 cpf = uci->cpu_sig.pf;
8de3eafc 935 if (has_newer_microcode(mc, csig, cpf, new_rev)) {
5cdd2de0 936 vfree(new_mc);
a0a29b62
DA
937 new_rev = mc_header.rev;
938 new_mc = mc;
938179b4
DS
939 mc = NULL; /* trigger new vmalloc */
940 }
a0a29b62
DA
941
942 ucode_ptr += mc_size;
943 leftover -= mc_size;
a30a6a2c
SL
944 }
945
5cdd2de0 946 vfree(mc);
938179b4 947
871b72dd 948 if (leftover) {
5cdd2de0 949 vfree(new_mc);
871b72dd 950 state = UCODE_ERROR;
4bae1967 951 goto out;
871b72dd 952 }
4bae1967 953
871b72dd
DA
954 if (!new_mc) {
955 state = UCODE_NFOUND;
4bae1967 956 goto out;
a30a6a2c 957 }
a0a29b62 958
5cdd2de0 959 vfree(uci->mc);
4bae1967
IM
960 uci->mc = (struct microcode_intel *)new_mc;
961
9cd4d78e
FY
962 /*
963 * If early loading microcode is supported, save this mc into
964 * permanent memory. So it will be loaded early when a CPU is hot added
965 * or resumes.
966 */
967 save_mc_for_early(new_mc);
968
f58e1f53
JP
969 pr_debug("CPU%d found a matching microcode update with version 0x%x (current=0x%x)\n",
970 cpu, new_rev, uci->cpu_sig.rev);
871b72dd
DA
971out:
972 return state;
a30a6a2c
SL
973}
974
a0a29b62
DA
975static int get_ucode_fw(void *to, const void *from, size_t n)
976{
977 memcpy(to, from, n);
978 return 0;
979}
a30a6a2c 980
48e30685
BP
981static enum ucode_state request_microcode_fw(int cpu, struct device *device,
982 bool refresh_fw)
a30a6a2c
SL
983{
984 char name[30];
92cb7612 985 struct cpuinfo_x86 *c = &cpu_data(cpu);
a30a6a2c 986 const struct firmware *firmware;
871b72dd 987 enum ucode_state ret;
a30a6a2c 988
3e135d88 989 sprintf(name, "intel-ucode/%02x-%02x-%02x",
a30a6a2c 990 c->x86, c->x86_model, c->x86_mask);
871b72dd 991
75da02b2 992 if (request_firmware_direct(&firmware, name, device)) {
f58e1f53 993 pr_debug("data file %s load failed\n", name);
871b72dd 994 return UCODE_NFOUND;
a30a6a2c 995 }
a0a29b62 996
dd3feda7
JSR
997 ret = generic_load_microcode(cpu, (void *)firmware->data,
998 firmware->size, &get_ucode_fw);
a0a29b62 999
a30a6a2c
SL
1000 release_firmware(firmware);
1001
a0a29b62
DA
1002 return ret;
1003}
1004
1005static int get_ucode_user(void *to, const void *from, size_t n)
1006{
1007 return copy_from_user(to, from, n);
1008}
1009
871b72dd
DA
1010static enum ucode_state
1011request_microcode_user(int cpu, const void __user *buf, size_t size)
a0a29b62 1012{
dd3feda7 1013 return generic_load_microcode(cpu, (void *)buf, size, &get_ucode_user);
a30a6a2c
SL
1014}
1015
8d86f390 1016static void microcode_fini_cpu(int cpu)
a30a6a2c
SL
1017{
1018 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
1019
18dbc916
DA
1020 vfree(uci->mc);
1021 uci->mc = NULL;
a30a6a2c 1022}
8d86f390 1023
4db646b1 1024static struct microcode_ops microcode_intel_ops = {
a0a29b62
DA
1025 .request_microcode_user = request_microcode_user,
1026 .request_microcode_fw = request_microcode_fw,
8d86f390 1027 .collect_cpu_info = collect_cpu_info,
532ed374 1028 .apply_microcode = apply_microcode_intel,
8d86f390
PO
1029 .microcode_fini_cpu = microcode_fini_cpu,
1030};
1031
18dbc916 1032struct microcode_ops * __init init_intel_microcode(void)
8d86f390 1033{
9a2bc335 1034 struct cpuinfo_x86 *c = &boot_cpu_data;
7164b3f5
SB
1035
1036 if (c->x86_vendor != X86_VENDOR_INTEL || c->x86 < 6 ||
1037 cpu_has(c, X86_FEATURE_IA64)) {
1038 pr_err("Intel CPU family 0x%x not supported\n", c->x86);
1039 return NULL;
1040 }
1041
18dbc916 1042 return &microcode_intel_ops;
8d86f390
PO
1043}
1044
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