Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Intel CPU Microcode Update Driver for Linux | |
3 | * | |
69688262 | 4 | * Copyright (C) 2000-2006 Tigran Aivazian <tigran@aivazian.fsnet.co.uk> |
9a3110bf | 5 | * 2006 Shaohua Li <shaohua.li@intel.com> |
1da177e4 LT |
6 | * |
7 | * This driver allows to upgrade microcode on Intel processors | |
bc4e0f9a | 8 | * belonging to IA-32 family - PentiumPro, Pentium II, |
1da177e4 LT |
9 | * Pentium III, Xeon, Pentium 4, etc. |
10 | * | |
bc4e0f9a BC |
11 | * Reference: Section 8.11 of Volume 3a, IA-32 Intel? Architecture |
12 | * Software Developer's Manual | |
13 | * Order Number 253668 or free download from: | |
14 | * | |
50a23e6e | 15 | * http://developer.intel.com/Assets/PDF/manual/253668.pdf |
1da177e4 LT |
16 | * |
17 | * For more information, go to http://www.urbanmyth.org/microcode | |
18 | * | |
19 | * This program is free software; you can redistribute it and/or | |
20 | * modify it under the terms of the GNU General Public License | |
21 | * as published by the Free Software Foundation; either version | |
22 | * 2 of the License, or (at your option) any later version. | |
23 | * | |
24 | * 1.0 16 Feb 2000, Tigran Aivazian <tigran@sco.com> | |
25 | * Initial release. | |
26 | * 1.01 18 Feb 2000, Tigran Aivazian <tigran@sco.com> | |
27 | * Added read() support + cleanups. | |
28 | * 1.02 21 Feb 2000, Tigran Aivazian <tigran@sco.com> | |
29 | * Added 'device trimming' support. open(O_WRONLY) zeroes | |
30 | * and frees the saved copy of applied microcode. | |
31 | * 1.03 29 Feb 2000, Tigran Aivazian <tigran@sco.com> | |
32 | * Made to use devfs (/dev/cpu/microcode) + cleanups. | |
33 | * 1.04 06 Jun 2000, Simon Trimmer <simon@veritas.com> | |
34 | * Added misc device support (now uses both devfs and misc). | |
35 | * Added MICROCODE_IOCFREE ioctl to clear memory. | |
36 | * 1.05 09 Jun 2000, Simon Trimmer <simon@veritas.com> | |
37 | * Messages for error cases (non Intel & no suitable microcode). | |
38 | * 1.06 03 Aug 2000, Tigran Aivazian <tigran@veritas.com> | |
39 | * Removed ->release(). Removed exclusive open and status bitmap. | |
40 | * Added microcode_rwsem to serialize read()/write()/ioctl(). | |
41 | * Removed global kernel lock usage. | |
42 | * 1.07 07 Sep 2000, Tigran Aivazian <tigran@veritas.com> | |
43 | * Write 0 to 0x8B msr and then cpuid before reading revision, | |
44 | * so that it works even if there were no update done by the | |
45 | * BIOS. Otherwise, reading from 0x8B gives junk (which happened | |
46 | * to be 0 on my machine which is why it worked even when I | |
47 | * disabled update by the BIOS) | |
48 | * Thanks to Eric W. Biederman <ebiederman@lnxi.com> for the fix. | |
49 | * 1.08 11 Dec 2000, Richard Schaal <richard.schaal@intel.com> and | |
50 | * Tigran Aivazian <tigran@veritas.com> | |
51 | * Intel Pentium 4 processor support and bugfixes. | |
52 | * 1.09 30 Oct 2001, Tigran Aivazian <tigran@veritas.com> | |
53 | * Bugfix for HT (Hyper-Threading) enabled processors | |
54 | * whereby processor resources are shared by all logical processors | |
55 | * in a single CPU package. | |
56 | * 1.10 28 Feb 2002 Asit K Mallick <asit.k.mallick@intel.com> and | |
57 | * Tigran Aivazian <tigran@veritas.com>, | |
f516526f PO |
58 | * Serialize updates as required on HT processors due to |
59 | * speculative nature of implementation. | |
1da177e4 LT |
60 | * 1.11 22 Mar 2002 Tigran Aivazian <tigran@veritas.com> |
61 | * Fix the panic when writing zero-length microcode chunk. | |
bc4e0f9a | 62 | * 1.12 29 Sep 2003 Nitin Kamble <nitin.a.kamble@intel.com>, |
1da177e4 LT |
63 | * Jun Nakajima <jun.nakajima@intel.com> |
64 | * Support for the microcode updates in the new format. | |
65 | * 1.13 10 Oct 2003 Tigran Aivazian <tigran@veritas.com> | |
66 | * Removed ->read() method and obsoleted MICROCODE_IOCFREE ioctl | |
bc4e0f9a | 67 | * because we no longer hold a copy of applied microcode |
1da177e4 LT |
68 | * in kernel memory. |
69 | * 1.14 25 Jun 2004 Tigran Aivazian <tigran@veritas.com> | |
70 | * Fix sigmatch() macro to handle old CPUs with pf == 0. | |
71 | * Thanks to Stuart Swales for pointing out this bug. | |
72 | */ | |
f58e1f53 JP |
73 | |
74 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
75 | ||
4bae1967 | 76 | #include <linux/firmware.h> |
4bae1967 | 77 | #include <linux/uaccess.h> |
4bae1967 IM |
78 | #include <linux/kernel.h> |
79 | #include <linux/module.h> | |
871b72dd | 80 | #include <linux/vmalloc.h> |
1da177e4 | 81 | |
9cd4d78e | 82 | #include <asm/microcode_intel.h> |
4bae1967 IM |
83 | #include <asm/processor.h> |
84 | #include <asm/msr.h> | |
1da177e4 | 85 | |
3e135d88 | 86 | MODULE_DESCRIPTION("Microcode Update Driver"); |
69688262 | 87 | MODULE_AUTHOR("Tigran Aivazian <tigran@aivazian.fsnet.co.uk>"); |
1da177e4 LT |
88 | MODULE_LICENSE("GPL"); |
89 | ||
d45de409 | 90 | static int collect_cpu_info(int cpu_num, struct cpu_signature *csig) |
1da177e4 | 91 | { |
92cb7612 | 92 | struct cpuinfo_x86 *c = &cpu_data(cpu_num); |
1da177e4 LT |
93 | unsigned int val[2]; |
94 | ||
d45de409 | 95 | memset(csig, 0, sizeof(*csig)); |
1da177e4 | 96 | |
d45de409 | 97 | csig->sig = cpuid_eax(0x00000001); |
9a3110bf SL |
98 | |
99 | if ((c->x86_model >= 5) || (c->x86 > 6)) { | |
100 | /* get processor flags from MSR 0x17 */ | |
101 | rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]); | |
d45de409 | 102 | csig->pf = 1 << ((val[1] >> 18) & 7); |
1da177e4 LT |
103 | } |
104 | ||
506ed6b5 | 105 | csig->rev = c->microcode; |
f58e1f53 JP |
106 | pr_info("CPU%d sig=0x%x, pf=0x%x, revision=0x%x\n", |
107 | cpu_num, csig->sig, csig->pf, csig->rev); | |
d45de409 DA |
108 | |
109 | return 0; | |
1da177e4 LT |
110 | } |
111 | ||
9a3110bf SL |
112 | /* |
113 | * return 0 - no update found | |
114 | * return 1 - found update | |
9a3110bf | 115 | */ |
9cd4d78e | 116 | static int get_matching_mc(struct microcode_intel *mc_intel, int cpu) |
9a3110bf | 117 | { |
9cd4d78e FY |
118 | struct cpu_signature cpu_sig; |
119 | unsigned int csig, cpf, crev; | |
9a3110bf | 120 | |
9cd4d78e | 121 | collect_cpu_info(cpu, &cpu_sig); |
a0a29b62 | 122 | |
9cd4d78e FY |
123 | csig = cpu_sig.sig; |
124 | cpf = cpu_sig.pf; | |
125 | crev = cpu_sig.rev; | |
9a3110bf | 126 | |
9cd4d78e | 127 | return get_matching_microcode(csig, cpf, mc_intel, crev); |
1da177e4 LT |
128 | } |
129 | ||
532ed374 | 130 | static int apply_microcode_intel(int cpu) |
1da177e4 | 131 | { |
4bae1967 IM |
132 | struct microcode_intel *mc_intel; |
133 | struct ucode_cpu_info *uci; | |
1da177e4 | 134 | unsigned int val[2]; |
506ed6b5 AK |
135 | int cpu_num = raw_smp_processor_id(); |
136 | struct cpuinfo_x86 *c = &cpu_data(cpu_num); | |
4bae1967 | 137 | |
4bae1967 IM |
138 | uci = ucode_cpu_info + cpu; |
139 | mc_intel = uci->mc; | |
1da177e4 | 140 | |
9a3110bf SL |
141 | /* We should bind the task to the CPU */ |
142 | BUG_ON(cpu_num != cpu); | |
143 | ||
18dbc916 | 144 | if (mc_intel == NULL) |
871b72dd | 145 | return 0; |
1da177e4 | 146 | |
9cd4d78e FY |
147 | /* |
148 | * Microcode on this CPU could be updated earlier. Only apply the | |
149 | * microcode patch in mc_intel when it is newer than the one on this | |
150 | * CPU. | |
151 | */ | |
152 | if (get_matching_mc(mc_intel, cpu) == 0) | |
153 | return 0; | |
154 | ||
1da177e4 LT |
155 | /* write microcode via MSR 0x79 */ |
156 | wrmsr(MSR_IA32_UCODE_WRITE, | |
18dbc916 DA |
157 | (unsigned long) mc_intel->bits, |
158 | (unsigned long) mc_intel->bits >> 16 >> 16); | |
1da177e4 LT |
159 | wrmsr(MSR_IA32_UCODE_REV, 0, 0); |
160 | ||
506ed6b5 | 161 | /* As documented in the SDM: Do a CPUID 1 here */ |
487472bc | 162 | sync_core(); |
245067d1 | 163 | |
1da177e4 LT |
164 | /* get the current revision from MSR 0x8B */ |
165 | rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]); | |
166 | ||
18dbc916 | 167 | if (val[1] != mc_intel->hdr.rev) { |
f58e1f53 JP |
168 | pr_err("CPU%d update to revision 0x%x failed\n", |
169 | cpu_num, mc_intel->hdr.rev); | |
871b72dd | 170 | return -1; |
9a3110bf | 171 | } |
3235dc3f | 172 | pr_info("CPU%d updated to revision 0x%x, date = %04x-%02x-%02x\n", |
871b72dd | 173 | cpu_num, val[1], |
18dbc916 DA |
174 | mc_intel->hdr.date & 0xffff, |
175 | mc_intel->hdr.date >> 24, | |
176 | (mc_intel->hdr.date >> 16) & 0xff); | |
4bae1967 | 177 | |
d45de409 | 178 | uci->cpu_sig.rev = val[1]; |
506ed6b5 | 179 | c->microcode = val[1]; |
871b72dd DA |
180 | |
181 | return 0; | |
1da177e4 LT |
182 | } |
183 | ||
871b72dd DA |
184 | static enum ucode_state generic_load_microcode(int cpu, void *data, size_t size, |
185 | int (*get_ucode_data)(void *, const void *, size_t)) | |
9a3110bf | 186 | { |
a0a29b62 | 187 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; |
938179b4 | 188 | u8 *ucode_ptr = data, *new_mc = NULL, *mc = NULL; |
a0a29b62 DA |
189 | int new_rev = uci->cpu_sig.rev; |
190 | unsigned int leftover = size; | |
871b72dd | 191 | enum ucode_state state = UCODE_OK; |
938179b4 | 192 | unsigned int curr_mc_size = 0; |
9cd4d78e | 193 | unsigned int csig, cpf; |
9a3110bf | 194 | |
a0a29b62 DA |
195 | while (leftover) { |
196 | struct microcode_header_intel mc_header; | |
197 | unsigned int mc_size; | |
9a3110bf | 198 | |
a0a29b62 DA |
199 | if (get_ucode_data(&mc_header, ucode_ptr, sizeof(mc_header))) |
200 | break; | |
a30a6a2c | 201 | |
a0a29b62 DA |
202 | mc_size = get_totalsize(&mc_header); |
203 | if (!mc_size || mc_size > leftover) { | |
f58e1f53 | 204 | pr_err("error! Bad data in microcode data file\n"); |
a0a29b62 DA |
205 | break; |
206 | } | |
a30a6a2c | 207 | |
938179b4 DS |
208 | /* For performance reasons, reuse mc area when possible */ |
209 | if (!mc || mc_size > curr_mc_size) { | |
5cdd2de0 | 210 | vfree(mc); |
938179b4 DS |
211 | mc = vmalloc(mc_size); |
212 | if (!mc) | |
213 | break; | |
214 | curr_mc_size = mc_size; | |
215 | } | |
a0a29b62 DA |
216 | |
217 | if (get_ucode_data(mc, ucode_ptr, mc_size) || | |
9cd4d78e | 218 | microcode_sanity_check(mc, 1) < 0) { |
a0a29b62 DA |
219 | break; |
220 | } | |
221 | ||
9cd4d78e FY |
222 | csig = uci->cpu_sig.sig; |
223 | cpf = uci->cpu_sig.pf; | |
224 | if (get_matching_microcode(csig, cpf, mc, new_rev)) { | |
5cdd2de0 | 225 | vfree(new_mc); |
a0a29b62 DA |
226 | new_rev = mc_header.rev; |
227 | new_mc = mc; | |
938179b4 DS |
228 | mc = NULL; /* trigger new vmalloc */ |
229 | } | |
a0a29b62 DA |
230 | |
231 | ucode_ptr += mc_size; | |
232 | leftover -= mc_size; | |
a30a6a2c SL |
233 | } |
234 | ||
5cdd2de0 | 235 | vfree(mc); |
938179b4 | 236 | |
871b72dd | 237 | if (leftover) { |
5cdd2de0 | 238 | vfree(new_mc); |
871b72dd | 239 | state = UCODE_ERROR; |
4bae1967 | 240 | goto out; |
871b72dd | 241 | } |
4bae1967 | 242 | |
871b72dd DA |
243 | if (!new_mc) { |
244 | state = UCODE_NFOUND; | |
4bae1967 | 245 | goto out; |
a30a6a2c | 246 | } |
a0a29b62 | 247 | |
5cdd2de0 | 248 | vfree(uci->mc); |
4bae1967 IM |
249 | uci->mc = (struct microcode_intel *)new_mc; |
250 | ||
9cd4d78e FY |
251 | /* |
252 | * If early loading microcode is supported, save this mc into | |
253 | * permanent memory. So it will be loaded early when a CPU is hot added | |
254 | * or resumes. | |
255 | */ | |
256 | save_mc_for_early(new_mc); | |
257 | ||
f58e1f53 JP |
258 | pr_debug("CPU%d found a matching microcode update with version 0x%x (current=0x%x)\n", |
259 | cpu, new_rev, uci->cpu_sig.rev); | |
871b72dd DA |
260 | out: |
261 | return state; | |
a30a6a2c SL |
262 | } |
263 | ||
a0a29b62 DA |
264 | static int get_ucode_fw(void *to, const void *from, size_t n) |
265 | { | |
266 | memcpy(to, from, n); | |
267 | return 0; | |
268 | } | |
a30a6a2c | 269 | |
48e30685 BP |
270 | static enum ucode_state request_microcode_fw(int cpu, struct device *device, |
271 | bool refresh_fw) | |
a30a6a2c SL |
272 | { |
273 | char name[30]; | |
92cb7612 | 274 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
a30a6a2c | 275 | const struct firmware *firmware; |
871b72dd | 276 | enum ucode_state ret; |
a30a6a2c | 277 | |
3e135d88 | 278 | sprintf(name, "intel-ucode/%02x-%02x-%02x", |
a30a6a2c | 279 | c->x86, c->x86_model, c->x86_mask); |
871b72dd | 280 | |
75da02b2 | 281 | if (request_firmware_direct(&firmware, name, device)) { |
f58e1f53 | 282 | pr_debug("data file %s load failed\n", name); |
871b72dd | 283 | return UCODE_NFOUND; |
a30a6a2c | 284 | } |
a0a29b62 | 285 | |
dd3feda7 JSR |
286 | ret = generic_load_microcode(cpu, (void *)firmware->data, |
287 | firmware->size, &get_ucode_fw); | |
a0a29b62 | 288 | |
a30a6a2c SL |
289 | release_firmware(firmware); |
290 | ||
a0a29b62 DA |
291 | return ret; |
292 | } | |
293 | ||
294 | static int get_ucode_user(void *to, const void *from, size_t n) | |
295 | { | |
296 | return copy_from_user(to, from, n); | |
297 | } | |
298 | ||
871b72dd DA |
299 | static enum ucode_state |
300 | request_microcode_user(int cpu, const void __user *buf, size_t size) | |
a0a29b62 | 301 | { |
dd3feda7 | 302 | return generic_load_microcode(cpu, (void *)buf, size, &get_ucode_user); |
a30a6a2c SL |
303 | } |
304 | ||
8d86f390 | 305 | static void microcode_fini_cpu(int cpu) |
a30a6a2c SL |
306 | { |
307 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; | |
308 | ||
18dbc916 DA |
309 | vfree(uci->mc); |
310 | uci->mc = NULL; | |
a30a6a2c | 311 | } |
8d86f390 | 312 | |
4db646b1 | 313 | static struct microcode_ops microcode_intel_ops = { |
a0a29b62 DA |
314 | .request_microcode_user = request_microcode_user, |
315 | .request_microcode_fw = request_microcode_fw, | |
8d86f390 | 316 | .collect_cpu_info = collect_cpu_info, |
532ed374 | 317 | .apply_microcode = apply_microcode_intel, |
8d86f390 PO |
318 | .microcode_fini_cpu = microcode_fini_cpu, |
319 | }; | |
320 | ||
18dbc916 | 321 | struct microcode_ops * __init init_intel_microcode(void) |
8d86f390 | 322 | { |
7164b3f5 SB |
323 | struct cpuinfo_x86 *c = &cpu_data(0); |
324 | ||
325 | if (c->x86_vendor != X86_VENDOR_INTEL || c->x86 < 6 || | |
326 | cpu_has(c, X86_FEATURE_IA64)) { | |
327 | pr_err("Intel CPU family 0x%x not supported\n", c->x86); | |
328 | return NULL; | |
329 | } | |
330 | ||
18dbc916 | 331 | return µcode_intel_ops; |
8d86f390 PO |
332 | } |
333 |