Commit | Line | Data |
---|---|---|
241771ef IM |
1 | /* |
2 | * Performance counter x86 architecture code | |
3 | * | |
98144511 IM |
4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> | |
241771ef IM |
9 | * |
10 | * For licencing details see kernel-base/COPYING | |
11 | */ | |
12 | ||
13 | #include <linux/perf_counter.h> | |
14 | #include <linux/capability.h> | |
15 | #include <linux/notifier.h> | |
16 | #include <linux/hardirq.h> | |
17 | #include <linux/kprobes.h> | |
4ac13294 | 18 | #include <linux/module.h> |
241771ef IM |
19 | #include <linux/kdebug.h> |
20 | #include <linux/sched.h> | |
d7d59fb3 | 21 | #include <linux/uaccess.h> |
241771ef | 22 | |
241771ef | 23 | #include <asm/apic.h> |
d7d59fb3 | 24 | #include <asm/stacktrace.h> |
4e935e47 | 25 | #include <asm/nmi.h> |
241771ef | 26 | |
862a1a5f | 27 | static u64 perf_counter_mask __read_mostly; |
703e937c | 28 | |
241771ef | 29 | struct cpu_hw_counters { |
862a1a5f | 30 | struct perf_counter *counters[X86_PMC_IDX_MAX]; |
43f6201a RR |
31 | unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
32 | unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
4b39fd96 | 33 | unsigned long interrupts; |
b0f3f28e | 34 | int enabled; |
241771ef IM |
35 | }; |
36 | ||
37 | /* | |
5f4ec28f | 38 | * struct x86_pmu - generic x86 pmu |
241771ef | 39 | */ |
5f4ec28f | 40 | struct x86_pmu { |
faa28ae0 RR |
41 | const char *name; |
42 | int version; | |
a3288106 | 43 | int (*handle_irq)(struct pt_regs *); |
9e35ad38 PZ |
44 | void (*disable_all)(void); |
45 | void (*enable_all)(void); | |
7c90cc45 | 46 | void (*enable)(struct hw_perf_counter *, int); |
d4369891 | 47 | void (*disable)(struct hw_perf_counter *, int); |
169e41eb JSR |
48 | unsigned eventsel; |
49 | unsigned perfctr; | |
b0f3f28e PZ |
50 | u64 (*event_map)(int); |
51 | u64 (*raw_event)(u64); | |
169e41eb | 52 | int max_events; |
0933e5c6 RR |
53 | int num_counters; |
54 | int num_counters_fixed; | |
55 | int counter_bits; | |
56 | u64 counter_mask; | |
c619b8ff | 57 | u64 max_period; |
9e35ad38 | 58 | u64 intel_ctrl; |
b56a3802 JSR |
59 | }; |
60 | ||
4a06bd85 | 61 | static struct x86_pmu x86_pmu __read_mostly; |
b56a3802 | 62 | |
b0f3f28e PZ |
63 | static DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters) = { |
64 | .enabled = 1, | |
65 | }; | |
241771ef | 66 | |
b56a3802 JSR |
67 | /* |
68 | * Intel PerfMon v3. Used on Core2 and later. | |
69 | */ | |
b0f3f28e | 70 | static const u64 intel_perfmon_event_map[] = |
241771ef | 71 | { |
f650a672 | 72 | [PERF_COUNT_CPU_CYCLES] = 0x003c, |
241771ef IM |
73 | [PERF_COUNT_INSTRUCTIONS] = 0x00c0, |
74 | [PERF_COUNT_CACHE_REFERENCES] = 0x4f2e, | |
75 | [PERF_COUNT_CACHE_MISSES] = 0x412e, | |
76 | [PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x00c4, | |
77 | [PERF_COUNT_BRANCH_MISSES] = 0x00c5, | |
f650a672 | 78 | [PERF_COUNT_BUS_CYCLES] = 0x013c, |
241771ef IM |
79 | }; |
80 | ||
5f4ec28f | 81 | static u64 intel_pmu_event_map(int event) |
b56a3802 JSR |
82 | { |
83 | return intel_perfmon_event_map[event]; | |
84 | } | |
241771ef | 85 | |
5f4ec28f | 86 | static u64 intel_pmu_raw_event(u64 event) |
b0f3f28e | 87 | { |
82bae4f8 PZ |
88 | #define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL |
89 | #define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL | |
ff99be57 PZ |
90 | #define CORE_EVNTSEL_EDGE_MASK 0x00040000ULL |
91 | #define CORE_EVNTSEL_INV_MASK 0x00800000ULL | |
82bae4f8 | 92 | #define CORE_EVNTSEL_COUNTER_MASK 0xFF000000ULL |
b0f3f28e PZ |
93 | |
94 | #define CORE_EVNTSEL_MASK \ | |
95 | (CORE_EVNTSEL_EVENT_MASK | \ | |
96 | CORE_EVNTSEL_UNIT_MASK | \ | |
ff99be57 PZ |
97 | CORE_EVNTSEL_EDGE_MASK | \ |
98 | CORE_EVNTSEL_INV_MASK | \ | |
b0f3f28e PZ |
99 | CORE_EVNTSEL_COUNTER_MASK) |
100 | ||
101 | return event & CORE_EVNTSEL_MASK; | |
102 | } | |
103 | ||
f87ad35d JSR |
104 | /* |
105 | * AMD Performance Monitor K7 and later. | |
106 | */ | |
b0f3f28e | 107 | static const u64 amd_perfmon_event_map[] = |
f87ad35d JSR |
108 | { |
109 | [PERF_COUNT_CPU_CYCLES] = 0x0076, | |
110 | [PERF_COUNT_INSTRUCTIONS] = 0x00c0, | |
111 | [PERF_COUNT_CACHE_REFERENCES] = 0x0080, | |
112 | [PERF_COUNT_CACHE_MISSES] = 0x0081, | |
113 | [PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x00c4, | |
114 | [PERF_COUNT_BRANCH_MISSES] = 0x00c5, | |
115 | }; | |
116 | ||
5f4ec28f | 117 | static u64 amd_pmu_event_map(int event) |
f87ad35d JSR |
118 | { |
119 | return amd_perfmon_event_map[event]; | |
120 | } | |
121 | ||
5f4ec28f | 122 | static u64 amd_pmu_raw_event(u64 event) |
b0f3f28e | 123 | { |
82bae4f8 PZ |
124 | #define K7_EVNTSEL_EVENT_MASK 0x7000000FFULL |
125 | #define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL | |
ff99be57 PZ |
126 | #define K7_EVNTSEL_EDGE_MASK 0x000040000ULL |
127 | #define K7_EVNTSEL_INV_MASK 0x000800000ULL | |
82bae4f8 | 128 | #define K7_EVNTSEL_COUNTER_MASK 0x0FF000000ULL |
b0f3f28e PZ |
129 | |
130 | #define K7_EVNTSEL_MASK \ | |
131 | (K7_EVNTSEL_EVENT_MASK | \ | |
132 | K7_EVNTSEL_UNIT_MASK | \ | |
ff99be57 PZ |
133 | K7_EVNTSEL_EDGE_MASK | \ |
134 | K7_EVNTSEL_INV_MASK | \ | |
b0f3f28e PZ |
135 | K7_EVNTSEL_COUNTER_MASK) |
136 | ||
137 | return event & K7_EVNTSEL_MASK; | |
138 | } | |
139 | ||
ee06094f IM |
140 | /* |
141 | * Propagate counter elapsed time into the generic counter. | |
142 | * Can only be executed on the CPU where the counter is active. | |
143 | * Returns the delta events processed. | |
144 | */ | |
4b7bfd0d | 145 | static u64 |
ee06094f IM |
146 | x86_perf_counter_update(struct perf_counter *counter, |
147 | struct hw_perf_counter *hwc, int idx) | |
148 | { | |
ec3232bd PZ |
149 | int shift = 64 - x86_pmu.counter_bits; |
150 | u64 prev_raw_count, new_raw_count; | |
151 | s64 delta; | |
ee06094f | 152 | |
ee06094f IM |
153 | /* |
154 | * Careful: an NMI might modify the previous counter value. | |
155 | * | |
156 | * Our tactic to handle this is to first atomically read and | |
157 | * exchange a new raw count - then add that new-prev delta | |
158 | * count to the generic counter atomically: | |
159 | */ | |
160 | again: | |
161 | prev_raw_count = atomic64_read(&hwc->prev_count); | |
162 | rdmsrl(hwc->counter_base + idx, new_raw_count); | |
163 | ||
164 | if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count, | |
165 | new_raw_count) != prev_raw_count) | |
166 | goto again; | |
167 | ||
168 | /* | |
169 | * Now we have the new raw value and have updated the prev | |
170 | * timestamp already. We can now calculate the elapsed delta | |
171 | * (counter-)time and add that to the generic counter. | |
172 | * | |
173 | * Careful, not all hw sign-extends above the physical width | |
ec3232bd | 174 | * of the count. |
ee06094f | 175 | */ |
ec3232bd PZ |
176 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
177 | delta >>= shift; | |
ee06094f IM |
178 | |
179 | atomic64_add(delta, &counter->count); | |
180 | atomic64_sub(delta, &hwc->period_left); | |
4b7bfd0d RR |
181 | |
182 | return new_raw_count; | |
ee06094f IM |
183 | } |
184 | ||
ba77813a | 185 | static atomic_t active_counters; |
4e935e47 PZ |
186 | static DEFINE_MUTEX(pmc_reserve_mutex); |
187 | ||
188 | static bool reserve_pmc_hardware(void) | |
189 | { | |
190 | int i; | |
191 | ||
192 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
193 | disable_lapic_nmi_watchdog(); | |
194 | ||
0933e5c6 | 195 | for (i = 0; i < x86_pmu.num_counters; i++) { |
4a06bd85 | 196 | if (!reserve_perfctr_nmi(x86_pmu.perfctr + i)) |
4e935e47 PZ |
197 | goto perfctr_fail; |
198 | } | |
199 | ||
0933e5c6 | 200 | for (i = 0; i < x86_pmu.num_counters; i++) { |
4a06bd85 | 201 | if (!reserve_evntsel_nmi(x86_pmu.eventsel + i)) |
4e935e47 PZ |
202 | goto eventsel_fail; |
203 | } | |
204 | ||
205 | return true; | |
206 | ||
207 | eventsel_fail: | |
208 | for (i--; i >= 0; i--) | |
4a06bd85 | 209 | release_evntsel_nmi(x86_pmu.eventsel + i); |
4e935e47 | 210 | |
0933e5c6 | 211 | i = x86_pmu.num_counters; |
4e935e47 PZ |
212 | |
213 | perfctr_fail: | |
214 | for (i--; i >= 0; i--) | |
4a06bd85 | 215 | release_perfctr_nmi(x86_pmu.perfctr + i); |
4e935e47 PZ |
216 | |
217 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
218 | enable_lapic_nmi_watchdog(); | |
219 | ||
220 | return false; | |
221 | } | |
222 | ||
223 | static void release_pmc_hardware(void) | |
224 | { | |
225 | int i; | |
226 | ||
0933e5c6 | 227 | for (i = 0; i < x86_pmu.num_counters; i++) { |
4a06bd85 RR |
228 | release_perfctr_nmi(x86_pmu.perfctr + i); |
229 | release_evntsel_nmi(x86_pmu.eventsel + i); | |
4e935e47 PZ |
230 | } |
231 | ||
232 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
233 | enable_lapic_nmi_watchdog(); | |
234 | } | |
235 | ||
236 | static void hw_perf_counter_destroy(struct perf_counter *counter) | |
237 | { | |
ba77813a | 238 | if (atomic_dec_and_mutex_lock(&active_counters, &pmc_reserve_mutex)) { |
4e935e47 PZ |
239 | release_pmc_hardware(); |
240 | mutex_unlock(&pmc_reserve_mutex); | |
241 | } | |
242 | } | |
243 | ||
85cf9dba RR |
244 | static inline int x86_pmu_initialized(void) |
245 | { | |
246 | return x86_pmu.handle_irq != NULL; | |
247 | } | |
248 | ||
241771ef | 249 | /* |
0d48696f | 250 | * Setup the hardware configuration for a given attr_type |
241771ef | 251 | */ |
621a01ea | 252 | static int __hw_perf_counter_init(struct perf_counter *counter) |
241771ef | 253 | { |
0d48696f | 254 | struct perf_counter_attr *attr = &counter->attr; |
241771ef | 255 | struct hw_perf_counter *hwc = &counter->hw; |
4e935e47 | 256 | int err; |
241771ef | 257 | |
85cf9dba RR |
258 | if (!x86_pmu_initialized()) |
259 | return -ENODEV; | |
241771ef | 260 | |
4e935e47 | 261 | err = 0; |
ba77813a | 262 | if (!atomic_inc_not_zero(&active_counters)) { |
4e935e47 | 263 | mutex_lock(&pmc_reserve_mutex); |
ba77813a | 264 | if (atomic_read(&active_counters) == 0 && !reserve_pmc_hardware()) |
4e935e47 PZ |
265 | err = -EBUSY; |
266 | else | |
ba77813a | 267 | atomic_inc(&active_counters); |
4e935e47 PZ |
268 | mutex_unlock(&pmc_reserve_mutex); |
269 | } | |
270 | if (err) | |
271 | return err; | |
272 | ||
241771ef | 273 | /* |
0475f9ea | 274 | * Generate PMC IRQs: |
241771ef IM |
275 | * (keep 'enabled' bit clear for now) |
276 | */ | |
0475f9ea | 277 | hwc->config = ARCH_PERFMON_EVENTSEL_INT; |
241771ef IM |
278 | |
279 | /* | |
0475f9ea | 280 | * Count user and OS events unless requested not to. |
241771ef | 281 | */ |
0d48696f | 282 | if (!attr->exclude_user) |
0475f9ea | 283 | hwc->config |= ARCH_PERFMON_EVENTSEL_USR; |
0d48696f | 284 | if (!attr->exclude_kernel) |
241771ef | 285 | hwc->config |= ARCH_PERFMON_EVENTSEL_OS; |
0475f9ea | 286 | |
b23f3325 PZ |
287 | if (!hwc->sample_period) |
288 | hwc->sample_period = x86_pmu.max_period; | |
d2517a49 | 289 | |
e4abb5d4 | 290 | atomic64_set(&hwc->period_left, hwc->sample_period); |
241771ef IM |
291 | |
292 | /* | |
dfa7c899 | 293 | * Raw event type provide the config in the event structure |
241771ef | 294 | */ |
0d48696f PZ |
295 | if (perf_event_raw(attr)) { |
296 | hwc->config |= x86_pmu.raw_event(perf_event_config(attr)); | |
241771ef | 297 | } else { |
0d48696f | 298 | if (perf_event_id(attr) >= x86_pmu.max_events) |
241771ef IM |
299 | return -EINVAL; |
300 | /* | |
301 | * The generic map: | |
302 | */ | |
0d48696f | 303 | hwc->config |= x86_pmu.event_map(perf_event_id(attr)); |
241771ef | 304 | } |
241771ef | 305 | |
4e935e47 PZ |
306 | counter->destroy = hw_perf_counter_destroy; |
307 | ||
241771ef IM |
308 | return 0; |
309 | } | |
310 | ||
9e35ad38 | 311 | static void intel_pmu_disable_all(void) |
4ac13294 | 312 | { |
862a1a5f | 313 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); |
241771ef | 314 | } |
b56a3802 | 315 | |
9e35ad38 | 316 | static void amd_pmu_disable_all(void) |
f87ad35d | 317 | { |
b0f3f28e | 318 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); |
9e35ad38 PZ |
319 | int idx; |
320 | ||
321 | if (!cpuc->enabled) | |
322 | return; | |
b0f3f28e | 323 | |
b0f3f28e | 324 | cpuc->enabled = 0; |
60b3df9c PZ |
325 | /* |
326 | * ensure we write the disable before we start disabling the | |
5f4ec28f RR |
327 | * counters proper, so that amd_pmu_enable_counter() does the |
328 | * right thing. | |
60b3df9c | 329 | */ |
b0f3f28e | 330 | barrier(); |
f87ad35d | 331 | |
0933e5c6 | 332 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
b0f3f28e PZ |
333 | u64 val; |
334 | ||
43f6201a | 335 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 336 | continue; |
f87ad35d | 337 | rdmsrl(MSR_K7_EVNTSEL0 + idx, val); |
4295ee62 RR |
338 | if (!(val & ARCH_PERFMON_EVENTSEL0_ENABLE)) |
339 | continue; | |
340 | val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE; | |
341 | wrmsrl(MSR_K7_EVNTSEL0 + idx, val); | |
f87ad35d | 342 | } |
f87ad35d JSR |
343 | } |
344 | ||
9e35ad38 | 345 | void hw_perf_disable(void) |
b56a3802 | 346 | { |
85cf9dba | 347 | if (!x86_pmu_initialized()) |
9e35ad38 PZ |
348 | return; |
349 | return x86_pmu.disable_all(); | |
b56a3802 | 350 | } |
241771ef | 351 | |
9e35ad38 | 352 | static void intel_pmu_enable_all(void) |
b56a3802 | 353 | { |
9e35ad38 | 354 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl); |
b56a3802 JSR |
355 | } |
356 | ||
9e35ad38 | 357 | static void amd_pmu_enable_all(void) |
f87ad35d | 358 | { |
b0f3f28e | 359 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); |
f87ad35d JSR |
360 | int idx; |
361 | ||
9e35ad38 | 362 | if (cpuc->enabled) |
b0f3f28e PZ |
363 | return; |
364 | ||
9e35ad38 PZ |
365 | cpuc->enabled = 1; |
366 | barrier(); | |
367 | ||
0933e5c6 | 368 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
4295ee62 | 369 | u64 val; |
b0f3f28e | 370 | |
43f6201a | 371 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 RR |
372 | continue; |
373 | rdmsrl(MSR_K7_EVNTSEL0 + idx, val); | |
374 | if (val & ARCH_PERFMON_EVENTSEL0_ENABLE) | |
375 | continue; | |
376 | val |= ARCH_PERFMON_EVENTSEL0_ENABLE; | |
377 | wrmsrl(MSR_K7_EVNTSEL0 + idx, val); | |
f87ad35d JSR |
378 | } |
379 | } | |
380 | ||
9e35ad38 | 381 | void hw_perf_enable(void) |
ee06094f | 382 | { |
85cf9dba | 383 | if (!x86_pmu_initialized()) |
2b9ff0db | 384 | return; |
9e35ad38 | 385 | x86_pmu.enable_all(); |
ee06094f | 386 | } |
ee06094f | 387 | |
19d84dab | 388 | static inline u64 intel_pmu_get_status(void) |
b0f3f28e PZ |
389 | { |
390 | u64 status; | |
391 | ||
b7f8859a | 392 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); |
b0f3f28e | 393 | |
b7f8859a | 394 | return status; |
b0f3f28e PZ |
395 | } |
396 | ||
dee5d906 | 397 | static inline void intel_pmu_ack_status(u64 ack) |
b0f3f28e PZ |
398 | { |
399 | wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); | |
400 | } | |
401 | ||
7c90cc45 | 402 | static inline void x86_pmu_enable_counter(struct hw_perf_counter *hwc, int idx) |
b0f3f28e | 403 | { |
7c90cc45 | 404 | int err; |
7c90cc45 RR |
405 | err = checking_wrmsrl(hwc->config_base + idx, |
406 | hwc->config | ARCH_PERFMON_EVENTSEL0_ENABLE); | |
b0f3f28e PZ |
407 | } |
408 | ||
d4369891 | 409 | static inline void x86_pmu_disable_counter(struct hw_perf_counter *hwc, int idx) |
b0f3f28e | 410 | { |
d4369891 | 411 | int err; |
d4369891 RR |
412 | err = checking_wrmsrl(hwc->config_base + idx, |
413 | hwc->config); | |
b0f3f28e PZ |
414 | } |
415 | ||
2f18d1e8 | 416 | static inline void |
d4369891 | 417 | intel_pmu_disable_fixed(struct hw_perf_counter *hwc, int __idx) |
2f18d1e8 IM |
418 | { |
419 | int idx = __idx - X86_PMC_IDX_FIXED; | |
420 | u64 ctrl_val, mask; | |
421 | int err; | |
422 | ||
423 | mask = 0xfULL << (idx * 4); | |
424 | ||
425 | rdmsrl(hwc->config_base, ctrl_val); | |
426 | ctrl_val &= ~mask; | |
427 | err = checking_wrmsrl(hwc->config_base, ctrl_val); | |
428 | } | |
429 | ||
7e2ae347 | 430 | static inline void |
d4369891 | 431 | intel_pmu_disable_counter(struct hw_perf_counter *hwc, int idx) |
7e2ae347 | 432 | { |
d4369891 RR |
433 | if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { |
434 | intel_pmu_disable_fixed(hwc, idx); | |
435 | return; | |
436 | } | |
437 | ||
438 | x86_pmu_disable_counter(hwc, idx); | |
439 | } | |
440 | ||
441 | static inline void | |
442 | amd_pmu_disable_counter(struct hw_perf_counter *hwc, int idx) | |
443 | { | |
444 | x86_pmu_disable_counter(hwc, idx); | |
7e2ae347 IM |
445 | } |
446 | ||
2f18d1e8 | 447 | static DEFINE_PER_CPU(u64, prev_left[X86_PMC_IDX_MAX]); |
241771ef | 448 | |
ee06094f IM |
449 | /* |
450 | * Set the next IRQ period, based on the hwc->period_left value. | |
451 | * To be called with the counter disabled in hw: | |
452 | */ | |
e4abb5d4 | 453 | static int |
26816c28 | 454 | x86_perf_counter_set_period(struct perf_counter *counter, |
ee06094f | 455 | struct hw_perf_counter *hwc, int idx) |
241771ef | 456 | { |
2f18d1e8 | 457 | s64 left = atomic64_read(&hwc->period_left); |
e4abb5d4 PZ |
458 | s64 period = hwc->sample_period; |
459 | int err, ret = 0; | |
ee06094f | 460 | |
ee06094f IM |
461 | /* |
462 | * If we are way outside a reasoable range then just skip forward: | |
463 | */ | |
464 | if (unlikely(left <= -period)) { | |
465 | left = period; | |
466 | atomic64_set(&hwc->period_left, left); | |
e4abb5d4 | 467 | ret = 1; |
ee06094f IM |
468 | } |
469 | ||
470 | if (unlikely(left <= 0)) { | |
471 | left += period; | |
472 | atomic64_set(&hwc->period_left, left); | |
e4abb5d4 | 473 | ret = 1; |
ee06094f | 474 | } |
1c80f4b5 IM |
475 | /* |
476 | * Quirk: certain CPUs dont like it if just 1 event is left: | |
477 | */ | |
478 | if (unlikely(left < 2)) | |
479 | left = 2; | |
241771ef | 480 | |
e4abb5d4 PZ |
481 | if (left > x86_pmu.max_period) |
482 | left = x86_pmu.max_period; | |
483 | ||
ee06094f IM |
484 | per_cpu(prev_left[idx], smp_processor_id()) = left; |
485 | ||
486 | /* | |
487 | * The hw counter starts counting from this counter offset, | |
488 | * mark it to be able to extra future deltas: | |
489 | */ | |
2f18d1e8 | 490 | atomic64_set(&hwc->prev_count, (u64)-left); |
ee06094f | 491 | |
2f18d1e8 | 492 | err = checking_wrmsrl(hwc->counter_base + idx, |
0933e5c6 | 493 | (u64)(-left) & x86_pmu.counter_mask); |
e4abb5d4 PZ |
494 | |
495 | return ret; | |
2f18d1e8 IM |
496 | } |
497 | ||
498 | static inline void | |
7c90cc45 | 499 | intel_pmu_enable_fixed(struct hw_perf_counter *hwc, int __idx) |
2f18d1e8 IM |
500 | { |
501 | int idx = __idx - X86_PMC_IDX_FIXED; | |
502 | u64 ctrl_val, bits, mask; | |
503 | int err; | |
504 | ||
505 | /* | |
0475f9ea PM |
506 | * Enable IRQ generation (0x8), |
507 | * and enable ring-3 counting (0x2) and ring-0 counting (0x1) | |
508 | * if requested: | |
2f18d1e8 | 509 | */ |
0475f9ea PM |
510 | bits = 0x8ULL; |
511 | if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) | |
512 | bits |= 0x2; | |
2f18d1e8 IM |
513 | if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) |
514 | bits |= 0x1; | |
515 | bits <<= (idx * 4); | |
516 | mask = 0xfULL << (idx * 4); | |
517 | ||
518 | rdmsrl(hwc->config_base, ctrl_val); | |
519 | ctrl_val &= ~mask; | |
520 | ctrl_val |= bits; | |
521 | err = checking_wrmsrl(hwc->config_base, ctrl_val); | |
7e2ae347 IM |
522 | } |
523 | ||
7c90cc45 | 524 | static void intel_pmu_enable_counter(struct hw_perf_counter *hwc, int idx) |
7e2ae347 | 525 | { |
7c90cc45 RR |
526 | if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { |
527 | intel_pmu_enable_fixed(hwc, idx); | |
528 | return; | |
529 | } | |
530 | ||
531 | x86_pmu_enable_counter(hwc, idx); | |
532 | } | |
533 | ||
534 | static void amd_pmu_enable_counter(struct hw_perf_counter *hwc, int idx) | |
535 | { | |
536 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
537 | ||
538 | if (cpuc->enabled) | |
539 | x86_pmu_enable_counter(hwc, idx); | |
2b583d8b | 540 | else |
d4369891 | 541 | x86_pmu_disable_counter(hwc, idx); |
241771ef IM |
542 | } |
543 | ||
2f18d1e8 IM |
544 | static int |
545 | fixed_mode_idx(struct perf_counter *counter, struct hw_perf_counter *hwc) | |
862a1a5f | 546 | { |
2f18d1e8 IM |
547 | unsigned int event; |
548 | ||
ef7b3e09 | 549 | if (!x86_pmu.num_counters_fixed) |
f87ad35d JSR |
550 | return -1; |
551 | ||
2f18d1e8 IM |
552 | event = hwc->config & ARCH_PERFMON_EVENT_MASK; |
553 | ||
4a06bd85 | 554 | if (unlikely(event == x86_pmu.event_map(PERF_COUNT_INSTRUCTIONS))) |
2f18d1e8 | 555 | return X86_PMC_IDX_FIXED_INSTRUCTIONS; |
4a06bd85 | 556 | if (unlikely(event == x86_pmu.event_map(PERF_COUNT_CPU_CYCLES))) |
2f18d1e8 | 557 | return X86_PMC_IDX_FIXED_CPU_CYCLES; |
4a06bd85 | 558 | if (unlikely(event == x86_pmu.event_map(PERF_COUNT_BUS_CYCLES))) |
2f18d1e8 IM |
559 | return X86_PMC_IDX_FIXED_BUS_CYCLES; |
560 | ||
862a1a5f IM |
561 | return -1; |
562 | } | |
563 | ||
ee06094f IM |
564 | /* |
565 | * Find a PMC slot for the freshly enabled / scheduled in counter: | |
566 | */ | |
4aeb0b42 | 567 | static int x86_pmu_enable(struct perf_counter *counter) |
241771ef IM |
568 | { |
569 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
570 | struct hw_perf_counter *hwc = &counter->hw; | |
2f18d1e8 | 571 | int idx; |
241771ef | 572 | |
2f18d1e8 IM |
573 | idx = fixed_mode_idx(counter, hwc); |
574 | if (idx >= 0) { | |
575 | /* | |
576 | * Try to get the fixed counter, if that is already taken | |
577 | * then try to get a generic counter: | |
578 | */ | |
43f6201a | 579 | if (test_and_set_bit(idx, cpuc->used_mask)) |
2f18d1e8 | 580 | goto try_generic; |
0dff86aa | 581 | |
2f18d1e8 IM |
582 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; |
583 | /* | |
584 | * We set it so that counter_base + idx in wrmsr/rdmsr maps to | |
585 | * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2: | |
586 | */ | |
587 | hwc->counter_base = | |
588 | MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED; | |
241771ef | 589 | hwc->idx = idx; |
2f18d1e8 IM |
590 | } else { |
591 | idx = hwc->idx; | |
592 | /* Try to get the previous generic counter again */ | |
43f6201a | 593 | if (test_and_set_bit(idx, cpuc->used_mask)) { |
2f18d1e8 | 594 | try_generic: |
43f6201a | 595 | idx = find_first_zero_bit(cpuc->used_mask, |
0933e5c6 RR |
596 | x86_pmu.num_counters); |
597 | if (idx == x86_pmu.num_counters) | |
2f18d1e8 IM |
598 | return -EAGAIN; |
599 | ||
43f6201a | 600 | set_bit(idx, cpuc->used_mask); |
2f18d1e8 IM |
601 | hwc->idx = idx; |
602 | } | |
4a06bd85 RR |
603 | hwc->config_base = x86_pmu.eventsel; |
604 | hwc->counter_base = x86_pmu.perfctr; | |
241771ef IM |
605 | } |
606 | ||
c323d95f | 607 | perf_counters_lapic_init(); |
53b441a5 | 608 | |
d4369891 | 609 | x86_pmu.disable(hwc, idx); |
241771ef | 610 | |
862a1a5f | 611 | cpuc->counters[idx] = counter; |
43f6201a | 612 | set_bit(idx, cpuc->active_mask); |
7e2ae347 | 613 | |
26816c28 | 614 | x86_perf_counter_set_period(counter, hwc, idx); |
7c90cc45 | 615 | x86_pmu.enable(hwc, idx); |
95cdd2e7 IM |
616 | |
617 | return 0; | |
241771ef IM |
618 | } |
619 | ||
a78ac325 PZ |
620 | static void x86_pmu_unthrottle(struct perf_counter *counter) |
621 | { | |
622 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
623 | struct hw_perf_counter *hwc = &counter->hw; | |
624 | ||
625 | if (WARN_ON_ONCE(hwc->idx >= X86_PMC_IDX_MAX || | |
626 | cpuc->counters[hwc->idx] != counter)) | |
627 | return; | |
628 | ||
629 | x86_pmu.enable(hwc, hwc->idx); | |
630 | } | |
631 | ||
241771ef IM |
632 | void perf_counter_print_debug(void) |
633 | { | |
2f18d1e8 | 634 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
0dff86aa | 635 | struct cpu_hw_counters *cpuc; |
5bb9efe3 | 636 | unsigned long flags; |
1e125676 IM |
637 | int cpu, idx; |
638 | ||
0933e5c6 | 639 | if (!x86_pmu.num_counters) |
1e125676 | 640 | return; |
241771ef | 641 | |
5bb9efe3 | 642 | local_irq_save(flags); |
241771ef IM |
643 | |
644 | cpu = smp_processor_id(); | |
0dff86aa | 645 | cpuc = &per_cpu(cpu_hw_counters, cpu); |
241771ef | 646 | |
faa28ae0 | 647 | if (x86_pmu.version >= 2) { |
a1ef58f4 JSR |
648 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
649 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
650 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
651 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); | |
652 | ||
653 | pr_info("\n"); | |
654 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
655 | pr_info("CPU#%d: status: %016llx\n", cpu, status); | |
656 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); | |
657 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); | |
f87ad35d | 658 | } |
43f6201a | 659 | pr_info("CPU#%d: used: %016llx\n", cpu, *(u64 *)cpuc->used_mask); |
241771ef | 660 | |
0933e5c6 | 661 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
4a06bd85 RR |
662 | rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl); |
663 | rdmsrl(x86_pmu.perfctr + idx, pmc_count); | |
241771ef | 664 | |
ee06094f | 665 | prev_left = per_cpu(prev_left[idx], cpu); |
241771ef | 666 | |
a1ef58f4 | 667 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 668 | cpu, idx, pmc_ctrl); |
a1ef58f4 | 669 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 670 | cpu, idx, pmc_count); |
a1ef58f4 | 671 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 672 | cpu, idx, prev_left); |
241771ef | 673 | } |
0933e5c6 | 674 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { |
2f18d1e8 IM |
675 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
676 | ||
a1ef58f4 | 677 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
2f18d1e8 IM |
678 | cpu, idx, pmc_count); |
679 | } | |
5bb9efe3 | 680 | local_irq_restore(flags); |
241771ef IM |
681 | } |
682 | ||
4aeb0b42 | 683 | static void x86_pmu_disable(struct perf_counter *counter) |
241771ef IM |
684 | { |
685 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
686 | struct hw_perf_counter *hwc = &counter->hw; | |
6f00cada | 687 | int idx = hwc->idx; |
241771ef | 688 | |
09534238 RR |
689 | /* |
690 | * Must be done before we disable, otherwise the nmi handler | |
691 | * could reenable again: | |
692 | */ | |
43f6201a | 693 | clear_bit(idx, cpuc->active_mask); |
d4369891 | 694 | x86_pmu.disable(hwc, idx); |
241771ef | 695 | |
2f18d1e8 IM |
696 | /* |
697 | * Make sure the cleared pointer becomes visible before we | |
698 | * (potentially) free the counter: | |
699 | */ | |
527e26af | 700 | barrier(); |
241771ef | 701 | |
ee06094f IM |
702 | /* |
703 | * Drain the remaining delta count out of a counter | |
704 | * that we are disabling: | |
705 | */ | |
706 | x86_perf_counter_update(counter, hwc, idx); | |
09534238 | 707 | cpuc->counters[idx] = NULL; |
43f6201a | 708 | clear_bit(idx, cpuc->used_mask); |
241771ef IM |
709 | } |
710 | ||
7e2ae347 | 711 | /* |
ee06094f IM |
712 | * Save and restart an expired counter. Called by NMI contexts, |
713 | * so it has to be careful about preempting normal counter ops: | |
7e2ae347 | 714 | */ |
e4abb5d4 | 715 | static int intel_pmu_save_and_restart(struct perf_counter *counter) |
241771ef IM |
716 | { |
717 | struct hw_perf_counter *hwc = &counter->hw; | |
718 | int idx = hwc->idx; | |
e4abb5d4 | 719 | int ret; |
241771ef | 720 | |
ee06094f | 721 | x86_perf_counter_update(counter, hwc, idx); |
e4abb5d4 | 722 | ret = x86_perf_counter_set_period(counter, hwc, idx); |
7e2ae347 | 723 | |
2f18d1e8 | 724 | if (counter->state == PERF_COUNTER_STATE_ACTIVE) |
7c90cc45 | 725 | intel_pmu_enable_counter(hwc, idx); |
e4abb5d4 PZ |
726 | |
727 | return ret; | |
241771ef IM |
728 | } |
729 | ||
aaba9801 IM |
730 | static void intel_pmu_reset(void) |
731 | { | |
732 | unsigned long flags; | |
733 | int idx; | |
734 | ||
735 | if (!x86_pmu.num_counters) | |
736 | return; | |
737 | ||
738 | local_irq_save(flags); | |
739 | ||
740 | printk("clearing PMU state on CPU#%d\n", smp_processor_id()); | |
741 | ||
742 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { | |
743 | checking_wrmsrl(x86_pmu.eventsel + idx, 0ull); | |
744 | checking_wrmsrl(x86_pmu.perfctr + idx, 0ull); | |
745 | } | |
746 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { | |
747 | checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull); | |
748 | } | |
749 | ||
750 | local_irq_restore(flags); | |
751 | } | |
752 | ||
753 | ||
241771ef IM |
754 | /* |
755 | * This handler is triggered by the local APIC, so the APIC IRQ handling | |
756 | * rules apply: | |
757 | */ | |
a3288106 | 758 | static int intel_pmu_handle_irq(struct pt_regs *regs) |
241771ef | 759 | { |
9029a5e3 IM |
760 | struct cpu_hw_counters *cpuc; |
761 | struct cpu_hw_counters; | |
762 | int bit, cpu, loops; | |
4b39fd96 | 763 | u64 ack, status; |
9029a5e3 IM |
764 | |
765 | cpu = smp_processor_id(); | |
766 | cpuc = &per_cpu(cpu_hw_counters, cpu); | |
241771ef | 767 | |
9e35ad38 | 768 | perf_disable(); |
19d84dab | 769 | status = intel_pmu_get_status(); |
9e35ad38 PZ |
770 | if (!status) { |
771 | perf_enable(); | |
772 | return 0; | |
773 | } | |
87b9cf46 | 774 | |
9029a5e3 | 775 | loops = 0; |
241771ef | 776 | again: |
9029a5e3 IM |
777 | if (++loops > 100) { |
778 | WARN_ONCE(1, "perfcounters: irq loop stuck!\n"); | |
34adc806 | 779 | perf_counter_print_debug(); |
aaba9801 IM |
780 | intel_pmu_reset(); |
781 | perf_enable(); | |
9029a5e3 IM |
782 | return 1; |
783 | } | |
784 | ||
d278c484 | 785 | inc_irq_stat(apic_perf_irqs); |
241771ef | 786 | ack = status; |
2f18d1e8 | 787 | for_each_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { |
862a1a5f | 788 | struct perf_counter *counter = cpuc->counters[bit]; |
241771ef IM |
789 | |
790 | clear_bit(bit, (unsigned long *) &status); | |
43f6201a | 791 | if (!test_bit(bit, cpuc->active_mask)) |
241771ef IM |
792 | continue; |
793 | ||
e4abb5d4 PZ |
794 | if (!intel_pmu_save_and_restart(counter)) |
795 | continue; | |
796 | ||
a3288106 | 797 | if (perf_counter_overflow(counter, 1, regs, 0)) |
d4369891 | 798 | intel_pmu_disable_counter(&counter->hw, bit); |
241771ef IM |
799 | } |
800 | ||
dee5d906 | 801 | intel_pmu_ack_status(ack); |
241771ef IM |
802 | |
803 | /* | |
804 | * Repeat if there is more work to be done: | |
805 | */ | |
19d84dab | 806 | status = intel_pmu_get_status(); |
241771ef IM |
807 | if (status) |
808 | goto again; | |
b0f3f28e | 809 | |
48e22d56 | 810 | perf_enable(); |
9e35ad38 PZ |
811 | |
812 | return 1; | |
1b023a96 MG |
813 | } |
814 | ||
a3288106 | 815 | static int amd_pmu_handle_irq(struct pt_regs *regs) |
a29aa8a7 | 816 | { |
48e22d56 | 817 | int cpu, idx, handled = 0; |
9029a5e3 | 818 | struct cpu_hw_counters *cpuc; |
a29aa8a7 RR |
819 | struct perf_counter *counter; |
820 | struct hw_perf_counter *hwc; | |
9029a5e3 IM |
821 | u64 val; |
822 | ||
823 | cpu = smp_processor_id(); | |
824 | cpuc = &per_cpu(cpu_hw_counters, cpu); | |
962bf7a6 | 825 | |
a29aa8a7 | 826 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
43f6201a | 827 | if (!test_bit(idx, cpuc->active_mask)) |
a29aa8a7 | 828 | continue; |
962bf7a6 | 829 | |
a29aa8a7 RR |
830 | counter = cpuc->counters[idx]; |
831 | hwc = &counter->hw; | |
a4016a79 | 832 | |
4b7bfd0d | 833 | val = x86_perf_counter_update(counter, hwc, idx); |
a29aa8a7 | 834 | if (val & (1ULL << (x86_pmu.counter_bits - 1))) |
48e22d56 | 835 | continue; |
962bf7a6 | 836 | |
a29aa8a7 | 837 | /* counter overflow */ |
a29aa8a7 RR |
838 | handled = 1; |
839 | inc_irq_stat(apic_perf_irqs); | |
e4abb5d4 PZ |
840 | if (!x86_perf_counter_set_period(counter, hwc, idx)) |
841 | continue; | |
842 | ||
a3288106 | 843 | if (perf_counter_overflow(counter, 1, regs, 0)) |
a29aa8a7 | 844 | amd_pmu_disable_counter(hwc, idx); |
a29aa8a7 | 845 | } |
962bf7a6 | 846 | |
a29aa8a7 RR |
847 | return handled; |
848 | } | |
39d81eab | 849 | |
b6276f35 PZ |
850 | void smp_perf_pending_interrupt(struct pt_regs *regs) |
851 | { | |
852 | irq_enter(); | |
853 | ack_APIC_irq(); | |
854 | inc_irq_stat(apic_pending_irqs); | |
855 | perf_counter_do_pending(); | |
856 | irq_exit(); | |
857 | } | |
858 | ||
859 | void set_perf_counter_pending(void) | |
860 | { | |
861 | apic->send_IPI_self(LOCAL_PENDING_VECTOR); | |
862 | } | |
863 | ||
c323d95f | 864 | void perf_counters_lapic_init(void) |
241771ef | 865 | { |
85cf9dba | 866 | if (!x86_pmu_initialized()) |
241771ef | 867 | return; |
85cf9dba | 868 | |
241771ef | 869 | /* |
c323d95f | 870 | * Always use NMI for PMU |
241771ef | 871 | */ |
c323d95f | 872 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
241771ef IM |
873 | } |
874 | ||
875 | static int __kprobes | |
876 | perf_counter_nmi_handler(struct notifier_block *self, | |
877 | unsigned long cmd, void *__args) | |
878 | { | |
879 | struct die_args *args = __args; | |
880 | struct pt_regs *regs; | |
b0f3f28e | 881 | |
ba77813a | 882 | if (!atomic_read(&active_counters)) |
63a809a2 PZ |
883 | return NOTIFY_DONE; |
884 | ||
b0f3f28e PZ |
885 | switch (cmd) { |
886 | case DIE_NMI: | |
887 | case DIE_NMI_IPI: | |
888 | break; | |
241771ef | 889 | |
b0f3f28e | 890 | default: |
241771ef | 891 | return NOTIFY_DONE; |
b0f3f28e | 892 | } |
241771ef IM |
893 | |
894 | regs = args->regs; | |
895 | ||
896 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
a4016a79 PZ |
897 | /* |
898 | * Can't rely on the handled return value to say it was our NMI, two | |
899 | * counters could trigger 'simultaneously' raising two back-to-back NMIs. | |
900 | * | |
901 | * If the first NMI handles both, the latter will be empty and daze | |
902 | * the CPU. | |
903 | */ | |
a3288106 | 904 | x86_pmu.handle_irq(regs); |
241771ef | 905 | |
a4016a79 | 906 | return NOTIFY_STOP; |
241771ef IM |
907 | } |
908 | ||
909 | static __read_mostly struct notifier_block perf_counter_nmi_notifier = { | |
5b75af0a MG |
910 | .notifier_call = perf_counter_nmi_handler, |
911 | .next = NULL, | |
912 | .priority = 1 | |
241771ef IM |
913 | }; |
914 | ||
5f4ec28f | 915 | static struct x86_pmu intel_pmu = { |
faa28ae0 | 916 | .name = "Intel", |
39d81eab | 917 | .handle_irq = intel_pmu_handle_irq, |
9e35ad38 PZ |
918 | .disable_all = intel_pmu_disable_all, |
919 | .enable_all = intel_pmu_enable_all, | |
5f4ec28f RR |
920 | .enable = intel_pmu_enable_counter, |
921 | .disable = intel_pmu_disable_counter, | |
b56a3802 JSR |
922 | .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, |
923 | .perfctr = MSR_ARCH_PERFMON_PERFCTR0, | |
5f4ec28f RR |
924 | .event_map = intel_pmu_event_map, |
925 | .raw_event = intel_pmu_raw_event, | |
b56a3802 | 926 | .max_events = ARRAY_SIZE(intel_perfmon_event_map), |
c619b8ff RR |
927 | /* |
928 | * Intel PMCs cannot be accessed sanely above 32 bit width, | |
929 | * so we install an artificial 1<<31 period regardless of | |
930 | * the generic counter period: | |
931 | */ | |
932 | .max_period = (1ULL << 31) - 1, | |
b56a3802 JSR |
933 | }; |
934 | ||
5f4ec28f | 935 | static struct x86_pmu amd_pmu = { |
faa28ae0 | 936 | .name = "AMD", |
39d81eab | 937 | .handle_irq = amd_pmu_handle_irq, |
9e35ad38 PZ |
938 | .disable_all = amd_pmu_disable_all, |
939 | .enable_all = amd_pmu_enable_all, | |
5f4ec28f RR |
940 | .enable = amd_pmu_enable_counter, |
941 | .disable = amd_pmu_disable_counter, | |
f87ad35d JSR |
942 | .eventsel = MSR_K7_EVNTSEL0, |
943 | .perfctr = MSR_K7_PERFCTR0, | |
5f4ec28f RR |
944 | .event_map = amd_pmu_event_map, |
945 | .raw_event = amd_pmu_raw_event, | |
f87ad35d | 946 | .max_events = ARRAY_SIZE(amd_perfmon_event_map), |
0933e5c6 RR |
947 | .num_counters = 4, |
948 | .counter_bits = 48, | |
949 | .counter_mask = (1ULL << 48) - 1, | |
c619b8ff RR |
950 | /* use highest bit to detect overflow */ |
951 | .max_period = (1ULL << 47) - 1, | |
f87ad35d JSR |
952 | }; |
953 | ||
72eae04d | 954 | static int intel_pmu_init(void) |
241771ef | 955 | { |
7bb497bd | 956 | union cpuid10_edx edx; |
241771ef | 957 | union cpuid10_eax eax; |
703e937c | 958 | unsigned int unused; |
7bb497bd | 959 | unsigned int ebx; |
faa28ae0 | 960 | int version; |
241771ef | 961 | |
da1a776b | 962 | if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) |
72eae04d | 963 | return -ENODEV; |
da1a776b | 964 | |
241771ef IM |
965 | /* |
966 | * Check whether the Architectural PerfMon supports | |
967 | * Branch Misses Retired Event or not. | |
968 | */ | |
703e937c | 969 | cpuid(10, &eax.full, &ebx, &unused, &edx.full); |
241771ef | 970 | if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED) |
72eae04d | 971 | return -ENODEV; |
241771ef | 972 | |
faa28ae0 RR |
973 | version = eax.split.version_id; |
974 | if (version < 2) | |
72eae04d | 975 | return -ENODEV; |
7bb497bd | 976 | |
4a06bd85 | 977 | x86_pmu = intel_pmu; |
faa28ae0 | 978 | x86_pmu.version = version; |
0933e5c6 | 979 | x86_pmu.num_counters = eax.split.num_counters; |
066d7dea IM |
980 | |
981 | /* | |
982 | * Quirk: v2 perfmon does not report fixed-purpose counters, so | |
983 | * assume at least 3 counters: | |
984 | */ | |
985 | x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3); | |
986 | ||
0933e5c6 RR |
987 | x86_pmu.counter_bits = eax.split.bit_width; |
988 | x86_pmu.counter_mask = (1ULL << eax.split.bit_width) - 1; | |
b56a3802 | 989 | |
9e35ad38 PZ |
990 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl); |
991 | ||
72eae04d | 992 | return 0; |
b56a3802 JSR |
993 | } |
994 | ||
72eae04d | 995 | static int amd_pmu_init(void) |
f87ad35d | 996 | { |
4a06bd85 | 997 | x86_pmu = amd_pmu; |
72eae04d | 998 | return 0; |
f87ad35d JSR |
999 | } |
1000 | ||
b56a3802 JSR |
1001 | void __init init_hw_perf_counters(void) |
1002 | { | |
72eae04d RR |
1003 | int err; |
1004 | ||
b56a3802 JSR |
1005 | switch (boot_cpu_data.x86_vendor) { |
1006 | case X86_VENDOR_INTEL: | |
72eae04d | 1007 | err = intel_pmu_init(); |
b56a3802 | 1008 | break; |
f87ad35d | 1009 | case X86_VENDOR_AMD: |
72eae04d | 1010 | err = amd_pmu_init(); |
f87ad35d | 1011 | break; |
4138960a RR |
1012 | default: |
1013 | return; | |
b56a3802 | 1014 | } |
72eae04d | 1015 | if (err != 0) |
b56a3802 JSR |
1016 | return; |
1017 | ||
faa28ae0 RR |
1018 | pr_info("%s Performance Monitoring support detected.\n", x86_pmu.name); |
1019 | pr_info("... version: %d\n", x86_pmu.version); | |
1020 | pr_info("... bit width: %d\n", x86_pmu.counter_bits); | |
1021 | ||
0933e5c6 RR |
1022 | pr_info("... num counters: %d\n", x86_pmu.num_counters); |
1023 | if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) { | |
1024 | x86_pmu.num_counters = X86_PMC_MAX_GENERIC; | |
241771ef | 1025 | WARN(1, KERN_ERR "hw perf counters %d > max(%d), clipping!", |
0933e5c6 | 1026 | x86_pmu.num_counters, X86_PMC_MAX_GENERIC); |
241771ef | 1027 | } |
0933e5c6 RR |
1028 | perf_counter_mask = (1 << x86_pmu.num_counters) - 1; |
1029 | perf_max_counters = x86_pmu.num_counters; | |
241771ef | 1030 | |
0933e5c6 | 1031 | pr_info("... value mask: %016Lx\n", x86_pmu.counter_mask); |
c619b8ff | 1032 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); |
2f18d1e8 | 1033 | |
0933e5c6 RR |
1034 | if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) { |
1035 | x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED; | |
703e937c | 1036 | WARN(1, KERN_ERR "hw perf counters fixed %d > max(%d), clipping!", |
0933e5c6 | 1037 | x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED); |
703e937c | 1038 | } |
0933e5c6 | 1039 | pr_info("... fixed counters: %d\n", x86_pmu.num_counters_fixed); |
862a1a5f | 1040 | |
0933e5c6 RR |
1041 | perf_counter_mask |= |
1042 | ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED; | |
241771ef | 1043 | |
a1ef58f4 | 1044 | pr_info("... counter mask: %016Lx\n", perf_counter_mask); |
75f224cf | 1045 | |
c323d95f | 1046 | perf_counters_lapic_init(); |
241771ef | 1047 | register_die_notifier(&perf_counter_nmi_notifier); |
241771ef | 1048 | } |
621a01ea | 1049 | |
bb775fc2 | 1050 | static inline void x86_pmu_read(struct perf_counter *counter) |
ee06094f IM |
1051 | { |
1052 | x86_perf_counter_update(counter, &counter->hw, counter->hw.idx); | |
1053 | } | |
1054 | ||
4aeb0b42 RR |
1055 | static const struct pmu pmu = { |
1056 | .enable = x86_pmu_enable, | |
1057 | .disable = x86_pmu_disable, | |
1058 | .read = x86_pmu_read, | |
a78ac325 | 1059 | .unthrottle = x86_pmu_unthrottle, |
621a01ea IM |
1060 | }; |
1061 | ||
4aeb0b42 | 1062 | const struct pmu *hw_perf_counter_init(struct perf_counter *counter) |
621a01ea IM |
1063 | { |
1064 | int err; | |
1065 | ||
1066 | err = __hw_perf_counter_init(counter); | |
1067 | if (err) | |
9ea98e19 | 1068 | return ERR_PTR(err); |
621a01ea | 1069 | |
4aeb0b42 | 1070 | return &pmu; |
621a01ea | 1071 | } |
d7d59fb3 PZ |
1072 | |
1073 | /* | |
1074 | * callchain support | |
1075 | */ | |
1076 | ||
1077 | static inline | |
1078 | void callchain_store(struct perf_callchain_entry *entry, unsigned long ip) | |
1079 | { | |
1080 | if (entry->nr < MAX_STACK_DEPTH) | |
1081 | entry->ip[entry->nr++] = ip; | |
1082 | } | |
1083 | ||
1084 | static DEFINE_PER_CPU(struct perf_callchain_entry, irq_entry); | |
1085 | static DEFINE_PER_CPU(struct perf_callchain_entry, nmi_entry); | |
1086 | ||
1087 | ||
1088 | static void | |
1089 | backtrace_warning_symbol(void *data, char *msg, unsigned long symbol) | |
1090 | { | |
1091 | /* Ignore warnings */ | |
1092 | } | |
1093 | ||
1094 | static void backtrace_warning(void *data, char *msg) | |
1095 | { | |
1096 | /* Ignore warnings */ | |
1097 | } | |
1098 | ||
1099 | static int backtrace_stack(void *data, char *name) | |
1100 | { | |
1101 | /* Don't bother with IRQ stacks for now */ | |
1102 | return -1; | |
1103 | } | |
1104 | ||
1105 | static void backtrace_address(void *data, unsigned long addr, int reliable) | |
1106 | { | |
1107 | struct perf_callchain_entry *entry = data; | |
1108 | ||
1109 | if (reliable) | |
1110 | callchain_store(entry, addr); | |
1111 | } | |
1112 | ||
1113 | static const struct stacktrace_ops backtrace_ops = { | |
1114 | .warning = backtrace_warning, | |
1115 | .warning_symbol = backtrace_warning_symbol, | |
1116 | .stack = backtrace_stack, | |
1117 | .address = backtrace_address, | |
1118 | }; | |
1119 | ||
1120 | static void | |
1121 | perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1122 | { | |
1123 | unsigned long bp; | |
1124 | char *stack; | |
5872bdb8 | 1125 | int nr = entry->nr; |
d7d59fb3 PZ |
1126 | |
1127 | callchain_store(entry, instruction_pointer(regs)); | |
1128 | ||
1129 | stack = ((char *)regs + sizeof(struct pt_regs)); | |
1130 | #ifdef CONFIG_FRAME_POINTER | |
1131 | bp = frame_pointer(regs); | |
1132 | #else | |
1133 | bp = 0; | |
1134 | #endif | |
1135 | ||
1136 | dump_trace(NULL, regs, (void *)stack, bp, &backtrace_ops, entry); | |
5872bdb8 PZ |
1137 | |
1138 | entry->kernel = entry->nr - nr; | |
d7d59fb3 PZ |
1139 | } |
1140 | ||
1141 | ||
1142 | struct stack_frame { | |
1143 | const void __user *next_fp; | |
1144 | unsigned long return_address; | |
1145 | }; | |
1146 | ||
1147 | static int copy_stack_frame(const void __user *fp, struct stack_frame *frame) | |
1148 | { | |
1149 | int ret; | |
1150 | ||
1151 | if (!access_ok(VERIFY_READ, fp, sizeof(*frame))) | |
1152 | return 0; | |
1153 | ||
1154 | ret = 1; | |
1155 | pagefault_disable(); | |
1156 | if (__copy_from_user_inatomic(frame, fp, sizeof(*frame))) | |
1157 | ret = 0; | |
1158 | pagefault_enable(); | |
1159 | ||
1160 | return ret; | |
1161 | } | |
1162 | ||
1163 | static void | |
1164 | perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1165 | { | |
1166 | struct stack_frame frame; | |
1167 | const void __user *fp; | |
5872bdb8 | 1168 | int nr = entry->nr; |
d7d59fb3 PZ |
1169 | |
1170 | regs = (struct pt_regs *)current->thread.sp0 - 1; | |
1171 | fp = (void __user *)regs->bp; | |
1172 | ||
1173 | callchain_store(entry, regs->ip); | |
1174 | ||
1175 | while (entry->nr < MAX_STACK_DEPTH) { | |
1176 | frame.next_fp = NULL; | |
1177 | frame.return_address = 0; | |
1178 | ||
1179 | if (!copy_stack_frame(fp, &frame)) | |
1180 | break; | |
1181 | ||
1182 | if ((unsigned long)fp < user_stack_pointer(regs)) | |
1183 | break; | |
1184 | ||
1185 | callchain_store(entry, frame.return_address); | |
1186 | fp = frame.next_fp; | |
1187 | } | |
5872bdb8 PZ |
1188 | |
1189 | entry->user = entry->nr - nr; | |
d7d59fb3 PZ |
1190 | } |
1191 | ||
1192 | static void | |
1193 | perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1194 | { | |
1195 | int is_user; | |
1196 | ||
1197 | if (!regs) | |
1198 | return; | |
1199 | ||
1200 | is_user = user_mode(regs); | |
1201 | ||
1202 | if (!current || current->pid == 0) | |
1203 | return; | |
1204 | ||
1205 | if (is_user && current->state != TASK_RUNNING) | |
1206 | return; | |
1207 | ||
1208 | if (!is_user) | |
1209 | perf_callchain_kernel(regs, entry); | |
1210 | ||
1211 | if (current->mm) | |
1212 | perf_callchain_user(regs, entry); | |
1213 | } | |
1214 | ||
1215 | struct perf_callchain_entry *perf_callchain(struct pt_regs *regs) | |
1216 | { | |
1217 | struct perf_callchain_entry *entry; | |
1218 | ||
1219 | if (in_nmi()) | |
1220 | entry = &__get_cpu_var(nmi_entry); | |
1221 | else | |
1222 | entry = &__get_cpu_var(irq_entry); | |
1223 | ||
1224 | entry->nr = 0; | |
5872bdb8 PZ |
1225 | entry->hv = 0; |
1226 | entry->kernel = 0; | |
1227 | entry->user = 0; | |
d7d59fb3 PZ |
1228 | |
1229 | perf_do_callchain(regs, entry); | |
1230 | ||
1231 | return entry; | |
1232 | } |