Commit | Line | Data |
---|---|---|
241771ef IM |
1 | /* |
2 | * Performance counter x86 architecture code | |
3 | * | |
4 | * Copyright(C) 2008 Thomas Gleixner <tglx@linutronix.de> | |
5 | * Copyright(C) 2008 Red Hat, Inc., Ingo Molnar | |
b56a3802 | 6 | * Copyright(C) 2009 Jaswinder Singh Rajput |
39d81eab | 7 | * Copyright(C) 2009 Advanced Micro Devices, Inc., Robert Richter |
241771ef IM |
8 | * |
9 | * For licencing details see kernel-base/COPYING | |
10 | */ | |
11 | ||
12 | #include <linux/perf_counter.h> | |
13 | #include <linux/capability.h> | |
14 | #include <linux/notifier.h> | |
15 | #include <linux/hardirq.h> | |
16 | #include <linux/kprobes.h> | |
4ac13294 | 17 | #include <linux/module.h> |
241771ef IM |
18 | #include <linux/kdebug.h> |
19 | #include <linux/sched.h> | |
d7d59fb3 | 20 | #include <linux/uaccess.h> |
241771ef | 21 | |
241771ef | 22 | #include <asm/apic.h> |
d7d59fb3 | 23 | #include <asm/stacktrace.h> |
4e935e47 | 24 | #include <asm/nmi.h> |
241771ef IM |
25 | |
26 | static bool perf_counters_initialized __read_mostly; | |
862a1a5f | 27 | static u64 perf_counter_mask __read_mostly; |
703e937c | 28 | |
241771ef | 29 | struct cpu_hw_counters { |
862a1a5f IM |
30 | struct perf_counter *counters[X86_PMC_IDX_MAX]; |
31 | unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
93904966 | 32 | unsigned long active[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
4b39fd96 | 33 | unsigned long interrupts; |
b0f3f28e | 34 | u64 throttle_ctrl; |
b0f3f28e | 35 | int enabled; |
241771ef IM |
36 | }; |
37 | ||
38 | /* | |
5f4ec28f | 39 | * struct x86_pmu - generic x86 pmu |
241771ef | 40 | */ |
5f4ec28f | 41 | struct x86_pmu { |
faa28ae0 RR |
42 | const char *name; |
43 | int version; | |
39d81eab | 44 | int (*handle_irq)(struct pt_regs *, int); |
169e41eb | 45 | u64 (*save_disable_all)(void); |
b0f3f28e | 46 | void (*restore_all)(u64); |
b0f3f28e PZ |
47 | void (*enable)(int, u64); |
48 | void (*disable)(int, u64); | |
169e41eb JSR |
49 | unsigned eventsel; |
50 | unsigned perfctr; | |
b0f3f28e PZ |
51 | u64 (*event_map)(int); |
52 | u64 (*raw_event)(u64); | |
169e41eb | 53 | int max_events; |
0933e5c6 RR |
54 | int num_counters; |
55 | int num_counters_fixed; | |
56 | int counter_bits; | |
57 | u64 counter_mask; | |
b56a3802 JSR |
58 | }; |
59 | ||
4a06bd85 | 60 | static struct x86_pmu x86_pmu __read_mostly; |
b56a3802 | 61 | |
b0f3f28e PZ |
62 | static DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters) = { |
63 | .enabled = 1, | |
64 | }; | |
241771ef | 65 | |
b56a3802 JSR |
66 | /* |
67 | * Intel PerfMon v3. Used on Core2 and later. | |
68 | */ | |
b0f3f28e | 69 | static const u64 intel_perfmon_event_map[] = |
241771ef | 70 | { |
f650a672 | 71 | [PERF_COUNT_CPU_CYCLES] = 0x003c, |
241771ef IM |
72 | [PERF_COUNT_INSTRUCTIONS] = 0x00c0, |
73 | [PERF_COUNT_CACHE_REFERENCES] = 0x4f2e, | |
74 | [PERF_COUNT_CACHE_MISSES] = 0x412e, | |
75 | [PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x00c4, | |
76 | [PERF_COUNT_BRANCH_MISSES] = 0x00c5, | |
f650a672 | 77 | [PERF_COUNT_BUS_CYCLES] = 0x013c, |
241771ef IM |
78 | }; |
79 | ||
5f4ec28f | 80 | static u64 intel_pmu_event_map(int event) |
b56a3802 JSR |
81 | { |
82 | return intel_perfmon_event_map[event]; | |
83 | } | |
241771ef | 84 | |
5f4ec28f | 85 | static u64 intel_pmu_raw_event(u64 event) |
b0f3f28e | 86 | { |
82bae4f8 PZ |
87 | #define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL |
88 | #define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL | |
89 | #define CORE_EVNTSEL_COUNTER_MASK 0xFF000000ULL | |
b0f3f28e PZ |
90 | |
91 | #define CORE_EVNTSEL_MASK \ | |
92 | (CORE_EVNTSEL_EVENT_MASK | \ | |
93 | CORE_EVNTSEL_UNIT_MASK | \ | |
94 | CORE_EVNTSEL_COUNTER_MASK) | |
95 | ||
96 | return event & CORE_EVNTSEL_MASK; | |
97 | } | |
98 | ||
f87ad35d JSR |
99 | /* |
100 | * AMD Performance Monitor K7 and later. | |
101 | */ | |
b0f3f28e | 102 | static const u64 amd_perfmon_event_map[] = |
f87ad35d JSR |
103 | { |
104 | [PERF_COUNT_CPU_CYCLES] = 0x0076, | |
105 | [PERF_COUNT_INSTRUCTIONS] = 0x00c0, | |
106 | [PERF_COUNT_CACHE_REFERENCES] = 0x0080, | |
107 | [PERF_COUNT_CACHE_MISSES] = 0x0081, | |
108 | [PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x00c4, | |
109 | [PERF_COUNT_BRANCH_MISSES] = 0x00c5, | |
110 | }; | |
111 | ||
5f4ec28f | 112 | static u64 amd_pmu_event_map(int event) |
f87ad35d JSR |
113 | { |
114 | return amd_perfmon_event_map[event]; | |
115 | } | |
116 | ||
5f4ec28f | 117 | static u64 amd_pmu_raw_event(u64 event) |
b0f3f28e | 118 | { |
82bae4f8 PZ |
119 | #define K7_EVNTSEL_EVENT_MASK 0x7000000FFULL |
120 | #define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL | |
121 | #define K7_EVNTSEL_COUNTER_MASK 0x0FF000000ULL | |
b0f3f28e PZ |
122 | |
123 | #define K7_EVNTSEL_MASK \ | |
124 | (K7_EVNTSEL_EVENT_MASK | \ | |
125 | K7_EVNTSEL_UNIT_MASK | \ | |
126 | K7_EVNTSEL_COUNTER_MASK) | |
127 | ||
128 | return event & K7_EVNTSEL_MASK; | |
129 | } | |
130 | ||
ee06094f IM |
131 | /* |
132 | * Propagate counter elapsed time into the generic counter. | |
133 | * Can only be executed on the CPU where the counter is active. | |
134 | * Returns the delta events processed. | |
135 | */ | |
136 | static void | |
137 | x86_perf_counter_update(struct perf_counter *counter, | |
138 | struct hw_perf_counter *hwc, int idx) | |
139 | { | |
140 | u64 prev_raw_count, new_raw_count, delta; | |
141 | ||
ee06094f IM |
142 | /* |
143 | * Careful: an NMI might modify the previous counter value. | |
144 | * | |
145 | * Our tactic to handle this is to first atomically read and | |
146 | * exchange a new raw count - then add that new-prev delta | |
147 | * count to the generic counter atomically: | |
148 | */ | |
149 | again: | |
150 | prev_raw_count = atomic64_read(&hwc->prev_count); | |
151 | rdmsrl(hwc->counter_base + idx, new_raw_count); | |
152 | ||
153 | if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count, | |
154 | new_raw_count) != prev_raw_count) | |
155 | goto again; | |
156 | ||
157 | /* | |
158 | * Now we have the new raw value and have updated the prev | |
159 | * timestamp already. We can now calculate the elapsed delta | |
160 | * (counter-)time and add that to the generic counter. | |
161 | * | |
162 | * Careful, not all hw sign-extends above the physical width | |
163 | * of the count, so we do that by clipping the delta to 32 bits: | |
164 | */ | |
165 | delta = (u64)(u32)((s32)new_raw_count - (s32)prev_raw_count); | |
ee06094f IM |
166 | |
167 | atomic64_add(delta, &counter->count); | |
168 | atomic64_sub(delta, &hwc->period_left); | |
169 | } | |
170 | ||
4e935e47 PZ |
171 | static atomic_t num_counters; |
172 | static DEFINE_MUTEX(pmc_reserve_mutex); | |
173 | ||
174 | static bool reserve_pmc_hardware(void) | |
175 | { | |
176 | int i; | |
177 | ||
178 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
179 | disable_lapic_nmi_watchdog(); | |
180 | ||
0933e5c6 | 181 | for (i = 0; i < x86_pmu.num_counters; i++) { |
4a06bd85 | 182 | if (!reserve_perfctr_nmi(x86_pmu.perfctr + i)) |
4e935e47 PZ |
183 | goto perfctr_fail; |
184 | } | |
185 | ||
0933e5c6 | 186 | for (i = 0; i < x86_pmu.num_counters; i++) { |
4a06bd85 | 187 | if (!reserve_evntsel_nmi(x86_pmu.eventsel + i)) |
4e935e47 PZ |
188 | goto eventsel_fail; |
189 | } | |
190 | ||
191 | return true; | |
192 | ||
193 | eventsel_fail: | |
194 | for (i--; i >= 0; i--) | |
4a06bd85 | 195 | release_evntsel_nmi(x86_pmu.eventsel + i); |
4e935e47 | 196 | |
0933e5c6 | 197 | i = x86_pmu.num_counters; |
4e935e47 PZ |
198 | |
199 | perfctr_fail: | |
200 | for (i--; i >= 0; i--) | |
4a06bd85 | 201 | release_perfctr_nmi(x86_pmu.perfctr + i); |
4e935e47 PZ |
202 | |
203 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
204 | enable_lapic_nmi_watchdog(); | |
205 | ||
206 | return false; | |
207 | } | |
208 | ||
209 | static void release_pmc_hardware(void) | |
210 | { | |
211 | int i; | |
212 | ||
0933e5c6 | 213 | for (i = 0; i < x86_pmu.num_counters; i++) { |
4a06bd85 RR |
214 | release_perfctr_nmi(x86_pmu.perfctr + i); |
215 | release_evntsel_nmi(x86_pmu.eventsel + i); | |
4e935e47 PZ |
216 | } |
217 | ||
218 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
219 | enable_lapic_nmi_watchdog(); | |
220 | } | |
221 | ||
222 | static void hw_perf_counter_destroy(struct perf_counter *counter) | |
223 | { | |
224 | if (atomic_dec_and_mutex_lock(&num_counters, &pmc_reserve_mutex)) { | |
225 | release_pmc_hardware(); | |
226 | mutex_unlock(&pmc_reserve_mutex); | |
227 | } | |
228 | } | |
229 | ||
241771ef IM |
230 | /* |
231 | * Setup the hardware configuration for a given hw_event_type | |
232 | */ | |
621a01ea | 233 | static int __hw_perf_counter_init(struct perf_counter *counter) |
241771ef | 234 | { |
9f66a381 | 235 | struct perf_counter_hw_event *hw_event = &counter->hw_event; |
241771ef | 236 | struct hw_perf_counter *hwc = &counter->hw; |
4e935e47 | 237 | int err; |
241771ef | 238 | |
39d81eab RR |
239 | /* disable temporarily */ |
240 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) | |
241 | return -ENOSYS; | |
242 | ||
241771ef IM |
243 | if (unlikely(!perf_counters_initialized)) |
244 | return -EINVAL; | |
245 | ||
4e935e47 PZ |
246 | err = 0; |
247 | if (atomic_inc_not_zero(&num_counters)) { | |
248 | mutex_lock(&pmc_reserve_mutex); | |
249 | if (atomic_read(&num_counters) == 0 && !reserve_pmc_hardware()) | |
250 | err = -EBUSY; | |
251 | else | |
252 | atomic_inc(&num_counters); | |
253 | mutex_unlock(&pmc_reserve_mutex); | |
254 | } | |
255 | if (err) | |
256 | return err; | |
257 | ||
241771ef | 258 | /* |
0475f9ea | 259 | * Generate PMC IRQs: |
241771ef IM |
260 | * (keep 'enabled' bit clear for now) |
261 | */ | |
0475f9ea | 262 | hwc->config = ARCH_PERFMON_EVENTSEL_INT; |
241771ef IM |
263 | |
264 | /* | |
0475f9ea | 265 | * Count user and OS events unless requested not to. |
241771ef | 266 | */ |
0475f9ea PM |
267 | if (!hw_event->exclude_user) |
268 | hwc->config |= ARCH_PERFMON_EVENTSEL_USR; | |
269 | if (!hw_event->exclude_kernel) | |
241771ef | 270 | hwc->config |= ARCH_PERFMON_EVENTSEL_OS; |
0475f9ea PM |
271 | |
272 | /* | |
273 | * If privileged enough, allow NMI events: | |
274 | */ | |
275 | hwc->nmi = 0; | |
276 | if (capable(CAP_SYS_ADMIN) && hw_event->nmi) | |
277 | hwc->nmi = 1; | |
241771ef | 278 | |
9f66a381 | 279 | hwc->irq_period = hw_event->irq_period; |
241771ef IM |
280 | /* |
281 | * Intel PMCs cannot be accessed sanely above 32 bit width, | |
282 | * so we install an artificial 1<<31 period regardless of | |
283 | * the generic counter period: | |
284 | */ | |
f87ad35d JSR |
285 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
286 | if ((s64)hwc->irq_period <= 0 || hwc->irq_period > 0x7FFFFFFF) | |
287 | hwc->irq_period = 0x7FFFFFFF; | |
241771ef | 288 | |
ee06094f | 289 | atomic64_set(&hwc->period_left, hwc->irq_period); |
241771ef IM |
290 | |
291 | /* | |
dfa7c899 | 292 | * Raw event type provide the config in the event structure |
241771ef | 293 | */ |
f4a2deb4 | 294 | if (perf_event_raw(hw_event)) { |
4a06bd85 | 295 | hwc->config |= x86_pmu.raw_event(perf_event_config(hw_event)); |
241771ef | 296 | } else { |
4a06bd85 | 297 | if (perf_event_id(hw_event) >= x86_pmu.max_events) |
241771ef IM |
298 | return -EINVAL; |
299 | /* | |
300 | * The generic map: | |
301 | */ | |
4a06bd85 | 302 | hwc->config |= x86_pmu.event_map(perf_event_id(hw_event)); |
241771ef | 303 | } |
241771ef | 304 | |
4e935e47 PZ |
305 | counter->destroy = hw_perf_counter_destroy; |
306 | ||
241771ef IM |
307 | return 0; |
308 | } | |
309 | ||
5f4ec28f | 310 | static u64 intel_pmu_save_disable_all(void) |
4ac13294 TG |
311 | { |
312 | u64 ctrl; | |
313 | ||
314 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); | |
862a1a5f | 315 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); |
2b9ff0db | 316 | |
4ac13294 | 317 | return ctrl; |
241771ef | 318 | } |
b56a3802 | 319 | |
5f4ec28f | 320 | static u64 amd_pmu_save_disable_all(void) |
f87ad35d | 321 | { |
b0f3f28e PZ |
322 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); |
323 | int enabled, idx; | |
324 | ||
325 | enabled = cpuc->enabled; | |
326 | cpuc->enabled = 0; | |
60b3df9c PZ |
327 | /* |
328 | * ensure we write the disable before we start disabling the | |
5f4ec28f RR |
329 | * counters proper, so that amd_pmu_enable_counter() does the |
330 | * right thing. | |
60b3df9c | 331 | */ |
b0f3f28e | 332 | barrier(); |
f87ad35d | 333 | |
0933e5c6 | 334 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
b0f3f28e PZ |
335 | u64 val; |
336 | ||
93904966 | 337 | if (!test_bit(idx, cpuc->active)) |
4295ee62 | 338 | continue; |
f87ad35d | 339 | rdmsrl(MSR_K7_EVNTSEL0 + idx, val); |
4295ee62 RR |
340 | if (!(val & ARCH_PERFMON_EVENTSEL0_ENABLE)) |
341 | continue; | |
342 | val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE; | |
343 | wrmsrl(MSR_K7_EVNTSEL0 + idx, val); | |
f87ad35d JSR |
344 | } |
345 | ||
b0f3f28e | 346 | return enabled; |
f87ad35d JSR |
347 | } |
348 | ||
b56a3802 JSR |
349 | u64 hw_perf_save_disable(void) |
350 | { | |
351 | if (unlikely(!perf_counters_initialized)) | |
352 | return 0; | |
353 | ||
4a06bd85 | 354 | return x86_pmu.save_disable_all(); |
b56a3802 | 355 | } |
b0f3f28e PZ |
356 | /* |
357 | * Exported because of ACPI idle | |
358 | */ | |
01b2838c | 359 | EXPORT_SYMBOL_GPL(hw_perf_save_disable); |
241771ef | 360 | |
5f4ec28f | 361 | static void intel_pmu_restore_all(u64 ctrl) |
b56a3802 JSR |
362 | { |
363 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); | |
364 | } | |
365 | ||
5f4ec28f | 366 | static void amd_pmu_restore_all(u64 ctrl) |
f87ad35d | 367 | { |
b0f3f28e | 368 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); |
f87ad35d JSR |
369 | int idx; |
370 | ||
b0f3f28e PZ |
371 | cpuc->enabled = ctrl; |
372 | barrier(); | |
373 | if (!ctrl) | |
374 | return; | |
375 | ||
0933e5c6 | 376 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
4295ee62 | 377 | u64 val; |
b0f3f28e | 378 | |
93904966 | 379 | if (!test_bit(idx, cpuc->active)) |
4295ee62 RR |
380 | continue; |
381 | rdmsrl(MSR_K7_EVNTSEL0 + idx, val); | |
382 | if (val & ARCH_PERFMON_EVENTSEL0_ENABLE) | |
383 | continue; | |
384 | val |= ARCH_PERFMON_EVENTSEL0_ENABLE; | |
385 | wrmsrl(MSR_K7_EVNTSEL0 + idx, val); | |
f87ad35d JSR |
386 | } |
387 | } | |
388 | ||
ee06094f IM |
389 | void hw_perf_restore(u64 ctrl) |
390 | { | |
2b9ff0db IM |
391 | if (unlikely(!perf_counters_initialized)) |
392 | return; | |
393 | ||
4a06bd85 | 394 | x86_pmu.restore_all(ctrl); |
ee06094f | 395 | } |
b0f3f28e PZ |
396 | /* |
397 | * Exported because of ACPI idle | |
398 | */ | |
ee06094f IM |
399 | EXPORT_SYMBOL_GPL(hw_perf_restore); |
400 | ||
b7f8859a | 401 | static inline u64 intel_pmu_get_status(u64 mask) |
b0f3f28e PZ |
402 | { |
403 | u64 status; | |
404 | ||
b0f3f28e PZ |
405 | if (unlikely(!perf_counters_initialized)) |
406 | return 0; | |
b7f8859a | 407 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); |
b0f3f28e | 408 | |
b7f8859a | 409 | return status; |
b0f3f28e PZ |
410 | } |
411 | ||
dee5d906 | 412 | static inline void intel_pmu_ack_status(u64 ack) |
b0f3f28e PZ |
413 | { |
414 | wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); | |
415 | } | |
416 | ||
5f4ec28f | 417 | static void intel_pmu_enable_counter(int idx, u64 config) |
b0f3f28e PZ |
418 | { |
419 | wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + idx, | |
420 | config | ARCH_PERFMON_EVENTSEL0_ENABLE); | |
421 | } | |
422 | ||
5f4ec28f | 423 | static void amd_pmu_enable_counter(int idx, u64 config) |
b0f3f28e PZ |
424 | { |
425 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
426 | ||
b0f3f28e PZ |
427 | if (cpuc->enabled) |
428 | config |= ARCH_PERFMON_EVENTSEL0_ENABLE; | |
429 | ||
430 | wrmsrl(MSR_K7_EVNTSEL0 + idx, config); | |
431 | } | |
432 | ||
433 | static void hw_perf_enable(int idx, u64 config) | |
434 | { | |
435 | if (unlikely(!perf_counters_initialized)) | |
436 | return; | |
437 | ||
4a06bd85 | 438 | x86_pmu.enable(idx, config); |
b0f3f28e PZ |
439 | } |
440 | ||
5f4ec28f | 441 | static void intel_pmu_disable_counter(int idx, u64 config) |
b0f3f28e PZ |
442 | { |
443 | wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + idx, config); | |
444 | } | |
445 | ||
5f4ec28f | 446 | static void amd_pmu_disable_counter(int idx, u64 config) |
b0f3f28e | 447 | { |
b0f3f28e PZ |
448 | wrmsrl(MSR_K7_EVNTSEL0 + idx, config); |
449 | ||
450 | } | |
451 | ||
452 | static void hw_perf_disable(int idx, u64 config) | |
453 | { | |
454 | if (unlikely(!perf_counters_initialized)) | |
455 | return; | |
456 | ||
4a06bd85 | 457 | x86_pmu.disable(idx, config); |
b0f3f28e PZ |
458 | } |
459 | ||
2f18d1e8 IM |
460 | static inline void |
461 | __pmc_fixed_disable(struct perf_counter *counter, | |
6f00cada | 462 | struct hw_perf_counter *hwc, int __idx) |
2f18d1e8 IM |
463 | { |
464 | int idx = __idx - X86_PMC_IDX_FIXED; | |
465 | u64 ctrl_val, mask; | |
466 | int err; | |
467 | ||
468 | mask = 0xfULL << (idx * 4); | |
469 | ||
470 | rdmsrl(hwc->config_base, ctrl_val); | |
471 | ctrl_val &= ~mask; | |
472 | err = checking_wrmsrl(hwc->config_base, ctrl_val); | |
473 | } | |
474 | ||
7e2ae347 | 475 | static inline void |
4aeb0b42 | 476 | __x86_pmu_disable(struct perf_counter *counter, |
6f00cada | 477 | struct hw_perf_counter *hwc, int idx) |
7e2ae347 | 478 | { |
2f18d1e8 | 479 | if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) |
2b583d8b JSR |
480 | __pmc_fixed_disable(counter, hwc, idx); |
481 | else | |
b0f3f28e | 482 | hw_perf_disable(idx, hwc->config); |
7e2ae347 IM |
483 | } |
484 | ||
2f18d1e8 | 485 | static DEFINE_PER_CPU(u64, prev_left[X86_PMC_IDX_MAX]); |
241771ef | 486 | |
ee06094f IM |
487 | /* |
488 | * Set the next IRQ period, based on the hwc->period_left value. | |
489 | * To be called with the counter disabled in hw: | |
490 | */ | |
491 | static void | |
26816c28 | 492 | x86_perf_counter_set_period(struct perf_counter *counter, |
ee06094f | 493 | struct hw_perf_counter *hwc, int idx) |
241771ef | 494 | { |
2f18d1e8 | 495 | s64 left = atomic64_read(&hwc->period_left); |
595258aa | 496 | s64 period = hwc->irq_period; |
2f18d1e8 | 497 | int err; |
ee06094f | 498 | |
ee06094f IM |
499 | /* |
500 | * If we are way outside a reasoable range then just skip forward: | |
501 | */ | |
502 | if (unlikely(left <= -period)) { | |
503 | left = period; | |
504 | atomic64_set(&hwc->period_left, left); | |
505 | } | |
506 | ||
507 | if (unlikely(left <= 0)) { | |
508 | left += period; | |
509 | atomic64_set(&hwc->period_left, left); | |
510 | } | |
241771ef | 511 | |
ee06094f IM |
512 | per_cpu(prev_left[idx], smp_processor_id()) = left; |
513 | ||
514 | /* | |
515 | * The hw counter starts counting from this counter offset, | |
516 | * mark it to be able to extra future deltas: | |
517 | */ | |
2f18d1e8 | 518 | atomic64_set(&hwc->prev_count, (u64)-left); |
ee06094f | 519 | |
2f18d1e8 | 520 | err = checking_wrmsrl(hwc->counter_base + idx, |
0933e5c6 | 521 | (u64)(-left) & x86_pmu.counter_mask); |
2f18d1e8 IM |
522 | } |
523 | ||
524 | static inline void | |
525 | __pmc_fixed_enable(struct perf_counter *counter, | |
6f00cada | 526 | struct hw_perf_counter *hwc, int __idx) |
2f18d1e8 IM |
527 | { |
528 | int idx = __idx - X86_PMC_IDX_FIXED; | |
529 | u64 ctrl_val, bits, mask; | |
530 | int err; | |
531 | ||
532 | /* | |
0475f9ea PM |
533 | * Enable IRQ generation (0x8), |
534 | * and enable ring-3 counting (0x2) and ring-0 counting (0x1) | |
535 | * if requested: | |
2f18d1e8 | 536 | */ |
0475f9ea PM |
537 | bits = 0x8ULL; |
538 | if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) | |
539 | bits |= 0x2; | |
2f18d1e8 IM |
540 | if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) |
541 | bits |= 0x1; | |
542 | bits <<= (idx * 4); | |
543 | mask = 0xfULL << (idx * 4); | |
544 | ||
545 | rdmsrl(hwc->config_base, ctrl_val); | |
546 | ctrl_val &= ~mask; | |
547 | ctrl_val |= bits; | |
548 | err = checking_wrmsrl(hwc->config_base, ctrl_val); | |
7e2ae347 IM |
549 | } |
550 | ||
ee06094f | 551 | static void |
4aeb0b42 RR |
552 | __x86_pmu_enable(struct perf_counter *counter, |
553 | struct hw_perf_counter *hwc, int idx) | |
7e2ae347 | 554 | { |
2f18d1e8 | 555 | if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) |
2b583d8b JSR |
556 | __pmc_fixed_enable(counter, hwc, idx); |
557 | else | |
b0f3f28e | 558 | hw_perf_enable(idx, hwc->config); |
241771ef IM |
559 | } |
560 | ||
2f18d1e8 IM |
561 | static int |
562 | fixed_mode_idx(struct perf_counter *counter, struct hw_perf_counter *hwc) | |
862a1a5f | 563 | { |
2f18d1e8 IM |
564 | unsigned int event; |
565 | ||
f87ad35d JSR |
566 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) |
567 | return -1; | |
568 | ||
2f18d1e8 IM |
569 | if (unlikely(hwc->nmi)) |
570 | return -1; | |
571 | ||
572 | event = hwc->config & ARCH_PERFMON_EVENT_MASK; | |
573 | ||
4a06bd85 | 574 | if (unlikely(event == x86_pmu.event_map(PERF_COUNT_INSTRUCTIONS))) |
2f18d1e8 | 575 | return X86_PMC_IDX_FIXED_INSTRUCTIONS; |
4a06bd85 | 576 | if (unlikely(event == x86_pmu.event_map(PERF_COUNT_CPU_CYCLES))) |
2f18d1e8 | 577 | return X86_PMC_IDX_FIXED_CPU_CYCLES; |
4a06bd85 | 578 | if (unlikely(event == x86_pmu.event_map(PERF_COUNT_BUS_CYCLES))) |
2f18d1e8 IM |
579 | return X86_PMC_IDX_FIXED_BUS_CYCLES; |
580 | ||
862a1a5f IM |
581 | return -1; |
582 | } | |
583 | ||
ee06094f IM |
584 | /* |
585 | * Find a PMC slot for the freshly enabled / scheduled in counter: | |
586 | */ | |
4aeb0b42 | 587 | static int x86_pmu_enable(struct perf_counter *counter) |
241771ef IM |
588 | { |
589 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
590 | struct hw_perf_counter *hwc = &counter->hw; | |
2f18d1e8 | 591 | int idx; |
241771ef | 592 | |
2f18d1e8 IM |
593 | idx = fixed_mode_idx(counter, hwc); |
594 | if (idx >= 0) { | |
595 | /* | |
596 | * Try to get the fixed counter, if that is already taken | |
597 | * then try to get a generic counter: | |
598 | */ | |
599 | if (test_and_set_bit(idx, cpuc->used)) | |
600 | goto try_generic; | |
0dff86aa | 601 | |
2f18d1e8 IM |
602 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; |
603 | /* | |
604 | * We set it so that counter_base + idx in wrmsr/rdmsr maps to | |
605 | * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2: | |
606 | */ | |
607 | hwc->counter_base = | |
608 | MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED; | |
241771ef | 609 | hwc->idx = idx; |
2f18d1e8 IM |
610 | } else { |
611 | idx = hwc->idx; | |
612 | /* Try to get the previous generic counter again */ | |
613 | if (test_and_set_bit(idx, cpuc->used)) { | |
614 | try_generic: | |
0933e5c6 RR |
615 | idx = find_first_zero_bit(cpuc->used, |
616 | x86_pmu.num_counters); | |
617 | if (idx == x86_pmu.num_counters) | |
2f18d1e8 IM |
618 | return -EAGAIN; |
619 | ||
620 | set_bit(idx, cpuc->used); | |
621 | hwc->idx = idx; | |
622 | } | |
4a06bd85 RR |
623 | hwc->config_base = x86_pmu.eventsel; |
624 | hwc->counter_base = x86_pmu.perfctr; | |
241771ef IM |
625 | } |
626 | ||
627 | perf_counters_lapic_init(hwc->nmi); | |
628 | ||
4aeb0b42 | 629 | __x86_pmu_disable(counter, hwc, idx); |
241771ef | 630 | |
862a1a5f | 631 | cpuc->counters[idx] = counter; |
09534238 | 632 | set_bit(idx, cpuc->active); |
7e2ae347 | 633 | |
26816c28 | 634 | x86_perf_counter_set_period(counter, hwc, idx); |
4aeb0b42 | 635 | __x86_pmu_enable(counter, hwc, idx); |
95cdd2e7 IM |
636 | |
637 | return 0; | |
241771ef IM |
638 | } |
639 | ||
640 | void perf_counter_print_debug(void) | |
641 | { | |
2f18d1e8 | 642 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
0dff86aa | 643 | struct cpu_hw_counters *cpuc; |
1e125676 IM |
644 | int cpu, idx; |
645 | ||
0933e5c6 | 646 | if (!x86_pmu.num_counters) |
1e125676 | 647 | return; |
241771ef IM |
648 | |
649 | local_irq_disable(); | |
650 | ||
651 | cpu = smp_processor_id(); | |
0dff86aa | 652 | cpuc = &per_cpu(cpu_hw_counters, cpu); |
241771ef | 653 | |
faa28ae0 | 654 | if (x86_pmu.version >= 2) { |
a1ef58f4 JSR |
655 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
656 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
657 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
658 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); | |
659 | ||
660 | pr_info("\n"); | |
661 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
662 | pr_info("CPU#%d: status: %016llx\n", cpu, status); | |
663 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); | |
664 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); | |
f87ad35d | 665 | } |
a1ef58f4 | 666 | pr_info("CPU#%d: used: %016llx\n", cpu, *(u64 *)cpuc->used); |
241771ef | 667 | |
0933e5c6 | 668 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
4a06bd85 RR |
669 | rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl); |
670 | rdmsrl(x86_pmu.perfctr + idx, pmc_count); | |
241771ef | 671 | |
ee06094f | 672 | prev_left = per_cpu(prev_left[idx], cpu); |
241771ef | 673 | |
a1ef58f4 | 674 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 675 | cpu, idx, pmc_ctrl); |
a1ef58f4 | 676 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 677 | cpu, idx, pmc_count); |
a1ef58f4 | 678 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 679 | cpu, idx, prev_left); |
241771ef | 680 | } |
0933e5c6 | 681 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { |
2f18d1e8 IM |
682 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
683 | ||
a1ef58f4 | 684 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
2f18d1e8 IM |
685 | cpu, idx, pmc_count); |
686 | } | |
241771ef IM |
687 | local_irq_enable(); |
688 | } | |
689 | ||
4aeb0b42 | 690 | static void x86_pmu_disable(struct perf_counter *counter) |
241771ef IM |
691 | { |
692 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
693 | struct hw_perf_counter *hwc = &counter->hw; | |
6f00cada | 694 | int idx = hwc->idx; |
241771ef | 695 | |
09534238 RR |
696 | /* |
697 | * Must be done before we disable, otherwise the nmi handler | |
698 | * could reenable again: | |
699 | */ | |
700 | clear_bit(idx, cpuc->active); | |
4aeb0b42 | 701 | __x86_pmu_disable(counter, hwc, idx); |
241771ef | 702 | |
2f18d1e8 IM |
703 | /* |
704 | * Make sure the cleared pointer becomes visible before we | |
705 | * (potentially) free the counter: | |
706 | */ | |
527e26af | 707 | barrier(); |
241771ef | 708 | |
ee06094f IM |
709 | /* |
710 | * Drain the remaining delta count out of a counter | |
711 | * that we are disabling: | |
712 | */ | |
713 | x86_perf_counter_update(counter, hwc, idx); | |
09534238 RR |
714 | cpuc->counters[idx] = NULL; |
715 | clear_bit(idx, cpuc->used); | |
241771ef IM |
716 | } |
717 | ||
7e2ae347 | 718 | /* |
ee06094f IM |
719 | * Save and restart an expired counter. Called by NMI contexts, |
720 | * so it has to be careful about preempting normal counter ops: | |
7e2ae347 | 721 | */ |
55de0f2e | 722 | static void intel_pmu_save_and_restart(struct perf_counter *counter) |
241771ef IM |
723 | { |
724 | struct hw_perf_counter *hwc = &counter->hw; | |
725 | int idx = hwc->idx; | |
241771ef | 726 | |
ee06094f | 727 | x86_perf_counter_update(counter, hwc, idx); |
26816c28 | 728 | x86_perf_counter_set_period(counter, hwc, idx); |
7e2ae347 | 729 | |
2f18d1e8 | 730 | if (counter->state == PERF_COUNTER_STATE_ACTIVE) |
4aeb0b42 | 731 | __x86_pmu_enable(counter, hwc, idx); |
241771ef IM |
732 | } |
733 | ||
4b39fd96 MG |
734 | /* |
735 | * Maximum interrupt frequency of 100KHz per CPU | |
736 | */ | |
169e41eb | 737 | #define PERFMON_MAX_INTERRUPTS (100000/HZ) |
4b39fd96 | 738 | |
241771ef IM |
739 | /* |
740 | * This handler is triggered by the local APIC, so the APIC IRQ handling | |
741 | * rules apply: | |
742 | */ | |
39d81eab | 743 | static int intel_pmu_handle_irq(struct pt_regs *regs, int nmi) |
241771ef IM |
744 | { |
745 | int bit, cpu = smp_processor_id(); | |
4b39fd96 | 746 | u64 ack, status; |
1b023a96 | 747 | struct cpu_hw_counters *cpuc = &per_cpu(cpu_hw_counters, cpu); |
b0f3f28e | 748 | int ret = 0; |
43874d23 | 749 | |
55de0f2e | 750 | cpuc->throttle_ctrl = intel_pmu_save_disable_all(); |
241771ef | 751 | |
b7f8859a | 752 | status = intel_pmu_get_status(cpuc->throttle_ctrl); |
87b9cf46 IM |
753 | if (!status) |
754 | goto out; | |
755 | ||
b0f3f28e | 756 | ret = 1; |
241771ef | 757 | again: |
d278c484 | 758 | inc_irq_stat(apic_perf_irqs); |
241771ef | 759 | ack = status; |
2f18d1e8 | 760 | for_each_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { |
862a1a5f | 761 | struct perf_counter *counter = cpuc->counters[bit]; |
241771ef IM |
762 | |
763 | clear_bit(bit, (unsigned long *) &status); | |
09534238 | 764 | if (!test_bit(bit, cpuc->active)) |
241771ef IM |
765 | continue; |
766 | ||
55de0f2e | 767 | intel_pmu_save_and_restart(counter); |
78f13e95 | 768 | if (perf_counter_overflow(counter, nmi, regs, 0)) |
4aeb0b42 | 769 | __x86_pmu_disable(counter, &counter->hw, bit); |
241771ef IM |
770 | } |
771 | ||
dee5d906 | 772 | intel_pmu_ack_status(ack); |
241771ef IM |
773 | |
774 | /* | |
775 | * Repeat if there is more work to be done: | |
776 | */ | |
b7f8859a | 777 | status = intel_pmu_get_status(cpuc->throttle_ctrl); |
241771ef IM |
778 | if (status) |
779 | goto again; | |
87b9cf46 | 780 | out: |
241771ef | 781 | /* |
1b023a96 | 782 | * Restore - do not reenable when global enable is off or throttled: |
241771ef | 783 | */ |
4b39fd96 | 784 | if (++cpuc->interrupts < PERFMON_MAX_INTERRUPTS) |
55de0f2e | 785 | intel_pmu_restore_all(cpuc->throttle_ctrl); |
b0f3f28e PZ |
786 | |
787 | return ret; | |
1b023a96 MG |
788 | } |
789 | ||
39d81eab RR |
790 | static int amd_pmu_handle_irq(struct pt_regs *regs, int nmi) { return 0; } |
791 | ||
1b023a96 MG |
792 | void perf_counter_unthrottle(void) |
793 | { | |
794 | struct cpu_hw_counters *cpuc; | |
795 | ||
796 | if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) | |
797 | return; | |
798 | ||
799 | if (unlikely(!perf_counters_initialized)) | |
800 | return; | |
801 | ||
b0f3f28e | 802 | cpuc = &__get_cpu_var(cpu_hw_counters); |
4b39fd96 | 803 | if (cpuc->interrupts >= PERFMON_MAX_INTERRUPTS) { |
1b023a96 | 804 | if (printk_ratelimit()) |
4b39fd96 | 805 | printk(KERN_WARNING "PERFMON: max interrupts exceeded!\n"); |
b0f3f28e | 806 | hw_perf_restore(cpuc->throttle_ctrl); |
1b023a96 | 807 | } |
4b39fd96 | 808 | cpuc->interrupts = 0; |
241771ef IM |
809 | } |
810 | ||
811 | void smp_perf_counter_interrupt(struct pt_regs *regs) | |
812 | { | |
813 | irq_enter(); | |
241771ef | 814 | apic_write(APIC_LVTPC, LOCAL_PERF_VECTOR); |
b0f3f28e | 815 | ack_APIC_irq(); |
4a06bd85 | 816 | x86_pmu.handle_irq(regs, 0); |
241771ef IM |
817 | irq_exit(); |
818 | } | |
819 | ||
b6276f35 PZ |
820 | void smp_perf_pending_interrupt(struct pt_regs *regs) |
821 | { | |
822 | irq_enter(); | |
823 | ack_APIC_irq(); | |
824 | inc_irq_stat(apic_pending_irqs); | |
825 | perf_counter_do_pending(); | |
826 | irq_exit(); | |
827 | } | |
828 | ||
829 | void set_perf_counter_pending(void) | |
830 | { | |
831 | apic->send_IPI_self(LOCAL_PENDING_VECTOR); | |
832 | } | |
833 | ||
3415dd91 | 834 | void perf_counters_lapic_init(int nmi) |
241771ef IM |
835 | { |
836 | u32 apic_val; | |
837 | ||
838 | if (!perf_counters_initialized) | |
839 | return; | |
840 | /* | |
841 | * Enable the performance counter vector in the APIC LVT: | |
842 | */ | |
843 | apic_val = apic_read(APIC_LVTERR); | |
844 | ||
845 | apic_write(APIC_LVTERR, apic_val | APIC_LVT_MASKED); | |
846 | if (nmi) | |
847 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
848 | else | |
849 | apic_write(APIC_LVTPC, LOCAL_PERF_VECTOR); | |
850 | apic_write(APIC_LVTERR, apic_val); | |
851 | } | |
852 | ||
853 | static int __kprobes | |
854 | perf_counter_nmi_handler(struct notifier_block *self, | |
855 | unsigned long cmd, void *__args) | |
856 | { | |
857 | struct die_args *args = __args; | |
858 | struct pt_regs *regs; | |
b0f3f28e PZ |
859 | int ret; |
860 | ||
861 | switch (cmd) { | |
862 | case DIE_NMI: | |
863 | case DIE_NMI_IPI: | |
864 | break; | |
241771ef | 865 | |
b0f3f28e | 866 | default: |
241771ef | 867 | return NOTIFY_DONE; |
b0f3f28e | 868 | } |
241771ef IM |
869 | |
870 | regs = args->regs; | |
871 | ||
872 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
4a06bd85 | 873 | ret = x86_pmu.handle_irq(regs, 1); |
241771ef | 874 | |
b0f3f28e | 875 | return ret ? NOTIFY_STOP : NOTIFY_OK; |
241771ef IM |
876 | } |
877 | ||
878 | static __read_mostly struct notifier_block perf_counter_nmi_notifier = { | |
5b75af0a MG |
879 | .notifier_call = perf_counter_nmi_handler, |
880 | .next = NULL, | |
881 | .priority = 1 | |
241771ef IM |
882 | }; |
883 | ||
5f4ec28f | 884 | static struct x86_pmu intel_pmu = { |
faa28ae0 | 885 | .name = "Intel", |
39d81eab | 886 | .handle_irq = intel_pmu_handle_irq, |
5f4ec28f RR |
887 | .save_disable_all = intel_pmu_save_disable_all, |
888 | .restore_all = intel_pmu_restore_all, | |
5f4ec28f RR |
889 | .enable = intel_pmu_enable_counter, |
890 | .disable = intel_pmu_disable_counter, | |
b56a3802 JSR |
891 | .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, |
892 | .perfctr = MSR_ARCH_PERFMON_PERFCTR0, | |
5f4ec28f RR |
893 | .event_map = intel_pmu_event_map, |
894 | .raw_event = intel_pmu_raw_event, | |
b56a3802 JSR |
895 | .max_events = ARRAY_SIZE(intel_perfmon_event_map), |
896 | }; | |
897 | ||
5f4ec28f | 898 | static struct x86_pmu amd_pmu = { |
faa28ae0 | 899 | .name = "AMD", |
39d81eab | 900 | .handle_irq = amd_pmu_handle_irq, |
5f4ec28f RR |
901 | .save_disable_all = amd_pmu_save_disable_all, |
902 | .restore_all = amd_pmu_restore_all, | |
5f4ec28f RR |
903 | .enable = amd_pmu_enable_counter, |
904 | .disable = amd_pmu_disable_counter, | |
f87ad35d JSR |
905 | .eventsel = MSR_K7_EVNTSEL0, |
906 | .perfctr = MSR_K7_PERFCTR0, | |
5f4ec28f RR |
907 | .event_map = amd_pmu_event_map, |
908 | .raw_event = amd_pmu_raw_event, | |
f87ad35d | 909 | .max_events = ARRAY_SIZE(amd_perfmon_event_map), |
0933e5c6 RR |
910 | .num_counters = 4, |
911 | .counter_bits = 48, | |
912 | .counter_mask = (1ULL << 48) - 1, | |
f87ad35d JSR |
913 | }; |
914 | ||
72eae04d | 915 | static int intel_pmu_init(void) |
241771ef | 916 | { |
7bb497bd | 917 | union cpuid10_edx edx; |
241771ef | 918 | union cpuid10_eax eax; |
703e937c | 919 | unsigned int unused; |
7bb497bd | 920 | unsigned int ebx; |
faa28ae0 | 921 | int version; |
241771ef | 922 | |
da1a776b | 923 | if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) |
72eae04d | 924 | return -ENODEV; |
da1a776b | 925 | |
241771ef IM |
926 | /* |
927 | * Check whether the Architectural PerfMon supports | |
928 | * Branch Misses Retired Event or not. | |
929 | */ | |
703e937c | 930 | cpuid(10, &eax.full, &ebx, &unused, &edx.full); |
241771ef | 931 | if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED) |
72eae04d | 932 | return -ENODEV; |
241771ef | 933 | |
faa28ae0 RR |
934 | version = eax.split.version_id; |
935 | if (version < 2) | |
72eae04d | 936 | return -ENODEV; |
7bb497bd | 937 | |
4a06bd85 | 938 | x86_pmu = intel_pmu; |
faa28ae0 | 939 | x86_pmu.version = version; |
0933e5c6 RR |
940 | x86_pmu.num_counters = eax.split.num_counters; |
941 | x86_pmu.num_counters_fixed = edx.split.num_counters_fixed; | |
942 | x86_pmu.counter_bits = eax.split.bit_width; | |
943 | x86_pmu.counter_mask = (1ULL << eax.split.bit_width) - 1; | |
b56a3802 | 944 | |
72eae04d | 945 | return 0; |
b56a3802 JSR |
946 | } |
947 | ||
72eae04d | 948 | static int amd_pmu_init(void) |
f87ad35d | 949 | { |
4a06bd85 | 950 | x86_pmu = amd_pmu; |
72eae04d | 951 | return 0; |
f87ad35d JSR |
952 | } |
953 | ||
b56a3802 JSR |
954 | void __init init_hw_perf_counters(void) |
955 | { | |
72eae04d RR |
956 | int err; |
957 | ||
b56a3802 JSR |
958 | switch (boot_cpu_data.x86_vendor) { |
959 | case X86_VENDOR_INTEL: | |
72eae04d | 960 | err = intel_pmu_init(); |
b56a3802 | 961 | break; |
f87ad35d | 962 | case X86_VENDOR_AMD: |
72eae04d | 963 | err = amd_pmu_init(); |
f87ad35d | 964 | break; |
4138960a RR |
965 | default: |
966 | return; | |
b56a3802 | 967 | } |
72eae04d | 968 | if (err != 0) |
b56a3802 JSR |
969 | return; |
970 | ||
faa28ae0 RR |
971 | pr_info("%s Performance Monitoring support detected.\n", x86_pmu.name); |
972 | pr_info("... version: %d\n", x86_pmu.version); | |
973 | pr_info("... bit width: %d\n", x86_pmu.counter_bits); | |
974 | ||
0933e5c6 RR |
975 | pr_info("... num counters: %d\n", x86_pmu.num_counters); |
976 | if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) { | |
977 | x86_pmu.num_counters = X86_PMC_MAX_GENERIC; | |
241771ef | 978 | WARN(1, KERN_ERR "hw perf counters %d > max(%d), clipping!", |
0933e5c6 | 979 | x86_pmu.num_counters, X86_PMC_MAX_GENERIC); |
241771ef | 980 | } |
0933e5c6 RR |
981 | perf_counter_mask = (1 << x86_pmu.num_counters) - 1; |
982 | perf_max_counters = x86_pmu.num_counters; | |
241771ef | 983 | |
0933e5c6 | 984 | pr_info("... value mask: %016Lx\n", x86_pmu.counter_mask); |
2f18d1e8 | 985 | |
0933e5c6 RR |
986 | if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) { |
987 | x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED; | |
703e937c | 988 | WARN(1, KERN_ERR "hw perf counters fixed %d > max(%d), clipping!", |
0933e5c6 | 989 | x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED); |
703e937c | 990 | } |
0933e5c6 | 991 | pr_info("... fixed counters: %d\n", x86_pmu.num_counters_fixed); |
862a1a5f | 992 | |
0933e5c6 RR |
993 | perf_counter_mask |= |
994 | ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED; | |
241771ef | 995 | |
a1ef58f4 | 996 | pr_info("... counter mask: %016Lx\n", perf_counter_mask); |
75f224cf IM |
997 | perf_counters_initialized = true; |
998 | ||
241771ef IM |
999 | perf_counters_lapic_init(0); |
1000 | register_die_notifier(&perf_counter_nmi_notifier); | |
241771ef | 1001 | } |
621a01ea | 1002 | |
bb775fc2 | 1003 | static inline void x86_pmu_read(struct perf_counter *counter) |
ee06094f IM |
1004 | { |
1005 | x86_perf_counter_update(counter, &counter->hw, counter->hw.idx); | |
1006 | } | |
1007 | ||
4aeb0b42 RR |
1008 | static const struct pmu pmu = { |
1009 | .enable = x86_pmu_enable, | |
1010 | .disable = x86_pmu_disable, | |
1011 | .read = x86_pmu_read, | |
621a01ea IM |
1012 | }; |
1013 | ||
4aeb0b42 | 1014 | const struct pmu *hw_perf_counter_init(struct perf_counter *counter) |
621a01ea IM |
1015 | { |
1016 | int err; | |
1017 | ||
1018 | err = __hw_perf_counter_init(counter); | |
1019 | if (err) | |
9ea98e19 | 1020 | return ERR_PTR(err); |
621a01ea | 1021 | |
4aeb0b42 | 1022 | return &pmu; |
621a01ea | 1023 | } |
d7d59fb3 PZ |
1024 | |
1025 | /* | |
1026 | * callchain support | |
1027 | */ | |
1028 | ||
1029 | static inline | |
1030 | void callchain_store(struct perf_callchain_entry *entry, unsigned long ip) | |
1031 | { | |
1032 | if (entry->nr < MAX_STACK_DEPTH) | |
1033 | entry->ip[entry->nr++] = ip; | |
1034 | } | |
1035 | ||
1036 | static DEFINE_PER_CPU(struct perf_callchain_entry, irq_entry); | |
1037 | static DEFINE_PER_CPU(struct perf_callchain_entry, nmi_entry); | |
1038 | ||
1039 | ||
1040 | static void | |
1041 | backtrace_warning_symbol(void *data, char *msg, unsigned long symbol) | |
1042 | { | |
1043 | /* Ignore warnings */ | |
1044 | } | |
1045 | ||
1046 | static void backtrace_warning(void *data, char *msg) | |
1047 | { | |
1048 | /* Ignore warnings */ | |
1049 | } | |
1050 | ||
1051 | static int backtrace_stack(void *data, char *name) | |
1052 | { | |
1053 | /* Don't bother with IRQ stacks for now */ | |
1054 | return -1; | |
1055 | } | |
1056 | ||
1057 | static void backtrace_address(void *data, unsigned long addr, int reliable) | |
1058 | { | |
1059 | struct perf_callchain_entry *entry = data; | |
1060 | ||
1061 | if (reliable) | |
1062 | callchain_store(entry, addr); | |
1063 | } | |
1064 | ||
1065 | static const struct stacktrace_ops backtrace_ops = { | |
1066 | .warning = backtrace_warning, | |
1067 | .warning_symbol = backtrace_warning_symbol, | |
1068 | .stack = backtrace_stack, | |
1069 | .address = backtrace_address, | |
1070 | }; | |
1071 | ||
1072 | static void | |
1073 | perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1074 | { | |
1075 | unsigned long bp; | |
1076 | char *stack; | |
5872bdb8 | 1077 | int nr = entry->nr; |
d7d59fb3 PZ |
1078 | |
1079 | callchain_store(entry, instruction_pointer(regs)); | |
1080 | ||
1081 | stack = ((char *)regs + sizeof(struct pt_regs)); | |
1082 | #ifdef CONFIG_FRAME_POINTER | |
1083 | bp = frame_pointer(regs); | |
1084 | #else | |
1085 | bp = 0; | |
1086 | #endif | |
1087 | ||
1088 | dump_trace(NULL, regs, (void *)stack, bp, &backtrace_ops, entry); | |
5872bdb8 PZ |
1089 | |
1090 | entry->kernel = entry->nr - nr; | |
d7d59fb3 PZ |
1091 | } |
1092 | ||
1093 | ||
1094 | struct stack_frame { | |
1095 | const void __user *next_fp; | |
1096 | unsigned long return_address; | |
1097 | }; | |
1098 | ||
1099 | static int copy_stack_frame(const void __user *fp, struct stack_frame *frame) | |
1100 | { | |
1101 | int ret; | |
1102 | ||
1103 | if (!access_ok(VERIFY_READ, fp, sizeof(*frame))) | |
1104 | return 0; | |
1105 | ||
1106 | ret = 1; | |
1107 | pagefault_disable(); | |
1108 | if (__copy_from_user_inatomic(frame, fp, sizeof(*frame))) | |
1109 | ret = 0; | |
1110 | pagefault_enable(); | |
1111 | ||
1112 | return ret; | |
1113 | } | |
1114 | ||
1115 | static void | |
1116 | perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1117 | { | |
1118 | struct stack_frame frame; | |
1119 | const void __user *fp; | |
5872bdb8 | 1120 | int nr = entry->nr; |
d7d59fb3 PZ |
1121 | |
1122 | regs = (struct pt_regs *)current->thread.sp0 - 1; | |
1123 | fp = (void __user *)regs->bp; | |
1124 | ||
1125 | callchain_store(entry, regs->ip); | |
1126 | ||
1127 | while (entry->nr < MAX_STACK_DEPTH) { | |
1128 | frame.next_fp = NULL; | |
1129 | frame.return_address = 0; | |
1130 | ||
1131 | if (!copy_stack_frame(fp, &frame)) | |
1132 | break; | |
1133 | ||
1134 | if ((unsigned long)fp < user_stack_pointer(regs)) | |
1135 | break; | |
1136 | ||
1137 | callchain_store(entry, frame.return_address); | |
1138 | fp = frame.next_fp; | |
1139 | } | |
5872bdb8 PZ |
1140 | |
1141 | entry->user = entry->nr - nr; | |
d7d59fb3 PZ |
1142 | } |
1143 | ||
1144 | static void | |
1145 | perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1146 | { | |
1147 | int is_user; | |
1148 | ||
1149 | if (!regs) | |
1150 | return; | |
1151 | ||
1152 | is_user = user_mode(regs); | |
1153 | ||
1154 | if (!current || current->pid == 0) | |
1155 | return; | |
1156 | ||
1157 | if (is_user && current->state != TASK_RUNNING) | |
1158 | return; | |
1159 | ||
1160 | if (!is_user) | |
1161 | perf_callchain_kernel(regs, entry); | |
1162 | ||
1163 | if (current->mm) | |
1164 | perf_callchain_user(regs, entry); | |
1165 | } | |
1166 | ||
1167 | struct perf_callchain_entry *perf_callchain(struct pt_regs *regs) | |
1168 | { | |
1169 | struct perf_callchain_entry *entry; | |
1170 | ||
1171 | if (in_nmi()) | |
1172 | entry = &__get_cpu_var(nmi_entry); | |
1173 | else | |
1174 | entry = &__get_cpu_var(irq_entry); | |
1175 | ||
1176 | entry->nr = 0; | |
5872bdb8 PZ |
1177 | entry->hv = 0; |
1178 | entry->kernel = 0; | |
1179 | entry->user = 0; | |
d7d59fb3 PZ |
1180 | |
1181 | perf_do_callchain(regs, entry); | |
1182 | ||
1183 | return entry; | |
1184 | } |