Commit | Line | Data |
---|---|---|
241771ef IM |
1 | /* |
2 | * Performance counter x86 architecture code | |
3 | * | |
4 | * Copyright(C) 2008 Thomas Gleixner <tglx@linutronix.de> | |
5 | * Copyright(C) 2008 Red Hat, Inc., Ingo Molnar | |
b56a3802 | 6 | * Copyright(C) 2009 Jaswinder Singh Rajput |
241771ef IM |
7 | * |
8 | * For licencing details see kernel-base/COPYING | |
9 | */ | |
10 | ||
11 | #include <linux/perf_counter.h> | |
12 | #include <linux/capability.h> | |
13 | #include <linux/notifier.h> | |
14 | #include <linux/hardirq.h> | |
15 | #include <linux/kprobes.h> | |
4ac13294 | 16 | #include <linux/module.h> |
241771ef IM |
17 | #include <linux/kdebug.h> |
18 | #include <linux/sched.h> | |
d7d59fb3 | 19 | #include <linux/uaccess.h> |
241771ef | 20 | |
241771ef | 21 | #include <asm/apic.h> |
d7d59fb3 | 22 | #include <asm/stacktrace.h> |
4e935e47 | 23 | #include <asm/nmi.h> |
241771ef IM |
24 | |
25 | static bool perf_counters_initialized __read_mostly; | |
26 | ||
27 | /* | |
28 | * Number of (generic) HW counters: | |
29 | */ | |
862a1a5f IM |
30 | static int nr_counters_generic __read_mostly; |
31 | static u64 perf_counter_mask __read_mostly; | |
2f18d1e8 | 32 | static u64 counter_value_mask __read_mostly; |
b0f3f28e | 33 | static int counter_value_bits __read_mostly; |
241771ef | 34 | |
862a1a5f | 35 | static int nr_counters_fixed __read_mostly; |
703e937c | 36 | |
241771ef | 37 | struct cpu_hw_counters { |
862a1a5f IM |
38 | struct perf_counter *counters[X86_PMC_IDX_MAX]; |
39 | unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
4b39fd96 | 40 | unsigned long interrupts; |
b0f3f28e | 41 | u64 throttle_ctrl; |
184fe4ab | 42 | unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
b0f3f28e | 43 | int enabled; |
241771ef IM |
44 | }; |
45 | ||
46 | /* | |
b56a3802 | 47 | * struct pmc_x86_ops - performance counter x86 ops |
241771ef | 48 | */ |
b56a3802 | 49 | struct pmc_x86_ops { |
169e41eb | 50 | u64 (*save_disable_all)(void); |
b0f3f28e PZ |
51 | void (*restore_all)(u64); |
52 | u64 (*get_status)(u64); | |
53 | void (*ack_status)(u64); | |
54 | void (*enable)(int, u64); | |
55 | void (*disable)(int, u64); | |
169e41eb JSR |
56 | unsigned eventsel; |
57 | unsigned perfctr; | |
b0f3f28e PZ |
58 | u64 (*event_map)(int); |
59 | u64 (*raw_event)(u64); | |
169e41eb | 60 | int max_events; |
b56a3802 JSR |
61 | }; |
62 | ||
7bb497bd | 63 | static struct pmc_x86_ops *pmc_ops __read_mostly; |
b56a3802 | 64 | |
b0f3f28e PZ |
65 | static DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters) = { |
66 | .enabled = 1, | |
67 | }; | |
241771ef | 68 | |
7bb497bd IM |
69 | static __read_mostly int intel_perfmon_version; |
70 | ||
b56a3802 JSR |
71 | /* |
72 | * Intel PerfMon v3. Used on Core2 and later. | |
73 | */ | |
b0f3f28e | 74 | static const u64 intel_perfmon_event_map[] = |
241771ef | 75 | { |
f650a672 | 76 | [PERF_COUNT_CPU_CYCLES] = 0x003c, |
241771ef IM |
77 | [PERF_COUNT_INSTRUCTIONS] = 0x00c0, |
78 | [PERF_COUNT_CACHE_REFERENCES] = 0x4f2e, | |
79 | [PERF_COUNT_CACHE_MISSES] = 0x412e, | |
80 | [PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x00c4, | |
81 | [PERF_COUNT_BRANCH_MISSES] = 0x00c5, | |
f650a672 | 82 | [PERF_COUNT_BUS_CYCLES] = 0x013c, |
241771ef IM |
83 | }; |
84 | ||
b0f3f28e | 85 | static u64 pmc_intel_event_map(int event) |
b56a3802 JSR |
86 | { |
87 | return intel_perfmon_event_map[event]; | |
88 | } | |
241771ef | 89 | |
b0f3f28e PZ |
90 | static u64 pmc_intel_raw_event(u64 event) |
91 | { | |
82bae4f8 PZ |
92 | #define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL |
93 | #define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL | |
94 | #define CORE_EVNTSEL_COUNTER_MASK 0xFF000000ULL | |
b0f3f28e PZ |
95 | |
96 | #define CORE_EVNTSEL_MASK \ | |
97 | (CORE_EVNTSEL_EVENT_MASK | \ | |
98 | CORE_EVNTSEL_UNIT_MASK | \ | |
99 | CORE_EVNTSEL_COUNTER_MASK) | |
100 | ||
101 | return event & CORE_EVNTSEL_MASK; | |
102 | } | |
103 | ||
f87ad35d JSR |
104 | /* |
105 | * AMD Performance Monitor K7 and later. | |
106 | */ | |
b0f3f28e | 107 | static const u64 amd_perfmon_event_map[] = |
f87ad35d JSR |
108 | { |
109 | [PERF_COUNT_CPU_CYCLES] = 0x0076, | |
110 | [PERF_COUNT_INSTRUCTIONS] = 0x00c0, | |
111 | [PERF_COUNT_CACHE_REFERENCES] = 0x0080, | |
112 | [PERF_COUNT_CACHE_MISSES] = 0x0081, | |
113 | [PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x00c4, | |
114 | [PERF_COUNT_BRANCH_MISSES] = 0x00c5, | |
115 | }; | |
116 | ||
b0f3f28e | 117 | static u64 pmc_amd_event_map(int event) |
f87ad35d JSR |
118 | { |
119 | return amd_perfmon_event_map[event]; | |
120 | } | |
121 | ||
b0f3f28e PZ |
122 | static u64 pmc_amd_raw_event(u64 event) |
123 | { | |
82bae4f8 PZ |
124 | #define K7_EVNTSEL_EVENT_MASK 0x7000000FFULL |
125 | #define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL | |
126 | #define K7_EVNTSEL_COUNTER_MASK 0x0FF000000ULL | |
b0f3f28e PZ |
127 | |
128 | #define K7_EVNTSEL_MASK \ | |
129 | (K7_EVNTSEL_EVENT_MASK | \ | |
130 | K7_EVNTSEL_UNIT_MASK | \ | |
131 | K7_EVNTSEL_COUNTER_MASK) | |
132 | ||
133 | return event & K7_EVNTSEL_MASK; | |
134 | } | |
135 | ||
ee06094f IM |
136 | /* |
137 | * Propagate counter elapsed time into the generic counter. | |
138 | * Can only be executed on the CPU where the counter is active. | |
139 | * Returns the delta events processed. | |
140 | */ | |
141 | static void | |
142 | x86_perf_counter_update(struct perf_counter *counter, | |
143 | struct hw_perf_counter *hwc, int idx) | |
144 | { | |
145 | u64 prev_raw_count, new_raw_count, delta; | |
146 | ||
ee06094f IM |
147 | /* |
148 | * Careful: an NMI might modify the previous counter value. | |
149 | * | |
150 | * Our tactic to handle this is to first atomically read and | |
151 | * exchange a new raw count - then add that new-prev delta | |
152 | * count to the generic counter atomically: | |
153 | */ | |
154 | again: | |
155 | prev_raw_count = atomic64_read(&hwc->prev_count); | |
156 | rdmsrl(hwc->counter_base + idx, new_raw_count); | |
157 | ||
158 | if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count, | |
159 | new_raw_count) != prev_raw_count) | |
160 | goto again; | |
161 | ||
162 | /* | |
163 | * Now we have the new raw value and have updated the prev | |
164 | * timestamp already. We can now calculate the elapsed delta | |
165 | * (counter-)time and add that to the generic counter. | |
166 | * | |
167 | * Careful, not all hw sign-extends above the physical width | |
168 | * of the count, so we do that by clipping the delta to 32 bits: | |
169 | */ | |
170 | delta = (u64)(u32)((s32)new_raw_count - (s32)prev_raw_count); | |
ee06094f IM |
171 | |
172 | atomic64_add(delta, &counter->count); | |
173 | atomic64_sub(delta, &hwc->period_left); | |
174 | } | |
175 | ||
4e935e47 PZ |
176 | static atomic_t num_counters; |
177 | static DEFINE_MUTEX(pmc_reserve_mutex); | |
178 | ||
179 | static bool reserve_pmc_hardware(void) | |
180 | { | |
181 | int i; | |
182 | ||
183 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
184 | disable_lapic_nmi_watchdog(); | |
185 | ||
186 | for (i = 0; i < nr_counters_generic; i++) { | |
187 | if (!reserve_perfctr_nmi(pmc_ops->perfctr + i)) | |
188 | goto perfctr_fail; | |
189 | } | |
190 | ||
191 | for (i = 0; i < nr_counters_generic; i++) { | |
192 | if (!reserve_evntsel_nmi(pmc_ops->eventsel + i)) | |
193 | goto eventsel_fail; | |
194 | } | |
195 | ||
196 | return true; | |
197 | ||
198 | eventsel_fail: | |
199 | for (i--; i >= 0; i--) | |
200 | release_evntsel_nmi(pmc_ops->eventsel + i); | |
201 | ||
202 | i = nr_counters_generic; | |
203 | ||
204 | perfctr_fail: | |
205 | for (i--; i >= 0; i--) | |
206 | release_perfctr_nmi(pmc_ops->perfctr + i); | |
207 | ||
208 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
209 | enable_lapic_nmi_watchdog(); | |
210 | ||
211 | return false; | |
212 | } | |
213 | ||
214 | static void release_pmc_hardware(void) | |
215 | { | |
216 | int i; | |
217 | ||
218 | for (i = 0; i < nr_counters_generic; i++) { | |
219 | release_perfctr_nmi(pmc_ops->perfctr + i); | |
220 | release_evntsel_nmi(pmc_ops->eventsel + i); | |
221 | } | |
222 | ||
223 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
224 | enable_lapic_nmi_watchdog(); | |
225 | } | |
226 | ||
227 | static void hw_perf_counter_destroy(struct perf_counter *counter) | |
228 | { | |
229 | if (atomic_dec_and_mutex_lock(&num_counters, &pmc_reserve_mutex)) { | |
230 | release_pmc_hardware(); | |
231 | mutex_unlock(&pmc_reserve_mutex); | |
232 | } | |
233 | } | |
234 | ||
241771ef IM |
235 | /* |
236 | * Setup the hardware configuration for a given hw_event_type | |
237 | */ | |
621a01ea | 238 | static int __hw_perf_counter_init(struct perf_counter *counter) |
241771ef | 239 | { |
9f66a381 | 240 | struct perf_counter_hw_event *hw_event = &counter->hw_event; |
241771ef | 241 | struct hw_perf_counter *hwc = &counter->hw; |
4e935e47 | 242 | int err; |
241771ef IM |
243 | |
244 | if (unlikely(!perf_counters_initialized)) | |
245 | return -EINVAL; | |
246 | ||
4e935e47 PZ |
247 | err = 0; |
248 | if (atomic_inc_not_zero(&num_counters)) { | |
249 | mutex_lock(&pmc_reserve_mutex); | |
250 | if (atomic_read(&num_counters) == 0 && !reserve_pmc_hardware()) | |
251 | err = -EBUSY; | |
252 | else | |
253 | atomic_inc(&num_counters); | |
254 | mutex_unlock(&pmc_reserve_mutex); | |
255 | } | |
256 | if (err) | |
257 | return err; | |
258 | ||
241771ef | 259 | /* |
0475f9ea | 260 | * Generate PMC IRQs: |
241771ef IM |
261 | * (keep 'enabled' bit clear for now) |
262 | */ | |
0475f9ea | 263 | hwc->config = ARCH_PERFMON_EVENTSEL_INT; |
241771ef IM |
264 | |
265 | /* | |
0475f9ea | 266 | * Count user and OS events unless requested not to. |
241771ef | 267 | */ |
0475f9ea PM |
268 | if (!hw_event->exclude_user) |
269 | hwc->config |= ARCH_PERFMON_EVENTSEL_USR; | |
270 | if (!hw_event->exclude_kernel) | |
241771ef | 271 | hwc->config |= ARCH_PERFMON_EVENTSEL_OS; |
0475f9ea PM |
272 | |
273 | /* | |
274 | * If privileged enough, allow NMI events: | |
275 | */ | |
276 | hwc->nmi = 0; | |
277 | if (capable(CAP_SYS_ADMIN) && hw_event->nmi) | |
278 | hwc->nmi = 1; | |
241771ef | 279 | |
9f66a381 | 280 | hwc->irq_period = hw_event->irq_period; |
241771ef IM |
281 | /* |
282 | * Intel PMCs cannot be accessed sanely above 32 bit width, | |
283 | * so we install an artificial 1<<31 period regardless of | |
284 | * the generic counter period: | |
285 | */ | |
f87ad35d JSR |
286 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
287 | if ((s64)hwc->irq_period <= 0 || hwc->irq_period > 0x7FFFFFFF) | |
288 | hwc->irq_period = 0x7FFFFFFF; | |
241771ef | 289 | |
ee06094f | 290 | atomic64_set(&hwc->period_left, hwc->irq_period); |
241771ef IM |
291 | |
292 | /* | |
dfa7c899 | 293 | * Raw event type provide the config in the event structure |
241771ef | 294 | */ |
f4a2deb4 PZ |
295 | if (perf_event_raw(hw_event)) { |
296 | hwc->config |= pmc_ops->raw_event(perf_event_config(hw_event)); | |
241771ef | 297 | } else { |
f4a2deb4 | 298 | if (perf_event_id(hw_event) >= pmc_ops->max_events) |
241771ef IM |
299 | return -EINVAL; |
300 | /* | |
301 | * The generic map: | |
302 | */ | |
f4a2deb4 | 303 | hwc->config |= pmc_ops->event_map(perf_event_id(hw_event)); |
241771ef | 304 | } |
241771ef | 305 | |
4e935e47 PZ |
306 | counter->destroy = hw_perf_counter_destroy; |
307 | ||
241771ef IM |
308 | return 0; |
309 | } | |
310 | ||
b56a3802 | 311 | static u64 pmc_intel_save_disable_all(void) |
4ac13294 TG |
312 | { |
313 | u64 ctrl; | |
314 | ||
315 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); | |
862a1a5f | 316 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); |
2b9ff0db | 317 | |
4ac13294 | 318 | return ctrl; |
241771ef | 319 | } |
b56a3802 | 320 | |
f87ad35d JSR |
321 | static u64 pmc_amd_save_disable_all(void) |
322 | { | |
b0f3f28e PZ |
323 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); |
324 | int enabled, idx; | |
325 | ||
326 | enabled = cpuc->enabled; | |
327 | cpuc->enabled = 0; | |
60b3df9c PZ |
328 | /* |
329 | * ensure we write the disable before we start disabling the | |
330 | * counters proper, so that pcm_amd_enable() does the right thing. | |
331 | */ | |
b0f3f28e | 332 | barrier(); |
f87ad35d JSR |
333 | |
334 | for (idx = 0; idx < nr_counters_generic; idx++) { | |
b0f3f28e PZ |
335 | u64 val; |
336 | ||
f87ad35d | 337 | rdmsrl(MSR_K7_EVNTSEL0 + idx, val); |
b0f3f28e PZ |
338 | if (val & ARCH_PERFMON_EVENTSEL0_ENABLE) { |
339 | val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE; | |
340 | wrmsrl(MSR_K7_EVNTSEL0 + idx, val); | |
341 | } | |
f87ad35d JSR |
342 | } |
343 | ||
b0f3f28e | 344 | return enabled; |
f87ad35d JSR |
345 | } |
346 | ||
b56a3802 JSR |
347 | u64 hw_perf_save_disable(void) |
348 | { | |
349 | if (unlikely(!perf_counters_initialized)) | |
350 | return 0; | |
351 | ||
352 | return pmc_ops->save_disable_all(); | |
353 | } | |
b0f3f28e PZ |
354 | /* |
355 | * Exported because of ACPI idle | |
356 | */ | |
01b2838c | 357 | EXPORT_SYMBOL_GPL(hw_perf_save_disable); |
241771ef | 358 | |
b56a3802 JSR |
359 | static void pmc_intel_restore_all(u64 ctrl) |
360 | { | |
361 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); | |
362 | } | |
363 | ||
f87ad35d JSR |
364 | static void pmc_amd_restore_all(u64 ctrl) |
365 | { | |
b0f3f28e | 366 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); |
f87ad35d JSR |
367 | int idx; |
368 | ||
b0f3f28e PZ |
369 | cpuc->enabled = ctrl; |
370 | barrier(); | |
371 | if (!ctrl) | |
372 | return; | |
373 | ||
f87ad35d | 374 | for (idx = 0; idx < nr_counters_generic; idx++) { |
184fe4ab | 375 | if (test_bit(idx, cpuc->active_mask)) { |
b0f3f28e PZ |
376 | u64 val; |
377 | ||
f87ad35d JSR |
378 | rdmsrl(MSR_K7_EVNTSEL0 + idx, val); |
379 | val |= ARCH_PERFMON_EVENTSEL0_ENABLE; | |
380 | wrmsrl(MSR_K7_EVNTSEL0 + idx, val); | |
381 | } | |
382 | } | |
383 | } | |
384 | ||
ee06094f IM |
385 | void hw_perf_restore(u64 ctrl) |
386 | { | |
2b9ff0db IM |
387 | if (unlikely(!perf_counters_initialized)) |
388 | return; | |
389 | ||
b56a3802 | 390 | pmc_ops->restore_all(ctrl); |
ee06094f | 391 | } |
b0f3f28e PZ |
392 | /* |
393 | * Exported because of ACPI idle | |
394 | */ | |
ee06094f IM |
395 | EXPORT_SYMBOL_GPL(hw_perf_restore); |
396 | ||
b0f3f28e PZ |
397 | static u64 pmc_intel_get_status(u64 mask) |
398 | { | |
399 | u64 status; | |
400 | ||
401 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
402 | ||
403 | return status; | |
404 | } | |
405 | ||
406 | static u64 pmc_amd_get_status(u64 mask) | |
407 | { | |
408 | u64 status = 0; | |
409 | int idx; | |
410 | ||
411 | for (idx = 0; idx < nr_counters_generic; idx++) { | |
412 | s64 val; | |
413 | ||
414 | if (!(mask & (1 << idx))) | |
415 | continue; | |
416 | ||
417 | rdmsrl(MSR_K7_PERFCTR0 + idx, val); | |
418 | val <<= (64 - counter_value_bits); | |
419 | if (val >= 0) | |
420 | status |= (1 << idx); | |
421 | } | |
422 | ||
423 | return status; | |
424 | } | |
425 | ||
426 | static u64 hw_perf_get_status(u64 mask) | |
427 | { | |
428 | if (unlikely(!perf_counters_initialized)) | |
429 | return 0; | |
430 | ||
431 | return pmc_ops->get_status(mask); | |
432 | } | |
433 | ||
434 | static void pmc_intel_ack_status(u64 ack) | |
435 | { | |
436 | wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); | |
437 | } | |
438 | ||
439 | static void pmc_amd_ack_status(u64 ack) | |
440 | { | |
441 | } | |
442 | ||
443 | static void hw_perf_ack_status(u64 ack) | |
444 | { | |
445 | if (unlikely(!perf_counters_initialized)) | |
446 | return; | |
447 | ||
448 | pmc_ops->ack_status(ack); | |
449 | } | |
450 | ||
451 | static void pmc_intel_enable(int idx, u64 config) | |
452 | { | |
453 | wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + idx, | |
454 | config | ARCH_PERFMON_EVENTSEL0_ENABLE); | |
455 | } | |
456 | ||
457 | static void pmc_amd_enable(int idx, u64 config) | |
458 | { | |
459 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
460 | ||
184fe4ab | 461 | set_bit(idx, cpuc->active_mask); |
b0f3f28e PZ |
462 | if (cpuc->enabled) |
463 | config |= ARCH_PERFMON_EVENTSEL0_ENABLE; | |
464 | ||
465 | wrmsrl(MSR_K7_EVNTSEL0 + idx, config); | |
466 | } | |
467 | ||
468 | static void hw_perf_enable(int idx, u64 config) | |
469 | { | |
470 | if (unlikely(!perf_counters_initialized)) | |
471 | return; | |
472 | ||
473 | pmc_ops->enable(idx, config); | |
474 | } | |
475 | ||
476 | static void pmc_intel_disable(int idx, u64 config) | |
477 | { | |
478 | wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + idx, config); | |
479 | } | |
480 | ||
481 | static void pmc_amd_disable(int idx, u64 config) | |
482 | { | |
483 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
484 | ||
184fe4ab | 485 | clear_bit(idx, cpuc->active_mask); |
b0f3f28e PZ |
486 | wrmsrl(MSR_K7_EVNTSEL0 + idx, config); |
487 | ||
488 | } | |
489 | ||
490 | static void hw_perf_disable(int idx, u64 config) | |
491 | { | |
492 | if (unlikely(!perf_counters_initialized)) | |
493 | return; | |
494 | ||
495 | pmc_ops->disable(idx, config); | |
496 | } | |
497 | ||
2f18d1e8 IM |
498 | static inline void |
499 | __pmc_fixed_disable(struct perf_counter *counter, | |
500 | struct hw_perf_counter *hwc, unsigned int __idx) | |
501 | { | |
502 | int idx = __idx - X86_PMC_IDX_FIXED; | |
503 | u64 ctrl_val, mask; | |
504 | int err; | |
505 | ||
506 | mask = 0xfULL << (idx * 4); | |
507 | ||
508 | rdmsrl(hwc->config_base, ctrl_val); | |
509 | ctrl_val &= ~mask; | |
510 | err = checking_wrmsrl(hwc->config_base, ctrl_val); | |
511 | } | |
512 | ||
7e2ae347 | 513 | static inline void |
eb2b8618 | 514 | __pmc_generic_disable(struct perf_counter *counter, |
ee06094f | 515 | struct hw_perf_counter *hwc, unsigned int idx) |
7e2ae347 | 516 | { |
2f18d1e8 | 517 | if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) |
2b583d8b JSR |
518 | __pmc_fixed_disable(counter, hwc, idx); |
519 | else | |
b0f3f28e | 520 | hw_perf_disable(idx, hwc->config); |
7e2ae347 IM |
521 | } |
522 | ||
2f18d1e8 | 523 | static DEFINE_PER_CPU(u64, prev_left[X86_PMC_IDX_MAX]); |
241771ef | 524 | |
ee06094f IM |
525 | /* |
526 | * Set the next IRQ period, based on the hwc->period_left value. | |
527 | * To be called with the counter disabled in hw: | |
528 | */ | |
529 | static void | |
530 | __hw_perf_counter_set_period(struct perf_counter *counter, | |
531 | struct hw_perf_counter *hwc, int idx) | |
241771ef | 532 | { |
2f18d1e8 | 533 | s64 left = atomic64_read(&hwc->period_left); |
595258aa | 534 | s64 period = hwc->irq_period; |
2f18d1e8 | 535 | int err; |
ee06094f | 536 | |
ee06094f IM |
537 | /* |
538 | * If we are way outside a reasoable range then just skip forward: | |
539 | */ | |
540 | if (unlikely(left <= -period)) { | |
541 | left = period; | |
542 | atomic64_set(&hwc->period_left, left); | |
543 | } | |
544 | ||
545 | if (unlikely(left <= 0)) { | |
546 | left += period; | |
547 | atomic64_set(&hwc->period_left, left); | |
548 | } | |
241771ef | 549 | |
ee06094f IM |
550 | per_cpu(prev_left[idx], smp_processor_id()) = left; |
551 | ||
552 | /* | |
553 | * The hw counter starts counting from this counter offset, | |
554 | * mark it to be able to extra future deltas: | |
555 | */ | |
2f18d1e8 | 556 | atomic64_set(&hwc->prev_count, (u64)-left); |
ee06094f | 557 | |
2f18d1e8 IM |
558 | err = checking_wrmsrl(hwc->counter_base + idx, |
559 | (u64)(-left) & counter_value_mask); | |
560 | } | |
561 | ||
562 | static inline void | |
563 | __pmc_fixed_enable(struct perf_counter *counter, | |
564 | struct hw_perf_counter *hwc, unsigned int __idx) | |
565 | { | |
566 | int idx = __idx - X86_PMC_IDX_FIXED; | |
567 | u64 ctrl_val, bits, mask; | |
568 | int err; | |
569 | ||
570 | /* | |
0475f9ea PM |
571 | * Enable IRQ generation (0x8), |
572 | * and enable ring-3 counting (0x2) and ring-0 counting (0x1) | |
573 | * if requested: | |
2f18d1e8 | 574 | */ |
0475f9ea PM |
575 | bits = 0x8ULL; |
576 | if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) | |
577 | bits |= 0x2; | |
2f18d1e8 IM |
578 | if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) |
579 | bits |= 0x1; | |
580 | bits <<= (idx * 4); | |
581 | mask = 0xfULL << (idx * 4); | |
582 | ||
583 | rdmsrl(hwc->config_base, ctrl_val); | |
584 | ctrl_val &= ~mask; | |
585 | ctrl_val |= bits; | |
586 | err = checking_wrmsrl(hwc->config_base, ctrl_val); | |
7e2ae347 IM |
587 | } |
588 | ||
ee06094f | 589 | static void |
eb2b8618 | 590 | __pmc_generic_enable(struct perf_counter *counter, |
ee06094f | 591 | struct hw_perf_counter *hwc, int idx) |
7e2ae347 | 592 | { |
2f18d1e8 | 593 | if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) |
2b583d8b JSR |
594 | __pmc_fixed_enable(counter, hwc, idx); |
595 | else | |
b0f3f28e | 596 | hw_perf_enable(idx, hwc->config); |
241771ef IM |
597 | } |
598 | ||
2f18d1e8 IM |
599 | static int |
600 | fixed_mode_idx(struct perf_counter *counter, struct hw_perf_counter *hwc) | |
862a1a5f | 601 | { |
2f18d1e8 IM |
602 | unsigned int event; |
603 | ||
f87ad35d JSR |
604 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) |
605 | return -1; | |
606 | ||
2f18d1e8 IM |
607 | if (unlikely(hwc->nmi)) |
608 | return -1; | |
609 | ||
610 | event = hwc->config & ARCH_PERFMON_EVENT_MASK; | |
611 | ||
b56a3802 | 612 | if (unlikely(event == pmc_ops->event_map(PERF_COUNT_INSTRUCTIONS))) |
2f18d1e8 | 613 | return X86_PMC_IDX_FIXED_INSTRUCTIONS; |
b56a3802 | 614 | if (unlikely(event == pmc_ops->event_map(PERF_COUNT_CPU_CYCLES))) |
2f18d1e8 | 615 | return X86_PMC_IDX_FIXED_CPU_CYCLES; |
b56a3802 | 616 | if (unlikely(event == pmc_ops->event_map(PERF_COUNT_BUS_CYCLES))) |
2f18d1e8 IM |
617 | return X86_PMC_IDX_FIXED_BUS_CYCLES; |
618 | ||
862a1a5f IM |
619 | return -1; |
620 | } | |
621 | ||
ee06094f IM |
622 | /* |
623 | * Find a PMC slot for the freshly enabled / scheduled in counter: | |
624 | */ | |
95cdd2e7 | 625 | static int pmc_generic_enable(struct perf_counter *counter) |
241771ef IM |
626 | { |
627 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
628 | struct hw_perf_counter *hwc = &counter->hw; | |
2f18d1e8 | 629 | int idx; |
241771ef | 630 | |
2f18d1e8 IM |
631 | idx = fixed_mode_idx(counter, hwc); |
632 | if (idx >= 0) { | |
633 | /* | |
634 | * Try to get the fixed counter, if that is already taken | |
635 | * then try to get a generic counter: | |
636 | */ | |
637 | if (test_and_set_bit(idx, cpuc->used)) | |
638 | goto try_generic; | |
0dff86aa | 639 | |
2f18d1e8 IM |
640 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; |
641 | /* | |
642 | * We set it so that counter_base + idx in wrmsr/rdmsr maps to | |
643 | * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2: | |
644 | */ | |
645 | hwc->counter_base = | |
646 | MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED; | |
241771ef | 647 | hwc->idx = idx; |
2f18d1e8 IM |
648 | } else { |
649 | idx = hwc->idx; | |
650 | /* Try to get the previous generic counter again */ | |
651 | if (test_and_set_bit(idx, cpuc->used)) { | |
652 | try_generic: | |
653 | idx = find_first_zero_bit(cpuc->used, nr_counters_generic); | |
654 | if (idx == nr_counters_generic) | |
655 | return -EAGAIN; | |
656 | ||
657 | set_bit(idx, cpuc->used); | |
658 | hwc->idx = idx; | |
659 | } | |
b56a3802 JSR |
660 | hwc->config_base = pmc_ops->eventsel; |
661 | hwc->counter_base = pmc_ops->perfctr; | |
241771ef IM |
662 | } |
663 | ||
664 | perf_counters_lapic_init(hwc->nmi); | |
665 | ||
eb2b8618 | 666 | __pmc_generic_disable(counter, hwc, idx); |
241771ef | 667 | |
862a1a5f | 668 | cpuc->counters[idx] = counter; |
2f18d1e8 IM |
669 | /* |
670 | * Make it visible before enabling the hw: | |
671 | */ | |
672 | smp_wmb(); | |
7e2ae347 | 673 | |
ee06094f | 674 | __hw_perf_counter_set_period(counter, hwc, idx); |
eb2b8618 | 675 | __pmc_generic_enable(counter, hwc, idx); |
95cdd2e7 IM |
676 | |
677 | return 0; | |
241771ef IM |
678 | } |
679 | ||
680 | void perf_counter_print_debug(void) | |
681 | { | |
2f18d1e8 | 682 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
0dff86aa | 683 | struct cpu_hw_counters *cpuc; |
1e125676 IM |
684 | int cpu, idx; |
685 | ||
862a1a5f | 686 | if (!nr_counters_generic) |
1e125676 | 687 | return; |
241771ef IM |
688 | |
689 | local_irq_disable(); | |
690 | ||
691 | cpu = smp_processor_id(); | |
0dff86aa | 692 | cpuc = &per_cpu(cpu_hw_counters, cpu); |
241771ef | 693 | |
7bb497bd | 694 | if (intel_perfmon_version >= 2) { |
a1ef58f4 JSR |
695 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
696 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
697 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
698 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); | |
699 | ||
700 | pr_info("\n"); | |
701 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
702 | pr_info("CPU#%d: status: %016llx\n", cpu, status); | |
703 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); | |
704 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); | |
f87ad35d | 705 | } |
a1ef58f4 | 706 | pr_info("CPU#%d: used: %016llx\n", cpu, *(u64 *)cpuc->used); |
241771ef | 707 | |
862a1a5f | 708 | for (idx = 0; idx < nr_counters_generic; idx++) { |
b56a3802 JSR |
709 | rdmsrl(pmc_ops->eventsel + idx, pmc_ctrl); |
710 | rdmsrl(pmc_ops->perfctr + idx, pmc_count); | |
241771ef | 711 | |
ee06094f | 712 | prev_left = per_cpu(prev_left[idx], cpu); |
241771ef | 713 | |
a1ef58f4 | 714 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 715 | cpu, idx, pmc_ctrl); |
a1ef58f4 | 716 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 717 | cpu, idx, pmc_count); |
a1ef58f4 | 718 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 719 | cpu, idx, prev_left); |
241771ef | 720 | } |
2f18d1e8 IM |
721 | for (idx = 0; idx < nr_counters_fixed; idx++) { |
722 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); | |
723 | ||
a1ef58f4 | 724 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
2f18d1e8 IM |
725 | cpu, idx, pmc_count); |
726 | } | |
241771ef IM |
727 | local_irq_enable(); |
728 | } | |
729 | ||
eb2b8618 | 730 | static void pmc_generic_disable(struct perf_counter *counter) |
241771ef IM |
731 | { |
732 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
733 | struct hw_perf_counter *hwc = &counter->hw; | |
734 | unsigned int idx = hwc->idx; | |
735 | ||
eb2b8618 | 736 | __pmc_generic_disable(counter, hwc, idx); |
241771ef IM |
737 | |
738 | clear_bit(idx, cpuc->used); | |
862a1a5f | 739 | cpuc->counters[idx] = NULL; |
2f18d1e8 IM |
740 | /* |
741 | * Make sure the cleared pointer becomes visible before we | |
742 | * (potentially) free the counter: | |
743 | */ | |
744 | smp_wmb(); | |
241771ef | 745 | |
ee06094f IM |
746 | /* |
747 | * Drain the remaining delta count out of a counter | |
748 | * that we are disabling: | |
749 | */ | |
750 | x86_perf_counter_update(counter, hwc, idx); | |
241771ef IM |
751 | } |
752 | ||
7e2ae347 | 753 | /* |
ee06094f IM |
754 | * Save and restart an expired counter. Called by NMI contexts, |
755 | * so it has to be careful about preempting normal counter ops: | |
7e2ae347 | 756 | */ |
241771ef IM |
757 | static void perf_save_and_restart(struct perf_counter *counter) |
758 | { | |
759 | struct hw_perf_counter *hwc = &counter->hw; | |
760 | int idx = hwc->idx; | |
241771ef | 761 | |
ee06094f IM |
762 | x86_perf_counter_update(counter, hwc, idx); |
763 | __hw_perf_counter_set_period(counter, hwc, idx); | |
7e2ae347 | 764 | |
2f18d1e8 | 765 | if (counter->state == PERF_COUNTER_STATE_ACTIVE) |
eb2b8618 | 766 | __pmc_generic_enable(counter, hwc, idx); |
241771ef IM |
767 | } |
768 | ||
4b39fd96 MG |
769 | /* |
770 | * Maximum interrupt frequency of 100KHz per CPU | |
771 | */ | |
169e41eb | 772 | #define PERFMON_MAX_INTERRUPTS (100000/HZ) |
4b39fd96 | 773 | |
241771ef IM |
774 | /* |
775 | * This handler is triggered by the local APIC, so the APIC IRQ handling | |
776 | * rules apply: | |
777 | */ | |
b0f3f28e | 778 | static int __smp_perf_counter_interrupt(struct pt_regs *regs, int nmi) |
241771ef IM |
779 | { |
780 | int bit, cpu = smp_processor_id(); | |
4b39fd96 | 781 | u64 ack, status; |
1b023a96 | 782 | struct cpu_hw_counters *cpuc = &per_cpu(cpu_hw_counters, cpu); |
b0f3f28e | 783 | int ret = 0; |
43874d23 | 784 | |
b0f3f28e | 785 | cpuc->throttle_ctrl = hw_perf_save_disable(); |
241771ef | 786 | |
b0f3f28e | 787 | status = hw_perf_get_status(cpuc->throttle_ctrl); |
87b9cf46 IM |
788 | if (!status) |
789 | goto out; | |
790 | ||
b0f3f28e | 791 | ret = 1; |
241771ef | 792 | again: |
d278c484 | 793 | inc_irq_stat(apic_perf_irqs); |
241771ef | 794 | ack = status; |
2f18d1e8 | 795 | for_each_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { |
862a1a5f | 796 | struct perf_counter *counter = cpuc->counters[bit]; |
241771ef IM |
797 | |
798 | clear_bit(bit, (unsigned long *) &status); | |
799 | if (!counter) | |
800 | continue; | |
801 | ||
802 | perf_save_and_restart(counter); | |
f6c7d5fe PZ |
803 | if (perf_counter_overflow(counter, nmi, regs)) |
804 | __pmc_generic_disable(counter, &counter->hw, bit); | |
241771ef IM |
805 | } |
806 | ||
b0f3f28e | 807 | hw_perf_ack_status(ack); |
241771ef IM |
808 | |
809 | /* | |
810 | * Repeat if there is more work to be done: | |
811 | */ | |
b0f3f28e | 812 | status = hw_perf_get_status(cpuc->throttle_ctrl); |
241771ef IM |
813 | if (status) |
814 | goto again; | |
87b9cf46 | 815 | out: |
241771ef | 816 | /* |
1b023a96 | 817 | * Restore - do not reenable when global enable is off or throttled: |
241771ef | 818 | */ |
4b39fd96 | 819 | if (++cpuc->interrupts < PERFMON_MAX_INTERRUPTS) |
b0f3f28e PZ |
820 | hw_perf_restore(cpuc->throttle_ctrl); |
821 | ||
822 | return ret; | |
1b023a96 MG |
823 | } |
824 | ||
825 | void perf_counter_unthrottle(void) | |
826 | { | |
827 | struct cpu_hw_counters *cpuc; | |
828 | ||
829 | if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) | |
830 | return; | |
831 | ||
832 | if (unlikely(!perf_counters_initialized)) | |
833 | return; | |
834 | ||
b0f3f28e | 835 | cpuc = &__get_cpu_var(cpu_hw_counters); |
4b39fd96 | 836 | if (cpuc->interrupts >= PERFMON_MAX_INTERRUPTS) { |
1b023a96 | 837 | if (printk_ratelimit()) |
4b39fd96 | 838 | printk(KERN_WARNING "PERFMON: max interrupts exceeded!\n"); |
b0f3f28e | 839 | hw_perf_restore(cpuc->throttle_ctrl); |
1b023a96 | 840 | } |
4b39fd96 | 841 | cpuc->interrupts = 0; |
241771ef IM |
842 | } |
843 | ||
844 | void smp_perf_counter_interrupt(struct pt_regs *regs) | |
845 | { | |
846 | irq_enter(); | |
241771ef | 847 | apic_write(APIC_LVTPC, LOCAL_PERF_VECTOR); |
b0f3f28e | 848 | ack_APIC_irq(); |
241771ef | 849 | __smp_perf_counter_interrupt(regs, 0); |
241771ef IM |
850 | irq_exit(); |
851 | } | |
852 | ||
b6276f35 PZ |
853 | void smp_perf_pending_interrupt(struct pt_regs *regs) |
854 | { | |
855 | irq_enter(); | |
856 | ack_APIC_irq(); | |
857 | inc_irq_stat(apic_pending_irqs); | |
858 | perf_counter_do_pending(); | |
859 | irq_exit(); | |
860 | } | |
861 | ||
862 | void set_perf_counter_pending(void) | |
863 | { | |
864 | apic->send_IPI_self(LOCAL_PENDING_VECTOR); | |
865 | } | |
866 | ||
3415dd91 | 867 | void perf_counters_lapic_init(int nmi) |
241771ef IM |
868 | { |
869 | u32 apic_val; | |
870 | ||
871 | if (!perf_counters_initialized) | |
872 | return; | |
873 | /* | |
874 | * Enable the performance counter vector in the APIC LVT: | |
875 | */ | |
876 | apic_val = apic_read(APIC_LVTERR); | |
877 | ||
878 | apic_write(APIC_LVTERR, apic_val | APIC_LVT_MASKED); | |
879 | if (nmi) | |
880 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
881 | else | |
882 | apic_write(APIC_LVTPC, LOCAL_PERF_VECTOR); | |
883 | apic_write(APIC_LVTERR, apic_val); | |
884 | } | |
885 | ||
886 | static int __kprobes | |
887 | perf_counter_nmi_handler(struct notifier_block *self, | |
888 | unsigned long cmd, void *__args) | |
889 | { | |
890 | struct die_args *args = __args; | |
891 | struct pt_regs *regs; | |
b0f3f28e PZ |
892 | int ret; |
893 | ||
894 | switch (cmd) { | |
895 | case DIE_NMI: | |
896 | case DIE_NMI_IPI: | |
897 | break; | |
241771ef | 898 | |
b0f3f28e | 899 | default: |
241771ef | 900 | return NOTIFY_DONE; |
b0f3f28e | 901 | } |
241771ef IM |
902 | |
903 | regs = args->regs; | |
904 | ||
905 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
b0f3f28e | 906 | ret = __smp_perf_counter_interrupt(regs, 1); |
241771ef | 907 | |
b0f3f28e | 908 | return ret ? NOTIFY_STOP : NOTIFY_OK; |
241771ef IM |
909 | } |
910 | ||
911 | static __read_mostly struct notifier_block perf_counter_nmi_notifier = { | |
5b75af0a MG |
912 | .notifier_call = perf_counter_nmi_handler, |
913 | .next = NULL, | |
914 | .priority = 1 | |
241771ef IM |
915 | }; |
916 | ||
b56a3802 JSR |
917 | static struct pmc_x86_ops pmc_intel_ops = { |
918 | .save_disable_all = pmc_intel_save_disable_all, | |
919 | .restore_all = pmc_intel_restore_all, | |
b0f3f28e PZ |
920 | .get_status = pmc_intel_get_status, |
921 | .ack_status = pmc_intel_ack_status, | |
922 | .enable = pmc_intel_enable, | |
923 | .disable = pmc_intel_disable, | |
b56a3802 JSR |
924 | .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, |
925 | .perfctr = MSR_ARCH_PERFMON_PERFCTR0, | |
926 | .event_map = pmc_intel_event_map, | |
b0f3f28e | 927 | .raw_event = pmc_intel_raw_event, |
b56a3802 JSR |
928 | .max_events = ARRAY_SIZE(intel_perfmon_event_map), |
929 | }; | |
930 | ||
f87ad35d JSR |
931 | static struct pmc_x86_ops pmc_amd_ops = { |
932 | .save_disable_all = pmc_amd_save_disable_all, | |
933 | .restore_all = pmc_amd_restore_all, | |
b0f3f28e PZ |
934 | .get_status = pmc_amd_get_status, |
935 | .ack_status = pmc_amd_ack_status, | |
936 | .enable = pmc_amd_enable, | |
937 | .disable = pmc_amd_disable, | |
f87ad35d JSR |
938 | .eventsel = MSR_K7_EVNTSEL0, |
939 | .perfctr = MSR_K7_PERFCTR0, | |
940 | .event_map = pmc_amd_event_map, | |
b0f3f28e | 941 | .raw_event = pmc_amd_raw_event, |
f87ad35d JSR |
942 | .max_events = ARRAY_SIZE(amd_perfmon_event_map), |
943 | }; | |
944 | ||
b56a3802 | 945 | static struct pmc_x86_ops *pmc_intel_init(void) |
241771ef | 946 | { |
7bb497bd | 947 | union cpuid10_edx edx; |
241771ef | 948 | union cpuid10_eax eax; |
703e937c | 949 | unsigned int unused; |
7bb497bd | 950 | unsigned int ebx; |
241771ef | 951 | |
241771ef IM |
952 | /* |
953 | * Check whether the Architectural PerfMon supports | |
954 | * Branch Misses Retired Event or not. | |
955 | */ | |
703e937c | 956 | cpuid(10, &eax.full, &ebx, &unused, &edx.full); |
241771ef | 957 | if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED) |
b56a3802 | 958 | return NULL; |
241771ef | 959 | |
7bb497bd IM |
960 | intel_perfmon_version = eax.split.version_id; |
961 | if (intel_perfmon_version < 2) | |
962 | return NULL; | |
963 | ||
a1ef58f4 | 964 | pr_info("Intel Performance Monitoring support detected.\n"); |
7bb497bd | 965 | pr_info("... version: %d\n", intel_perfmon_version); |
a1ef58f4 JSR |
966 | pr_info("... bit width: %d\n", eax.split.bit_width); |
967 | pr_info("... mask length: %d\n", eax.split.mask_length); | |
b56a3802 | 968 | |
862a1a5f | 969 | nr_counters_generic = eax.split.num_counters; |
b56a3802 JSR |
970 | nr_counters_fixed = edx.split.num_counters_fixed; |
971 | counter_value_mask = (1ULL << eax.split.bit_width) - 1; | |
972 | ||
973 | return &pmc_intel_ops; | |
974 | } | |
975 | ||
f87ad35d JSR |
976 | static struct pmc_x86_ops *pmc_amd_init(void) |
977 | { | |
978 | nr_counters_generic = 4; | |
979 | nr_counters_fixed = 0; | |
b5e8acf6 PZ |
980 | counter_value_mask = 0x0000FFFFFFFFFFFFULL; |
981 | counter_value_bits = 48; | |
f87ad35d | 982 | |
a1ef58f4 | 983 | pr_info("AMD Performance Monitoring support detected.\n"); |
f87ad35d JSR |
984 | |
985 | return &pmc_amd_ops; | |
986 | } | |
987 | ||
b56a3802 JSR |
988 | void __init init_hw_perf_counters(void) |
989 | { | |
990 | if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) | |
991 | return; | |
992 | ||
993 | switch (boot_cpu_data.x86_vendor) { | |
994 | case X86_VENDOR_INTEL: | |
995 | pmc_ops = pmc_intel_init(); | |
996 | break; | |
f87ad35d JSR |
997 | case X86_VENDOR_AMD: |
998 | pmc_ops = pmc_amd_init(); | |
999 | break; | |
b56a3802 JSR |
1000 | } |
1001 | if (!pmc_ops) | |
1002 | return; | |
1003 | ||
a1ef58f4 | 1004 | pr_info("... num counters: %d\n", nr_counters_generic); |
862a1a5f IM |
1005 | if (nr_counters_generic > X86_PMC_MAX_GENERIC) { |
1006 | nr_counters_generic = X86_PMC_MAX_GENERIC; | |
241771ef | 1007 | WARN(1, KERN_ERR "hw perf counters %d > max(%d), clipping!", |
862a1a5f | 1008 | nr_counters_generic, X86_PMC_MAX_GENERIC); |
241771ef | 1009 | } |
862a1a5f IM |
1010 | perf_counter_mask = (1 << nr_counters_generic) - 1; |
1011 | perf_max_counters = nr_counters_generic; | |
241771ef | 1012 | |
a1ef58f4 | 1013 | pr_info("... value mask: %016Lx\n", counter_value_mask); |
2f18d1e8 | 1014 | |
862a1a5f IM |
1015 | if (nr_counters_fixed > X86_PMC_MAX_FIXED) { |
1016 | nr_counters_fixed = X86_PMC_MAX_FIXED; | |
703e937c | 1017 | WARN(1, KERN_ERR "hw perf counters fixed %d > max(%d), clipping!", |
862a1a5f | 1018 | nr_counters_fixed, X86_PMC_MAX_FIXED); |
703e937c | 1019 | } |
a1ef58f4 | 1020 | pr_info("... fixed counters: %d\n", nr_counters_fixed); |
862a1a5f IM |
1021 | |
1022 | perf_counter_mask |= ((1LL << nr_counters_fixed)-1) << X86_PMC_IDX_FIXED; | |
241771ef | 1023 | |
a1ef58f4 | 1024 | pr_info("... counter mask: %016Lx\n", perf_counter_mask); |
75f224cf IM |
1025 | perf_counters_initialized = true; |
1026 | ||
241771ef IM |
1027 | perf_counters_lapic_init(0); |
1028 | register_die_notifier(&perf_counter_nmi_notifier); | |
241771ef | 1029 | } |
621a01ea | 1030 | |
eb2b8618 | 1031 | static void pmc_generic_read(struct perf_counter *counter) |
ee06094f IM |
1032 | { |
1033 | x86_perf_counter_update(counter, &counter->hw, counter->hw.idx); | |
1034 | } | |
1035 | ||
5c92d124 | 1036 | static const struct hw_perf_counter_ops x86_perf_counter_ops = { |
7671581f IM |
1037 | .enable = pmc_generic_enable, |
1038 | .disable = pmc_generic_disable, | |
1039 | .read = pmc_generic_read, | |
621a01ea IM |
1040 | }; |
1041 | ||
5c92d124 IM |
1042 | const struct hw_perf_counter_ops * |
1043 | hw_perf_counter_init(struct perf_counter *counter) | |
621a01ea IM |
1044 | { |
1045 | int err; | |
1046 | ||
1047 | err = __hw_perf_counter_init(counter); | |
1048 | if (err) | |
9ea98e19 | 1049 | return ERR_PTR(err); |
621a01ea IM |
1050 | |
1051 | return &x86_perf_counter_ops; | |
1052 | } | |
d7d59fb3 PZ |
1053 | |
1054 | /* | |
1055 | * callchain support | |
1056 | */ | |
1057 | ||
1058 | static inline | |
1059 | void callchain_store(struct perf_callchain_entry *entry, unsigned long ip) | |
1060 | { | |
1061 | if (entry->nr < MAX_STACK_DEPTH) | |
1062 | entry->ip[entry->nr++] = ip; | |
1063 | } | |
1064 | ||
1065 | static DEFINE_PER_CPU(struct perf_callchain_entry, irq_entry); | |
1066 | static DEFINE_PER_CPU(struct perf_callchain_entry, nmi_entry); | |
1067 | ||
1068 | ||
1069 | static void | |
1070 | backtrace_warning_symbol(void *data, char *msg, unsigned long symbol) | |
1071 | { | |
1072 | /* Ignore warnings */ | |
1073 | } | |
1074 | ||
1075 | static void backtrace_warning(void *data, char *msg) | |
1076 | { | |
1077 | /* Ignore warnings */ | |
1078 | } | |
1079 | ||
1080 | static int backtrace_stack(void *data, char *name) | |
1081 | { | |
1082 | /* Don't bother with IRQ stacks for now */ | |
1083 | return -1; | |
1084 | } | |
1085 | ||
1086 | static void backtrace_address(void *data, unsigned long addr, int reliable) | |
1087 | { | |
1088 | struct perf_callchain_entry *entry = data; | |
1089 | ||
1090 | if (reliable) | |
1091 | callchain_store(entry, addr); | |
1092 | } | |
1093 | ||
1094 | static const struct stacktrace_ops backtrace_ops = { | |
1095 | .warning = backtrace_warning, | |
1096 | .warning_symbol = backtrace_warning_symbol, | |
1097 | .stack = backtrace_stack, | |
1098 | .address = backtrace_address, | |
1099 | }; | |
1100 | ||
1101 | static void | |
1102 | perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1103 | { | |
1104 | unsigned long bp; | |
1105 | char *stack; | |
5872bdb8 | 1106 | int nr = entry->nr; |
d7d59fb3 PZ |
1107 | |
1108 | callchain_store(entry, instruction_pointer(regs)); | |
1109 | ||
1110 | stack = ((char *)regs + sizeof(struct pt_regs)); | |
1111 | #ifdef CONFIG_FRAME_POINTER | |
1112 | bp = frame_pointer(regs); | |
1113 | #else | |
1114 | bp = 0; | |
1115 | #endif | |
1116 | ||
1117 | dump_trace(NULL, regs, (void *)stack, bp, &backtrace_ops, entry); | |
5872bdb8 PZ |
1118 | |
1119 | entry->kernel = entry->nr - nr; | |
d7d59fb3 PZ |
1120 | } |
1121 | ||
1122 | ||
1123 | struct stack_frame { | |
1124 | const void __user *next_fp; | |
1125 | unsigned long return_address; | |
1126 | }; | |
1127 | ||
1128 | static int copy_stack_frame(const void __user *fp, struct stack_frame *frame) | |
1129 | { | |
1130 | int ret; | |
1131 | ||
1132 | if (!access_ok(VERIFY_READ, fp, sizeof(*frame))) | |
1133 | return 0; | |
1134 | ||
1135 | ret = 1; | |
1136 | pagefault_disable(); | |
1137 | if (__copy_from_user_inatomic(frame, fp, sizeof(*frame))) | |
1138 | ret = 0; | |
1139 | pagefault_enable(); | |
1140 | ||
1141 | return ret; | |
1142 | } | |
1143 | ||
1144 | static void | |
1145 | perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1146 | { | |
1147 | struct stack_frame frame; | |
1148 | const void __user *fp; | |
5872bdb8 | 1149 | int nr = entry->nr; |
d7d59fb3 PZ |
1150 | |
1151 | regs = (struct pt_regs *)current->thread.sp0 - 1; | |
1152 | fp = (void __user *)regs->bp; | |
1153 | ||
1154 | callchain_store(entry, regs->ip); | |
1155 | ||
1156 | while (entry->nr < MAX_STACK_DEPTH) { | |
1157 | frame.next_fp = NULL; | |
1158 | frame.return_address = 0; | |
1159 | ||
1160 | if (!copy_stack_frame(fp, &frame)) | |
1161 | break; | |
1162 | ||
1163 | if ((unsigned long)fp < user_stack_pointer(regs)) | |
1164 | break; | |
1165 | ||
1166 | callchain_store(entry, frame.return_address); | |
1167 | fp = frame.next_fp; | |
1168 | } | |
5872bdb8 PZ |
1169 | |
1170 | entry->user = entry->nr - nr; | |
d7d59fb3 PZ |
1171 | } |
1172 | ||
1173 | static void | |
1174 | perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1175 | { | |
1176 | int is_user; | |
1177 | ||
1178 | if (!regs) | |
1179 | return; | |
1180 | ||
1181 | is_user = user_mode(regs); | |
1182 | ||
1183 | if (!current || current->pid == 0) | |
1184 | return; | |
1185 | ||
1186 | if (is_user && current->state != TASK_RUNNING) | |
1187 | return; | |
1188 | ||
1189 | if (!is_user) | |
1190 | perf_callchain_kernel(regs, entry); | |
1191 | ||
1192 | if (current->mm) | |
1193 | perf_callchain_user(regs, entry); | |
1194 | } | |
1195 | ||
1196 | struct perf_callchain_entry *perf_callchain(struct pt_regs *regs) | |
1197 | { | |
1198 | struct perf_callchain_entry *entry; | |
1199 | ||
1200 | if (in_nmi()) | |
1201 | entry = &__get_cpu_var(nmi_entry); | |
1202 | else | |
1203 | entry = &__get_cpu_var(irq_entry); | |
1204 | ||
1205 | entry->nr = 0; | |
5872bdb8 PZ |
1206 | entry->hv = 0; |
1207 | entry->kernel = 0; | |
1208 | entry->user = 0; | |
d7d59fb3 PZ |
1209 | |
1210 | perf_do_callchain(regs, entry); | |
1211 | ||
1212 | return entry; | |
1213 | } |