Commit | Line | Data |
---|---|---|
241771ef | 1 | /* |
cdd6c482 | 2 | * Performance events x86 architecture code |
241771ef | 3 | * |
98144511 IM |
4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> | |
30dd568c | 9 | * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> |
1da53e02 | 10 | * Copyright (C) 2009 Google, Inc., Stephane Eranian |
241771ef IM |
11 | * |
12 | * For licencing details see kernel-base/COPYING | |
13 | */ | |
14 | ||
cdd6c482 | 15 | #include <linux/perf_event.h> |
241771ef IM |
16 | #include <linux/capability.h> |
17 | #include <linux/notifier.h> | |
18 | #include <linux/hardirq.h> | |
19 | #include <linux/kprobes.h> | |
4ac13294 | 20 | #include <linux/module.h> |
241771ef IM |
21 | #include <linux/kdebug.h> |
22 | #include <linux/sched.h> | |
d7d59fb3 | 23 | #include <linux/uaccess.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
30dd568c | 25 | #include <linux/cpu.h> |
272d30be | 26 | #include <linux/bitops.h> |
0c9d42ed | 27 | #include <linux/device.h> |
241771ef | 28 | |
241771ef | 29 | #include <asm/apic.h> |
d7d59fb3 | 30 | #include <asm/stacktrace.h> |
4e935e47 | 31 | #include <asm/nmi.h> |
69092624 | 32 | #include <asm/smp.h> |
c8e5910e | 33 | #include <asm/alternative.h> |
e3f3541c | 34 | #include <asm/timer.h> |
d07bdfd3 PZ |
35 | #include <asm/desc.h> |
36 | #include <asm/ldt.h> | |
241771ef | 37 | |
de0428a7 KW |
38 | #include "perf_event.h" |
39 | ||
de0428a7 | 40 | struct x86_pmu x86_pmu __read_mostly; |
efc9f05d | 41 | |
de0428a7 | 42 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { |
b0f3f28e PZ |
43 | .enabled = 1, |
44 | }; | |
241771ef | 45 | |
de0428a7 | 46 | u64 __read_mostly hw_cache_event_ids |
8326f44d IM |
47 | [PERF_COUNT_HW_CACHE_MAX] |
48 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
49 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
de0428a7 | 50 | u64 __read_mostly hw_cache_extra_regs |
e994d7d2 AK |
51 | [PERF_COUNT_HW_CACHE_MAX] |
52 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
53 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
8326f44d | 54 | |
ee06094f | 55 | /* |
cdd6c482 IM |
56 | * Propagate event elapsed time into the generic event. |
57 | * Can only be executed on the CPU where the event is active. | |
ee06094f IM |
58 | * Returns the delta events processed. |
59 | */ | |
de0428a7 | 60 | u64 x86_perf_event_update(struct perf_event *event) |
ee06094f | 61 | { |
cc2ad4ba | 62 | struct hw_perf_event *hwc = &event->hw; |
948b1bb8 | 63 | int shift = 64 - x86_pmu.cntval_bits; |
ec3232bd | 64 | u64 prev_raw_count, new_raw_count; |
cc2ad4ba | 65 | int idx = hwc->idx; |
ec3232bd | 66 | s64 delta; |
ee06094f | 67 | |
15c7ad51 | 68 | if (idx == INTEL_PMC_IDX_FIXED_BTS) |
30dd568c MM |
69 | return 0; |
70 | ||
ee06094f | 71 | /* |
cdd6c482 | 72 | * Careful: an NMI might modify the previous event value. |
ee06094f IM |
73 | * |
74 | * Our tactic to handle this is to first atomically read and | |
75 | * exchange a new raw count - then add that new-prev delta | |
cdd6c482 | 76 | * count to the generic event atomically: |
ee06094f IM |
77 | */ |
78 | again: | |
e7850595 | 79 | prev_raw_count = local64_read(&hwc->prev_count); |
c48b6053 | 80 | rdpmcl(hwc->event_base_rdpmc, new_raw_count); |
ee06094f | 81 | |
e7850595 | 82 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
ee06094f IM |
83 | new_raw_count) != prev_raw_count) |
84 | goto again; | |
85 | ||
86 | /* | |
87 | * Now we have the new raw value and have updated the prev | |
88 | * timestamp already. We can now calculate the elapsed delta | |
cdd6c482 | 89 | * (event-)time and add that to the generic event. |
ee06094f IM |
90 | * |
91 | * Careful, not all hw sign-extends above the physical width | |
ec3232bd | 92 | * of the count. |
ee06094f | 93 | */ |
ec3232bd PZ |
94 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
95 | delta >>= shift; | |
ee06094f | 96 | |
e7850595 PZ |
97 | local64_add(delta, &event->count); |
98 | local64_sub(delta, &hwc->period_left); | |
4b7bfd0d RR |
99 | |
100 | return new_raw_count; | |
ee06094f IM |
101 | } |
102 | ||
a7e3ed1e AK |
103 | /* |
104 | * Find and validate any extra registers to set up. | |
105 | */ | |
106 | static int x86_pmu_extra_regs(u64 config, struct perf_event *event) | |
107 | { | |
efc9f05d | 108 | struct hw_perf_event_extra *reg; |
a7e3ed1e AK |
109 | struct extra_reg *er; |
110 | ||
efc9f05d | 111 | reg = &event->hw.extra_reg; |
a7e3ed1e AK |
112 | |
113 | if (!x86_pmu.extra_regs) | |
114 | return 0; | |
115 | ||
116 | for (er = x86_pmu.extra_regs; er->msr; er++) { | |
117 | if (er->event != (config & er->config_mask)) | |
118 | continue; | |
119 | if (event->attr.config1 & ~er->valid_mask) | |
120 | return -EINVAL; | |
338b522c KL |
121 | /* Check if the extra msrs can be safely accessed*/ |
122 | if (!er->extra_msr_access) | |
123 | return -ENXIO; | |
efc9f05d SE |
124 | |
125 | reg->idx = er->idx; | |
126 | reg->config = event->attr.config1; | |
127 | reg->reg = er->msr; | |
a7e3ed1e AK |
128 | break; |
129 | } | |
130 | return 0; | |
131 | } | |
132 | ||
cdd6c482 | 133 | static atomic_t active_events; |
4e935e47 PZ |
134 | static DEFINE_MUTEX(pmc_reserve_mutex); |
135 | ||
b27ea29c RR |
136 | #ifdef CONFIG_X86_LOCAL_APIC |
137 | ||
4e935e47 PZ |
138 | static bool reserve_pmc_hardware(void) |
139 | { | |
140 | int i; | |
141 | ||
948b1bb8 | 142 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 | 143 | if (!reserve_perfctr_nmi(x86_pmu_event_addr(i))) |
4e935e47 PZ |
144 | goto perfctr_fail; |
145 | } | |
146 | ||
948b1bb8 | 147 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 | 148 | if (!reserve_evntsel_nmi(x86_pmu_config_addr(i))) |
4e935e47 PZ |
149 | goto eventsel_fail; |
150 | } | |
151 | ||
152 | return true; | |
153 | ||
154 | eventsel_fail: | |
155 | for (i--; i >= 0; i--) | |
41bf4989 | 156 | release_evntsel_nmi(x86_pmu_config_addr(i)); |
4e935e47 | 157 | |
948b1bb8 | 158 | i = x86_pmu.num_counters; |
4e935e47 PZ |
159 | |
160 | perfctr_fail: | |
161 | for (i--; i >= 0; i--) | |
41bf4989 | 162 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
4e935e47 | 163 | |
4e935e47 PZ |
164 | return false; |
165 | } | |
166 | ||
167 | static void release_pmc_hardware(void) | |
168 | { | |
169 | int i; | |
170 | ||
948b1bb8 | 171 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 RR |
172 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
173 | release_evntsel_nmi(x86_pmu_config_addr(i)); | |
4e935e47 | 174 | } |
4e935e47 PZ |
175 | } |
176 | ||
b27ea29c RR |
177 | #else |
178 | ||
179 | static bool reserve_pmc_hardware(void) { return true; } | |
180 | static void release_pmc_hardware(void) {} | |
181 | ||
182 | #endif | |
183 | ||
33c6d6a7 DZ |
184 | static bool check_hw_exists(void) |
185 | { | |
a5ebe0ba GD |
186 | u64 val, val_fail, val_new= ~0; |
187 | int i, reg, reg_fail, ret = 0; | |
188 | int bios_fail = 0; | |
33c6d6a7 | 189 | |
4407204c PZ |
190 | /* |
191 | * Check to see if the BIOS enabled any of the counters, if so | |
192 | * complain and bail. | |
193 | */ | |
194 | for (i = 0; i < x86_pmu.num_counters; i++) { | |
41bf4989 | 195 | reg = x86_pmu_config_addr(i); |
4407204c PZ |
196 | ret = rdmsrl_safe(reg, &val); |
197 | if (ret) | |
198 | goto msr_fail; | |
a5ebe0ba GD |
199 | if (val & ARCH_PERFMON_EVENTSEL_ENABLE) { |
200 | bios_fail = 1; | |
201 | val_fail = val; | |
202 | reg_fail = reg; | |
203 | } | |
4407204c PZ |
204 | } |
205 | ||
206 | if (x86_pmu.num_counters_fixed) { | |
207 | reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; | |
208 | ret = rdmsrl_safe(reg, &val); | |
209 | if (ret) | |
210 | goto msr_fail; | |
211 | for (i = 0; i < x86_pmu.num_counters_fixed; i++) { | |
a5ebe0ba GD |
212 | if (val & (0x03 << i*4)) { |
213 | bios_fail = 1; | |
214 | val_fail = val; | |
215 | reg_fail = reg; | |
216 | } | |
4407204c PZ |
217 | } |
218 | } | |
219 | ||
220 | /* | |
bffd5fc2 AP |
221 | * Read the current value, change it and read it back to see if it |
222 | * matches, this is needed to detect certain hardware emulators | |
223 | * (qemu/kvm) that don't trap on the MSR access and always return 0s. | |
4407204c | 224 | */ |
f285f92f | 225 | reg = x86_pmu_event_addr(0); |
bffd5fc2 AP |
226 | if (rdmsrl_safe(reg, &val)) |
227 | goto msr_fail; | |
228 | val ^= 0xffffUL; | |
f285f92f RR |
229 | ret = wrmsrl_safe(reg, val); |
230 | ret |= rdmsrl_safe(reg, &val_new); | |
33c6d6a7 | 231 | if (ret || val != val_new) |
4407204c | 232 | goto msr_fail; |
33c6d6a7 | 233 | |
45daae57 IM |
234 | /* |
235 | * We still allow the PMU driver to operate: | |
236 | */ | |
a5ebe0ba GD |
237 | if (bios_fail) { |
238 | printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n"); | |
239 | printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg_fail, val_fail); | |
240 | } | |
45daae57 IM |
241 | |
242 | return true; | |
4407204c PZ |
243 | |
244 | msr_fail: | |
245 | printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n"); | |
65d71fe1 PZI |
246 | printk("%sFailed to access perfctr msr (MSR %x is %Lx)\n", |
247 | boot_cpu_has(X86_FEATURE_HYPERVISOR) ? KERN_INFO : KERN_ERR, | |
248 | reg, val_new); | |
45daae57 | 249 | |
4407204c | 250 | return false; |
33c6d6a7 DZ |
251 | } |
252 | ||
cdd6c482 | 253 | static void hw_perf_event_destroy(struct perf_event *event) |
4e935e47 | 254 | { |
cdd6c482 | 255 | if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) { |
4e935e47 | 256 | release_pmc_hardware(); |
ca037701 | 257 | release_ds_buffers(); |
4e935e47 PZ |
258 | mutex_unlock(&pmc_reserve_mutex); |
259 | } | |
260 | } | |
261 | ||
85cf9dba RR |
262 | static inline int x86_pmu_initialized(void) |
263 | { | |
264 | return x86_pmu.handle_irq != NULL; | |
265 | } | |
266 | ||
8326f44d | 267 | static inline int |
e994d7d2 | 268 | set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event) |
8326f44d | 269 | { |
e994d7d2 | 270 | struct perf_event_attr *attr = &event->attr; |
8326f44d IM |
271 | unsigned int cache_type, cache_op, cache_result; |
272 | u64 config, val; | |
273 | ||
274 | config = attr->config; | |
275 | ||
276 | cache_type = (config >> 0) & 0xff; | |
277 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
278 | return -EINVAL; | |
279 | ||
280 | cache_op = (config >> 8) & 0xff; | |
281 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
282 | return -EINVAL; | |
283 | ||
284 | cache_result = (config >> 16) & 0xff; | |
285 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
286 | return -EINVAL; | |
287 | ||
288 | val = hw_cache_event_ids[cache_type][cache_op][cache_result]; | |
289 | ||
290 | if (val == 0) | |
291 | return -ENOENT; | |
292 | ||
293 | if (val == -1) | |
294 | return -EINVAL; | |
295 | ||
296 | hwc->config |= val; | |
e994d7d2 AK |
297 | attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result]; |
298 | return x86_pmu_extra_regs(val, event); | |
8326f44d IM |
299 | } |
300 | ||
de0428a7 | 301 | int x86_setup_perfctr(struct perf_event *event) |
c1726f34 RR |
302 | { |
303 | struct perf_event_attr *attr = &event->attr; | |
304 | struct hw_perf_event *hwc = &event->hw; | |
305 | u64 config; | |
306 | ||
6c7e550f | 307 | if (!is_sampling_event(event)) { |
c1726f34 RR |
308 | hwc->sample_period = x86_pmu.max_period; |
309 | hwc->last_period = hwc->sample_period; | |
e7850595 | 310 | local64_set(&hwc->period_left, hwc->sample_period); |
c1726f34 RR |
311 | } |
312 | ||
313 | if (attr->type == PERF_TYPE_RAW) | |
ed13ec58 | 314 | return x86_pmu_extra_regs(event->attr.config, event); |
c1726f34 RR |
315 | |
316 | if (attr->type == PERF_TYPE_HW_CACHE) | |
e994d7d2 | 317 | return set_ext_hw_attr(hwc, event); |
c1726f34 RR |
318 | |
319 | if (attr->config >= x86_pmu.max_events) | |
320 | return -EINVAL; | |
321 | ||
322 | /* | |
323 | * The generic map: | |
324 | */ | |
325 | config = x86_pmu.event_map(attr->config); | |
326 | ||
327 | if (config == 0) | |
328 | return -ENOENT; | |
329 | ||
330 | if (config == -1LL) | |
331 | return -EINVAL; | |
332 | ||
333 | /* | |
334 | * Branch tracing: | |
335 | */ | |
18a073a3 PZ |
336 | if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS && |
337 | !attr->freq && hwc->sample_period == 1) { | |
c1726f34 | 338 | /* BTS is not supported by this architecture. */ |
6809b6ea | 339 | if (!x86_pmu.bts_active) |
c1726f34 RR |
340 | return -EOPNOTSUPP; |
341 | ||
342 | /* BTS is currently only allowed for user-mode. */ | |
343 | if (!attr->exclude_kernel) | |
344 | return -EOPNOTSUPP; | |
345 | } | |
346 | ||
347 | hwc->config |= config; | |
348 | ||
349 | return 0; | |
350 | } | |
4261e0e0 | 351 | |
ff3fb511 SE |
352 | /* |
353 | * check that branch_sample_type is compatible with | |
354 | * settings needed for precise_ip > 1 which implies | |
355 | * using the LBR to capture ALL taken branches at the | |
356 | * priv levels of the measurement | |
357 | */ | |
358 | static inline int precise_br_compat(struct perf_event *event) | |
359 | { | |
360 | u64 m = event->attr.branch_sample_type; | |
361 | u64 b = 0; | |
362 | ||
363 | /* must capture all branches */ | |
364 | if (!(m & PERF_SAMPLE_BRANCH_ANY)) | |
365 | return 0; | |
366 | ||
367 | m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER; | |
368 | ||
369 | if (!event->attr.exclude_user) | |
370 | b |= PERF_SAMPLE_BRANCH_USER; | |
371 | ||
372 | if (!event->attr.exclude_kernel) | |
373 | b |= PERF_SAMPLE_BRANCH_KERNEL; | |
374 | ||
375 | /* | |
376 | * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86 | |
377 | */ | |
378 | ||
379 | return m == b; | |
380 | } | |
381 | ||
de0428a7 | 382 | int x86_pmu_hw_config(struct perf_event *event) |
a072738e | 383 | { |
ab608344 PZ |
384 | if (event->attr.precise_ip) { |
385 | int precise = 0; | |
386 | ||
387 | /* Support for constant skid */ | |
c93dc84c | 388 | if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) { |
ab608344 PZ |
389 | precise++; |
390 | ||
5553be26 | 391 | /* Support for IP fixup */ |
03de874a | 392 | if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2) |
5553be26 PZ |
393 | precise++; |
394 | } | |
ab608344 PZ |
395 | |
396 | if (event->attr.precise_ip > precise) | |
397 | return -EOPNOTSUPP; | |
ff3fb511 SE |
398 | /* |
399 | * check that PEBS LBR correction does not conflict with | |
400 | * whatever the user is asking with attr->branch_sample_type | |
401 | */ | |
130768b8 AK |
402 | if (event->attr.precise_ip > 1 && |
403 | x86_pmu.intel_cap.pebs_format < 2) { | |
ff3fb511 SE |
404 | u64 *br_type = &event->attr.branch_sample_type; |
405 | ||
406 | if (has_branch_stack(event)) { | |
407 | if (!precise_br_compat(event)) | |
408 | return -EOPNOTSUPP; | |
409 | ||
410 | /* branch_sample_type is compatible */ | |
411 | ||
412 | } else { | |
413 | /* | |
414 | * user did not specify branch_sample_type | |
415 | * | |
416 | * For PEBS fixups, we capture all | |
417 | * the branches at the priv level of the | |
418 | * event. | |
419 | */ | |
420 | *br_type = PERF_SAMPLE_BRANCH_ANY; | |
421 | ||
422 | if (!event->attr.exclude_user) | |
423 | *br_type |= PERF_SAMPLE_BRANCH_USER; | |
424 | ||
425 | if (!event->attr.exclude_kernel) | |
426 | *br_type |= PERF_SAMPLE_BRANCH_KERNEL; | |
427 | } | |
428 | } | |
ab608344 PZ |
429 | } |
430 | ||
a072738e CG |
431 | /* |
432 | * Generate PMC IRQs: | |
433 | * (keep 'enabled' bit clear for now) | |
434 | */ | |
b4cdc5c2 | 435 | event->hw.config = ARCH_PERFMON_EVENTSEL_INT; |
a072738e CG |
436 | |
437 | /* | |
438 | * Count user and OS events unless requested not to | |
439 | */ | |
b4cdc5c2 PZ |
440 | if (!event->attr.exclude_user) |
441 | event->hw.config |= ARCH_PERFMON_EVENTSEL_USR; | |
442 | if (!event->attr.exclude_kernel) | |
443 | event->hw.config |= ARCH_PERFMON_EVENTSEL_OS; | |
a072738e | 444 | |
b4cdc5c2 PZ |
445 | if (event->attr.type == PERF_TYPE_RAW) |
446 | event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK; | |
a072738e | 447 | |
9d0fcba6 | 448 | return x86_setup_perfctr(event); |
a098f448 RR |
449 | } |
450 | ||
241771ef | 451 | /* |
0d48696f | 452 | * Setup the hardware configuration for a given attr_type |
241771ef | 453 | */ |
b0a873eb | 454 | static int __x86_pmu_event_init(struct perf_event *event) |
241771ef | 455 | { |
4e935e47 | 456 | int err; |
241771ef | 457 | |
85cf9dba RR |
458 | if (!x86_pmu_initialized()) |
459 | return -ENODEV; | |
241771ef | 460 | |
4e935e47 | 461 | err = 0; |
cdd6c482 | 462 | if (!atomic_inc_not_zero(&active_events)) { |
4e935e47 | 463 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 | 464 | if (atomic_read(&active_events) == 0) { |
30dd568c MM |
465 | if (!reserve_pmc_hardware()) |
466 | err = -EBUSY; | |
f80c9e30 PZ |
467 | else |
468 | reserve_ds_buffers(); | |
30dd568c MM |
469 | } |
470 | if (!err) | |
cdd6c482 | 471 | atomic_inc(&active_events); |
4e935e47 PZ |
472 | mutex_unlock(&pmc_reserve_mutex); |
473 | } | |
474 | if (err) | |
475 | return err; | |
476 | ||
cdd6c482 | 477 | event->destroy = hw_perf_event_destroy; |
a1792cda | 478 | |
4261e0e0 RR |
479 | event->hw.idx = -1; |
480 | event->hw.last_cpu = -1; | |
481 | event->hw.last_tag = ~0ULL; | |
b690081d | 482 | |
efc9f05d SE |
483 | /* mark unused */ |
484 | event->hw.extra_reg.idx = EXTRA_REG_NONE; | |
b36817e8 SE |
485 | event->hw.branch_reg.idx = EXTRA_REG_NONE; |
486 | ||
9d0fcba6 | 487 | return x86_pmu.hw_config(event); |
4261e0e0 RR |
488 | } |
489 | ||
de0428a7 | 490 | void x86_pmu_disable_all(void) |
f87ad35d | 491 | { |
89cbc767 | 492 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
9e35ad38 PZ |
493 | int idx; |
494 | ||
948b1bb8 | 495 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
b0f3f28e PZ |
496 | u64 val; |
497 | ||
43f6201a | 498 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 499 | continue; |
41bf4989 | 500 | rdmsrl(x86_pmu_config_addr(idx), val); |
bb1165d6 | 501 | if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE)) |
4295ee62 | 502 | continue; |
bb1165d6 | 503 | val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; |
41bf4989 | 504 | wrmsrl(x86_pmu_config_addr(idx), val); |
f87ad35d | 505 | } |
f87ad35d JSR |
506 | } |
507 | ||
a4eaf7f1 | 508 | static void x86_pmu_disable(struct pmu *pmu) |
b56a3802 | 509 | { |
89cbc767 | 510 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
1da53e02 | 511 | |
85cf9dba | 512 | if (!x86_pmu_initialized()) |
9e35ad38 | 513 | return; |
1da53e02 | 514 | |
1a6e21f7 PZ |
515 | if (!cpuc->enabled) |
516 | return; | |
517 | ||
518 | cpuc->n_added = 0; | |
519 | cpuc->enabled = 0; | |
520 | barrier(); | |
1da53e02 SE |
521 | |
522 | x86_pmu.disable_all(); | |
b56a3802 | 523 | } |
241771ef | 524 | |
de0428a7 | 525 | void x86_pmu_enable_all(int added) |
f87ad35d | 526 | { |
89cbc767 | 527 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
f87ad35d JSR |
528 | int idx; |
529 | ||
948b1bb8 | 530 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
d45dd923 | 531 | struct hw_perf_event *hwc = &cpuc->events[idx]->hw; |
b0f3f28e | 532 | |
43f6201a | 533 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 534 | continue; |
984b838c | 535 | |
d45dd923 | 536 | __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); |
f87ad35d JSR |
537 | } |
538 | } | |
539 | ||
51b0fe39 | 540 | static struct pmu pmu; |
1da53e02 SE |
541 | |
542 | static inline int is_x86_event(struct perf_event *event) | |
543 | { | |
544 | return event->pmu == &pmu; | |
545 | } | |
546 | ||
1e2ad28f RR |
547 | /* |
548 | * Event scheduler state: | |
549 | * | |
550 | * Assign events iterating over all events and counters, beginning | |
551 | * with events with least weights first. Keep the current iterator | |
552 | * state in struct sched_state. | |
553 | */ | |
554 | struct sched_state { | |
555 | int weight; | |
556 | int event; /* event index */ | |
557 | int counter; /* counter index */ | |
558 | int unassigned; /* number of events to be assigned left */ | |
559 | unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
560 | }; | |
561 | ||
bc1738f6 RR |
562 | /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */ |
563 | #define SCHED_STATES_MAX 2 | |
564 | ||
1e2ad28f RR |
565 | struct perf_sched { |
566 | int max_weight; | |
567 | int max_events; | |
43b45780 | 568 | struct perf_event **events; |
1e2ad28f | 569 | struct sched_state state; |
bc1738f6 RR |
570 | int saved_states; |
571 | struct sched_state saved[SCHED_STATES_MAX]; | |
1e2ad28f RR |
572 | }; |
573 | ||
574 | /* | |
575 | * Initialize interator that runs through all events and counters. | |
576 | */ | |
43b45780 | 577 | static void perf_sched_init(struct perf_sched *sched, struct perf_event **events, |
1e2ad28f RR |
578 | int num, int wmin, int wmax) |
579 | { | |
580 | int idx; | |
581 | ||
582 | memset(sched, 0, sizeof(*sched)); | |
583 | sched->max_events = num; | |
584 | sched->max_weight = wmax; | |
43b45780 | 585 | sched->events = events; |
1e2ad28f RR |
586 | |
587 | for (idx = 0; idx < num; idx++) { | |
43b45780 | 588 | if (events[idx]->hw.constraint->weight == wmin) |
1e2ad28f RR |
589 | break; |
590 | } | |
591 | ||
592 | sched->state.event = idx; /* start with min weight */ | |
593 | sched->state.weight = wmin; | |
594 | sched->state.unassigned = num; | |
595 | } | |
596 | ||
bc1738f6 RR |
597 | static void perf_sched_save_state(struct perf_sched *sched) |
598 | { | |
599 | if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX)) | |
600 | return; | |
601 | ||
602 | sched->saved[sched->saved_states] = sched->state; | |
603 | sched->saved_states++; | |
604 | } | |
605 | ||
606 | static bool perf_sched_restore_state(struct perf_sched *sched) | |
607 | { | |
608 | if (!sched->saved_states) | |
609 | return false; | |
610 | ||
611 | sched->saved_states--; | |
612 | sched->state = sched->saved[sched->saved_states]; | |
613 | ||
614 | /* continue with next counter: */ | |
615 | clear_bit(sched->state.counter++, sched->state.used); | |
616 | ||
617 | return true; | |
618 | } | |
619 | ||
1e2ad28f RR |
620 | /* |
621 | * Select a counter for the current event to schedule. Return true on | |
622 | * success. | |
623 | */ | |
bc1738f6 | 624 | static bool __perf_sched_find_counter(struct perf_sched *sched) |
1e2ad28f RR |
625 | { |
626 | struct event_constraint *c; | |
627 | int idx; | |
628 | ||
629 | if (!sched->state.unassigned) | |
630 | return false; | |
631 | ||
632 | if (sched->state.event >= sched->max_events) | |
633 | return false; | |
634 | ||
43b45780 | 635 | c = sched->events[sched->state.event]->hw.constraint; |
4defea85 | 636 | /* Prefer fixed purpose counters */ |
15c7ad51 RR |
637 | if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) { |
638 | idx = INTEL_PMC_IDX_FIXED; | |
307b1cd7 | 639 | for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) { |
4defea85 PZ |
640 | if (!__test_and_set_bit(idx, sched->state.used)) |
641 | goto done; | |
642 | } | |
643 | } | |
1e2ad28f RR |
644 | /* Grab the first unused counter starting with idx */ |
645 | idx = sched->state.counter; | |
15c7ad51 | 646 | for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) { |
1e2ad28f | 647 | if (!__test_and_set_bit(idx, sched->state.used)) |
4defea85 | 648 | goto done; |
1e2ad28f | 649 | } |
1e2ad28f | 650 | |
4defea85 PZ |
651 | return false; |
652 | ||
653 | done: | |
654 | sched->state.counter = idx; | |
1e2ad28f | 655 | |
bc1738f6 RR |
656 | if (c->overlap) |
657 | perf_sched_save_state(sched); | |
658 | ||
659 | return true; | |
660 | } | |
661 | ||
662 | static bool perf_sched_find_counter(struct perf_sched *sched) | |
663 | { | |
664 | while (!__perf_sched_find_counter(sched)) { | |
665 | if (!perf_sched_restore_state(sched)) | |
666 | return false; | |
667 | } | |
668 | ||
1e2ad28f RR |
669 | return true; |
670 | } | |
671 | ||
672 | /* | |
673 | * Go through all unassigned events and find the next one to schedule. | |
674 | * Take events with the least weight first. Return true on success. | |
675 | */ | |
676 | static bool perf_sched_next_event(struct perf_sched *sched) | |
677 | { | |
678 | struct event_constraint *c; | |
679 | ||
680 | if (!sched->state.unassigned || !--sched->state.unassigned) | |
681 | return false; | |
682 | ||
683 | do { | |
684 | /* next event */ | |
685 | sched->state.event++; | |
686 | if (sched->state.event >= sched->max_events) { | |
687 | /* next weight */ | |
688 | sched->state.event = 0; | |
689 | sched->state.weight++; | |
690 | if (sched->state.weight > sched->max_weight) | |
691 | return false; | |
692 | } | |
43b45780 | 693 | c = sched->events[sched->state.event]->hw.constraint; |
1e2ad28f RR |
694 | } while (c->weight != sched->state.weight); |
695 | ||
696 | sched->state.counter = 0; /* start with first counter */ | |
697 | ||
698 | return true; | |
699 | } | |
700 | ||
701 | /* | |
702 | * Assign a counter for each event. | |
703 | */ | |
43b45780 | 704 | int perf_assign_events(struct perf_event **events, int n, |
4b4969b1 | 705 | int wmin, int wmax, int *assign) |
1e2ad28f RR |
706 | { |
707 | struct perf_sched sched; | |
708 | ||
43b45780 | 709 | perf_sched_init(&sched, events, n, wmin, wmax); |
1e2ad28f RR |
710 | |
711 | do { | |
712 | if (!perf_sched_find_counter(&sched)) | |
713 | break; /* failed */ | |
714 | if (assign) | |
715 | assign[sched.state.event] = sched.state.counter; | |
716 | } while (perf_sched_next_event(&sched)); | |
717 | ||
718 | return sched.state.unassigned; | |
719 | } | |
4a3dc121 | 720 | EXPORT_SYMBOL_GPL(perf_assign_events); |
1e2ad28f | 721 | |
de0428a7 | 722 | int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) |
1da53e02 | 723 | { |
43b45780 | 724 | struct event_constraint *c; |
1da53e02 | 725 | unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
2f7f73a5 | 726 | struct perf_event *e; |
1e2ad28f | 727 | int i, wmin, wmax, num = 0; |
1da53e02 SE |
728 | struct hw_perf_event *hwc; |
729 | ||
730 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); | |
731 | ||
1e2ad28f | 732 | for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) { |
43b45780 | 733 | hwc = &cpuc->event_list[i]->hw; |
b622d644 | 734 | c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]); |
43b45780 AH |
735 | hwc->constraint = c; |
736 | ||
1e2ad28f RR |
737 | wmin = min(wmin, c->weight); |
738 | wmax = max(wmax, c->weight); | |
1da53e02 SE |
739 | } |
740 | ||
8113070d SE |
741 | /* |
742 | * fastpath, try to reuse previous register | |
743 | */ | |
c933c1a6 | 744 | for (i = 0; i < n; i++) { |
8113070d | 745 | hwc = &cpuc->event_list[i]->hw; |
43b45780 | 746 | c = hwc->constraint; |
8113070d SE |
747 | |
748 | /* never assigned */ | |
749 | if (hwc->idx == -1) | |
750 | break; | |
751 | ||
752 | /* constraint still honored */ | |
63b14649 | 753 | if (!test_bit(hwc->idx, c->idxmsk)) |
8113070d SE |
754 | break; |
755 | ||
756 | /* not already used */ | |
757 | if (test_bit(hwc->idx, used_mask)) | |
758 | break; | |
759 | ||
34538ee7 | 760 | __set_bit(hwc->idx, used_mask); |
8113070d SE |
761 | if (assign) |
762 | assign[i] = hwc->idx; | |
763 | } | |
8113070d | 764 | |
1e2ad28f RR |
765 | /* slow path */ |
766 | if (i != n) | |
43b45780 AH |
767 | num = perf_assign_events(cpuc->event_list, n, wmin, |
768 | wmax, assign); | |
8113070d | 769 | |
2f7f73a5 SE |
770 | /* |
771 | * Mark the event as committed, so we do not put_constraint() | |
772 | * in case new events are added and fail scheduling. | |
773 | */ | |
774 | if (!num && assign) { | |
775 | for (i = 0; i < n; i++) { | |
776 | e = cpuc->event_list[i]; | |
777 | e->hw.flags |= PERF_X86_EVENT_COMMITTED; | |
778 | } | |
779 | } | |
1da53e02 SE |
780 | /* |
781 | * scheduling failed or is just a simulation, | |
782 | * free resources if necessary | |
783 | */ | |
784 | if (!assign || num) { | |
785 | for (i = 0; i < n; i++) { | |
2f7f73a5 SE |
786 | e = cpuc->event_list[i]; |
787 | /* | |
788 | * do not put_constraint() on comitted events, | |
789 | * because they are good to go | |
790 | */ | |
791 | if ((e->hw.flags & PERF_X86_EVENT_COMMITTED)) | |
792 | continue; | |
793 | ||
1da53e02 | 794 | if (x86_pmu.put_event_constraints) |
2f7f73a5 | 795 | x86_pmu.put_event_constraints(cpuc, e); |
1da53e02 SE |
796 | } |
797 | } | |
aa2bc1ad | 798 | return num ? -EINVAL : 0; |
1da53e02 SE |
799 | } |
800 | ||
801 | /* | |
802 | * dogrp: true if must collect siblings events (group) | |
803 | * returns total number of events and error code | |
804 | */ | |
805 | static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp) | |
806 | { | |
807 | struct perf_event *event; | |
808 | int n, max_count; | |
809 | ||
948b1bb8 | 810 | max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed; |
1da53e02 SE |
811 | |
812 | /* current number of events already accepted */ | |
813 | n = cpuc->n_events; | |
814 | ||
815 | if (is_x86_event(leader)) { | |
816 | if (n >= max_count) | |
aa2bc1ad | 817 | return -EINVAL; |
1da53e02 SE |
818 | cpuc->event_list[n] = leader; |
819 | n++; | |
820 | } | |
821 | if (!dogrp) | |
822 | return n; | |
823 | ||
824 | list_for_each_entry(event, &leader->sibling_list, group_entry) { | |
825 | if (!is_x86_event(event) || | |
8113070d | 826 | event->state <= PERF_EVENT_STATE_OFF) |
1da53e02 SE |
827 | continue; |
828 | ||
829 | if (n >= max_count) | |
aa2bc1ad | 830 | return -EINVAL; |
1da53e02 SE |
831 | |
832 | cpuc->event_list[n] = event; | |
833 | n++; | |
834 | } | |
835 | return n; | |
836 | } | |
837 | ||
1da53e02 | 838 | static inline void x86_assign_hw_event(struct perf_event *event, |
447a194b | 839 | struct cpu_hw_events *cpuc, int i) |
1da53e02 | 840 | { |
447a194b SE |
841 | struct hw_perf_event *hwc = &event->hw; |
842 | ||
843 | hwc->idx = cpuc->assign[i]; | |
844 | hwc->last_cpu = smp_processor_id(); | |
845 | hwc->last_tag = ++cpuc->tags[i]; | |
1da53e02 | 846 | |
15c7ad51 | 847 | if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) { |
1da53e02 SE |
848 | hwc->config_base = 0; |
849 | hwc->event_base = 0; | |
15c7ad51 | 850 | } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) { |
1da53e02 | 851 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; |
15c7ad51 RR |
852 | hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED); |
853 | hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30; | |
1da53e02 | 854 | } else { |
73d6e522 RR |
855 | hwc->config_base = x86_pmu_config_addr(hwc->idx); |
856 | hwc->event_base = x86_pmu_event_addr(hwc->idx); | |
0fbdad07 | 857 | hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx); |
1da53e02 SE |
858 | } |
859 | } | |
860 | ||
447a194b SE |
861 | static inline int match_prev_assignment(struct hw_perf_event *hwc, |
862 | struct cpu_hw_events *cpuc, | |
863 | int i) | |
864 | { | |
865 | return hwc->idx == cpuc->assign[i] && | |
866 | hwc->last_cpu == smp_processor_id() && | |
867 | hwc->last_tag == cpuc->tags[i]; | |
868 | } | |
869 | ||
a4eaf7f1 | 870 | static void x86_pmu_start(struct perf_event *event, int flags); |
2e841873 | 871 | |
a4eaf7f1 | 872 | static void x86_pmu_enable(struct pmu *pmu) |
ee06094f | 873 | { |
89cbc767 | 874 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
1da53e02 SE |
875 | struct perf_event *event; |
876 | struct hw_perf_event *hwc; | |
11164cd4 | 877 | int i, added = cpuc->n_added; |
1da53e02 | 878 | |
85cf9dba | 879 | if (!x86_pmu_initialized()) |
2b9ff0db | 880 | return; |
1a6e21f7 PZ |
881 | |
882 | if (cpuc->enabled) | |
883 | return; | |
884 | ||
1da53e02 | 885 | if (cpuc->n_added) { |
19925ce7 | 886 | int n_running = cpuc->n_events - cpuc->n_added; |
1da53e02 SE |
887 | /* |
888 | * apply assignment obtained either from | |
889 | * hw_perf_group_sched_in() or x86_pmu_enable() | |
890 | * | |
891 | * step1: save events moving to new counters | |
1da53e02 | 892 | */ |
19925ce7 | 893 | for (i = 0; i < n_running; i++) { |
1da53e02 SE |
894 | event = cpuc->event_list[i]; |
895 | hwc = &event->hw; | |
896 | ||
447a194b SE |
897 | /* |
898 | * we can avoid reprogramming counter if: | |
899 | * - assigned same counter as last time | |
900 | * - running on same CPU as last time | |
901 | * - no other event has used the counter since | |
902 | */ | |
903 | if (hwc->idx == -1 || | |
904 | match_prev_assignment(hwc, cpuc, i)) | |
1da53e02 SE |
905 | continue; |
906 | ||
a4eaf7f1 PZ |
907 | /* |
908 | * Ensure we don't accidentally enable a stopped | |
909 | * counter simply because we rescheduled. | |
910 | */ | |
911 | if (hwc->state & PERF_HES_STOPPED) | |
912 | hwc->state |= PERF_HES_ARCH; | |
913 | ||
914 | x86_pmu_stop(event, PERF_EF_UPDATE); | |
1da53e02 SE |
915 | } |
916 | ||
c347a2f1 PZ |
917 | /* |
918 | * step2: reprogram moved events into new counters | |
919 | */ | |
1da53e02 | 920 | for (i = 0; i < cpuc->n_events; i++) { |
1da53e02 SE |
921 | event = cpuc->event_list[i]; |
922 | hwc = &event->hw; | |
923 | ||
45e16a68 | 924 | if (!match_prev_assignment(hwc, cpuc, i)) |
447a194b | 925 | x86_assign_hw_event(event, cpuc, i); |
45e16a68 PZ |
926 | else if (i < n_running) |
927 | continue; | |
1da53e02 | 928 | |
a4eaf7f1 PZ |
929 | if (hwc->state & PERF_HES_ARCH) |
930 | continue; | |
931 | ||
932 | x86_pmu_start(event, PERF_EF_RELOAD); | |
1da53e02 SE |
933 | } |
934 | cpuc->n_added = 0; | |
935 | perf_events_lapic_init(); | |
936 | } | |
1a6e21f7 PZ |
937 | |
938 | cpuc->enabled = 1; | |
939 | barrier(); | |
940 | ||
11164cd4 | 941 | x86_pmu.enable_all(added); |
ee06094f | 942 | } |
ee06094f | 943 | |
245b2e70 | 944 | static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); |
241771ef | 945 | |
ee06094f IM |
946 | /* |
947 | * Set the next IRQ period, based on the hwc->period_left value. | |
cdd6c482 | 948 | * To be called with the event disabled in hw: |
ee06094f | 949 | */ |
de0428a7 | 950 | int x86_perf_event_set_period(struct perf_event *event) |
241771ef | 951 | { |
07088edb | 952 | struct hw_perf_event *hwc = &event->hw; |
e7850595 | 953 | s64 left = local64_read(&hwc->period_left); |
e4abb5d4 | 954 | s64 period = hwc->sample_period; |
7645a24c | 955 | int ret = 0, idx = hwc->idx; |
ee06094f | 956 | |
15c7ad51 | 957 | if (idx == INTEL_PMC_IDX_FIXED_BTS) |
30dd568c MM |
958 | return 0; |
959 | ||
ee06094f | 960 | /* |
af901ca1 | 961 | * If we are way outside a reasonable range then just skip forward: |
ee06094f IM |
962 | */ |
963 | if (unlikely(left <= -period)) { | |
964 | left = period; | |
e7850595 | 965 | local64_set(&hwc->period_left, left); |
9e350de3 | 966 | hwc->last_period = period; |
e4abb5d4 | 967 | ret = 1; |
ee06094f IM |
968 | } |
969 | ||
970 | if (unlikely(left <= 0)) { | |
971 | left += period; | |
e7850595 | 972 | local64_set(&hwc->period_left, left); |
9e350de3 | 973 | hwc->last_period = period; |
e4abb5d4 | 974 | ret = 1; |
ee06094f | 975 | } |
1c80f4b5 | 976 | /* |
dfc65094 | 977 | * Quirk: certain CPUs dont like it if just 1 hw_event is left: |
1c80f4b5 IM |
978 | */ |
979 | if (unlikely(left < 2)) | |
980 | left = 2; | |
241771ef | 981 | |
e4abb5d4 PZ |
982 | if (left > x86_pmu.max_period) |
983 | left = x86_pmu.max_period; | |
984 | ||
245b2e70 | 985 | per_cpu(pmc_prev_left[idx], smp_processor_id()) = left; |
ee06094f IM |
986 | |
987 | /* | |
cdd6c482 | 988 | * The hw event starts counting from this event offset, |
ee06094f IM |
989 | * mark it to be able to extra future deltas: |
990 | */ | |
e7850595 | 991 | local64_set(&hwc->prev_count, (u64)-left); |
ee06094f | 992 | |
73d6e522 | 993 | wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac CG |
994 | |
995 | /* | |
996 | * Due to erratum on certan cpu we need | |
997 | * a second write to be sure the register | |
998 | * is updated properly | |
999 | */ | |
1000 | if (x86_pmu.perfctr_second_write) { | |
73d6e522 | 1001 | wrmsrl(hwc->event_base, |
948b1bb8 | 1002 | (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac | 1003 | } |
e4abb5d4 | 1004 | |
cdd6c482 | 1005 | perf_event_update_userpage(event); |
194002b2 | 1006 | |
e4abb5d4 | 1007 | return ret; |
2f18d1e8 IM |
1008 | } |
1009 | ||
de0428a7 | 1010 | void x86_pmu_enable_event(struct perf_event *event) |
7c90cc45 | 1011 | { |
0a3aee0d | 1012 | if (__this_cpu_read(cpu_hw_events.enabled)) |
31fa58af RR |
1013 | __x86_pmu_enable_event(&event->hw, |
1014 | ARCH_PERFMON_EVENTSEL_ENABLE); | |
241771ef IM |
1015 | } |
1016 | ||
b690081d | 1017 | /* |
a4eaf7f1 | 1018 | * Add a single event to the PMU. |
1da53e02 SE |
1019 | * |
1020 | * The event is added to the group of enabled events | |
1021 | * but only if it can be scehduled with existing events. | |
fe9081cc | 1022 | */ |
a4eaf7f1 | 1023 | static int x86_pmu_add(struct perf_event *event, int flags) |
fe9081cc | 1024 | { |
89cbc767 | 1025 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
1da53e02 SE |
1026 | struct hw_perf_event *hwc; |
1027 | int assign[X86_PMC_IDX_MAX]; | |
1028 | int n, n0, ret; | |
fe9081cc | 1029 | |
1da53e02 | 1030 | hwc = &event->hw; |
fe9081cc | 1031 | |
33696fc0 | 1032 | perf_pmu_disable(event->pmu); |
1da53e02 | 1033 | n0 = cpuc->n_events; |
24cd7f54 PZ |
1034 | ret = n = collect_events(cpuc, event, false); |
1035 | if (ret < 0) | |
1036 | goto out; | |
53b441a5 | 1037 | |
a4eaf7f1 PZ |
1038 | hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; |
1039 | if (!(flags & PERF_EF_START)) | |
1040 | hwc->state |= PERF_HES_ARCH; | |
1041 | ||
4d1c52b0 LM |
1042 | /* |
1043 | * If group events scheduling transaction was started, | |
0d2eb44f | 1044 | * skip the schedulability test here, it will be performed |
c347a2f1 | 1045 | * at commit time (->commit_txn) as a whole. |
4d1c52b0 | 1046 | */ |
8d2cacbb | 1047 | if (cpuc->group_flag & PERF_EVENT_TXN) |
24cd7f54 | 1048 | goto done_collect; |
4d1c52b0 | 1049 | |
a072738e | 1050 | ret = x86_pmu.schedule_events(cpuc, n, assign); |
1da53e02 | 1051 | if (ret) |
24cd7f54 | 1052 | goto out; |
1da53e02 SE |
1053 | /* |
1054 | * copy new assignment, now we know it is possible | |
1055 | * will be used by hw_perf_enable() | |
1056 | */ | |
1057 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
7e2ae347 | 1058 | |
24cd7f54 | 1059 | done_collect: |
c347a2f1 PZ |
1060 | /* |
1061 | * Commit the collect_events() state. See x86_pmu_del() and | |
1062 | * x86_pmu_*_txn(). | |
1063 | */ | |
1da53e02 | 1064 | cpuc->n_events = n; |
356e1f2e | 1065 | cpuc->n_added += n - n0; |
90151c35 | 1066 | cpuc->n_txn += n - n0; |
95cdd2e7 | 1067 | |
24cd7f54 PZ |
1068 | ret = 0; |
1069 | out: | |
33696fc0 | 1070 | perf_pmu_enable(event->pmu); |
24cd7f54 | 1071 | return ret; |
241771ef IM |
1072 | } |
1073 | ||
a4eaf7f1 | 1074 | static void x86_pmu_start(struct perf_event *event, int flags) |
d76a0812 | 1075 | { |
89cbc767 | 1076 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
c08053e6 PZ |
1077 | int idx = event->hw.idx; |
1078 | ||
a4eaf7f1 PZ |
1079 | if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) |
1080 | return; | |
1081 | ||
1082 | if (WARN_ON_ONCE(idx == -1)) | |
1083 | return; | |
1084 | ||
1085 | if (flags & PERF_EF_RELOAD) { | |
1086 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); | |
1087 | x86_perf_event_set_period(event); | |
1088 | } | |
1089 | ||
1090 | event->hw.state = 0; | |
d76a0812 | 1091 | |
c08053e6 PZ |
1092 | cpuc->events[idx] = event; |
1093 | __set_bit(idx, cpuc->active_mask); | |
63e6be6d | 1094 | __set_bit(idx, cpuc->running); |
aff3d91a | 1095 | x86_pmu.enable(event); |
c08053e6 | 1096 | perf_event_update_userpage(event); |
a78ac325 PZ |
1097 | } |
1098 | ||
cdd6c482 | 1099 | void perf_event_print_debug(void) |
241771ef | 1100 | { |
2f18d1e8 | 1101 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
ca037701 | 1102 | u64 pebs; |
cdd6c482 | 1103 | struct cpu_hw_events *cpuc; |
5bb9efe3 | 1104 | unsigned long flags; |
1e125676 IM |
1105 | int cpu, idx; |
1106 | ||
948b1bb8 | 1107 | if (!x86_pmu.num_counters) |
1e125676 | 1108 | return; |
241771ef | 1109 | |
5bb9efe3 | 1110 | local_irq_save(flags); |
241771ef IM |
1111 | |
1112 | cpu = smp_processor_id(); | |
cdd6c482 | 1113 | cpuc = &per_cpu(cpu_hw_events, cpu); |
241771ef | 1114 | |
faa28ae0 | 1115 | if (x86_pmu.version >= 2) { |
a1ef58f4 JSR |
1116 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
1117 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
1118 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
1119 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); | |
ca037701 | 1120 | rdmsrl(MSR_IA32_PEBS_ENABLE, pebs); |
a1ef58f4 JSR |
1121 | |
1122 | pr_info("\n"); | |
1123 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
1124 | pr_info("CPU#%d: status: %016llx\n", cpu, status); | |
1125 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); | |
1126 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); | |
ca037701 | 1127 | pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs); |
f87ad35d | 1128 | } |
7645a24c | 1129 | pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); |
241771ef | 1130 | |
948b1bb8 | 1131 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
41bf4989 RR |
1132 | rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl); |
1133 | rdmsrl(x86_pmu_event_addr(idx), pmc_count); | |
241771ef | 1134 | |
245b2e70 | 1135 | prev_left = per_cpu(pmc_prev_left[idx], cpu); |
241771ef | 1136 | |
a1ef58f4 | 1137 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 1138 | cpu, idx, pmc_ctrl); |
a1ef58f4 | 1139 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 1140 | cpu, idx, pmc_count); |
a1ef58f4 | 1141 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 1142 | cpu, idx, prev_left); |
241771ef | 1143 | } |
948b1bb8 | 1144 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { |
2f18d1e8 IM |
1145 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
1146 | ||
a1ef58f4 | 1147 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
2f18d1e8 IM |
1148 | cpu, idx, pmc_count); |
1149 | } | |
5bb9efe3 | 1150 | local_irq_restore(flags); |
241771ef IM |
1151 | } |
1152 | ||
de0428a7 | 1153 | void x86_pmu_stop(struct perf_event *event, int flags) |
241771ef | 1154 | { |
89cbc767 | 1155 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
cdd6c482 | 1156 | struct hw_perf_event *hwc = &event->hw; |
241771ef | 1157 | |
a4eaf7f1 PZ |
1158 | if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) { |
1159 | x86_pmu.disable(event); | |
1160 | cpuc->events[hwc->idx] = NULL; | |
1161 | WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); | |
1162 | hwc->state |= PERF_HES_STOPPED; | |
1163 | } | |
30dd568c | 1164 | |
a4eaf7f1 PZ |
1165 | if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { |
1166 | /* | |
1167 | * Drain the remaining delta count out of a event | |
1168 | * that we are disabling: | |
1169 | */ | |
1170 | x86_perf_event_update(event); | |
1171 | hwc->state |= PERF_HES_UPTODATE; | |
1172 | } | |
2e841873 PZ |
1173 | } |
1174 | ||
a4eaf7f1 | 1175 | static void x86_pmu_del(struct perf_event *event, int flags) |
2e841873 | 1176 | { |
89cbc767 | 1177 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
2e841873 PZ |
1178 | int i; |
1179 | ||
2f7f73a5 SE |
1180 | /* |
1181 | * event is descheduled | |
1182 | */ | |
1183 | event->hw.flags &= ~PERF_X86_EVENT_COMMITTED; | |
1184 | ||
90151c35 SE |
1185 | /* |
1186 | * If we're called during a txn, we don't need to do anything. | |
1187 | * The events never got scheduled and ->cancel_txn will truncate | |
1188 | * the event_list. | |
c347a2f1 PZ |
1189 | * |
1190 | * XXX assumes any ->del() called during a TXN will only be on | |
1191 | * an event added during that same TXN. | |
90151c35 | 1192 | */ |
8d2cacbb | 1193 | if (cpuc->group_flag & PERF_EVENT_TXN) |
90151c35 SE |
1194 | return; |
1195 | ||
c347a2f1 PZ |
1196 | /* |
1197 | * Not a TXN, therefore cleanup properly. | |
1198 | */ | |
a4eaf7f1 | 1199 | x86_pmu_stop(event, PERF_EF_UPDATE); |
194002b2 | 1200 | |
1da53e02 | 1201 | for (i = 0; i < cpuc->n_events; i++) { |
c347a2f1 PZ |
1202 | if (event == cpuc->event_list[i]) |
1203 | break; | |
1204 | } | |
1da53e02 | 1205 | |
c347a2f1 PZ |
1206 | if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */ |
1207 | return; | |
26e61e89 | 1208 | |
c347a2f1 PZ |
1209 | /* If we have a newly added event; make sure to decrease n_added. */ |
1210 | if (i >= cpuc->n_events - cpuc->n_added) | |
1211 | --cpuc->n_added; | |
1da53e02 | 1212 | |
c347a2f1 PZ |
1213 | if (x86_pmu.put_event_constraints) |
1214 | x86_pmu.put_event_constraints(cpuc, event); | |
1215 | ||
1216 | /* Delete the array entry. */ | |
1217 | while (++i < cpuc->n_events) | |
1218 | cpuc->event_list[i-1] = cpuc->event_list[i]; | |
1219 | --cpuc->n_events; | |
1da53e02 | 1220 | |
cdd6c482 | 1221 | perf_event_update_userpage(event); |
241771ef IM |
1222 | } |
1223 | ||
de0428a7 | 1224 | int x86_pmu_handle_irq(struct pt_regs *regs) |
a29aa8a7 | 1225 | { |
df1a132b | 1226 | struct perf_sample_data data; |
cdd6c482 IM |
1227 | struct cpu_hw_events *cpuc; |
1228 | struct perf_event *event; | |
11d1578f | 1229 | int idx, handled = 0; |
9029a5e3 IM |
1230 | u64 val; |
1231 | ||
89cbc767 | 1232 | cpuc = this_cpu_ptr(&cpu_hw_events); |
962bf7a6 | 1233 | |
2bce5dac DZ |
1234 | /* |
1235 | * Some chipsets need to unmask the LVTPC in a particular spot | |
1236 | * inside the nmi handler. As a result, the unmasking was pushed | |
1237 | * into all the nmi handlers. | |
1238 | * | |
1239 | * This generic handler doesn't seem to have any issues where the | |
1240 | * unmasking occurs so it was left at the top. | |
1241 | */ | |
1242 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
1243 | ||
948b1bb8 | 1244 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
63e6be6d RR |
1245 | if (!test_bit(idx, cpuc->active_mask)) { |
1246 | /* | |
1247 | * Though we deactivated the counter some cpus | |
1248 | * might still deliver spurious interrupts still | |
1249 | * in flight. Catch them: | |
1250 | */ | |
1251 | if (__test_and_clear_bit(idx, cpuc->running)) | |
1252 | handled++; | |
a29aa8a7 | 1253 | continue; |
63e6be6d | 1254 | } |
962bf7a6 | 1255 | |
cdd6c482 | 1256 | event = cpuc->events[idx]; |
a4016a79 | 1257 | |
cc2ad4ba | 1258 | val = x86_perf_event_update(event); |
948b1bb8 | 1259 | if (val & (1ULL << (x86_pmu.cntval_bits - 1))) |
48e22d56 | 1260 | continue; |
962bf7a6 | 1261 | |
9e350de3 | 1262 | /* |
cdd6c482 | 1263 | * event overflow |
9e350de3 | 1264 | */ |
4177c42a | 1265 | handled++; |
fd0d000b | 1266 | perf_sample_data_init(&data, 0, event->hw.last_period); |
9e350de3 | 1267 | |
07088edb | 1268 | if (!x86_perf_event_set_period(event)) |
e4abb5d4 PZ |
1269 | continue; |
1270 | ||
a8b0ca17 | 1271 | if (perf_event_overflow(event, &data, regs)) |
a4eaf7f1 | 1272 | x86_pmu_stop(event, 0); |
a29aa8a7 | 1273 | } |
962bf7a6 | 1274 | |
9e350de3 PZ |
1275 | if (handled) |
1276 | inc_irq_stat(apic_perf_irqs); | |
1277 | ||
a29aa8a7 RR |
1278 | return handled; |
1279 | } | |
39d81eab | 1280 | |
cdd6c482 | 1281 | void perf_events_lapic_init(void) |
241771ef | 1282 | { |
04da8a43 | 1283 | if (!x86_pmu.apic || !x86_pmu_initialized()) |
241771ef | 1284 | return; |
85cf9dba | 1285 | |
241771ef | 1286 | /* |
c323d95f | 1287 | * Always use NMI for PMU |
241771ef | 1288 | */ |
c323d95f | 1289 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
241771ef IM |
1290 | } |
1291 | ||
9326638c | 1292 | static int |
9c48f1c6 | 1293 | perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs) |
241771ef | 1294 | { |
14c63f17 DH |
1295 | u64 start_clock; |
1296 | u64 finish_clock; | |
e8a923cc | 1297 | int ret; |
14c63f17 | 1298 | |
cdd6c482 | 1299 | if (!atomic_read(&active_events)) |
9c48f1c6 | 1300 | return NMI_DONE; |
4177c42a | 1301 | |
e8a923cc | 1302 | start_clock = sched_clock(); |
14c63f17 | 1303 | ret = x86_pmu.handle_irq(regs); |
e8a923cc | 1304 | finish_clock = sched_clock(); |
14c63f17 DH |
1305 | |
1306 | perf_sample_event_took(finish_clock - start_clock); | |
1307 | ||
1308 | return ret; | |
241771ef | 1309 | } |
9326638c | 1310 | NOKPROBE_SYMBOL(perf_event_nmi_handler); |
241771ef | 1311 | |
de0428a7 KW |
1312 | struct event_constraint emptyconstraint; |
1313 | struct event_constraint unconstrained; | |
f87ad35d | 1314 | |
148f9bb8 | 1315 | static int |
3f6da390 PZ |
1316 | x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) |
1317 | { | |
1318 | unsigned int cpu = (long)hcpu; | |
7fdba1ca | 1319 | struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); |
b38b24ea | 1320 | int ret = NOTIFY_OK; |
3f6da390 PZ |
1321 | |
1322 | switch (action & ~CPU_TASKS_FROZEN) { | |
1323 | case CPU_UP_PREPARE: | |
7fdba1ca | 1324 | cpuc->kfree_on_online = NULL; |
3f6da390 | 1325 | if (x86_pmu.cpu_prepare) |
b38b24ea | 1326 | ret = x86_pmu.cpu_prepare(cpu); |
3f6da390 PZ |
1327 | break; |
1328 | ||
1329 | case CPU_STARTING: | |
0c9d42ed PZ |
1330 | if (x86_pmu.attr_rdpmc) |
1331 | set_in_cr4(X86_CR4_PCE); | |
3f6da390 PZ |
1332 | if (x86_pmu.cpu_starting) |
1333 | x86_pmu.cpu_starting(cpu); | |
1334 | break; | |
1335 | ||
7fdba1ca PZ |
1336 | case CPU_ONLINE: |
1337 | kfree(cpuc->kfree_on_online); | |
1338 | break; | |
1339 | ||
3f6da390 PZ |
1340 | case CPU_DYING: |
1341 | if (x86_pmu.cpu_dying) | |
1342 | x86_pmu.cpu_dying(cpu); | |
1343 | break; | |
1344 | ||
b38b24ea | 1345 | case CPU_UP_CANCELED: |
3f6da390 PZ |
1346 | case CPU_DEAD: |
1347 | if (x86_pmu.cpu_dead) | |
1348 | x86_pmu.cpu_dead(cpu); | |
1349 | break; | |
1350 | ||
1351 | default: | |
1352 | break; | |
1353 | } | |
1354 | ||
b38b24ea | 1355 | return ret; |
3f6da390 PZ |
1356 | } |
1357 | ||
12558038 CG |
1358 | static void __init pmu_check_apic(void) |
1359 | { | |
1360 | if (cpu_has_apic) | |
1361 | return; | |
1362 | ||
1363 | x86_pmu.apic = 0; | |
1364 | pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n"); | |
1365 | pr_info("no hardware sampling interrupt available.\n"); | |
c184c980 VW |
1366 | |
1367 | /* | |
1368 | * If we have a PMU initialized but no APIC | |
1369 | * interrupts, we cannot sample hardware | |
1370 | * events (user-space has to fall back and | |
1371 | * sample via a hrtimer based software event): | |
1372 | */ | |
1373 | pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT; | |
1374 | ||
12558038 CG |
1375 | } |
1376 | ||
641cc938 JO |
1377 | static struct attribute_group x86_pmu_format_group = { |
1378 | .name = "format", | |
1379 | .attrs = NULL, | |
1380 | }; | |
1381 | ||
8300daa2 JO |
1382 | /* |
1383 | * Remove all undefined events (x86_pmu.event_map(id) == 0) | |
1384 | * out of events_attr attributes. | |
1385 | */ | |
1386 | static void __init filter_events(struct attribute **attrs) | |
1387 | { | |
3a54aaa0 SE |
1388 | struct device_attribute *d; |
1389 | struct perf_pmu_events_attr *pmu_attr; | |
8300daa2 JO |
1390 | int i, j; |
1391 | ||
1392 | for (i = 0; attrs[i]; i++) { | |
3a54aaa0 SE |
1393 | d = (struct device_attribute *)attrs[i]; |
1394 | pmu_attr = container_of(d, struct perf_pmu_events_attr, attr); | |
1395 | /* str trumps id */ | |
1396 | if (pmu_attr->event_str) | |
1397 | continue; | |
8300daa2 JO |
1398 | if (x86_pmu.event_map(i)) |
1399 | continue; | |
1400 | ||
1401 | for (j = i; attrs[j]; j++) | |
1402 | attrs[j] = attrs[j + 1]; | |
1403 | ||
1404 | /* Check the shifted attr. */ | |
1405 | i--; | |
1406 | } | |
1407 | } | |
1408 | ||
1a6461b1 AK |
1409 | /* Merge two pointer arrays */ |
1410 | static __init struct attribute **merge_attr(struct attribute **a, struct attribute **b) | |
1411 | { | |
1412 | struct attribute **new; | |
1413 | int j, i; | |
1414 | ||
1415 | for (j = 0; a[j]; j++) | |
1416 | ; | |
1417 | for (i = 0; b[i]; i++) | |
1418 | j++; | |
1419 | j++; | |
1420 | ||
1421 | new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL); | |
1422 | if (!new) | |
1423 | return NULL; | |
1424 | ||
1425 | j = 0; | |
1426 | for (i = 0; a[i]; i++) | |
1427 | new[j++] = a[i]; | |
1428 | for (i = 0; b[i]; i++) | |
1429 | new[j++] = b[i]; | |
1430 | new[j] = NULL; | |
1431 | ||
1432 | return new; | |
1433 | } | |
1434 | ||
f20093ee | 1435 | ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, |
a4747393 JO |
1436 | char *page) |
1437 | { | |
1438 | struct perf_pmu_events_attr *pmu_attr = \ | |
1439 | container_of(attr, struct perf_pmu_events_attr, attr); | |
a4747393 | 1440 | u64 config = x86_pmu.event_map(pmu_attr->id); |
a4747393 | 1441 | |
3a54aaa0 SE |
1442 | /* string trumps id */ |
1443 | if (pmu_attr->event_str) | |
1444 | return sprintf(page, "%s", pmu_attr->event_str); | |
a4747393 | 1445 | |
3a54aaa0 SE |
1446 | return x86_pmu.events_sysfs_show(page, config); |
1447 | } | |
a4747393 JO |
1448 | |
1449 | EVENT_ATTR(cpu-cycles, CPU_CYCLES ); | |
1450 | EVENT_ATTR(instructions, INSTRUCTIONS ); | |
1451 | EVENT_ATTR(cache-references, CACHE_REFERENCES ); | |
1452 | EVENT_ATTR(cache-misses, CACHE_MISSES ); | |
1453 | EVENT_ATTR(branch-instructions, BRANCH_INSTRUCTIONS ); | |
1454 | EVENT_ATTR(branch-misses, BRANCH_MISSES ); | |
1455 | EVENT_ATTR(bus-cycles, BUS_CYCLES ); | |
1456 | EVENT_ATTR(stalled-cycles-frontend, STALLED_CYCLES_FRONTEND ); | |
1457 | EVENT_ATTR(stalled-cycles-backend, STALLED_CYCLES_BACKEND ); | |
1458 | EVENT_ATTR(ref-cycles, REF_CPU_CYCLES ); | |
1459 | ||
1460 | static struct attribute *empty_attrs; | |
1461 | ||
95d18aa2 | 1462 | static struct attribute *events_attr[] = { |
a4747393 JO |
1463 | EVENT_PTR(CPU_CYCLES), |
1464 | EVENT_PTR(INSTRUCTIONS), | |
1465 | EVENT_PTR(CACHE_REFERENCES), | |
1466 | EVENT_PTR(CACHE_MISSES), | |
1467 | EVENT_PTR(BRANCH_INSTRUCTIONS), | |
1468 | EVENT_PTR(BRANCH_MISSES), | |
1469 | EVENT_PTR(BUS_CYCLES), | |
1470 | EVENT_PTR(STALLED_CYCLES_FRONTEND), | |
1471 | EVENT_PTR(STALLED_CYCLES_BACKEND), | |
1472 | EVENT_PTR(REF_CPU_CYCLES), | |
1473 | NULL, | |
1474 | }; | |
1475 | ||
1476 | static struct attribute_group x86_pmu_events_group = { | |
1477 | .name = "events", | |
1478 | .attrs = events_attr, | |
1479 | }; | |
1480 | ||
0bf79d44 | 1481 | ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event) |
43c032fe | 1482 | { |
43c032fe JO |
1483 | u64 umask = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8; |
1484 | u64 cmask = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24; | |
1485 | bool edge = (config & ARCH_PERFMON_EVENTSEL_EDGE); | |
1486 | bool pc = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL); | |
1487 | bool any = (config & ARCH_PERFMON_EVENTSEL_ANY); | |
1488 | bool inv = (config & ARCH_PERFMON_EVENTSEL_INV); | |
1489 | ssize_t ret; | |
1490 | ||
1491 | /* | |
1492 | * We have whole page size to spend and just little data | |
1493 | * to write, so we can safely use sprintf. | |
1494 | */ | |
1495 | ret = sprintf(page, "event=0x%02llx", event); | |
1496 | ||
1497 | if (umask) | |
1498 | ret += sprintf(page + ret, ",umask=0x%02llx", umask); | |
1499 | ||
1500 | if (edge) | |
1501 | ret += sprintf(page + ret, ",edge"); | |
1502 | ||
1503 | if (pc) | |
1504 | ret += sprintf(page + ret, ",pc"); | |
1505 | ||
1506 | if (any) | |
1507 | ret += sprintf(page + ret, ",any"); | |
1508 | ||
1509 | if (inv) | |
1510 | ret += sprintf(page + ret, ",inv"); | |
1511 | ||
1512 | if (cmask) | |
1513 | ret += sprintf(page + ret, ",cmask=0x%02llx", cmask); | |
1514 | ||
1515 | ret += sprintf(page + ret, "\n"); | |
1516 | ||
1517 | return ret; | |
1518 | } | |
1519 | ||
dda99116 | 1520 | static int __init init_hw_perf_events(void) |
b56a3802 | 1521 | { |
c1d6f42f | 1522 | struct x86_pmu_quirk *quirk; |
72eae04d RR |
1523 | int err; |
1524 | ||
cdd6c482 | 1525 | pr_info("Performance Events: "); |
1123e3ad | 1526 | |
b56a3802 JSR |
1527 | switch (boot_cpu_data.x86_vendor) { |
1528 | case X86_VENDOR_INTEL: | |
72eae04d | 1529 | err = intel_pmu_init(); |
b56a3802 | 1530 | break; |
f87ad35d | 1531 | case X86_VENDOR_AMD: |
72eae04d | 1532 | err = amd_pmu_init(); |
f87ad35d | 1533 | break; |
4138960a | 1534 | default: |
8a3da6c7 | 1535 | err = -ENOTSUPP; |
b56a3802 | 1536 | } |
1123e3ad | 1537 | if (err != 0) { |
cdd6c482 | 1538 | pr_cont("no PMU driver, software events only.\n"); |
004417a6 | 1539 | return 0; |
1123e3ad | 1540 | } |
b56a3802 | 1541 | |
12558038 CG |
1542 | pmu_check_apic(); |
1543 | ||
33c6d6a7 | 1544 | /* sanity check that the hardware exists or is emulated */ |
4407204c | 1545 | if (!check_hw_exists()) |
004417a6 | 1546 | return 0; |
33c6d6a7 | 1547 | |
1123e3ad | 1548 | pr_cont("%s PMU driver.\n", x86_pmu.name); |
faa28ae0 | 1549 | |
e97df763 PZ |
1550 | x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */ |
1551 | ||
c1d6f42f PZ |
1552 | for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next) |
1553 | quirk->func(); | |
3c44780b | 1554 | |
a1eac7ac RR |
1555 | if (!x86_pmu.intel_ctrl) |
1556 | x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1; | |
241771ef | 1557 | |
cdd6c482 | 1558 | perf_events_lapic_init(); |
9c48f1c6 | 1559 | register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI"); |
1123e3ad | 1560 | |
63b14649 | 1561 | unconstrained = (struct event_constraint) |
948b1bb8 | 1562 | __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1, |
9fac2cf3 | 1563 | 0, x86_pmu.num_counters, 0, 0); |
63b14649 | 1564 | |
641cc938 | 1565 | x86_pmu_format_group.attrs = x86_pmu.format_attrs; |
0c9d42ed | 1566 | |
f20093ee SE |
1567 | if (x86_pmu.event_attrs) |
1568 | x86_pmu_events_group.attrs = x86_pmu.event_attrs; | |
1569 | ||
a4747393 JO |
1570 | if (!x86_pmu.events_sysfs_show) |
1571 | x86_pmu_events_group.attrs = &empty_attrs; | |
8300daa2 JO |
1572 | else |
1573 | filter_events(x86_pmu_events_group.attrs); | |
a4747393 | 1574 | |
1a6461b1 AK |
1575 | if (x86_pmu.cpu_events) { |
1576 | struct attribute **tmp; | |
1577 | ||
1578 | tmp = merge_attr(x86_pmu_events_group.attrs, x86_pmu.cpu_events); | |
1579 | if (!WARN_ON(!tmp)) | |
1580 | x86_pmu_events_group.attrs = tmp; | |
1581 | } | |
1582 | ||
57c0c15b | 1583 | pr_info("... version: %d\n", x86_pmu.version); |
948b1bb8 RR |
1584 | pr_info("... bit width: %d\n", x86_pmu.cntval_bits); |
1585 | pr_info("... generic registers: %d\n", x86_pmu.num_counters); | |
1586 | pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask); | |
57c0c15b | 1587 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); |
948b1bb8 | 1588 | pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed); |
d6dc0b4e | 1589 | pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl); |
3f6da390 | 1590 | |
2e80a82a | 1591 | perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); |
3f6da390 | 1592 | perf_cpu_notifier(x86_pmu_notifier); |
004417a6 PZ |
1593 | |
1594 | return 0; | |
241771ef | 1595 | } |
004417a6 | 1596 | early_initcall(init_hw_perf_events); |
621a01ea | 1597 | |
cdd6c482 | 1598 | static inline void x86_pmu_read(struct perf_event *event) |
ee06094f | 1599 | { |
cc2ad4ba | 1600 | x86_perf_event_update(event); |
ee06094f IM |
1601 | } |
1602 | ||
4d1c52b0 LM |
1603 | /* |
1604 | * Start group events scheduling transaction | |
1605 | * Set the flag to make pmu::enable() not perform the | |
1606 | * schedulability test, it will be performed at commit time | |
1607 | */ | |
51b0fe39 | 1608 | static void x86_pmu_start_txn(struct pmu *pmu) |
4d1c52b0 | 1609 | { |
33696fc0 | 1610 | perf_pmu_disable(pmu); |
0a3aee0d TH |
1611 | __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN); |
1612 | __this_cpu_write(cpu_hw_events.n_txn, 0); | |
4d1c52b0 LM |
1613 | } |
1614 | ||
1615 | /* | |
1616 | * Stop group events scheduling transaction | |
1617 | * Clear the flag and pmu::enable() will perform the | |
1618 | * schedulability test. | |
1619 | */ | |
51b0fe39 | 1620 | static void x86_pmu_cancel_txn(struct pmu *pmu) |
4d1c52b0 | 1621 | { |
0a3aee0d | 1622 | __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN); |
90151c35 | 1623 | /* |
c347a2f1 PZ |
1624 | * Truncate collected array by the number of events added in this |
1625 | * transaction. See x86_pmu_add() and x86_pmu_*_txn(). | |
90151c35 | 1626 | */ |
0a3aee0d TH |
1627 | __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn)); |
1628 | __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn)); | |
33696fc0 | 1629 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1630 | } |
1631 | ||
1632 | /* | |
1633 | * Commit group events scheduling transaction | |
1634 | * Perform the group schedulability test as a whole | |
1635 | * Return 0 if success | |
c347a2f1 PZ |
1636 | * |
1637 | * Does not cancel the transaction on failure; expects the caller to do this. | |
4d1c52b0 | 1638 | */ |
51b0fe39 | 1639 | static int x86_pmu_commit_txn(struct pmu *pmu) |
4d1c52b0 | 1640 | { |
89cbc767 | 1641 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
4d1c52b0 LM |
1642 | int assign[X86_PMC_IDX_MAX]; |
1643 | int n, ret; | |
1644 | ||
1645 | n = cpuc->n_events; | |
1646 | ||
1647 | if (!x86_pmu_initialized()) | |
1648 | return -EAGAIN; | |
1649 | ||
1650 | ret = x86_pmu.schedule_events(cpuc, n, assign); | |
1651 | if (ret) | |
1652 | return ret; | |
1653 | ||
1654 | /* | |
1655 | * copy new assignment, now we know it is possible | |
1656 | * will be used by hw_perf_enable() | |
1657 | */ | |
1658 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
1659 | ||
8d2cacbb | 1660 | cpuc->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 1661 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1662 | return 0; |
1663 | } | |
cd8a38d3 SE |
1664 | /* |
1665 | * a fake_cpuc is used to validate event groups. Due to | |
1666 | * the extra reg logic, we need to also allocate a fake | |
1667 | * per_core and per_cpu structure. Otherwise, group events | |
1668 | * using extra reg may conflict without the kernel being | |
1669 | * able to catch this when the last event gets added to | |
1670 | * the group. | |
1671 | */ | |
1672 | static void free_fake_cpuc(struct cpu_hw_events *cpuc) | |
1673 | { | |
1674 | kfree(cpuc->shared_regs); | |
1675 | kfree(cpuc); | |
1676 | } | |
1677 | ||
1678 | static struct cpu_hw_events *allocate_fake_cpuc(void) | |
1679 | { | |
1680 | struct cpu_hw_events *cpuc; | |
1681 | int cpu = raw_smp_processor_id(); | |
1682 | ||
1683 | cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL); | |
1684 | if (!cpuc) | |
1685 | return ERR_PTR(-ENOMEM); | |
1686 | ||
1687 | /* only needed, if we have extra_regs */ | |
1688 | if (x86_pmu.extra_regs) { | |
1689 | cpuc->shared_regs = allocate_shared_regs(cpu); | |
1690 | if (!cpuc->shared_regs) | |
1691 | goto error; | |
1692 | } | |
b430f7c4 | 1693 | cpuc->is_fake = 1; |
cd8a38d3 SE |
1694 | return cpuc; |
1695 | error: | |
1696 | free_fake_cpuc(cpuc); | |
1697 | return ERR_PTR(-ENOMEM); | |
1698 | } | |
4d1c52b0 | 1699 | |
ca037701 PZ |
1700 | /* |
1701 | * validate that we can schedule this event | |
1702 | */ | |
1703 | static int validate_event(struct perf_event *event) | |
1704 | { | |
1705 | struct cpu_hw_events *fake_cpuc; | |
1706 | struct event_constraint *c; | |
1707 | int ret = 0; | |
1708 | ||
cd8a38d3 SE |
1709 | fake_cpuc = allocate_fake_cpuc(); |
1710 | if (IS_ERR(fake_cpuc)) | |
1711 | return PTR_ERR(fake_cpuc); | |
ca037701 PZ |
1712 | |
1713 | c = x86_pmu.get_event_constraints(fake_cpuc, event); | |
1714 | ||
1715 | if (!c || !c->weight) | |
aa2bc1ad | 1716 | ret = -EINVAL; |
ca037701 PZ |
1717 | |
1718 | if (x86_pmu.put_event_constraints) | |
1719 | x86_pmu.put_event_constraints(fake_cpuc, event); | |
1720 | ||
cd8a38d3 | 1721 | free_fake_cpuc(fake_cpuc); |
ca037701 PZ |
1722 | |
1723 | return ret; | |
1724 | } | |
1725 | ||
1da53e02 SE |
1726 | /* |
1727 | * validate a single event group | |
1728 | * | |
1729 | * validation include: | |
184f412c IM |
1730 | * - check events are compatible which each other |
1731 | * - events do not compete for the same counter | |
1732 | * - number of events <= number of counters | |
1da53e02 SE |
1733 | * |
1734 | * validation ensures the group can be loaded onto the | |
1735 | * PMU if it was the only group available. | |
1736 | */ | |
fe9081cc PZ |
1737 | static int validate_group(struct perf_event *event) |
1738 | { | |
1da53e02 | 1739 | struct perf_event *leader = event->group_leader; |
502568d5 | 1740 | struct cpu_hw_events *fake_cpuc; |
aa2bc1ad | 1741 | int ret = -EINVAL, n; |
fe9081cc | 1742 | |
cd8a38d3 SE |
1743 | fake_cpuc = allocate_fake_cpuc(); |
1744 | if (IS_ERR(fake_cpuc)) | |
1745 | return PTR_ERR(fake_cpuc); | |
1da53e02 SE |
1746 | /* |
1747 | * the event is not yet connected with its | |
1748 | * siblings therefore we must first collect | |
1749 | * existing siblings, then add the new event | |
1750 | * before we can simulate the scheduling | |
1751 | */ | |
502568d5 | 1752 | n = collect_events(fake_cpuc, leader, true); |
1da53e02 | 1753 | if (n < 0) |
cd8a38d3 | 1754 | goto out; |
fe9081cc | 1755 | |
502568d5 PZ |
1756 | fake_cpuc->n_events = n; |
1757 | n = collect_events(fake_cpuc, event, false); | |
1da53e02 | 1758 | if (n < 0) |
cd8a38d3 | 1759 | goto out; |
fe9081cc | 1760 | |
502568d5 | 1761 | fake_cpuc->n_events = n; |
1da53e02 | 1762 | |
a072738e | 1763 | ret = x86_pmu.schedule_events(fake_cpuc, n, NULL); |
502568d5 | 1764 | |
502568d5 | 1765 | out: |
cd8a38d3 | 1766 | free_fake_cpuc(fake_cpuc); |
502568d5 | 1767 | return ret; |
fe9081cc PZ |
1768 | } |
1769 | ||
dda99116 | 1770 | static int x86_pmu_event_init(struct perf_event *event) |
621a01ea | 1771 | { |
51b0fe39 | 1772 | struct pmu *tmp; |
621a01ea IM |
1773 | int err; |
1774 | ||
b0a873eb PZ |
1775 | switch (event->attr.type) { |
1776 | case PERF_TYPE_RAW: | |
1777 | case PERF_TYPE_HARDWARE: | |
1778 | case PERF_TYPE_HW_CACHE: | |
1779 | break; | |
1780 | ||
1781 | default: | |
1782 | return -ENOENT; | |
1783 | } | |
1784 | ||
1785 | err = __x86_pmu_event_init(event); | |
fe9081cc | 1786 | if (!err) { |
8113070d SE |
1787 | /* |
1788 | * we temporarily connect event to its pmu | |
1789 | * such that validate_group() can classify | |
1790 | * it as an x86 event using is_x86_event() | |
1791 | */ | |
1792 | tmp = event->pmu; | |
1793 | event->pmu = &pmu; | |
1794 | ||
fe9081cc PZ |
1795 | if (event->group_leader != event) |
1796 | err = validate_group(event); | |
ca037701 PZ |
1797 | else |
1798 | err = validate_event(event); | |
8113070d SE |
1799 | |
1800 | event->pmu = tmp; | |
fe9081cc | 1801 | } |
a1792cda | 1802 | if (err) { |
cdd6c482 IM |
1803 | if (event->destroy) |
1804 | event->destroy(event); | |
a1792cda | 1805 | } |
621a01ea | 1806 | |
b0a873eb | 1807 | return err; |
621a01ea | 1808 | } |
d7d59fb3 | 1809 | |
fe4a3308 PZ |
1810 | static int x86_pmu_event_idx(struct perf_event *event) |
1811 | { | |
1812 | int idx = event->hw.idx; | |
1813 | ||
c7206205 PZ |
1814 | if (!x86_pmu.attr_rdpmc) |
1815 | return 0; | |
1816 | ||
15c7ad51 RR |
1817 | if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) { |
1818 | idx -= INTEL_PMC_IDX_FIXED; | |
fe4a3308 PZ |
1819 | idx |= 1 << 30; |
1820 | } | |
1821 | ||
1822 | return idx + 1; | |
1823 | } | |
1824 | ||
0c9d42ed PZ |
1825 | static ssize_t get_attr_rdpmc(struct device *cdev, |
1826 | struct device_attribute *attr, | |
1827 | char *buf) | |
1828 | { | |
1829 | return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc); | |
1830 | } | |
1831 | ||
1832 | static void change_rdpmc(void *info) | |
1833 | { | |
1834 | bool enable = !!(unsigned long)info; | |
1835 | ||
1836 | if (enable) | |
1837 | set_in_cr4(X86_CR4_PCE); | |
1838 | else | |
1839 | clear_in_cr4(X86_CR4_PCE); | |
1840 | } | |
1841 | ||
1842 | static ssize_t set_attr_rdpmc(struct device *cdev, | |
1843 | struct device_attribute *attr, | |
1844 | const char *buf, size_t count) | |
1845 | { | |
e2b297fc SK |
1846 | unsigned long val; |
1847 | ssize_t ret; | |
1848 | ||
1849 | ret = kstrtoul(buf, 0, &val); | |
1850 | if (ret) | |
1851 | return ret; | |
e97df763 PZ |
1852 | |
1853 | if (x86_pmu.attr_rdpmc_broken) | |
1854 | return -ENOTSUPP; | |
0c9d42ed PZ |
1855 | |
1856 | if (!!val != !!x86_pmu.attr_rdpmc) { | |
1857 | x86_pmu.attr_rdpmc = !!val; | |
0e9f2204 | 1858 | on_each_cpu(change_rdpmc, (void *)val, 1); |
0c9d42ed PZ |
1859 | } |
1860 | ||
1861 | return count; | |
1862 | } | |
1863 | ||
1864 | static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc); | |
1865 | ||
1866 | static struct attribute *x86_pmu_attrs[] = { | |
1867 | &dev_attr_rdpmc.attr, | |
1868 | NULL, | |
1869 | }; | |
1870 | ||
1871 | static struct attribute_group x86_pmu_attr_group = { | |
1872 | .attrs = x86_pmu_attrs, | |
1873 | }; | |
1874 | ||
1875 | static const struct attribute_group *x86_pmu_attr_groups[] = { | |
1876 | &x86_pmu_attr_group, | |
641cc938 | 1877 | &x86_pmu_format_group, |
a4747393 | 1878 | &x86_pmu_events_group, |
0c9d42ed PZ |
1879 | NULL, |
1880 | }; | |
1881 | ||
d010b332 SE |
1882 | static void x86_pmu_flush_branch_stack(void) |
1883 | { | |
1884 | if (x86_pmu.flush_branch_stack) | |
1885 | x86_pmu.flush_branch_stack(); | |
1886 | } | |
1887 | ||
c93dc84c PZ |
1888 | void perf_check_microcode(void) |
1889 | { | |
1890 | if (x86_pmu.check_microcode) | |
1891 | x86_pmu.check_microcode(); | |
1892 | } | |
1893 | EXPORT_SYMBOL_GPL(perf_check_microcode); | |
1894 | ||
b0a873eb | 1895 | static struct pmu pmu = { |
d010b332 SE |
1896 | .pmu_enable = x86_pmu_enable, |
1897 | .pmu_disable = x86_pmu_disable, | |
a4eaf7f1 | 1898 | |
c93dc84c | 1899 | .attr_groups = x86_pmu_attr_groups, |
0c9d42ed | 1900 | |
c93dc84c | 1901 | .event_init = x86_pmu_event_init, |
a4eaf7f1 | 1902 | |
d010b332 SE |
1903 | .add = x86_pmu_add, |
1904 | .del = x86_pmu_del, | |
1905 | .start = x86_pmu_start, | |
1906 | .stop = x86_pmu_stop, | |
1907 | .read = x86_pmu_read, | |
a4eaf7f1 | 1908 | |
c93dc84c PZ |
1909 | .start_txn = x86_pmu_start_txn, |
1910 | .cancel_txn = x86_pmu_cancel_txn, | |
1911 | .commit_txn = x86_pmu_commit_txn, | |
fe4a3308 | 1912 | |
c93dc84c | 1913 | .event_idx = x86_pmu_event_idx, |
d010b332 | 1914 | .flush_branch_stack = x86_pmu_flush_branch_stack, |
b0a873eb PZ |
1915 | }; |
1916 | ||
c7206205 | 1917 | void arch_perf_update_userpage(struct perf_event_mmap_page *userpg, u64 now) |
e3f3541c | 1918 | { |
20d1c86a PZ |
1919 | struct cyc2ns_data *data; |
1920 | ||
fa731587 PZ |
1921 | userpg->cap_user_time = 0; |
1922 | userpg->cap_user_time_zero = 0; | |
1923 | userpg->cap_user_rdpmc = x86_pmu.attr_rdpmc; | |
c7206205 PZ |
1924 | userpg->pmc_width = x86_pmu.cntval_bits; |
1925 | ||
35af99e6 | 1926 | if (!sched_clock_stable()) |
e3f3541c PZ |
1927 | return; |
1928 | ||
20d1c86a PZ |
1929 | data = cyc2ns_read_begin(); |
1930 | ||
fa731587 | 1931 | userpg->cap_user_time = 1; |
20d1c86a PZ |
1932 | userpg->time_mult = data->cyc2ns_mul; |
1933 | userpg->time_shift = data->cyc2ns_shift; | |
1934 | userpg->time_offset = data->cyc2ns_offset - now; | |
c73deb6a | 1935 | |
d8b11a0c | 1936 | userpg->cap_user_time_zero = 1; |
20d1c86a PZ |
1937 | userpg->time_zero = data->cyc2ns_offset; |
1938 | ||
1939 | cyc2ns_read_end(data); | |
e3f3541c PZ |
1940 | } |
1941 | ||
d7d59fb3 PZ |
1942 | /* |
1943 | * callchain support | |
1944 | */ | |
1945 | ||
d7d59fb3 PZ |
1946 | static int backtrace_stack(void *data, char *name) |
1947 | { | |
038e836e | 1948 | return 0; |
d7d59fb3 PZ |
1949 | } |
1950 | ||
1951 | static void backtrace_address(void *data, unsigned long addr, int reliable) | |
1952 | { | |
1953 | struct perf_callchain_entry *entry = data; | |
1954 | ||
70791ce9 | 1955 | perf_callchain_store(entry, addr); |
d7d59fb3 PZ |
1956 | } |
1957 | ||
1958 | static const struct stacktrace_ops backtrace_ops = { | |
d7d59fb3 PZ |
1959 | .stack = backtrace_stack, |
1960 | .address = backtrace_address, | |
06d65bda | 1961 | .walk_stack = print_context_stack_bp, |
d7d59fb3 PZ |
1962 | }; |
1963 | ||
56962b44 FW |
1964 | void |
1965 | perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 | 1966 | { |
927c7a9e FW |
1967 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
1968 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 1969 | return; |
927c7a9e FW |
1970 | } |
1971 | ||
70791ce9 | 1972 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 1973 | |
e8e999cf | 1974 | dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry); |
d7d59fb3 PZ |
1975 | } |
1976 | ||
bc6ca7b3 AS |
1977 | static inline int |
1978 | valid_user_frame(const void __user *fp, unsigned long size) | |
1979 | { | |
1980 | return (__range_not_ok(fp, size, TASK_SIZE) == 0); | |
1981 | } | |
1982 | ||
d07bdfd3 PZ |
1983 | static unsigned long get_segment_base(unsigned int segment) |
1984 | { | |
1985 | struct desc_struct *desc; | |
1986 | int idx = segment >> 3; | |
1987 | ||
1988 | if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) { | |
1989 | if (idx > LDT_ENTRIES) | |
1990 | return 0; | |
1991 | ||
1992 | if (idx > current->active_mm->context.size) | |
1993 | return 0; | |
1994 | ||
1995 | desc = current->active_mm->context.ldt; | |
1996 | } else { | |
1997 | if (idx > GDT_ENTRIES) | |
1998 | return 0; | |
1999 | ||
89cbc767 | 2000 | desc = raw_cpu_ptr(gdt_page.gdt); |
d07bdfd3 PZ |
2001 | } |
2002 | ||
2003 | return get_desc_base(desc + idx); | |
2004 | } | |
2005 | ||
257ef9d2 | 2006 | #ifdef CONFIG_COMPAT |
d1a797f3 PA |
2007 | |
2008 | #include <asm/compat.h> | |
2009 | ||
257ef9d2 TE |
2010 | static inline int |
2011 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
74193ef0 | 2012 | { |
257ef9d2 | 2013 | /* 32-bit process in 64-bit kernel. */ |
d07bdfd3 | 2014 | unsigned long ss_base, cs_base; |
257ef9d2 TE |
2015 | struct stack_frame_ia32 frame; |
2016 | const void __user *fp; | |
74193ef0 | 2017 | |
257ef9d2 TE |
2018 | if (!test_thread_flag(TIF_IA32)) |
2019 | return 0; | |
2020 | ||
d07bdfd3 PZ |
2021 | cs_base = get_segment_base(regs->cs); |
2022 | ss_base = get_segment_base(regs->ss); | |
2023 | ||
2024 | fp = compat_ptr(ss_base + regs->bp); | |
257ef9d2 TE |
2025 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
2026 | unsigned long bytes; | |
2027 | frame.next_frame = 0; | |
2028 | frame.return_address = 0; | |
2029 | ||
2030 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); | |
0a196848 | 2031 | if (bytes != 0) |
257ef9d2 | 2032 | break; |
74193ef0 | 2033 | |
bc6ca7b3 AS |
2034 | if (!valid_user_frame(fp, sizeof(frame))) |
2035 | break; | |
2036 | ||
d07bdfd3 PZ |
2037 | perf_callchain_store(entry, cs_base + frame.return_address); |
2038 | fp = compat_ptr(ss_base + frame.next_frame); | |
257ef9d2 TE |
2039 | } |
2040 | return 1; | |
d7d59fb3 | 2041 | } |
257ef9d2 TE |
2042 | #else |
2043 | static inline int | |
2044 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
2045 | { | |
2046 | return 0; | |
2047 | } | |
2048 | #endif | |
d7d59fb3 | 2049 | |
56962b44 FW |
2050 | void |
2051 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 PZ |
2052 | { |
2053 | struct stack_frame frame; | |
2054 | const void __user *fp; | |
2055 | ||
927c7a9e FW |
2056 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
2057 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 2058 | return; |
927c7a9e | 2059 | } |
5a6cec3a | 2060 | |
d07bdfd3 PZ |
2061 | /* |
2062 | * We don't know what to do with VM86 stacks.. ignore them for now. | |
2063 | */ | |
2064 | if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM)) | |
2065 | return; | |
2066 | ||
74193ef0 | 2067 | fp = (void __user *)regs->bp; |
d7d59fb3 | 2068 | |
70791ce9 | 2069 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 2070 | |
20afc60f AV |
2071 | if (!current->mm) |
2072 | return; | |
2073 | ||
257ef9d2 TE |
2074 | if (perf_callchain_user32(regs, entry)) |
2075 | return; | |
2076 | ||
f9188e02 | 2077 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
257ef9d2 | 2078 | unsigned long bytes; |
038e836e | 2079 | frame.next_frame = NULL; |
d7d59fb3 PZ |
2080 | frame.return_address = 0; |
2081 | ||
257ef9d2 | 2082 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); |
0a196848 | 2083 | if (bytes != 0) |
d7d59fb3 PZ |
2084 | break; |
2085 | ||
bc6ca7b3 AS |
2086 | if (!valid_user_frame(fp, sizeof(frame))) |
2087 | break; | |
2088 | ||
70791ce9 | 2089 | perf_callchain_store(entry, frame.return_address); |
038e836e | 2090 | fp = frame.next_frame; |
d7d59fb3 PZ |
2091 | } |
2092 | } | |
2093 | ||
d07bdfd3 PZ |
2094 | /* |
2095 | * Deal with code segment offsets for the various execution modes: | |
2096 | * | |
2097 | * VM86 - the good olde 16 bit days, where the linear address is | |
2098 | * 20 bits and we use regs->ip + 0x10 * regs->cs. | |
2099 | * | |
2100 | * IA32 - Where we need to look at GDT/LDT segment descriptor tables | |
2101 | * to figure out what the 32bit base address is. | |
2102 | * | |
2103 | * X32 - has TIF_X32 set, but is running in x86_64 | |
2104 | * | |
2105 | * X86_64 - CS,DS,SS,ES are all zero based. | |
2106 | */ | |
2107 | static unsigned long code_segment_base(struct pt_regs *regs) | |
39447b38 | 2108 | { |
d07bdfd3 PZ |
2109 | /* |
2110 | * If we are in VM86 mode, add the segment offset to convert to a | |
2111 | * linear address. | |
2112 | */ | |
2113 | if (regs->flags & X86_VM_MASK) | |
2114 | return 0x10 * regs->cs; | |
2115 | ||
2116 | /* | |
2117 | * For IA32 we look at the GDT/LDT segment base to convert the | |
2118 | * effective IP to a linear address. | |
2119 | */ | |
2120 | #ifdef CONFIG_X86_32 | |
2121 | if (user_mode(regs) && regs->cs != __USER_CS) | |
2122 | return get_segment_base(regs->cs); | |
2123 | #else | |
2124 | if (test_thread_flag(TIF_IA32)) { | |
2125 | if (user_mode(regs) && regs->cs != __USER32_CS) | |
2126 | return get_segment_base(regs->cs); | |
2127 | } | |
2128 | #endif | |
2129 | return 0; | |
2130 | } | |
dcf46b94 | 2131 | |
d07bdfd3 PZ |
2132 | unsigned long perf_instruction_pointer(struct pt_regs *regs) |
2133 | { | |
39447b38 | 2134 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) |
d07bdfd3 | 2135 | return perf_guest_cbs->get_guest_ip(); |
dcf46b94 | 2136 | |
d07bdfd3 | 2137 | return regs->ip + code_segment_base(regs); |
39447b38 ZY |
2138 | } |
2139 | ||
2140 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
2141 | { | |
2142 | int misc = 0; | |
dcf46b94 | 2143 | |
39447b38 | 2144 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
dcf46b94 ZY |
2145 | if (perf_guest_cbs->is_user_mode()) |
2146 | misc |= PERF_RECORD_MISC_GUEST_USER; | |
2147 | else | |
2148 | misc |= PERF_RECORD_MISC_GUEST_KERNEL; | |
2149 | } else { | |
d07bdfd3 | 2150 | if (user_mode(regs)) |
dcf46b94 ZY |
2151 | misc |= PERF_RECORD_MISC_USER; |
2152 | else | |
2153 | misc |= PERF_RECORD_MISC_KERNEL; | |
2154 | } | |
2155 | ||
39447b38 | 2156 | if (regs->flags & PERF_EFLAGS_EXACT) |
ab608344 | 2157 | misc |= PERF_RECORD_MISC_EXACT_IP; |
39447b38 ZY |
2158 | |
2159 | return misc; | |
2160 | } | |
b3d9468a GN |
2161 | |
2162 | void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap) | |
2163 | { | |
2164 | cap->version = x86_pmu.version; | |
2165 | cap->num_counters_gp = x86_pmu.num_counters; | |
2166 | cap->num_counters_fixed = x86_pmu.num_counters_fixed; | |
2167 | cap->bit_width_gp = x86_pmu.cntval_bits; | |
2168 | cap->bit_width_fixed = x86_pmu.cntval_bits; | |
2169 | cap->events_mask = (unsigned int)x86_pmu.events_maskl; | |
2170 | cap->events_mask_len = x86_pmu.events_mask_len; | |
2171 | } | |
2172 | EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability); |