Commit | Line | Data |
---|---|---|
241771ef | 1 | /* |
cdd6c482 | 2 | * Performance events x86 architecture code |
241771ef | 3 | * |
98144511 IM |
4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> | |
30dd568c | 9 | * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> |
1da53e02 | 10 | * Copyright (C) 2009 Google, Inc., Stephane Eranian |
241771ef IM |
11 | * |
12 | * For licencing details see kernel-base/COPYING | |
13 | */ | |
14 | ||
cdd6c482 | 15 | #include <linux/perf_event.h> |
241771ef IM |
16 | #include <linux/capability.h> |
17 | #include <linux/notifier.h> | |
18 | #include <linux/hardirq.h> | |
19 | #include <linux/kprobes.h> | |
4ac13294 | 20 | #include <linux/module.h> |
241771ef IM |
21 | #include <linux/kdebug.h> |
22 | #include <linux/sched.h> | |
d7d59fb3 | 23 | #include <linux/uaccess.h> |
74193ef0 | 24 | #include <linux/highmem.h> |
30dd568c | 25 | #include <linux/cpu.h> |
272d30be | 26 | #include <linux/bitops.h> |
241771ef | 27 | |
241771ef | 28 | #include <asm/apic.h> |
d7d59fb3 | 29 | #include <asm/stacktrace.h> |
4e935e47 | 30 | #include <asm/nmi.h> |
241771ef | 31 | |
7645a24c PZ |
32 | #if 0 |
33 | #undef wrmsrl | |
34 | #define wrmsrl(msr, val) \ | |
35 | do { \ | |
36 | trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\ | |
37 | (unsigned long)(val)); \ | |
38 | native_write_msr((msr), (u32)((u64)(val)), \ | |
39 | (u32)((u64)(val) >> 32)); \ | |
40 | } while (0) | |
41 | #endif | |
42 | ||
ef21f683 PZ |
43 | /* |
44 | * best effort, GUP based copy_from_user() that assumes IRQ or NMI context | |
45 | */ | |
46 | static unsigned long | |
47 | copy_from_user_nmi(void *to, const void __user *from, unsigned long n) | |
48 | { | |
49 | unsigned long offset, addr = (unsigned long)from; | |
50 | int type = in_nmi() ? KM_NMI : KM_IRQ0; | |
51 | unsigned long size, len = 0; | |
52 | struct page *page; | |
53 | void *map; | |
54 | int ret; | |
55 | ||
56 | do { | |
57 | ret = __get_user_pages_fast(addr, 1, 0, &page); | |
58 | if (!ret) | |
59 | break; | |
60 | ||
61 | offset = addr & (PAGE_SIZE - 1); | |
62 | size = min(PAGE_SIZE - offset, n - len); | |
63 | ||
64 | map = kmap_atomic(page, type); | |
65 | memcpy(to, map+offset, size); | |
66 | kunmap_atomic(map, type); | |
67 | put_page(page); | |
68 | ||
69 | len += size; | |
70 | to += size; | |
71 | addr += size; | |
72 | ||
73 | } while (len < n); | |
74 | ||
75 | return len; | |
76 | } | |
77 | ||
cdd6c482 | 78 | static u64 perf_event_mask __read_mostly; |
703e937c | 79 | |
1da53e02 | 80 | struct event_constraint { |
c91e0f5d PZ |
81 | union { |
82 | unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
b622d644 | 83 | u64 idxmsk64; |
c91e0f5d | 84 | }; |
b622d644 PZ |
85 | u64 code; |
86 | u64 cmask; | |
272d30be | 87 | int weight; |
1da53e02 SE |
88 | }; |
89 | ||
38331f62 SE |
90 | struct amd_nb { |
91 | int nb_id; /* NorthBridge id */ | |
92 | int refcnt; /* reference count */ | |
93 | struct perf_event *owners[X86_PMC_IDX_MAX]; | |
94 | struct event_constraint event_constraints[X86_PMC_IDX_MAX]; | |
95 | }; | |
96 | ||
caff2bef PZ |
97 | #define MAX_LBR_ENTRIES 16 |
98 | ||
cdd6c482 | 99 | struct cpu_hw_events { |
ca037701 PZ |
100 | /* |
101 | * Generic x86 PMC bits | |
102 | */ | |
1da53e02 | 103 | struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */ |
43f6201a | 104 | unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
4b39fd96 | 105 | unsigned long interrupts; |
b0f3f28e | 106 | int enabled; |
241771ef | 107 | |
1da53e02 SE |
108 | int n_events; |
109 | int n_added; | |
110 | int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */ | |
447a194b | 111 | u64 tags[X86_PMC_IDX_MAX]; |
1da53e02 | 112 | struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */ |
ca037701 PZ |
113 | |
114 | /* | |
115 | * Intel DebugStore bits | |
116 | */ | |
117 | struct debug_store *ds; | |
118 | u64 pebs_enabled; | |
119 | ||
caff2bef PZ |
120 | /* |
121 | * Intel LBR bits | |
122 | */ | |
123 | int lbr_users; | |
124 | void *lbr_context; | |
125 | struct perf_branch_stack lbr_stack; | |
126 | struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES]; | |
127 | ||
ca037701 PZ |
128 | /* |
129 | * AMD specific bits | |
130 | */ | |
38331f62 | 131 | struct amd_nb *amd_nb; |
b690081d SE |
132 | }; |
133 | ||
fce877e3 | 134 | #define __EVENT_CONSTRAINT(c, n, m, w) {\ |
b622d644 | 135 | { .idxmsk64 = (n) }, \ |
c91e0f5d PZ |
136 | .code = (c), \ |
137 | .cmask = (m), \ | |
fce877e3 | 138 | .weight = (w), \ |
c91e0f5d | 139 | } |
b690081d | 140 | |
fce877e3 PZ |
141 | #define EVENT_CONSTRAINT(c, n, m) \ |
142 | __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n)) | |
143 | ||
ca037701 PZ |
144 | /* |
145 | * Constraint on the Event code. | |
146 | */ | |
ed8777fc PZ |
147 | #define INTEL_EVENT_CONSTRAINT(c, n) \ |
148 | EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVTSEL_MASK) | |
8433be11 | 149 | |
ca037701 PZ |
150 | /* |
151 | * Constraint on the Event code + UMask + fixed-mask | |
152 | */ | |
ed8777fc | 153 | #define FIXED_EVENT_CONSTRAINT(c, n) \ |
b622d644 | 154 | EVENT_CONSTRAINT(c, (1ULL << (32+n)), INTEL_ARCH_FIXED_MASK) |
8433be11 | 155 | |
ca037701 PZ |
156 | /* |
157 | * Constraint on the Event code + UMask | |
158 | */ | |
159 | #define PEBS_EVENT_CONSTRAINT(c, n) \ | |
160 | EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK) | |
161 | ||
ed8777fc PZ |
162 | #define EVENT_CONSTRAINT_END \ |
163 | EVENT_CONSTRAINT(0, 0, 0) | |
164 | ||
165 | #define for_each_event_constraint(e, c) \ | |
166 | for ((e) = (c); (e)->cmask; (e)++) | |
b690081d | 167 | |
8db909a7 PZ |
168 | union perf_capabilities { |
169 | struct { | |
170 | u64 lbr_format : 6; | |
171 | u64 pebs_trap : 1; | |
172 | u64 pebs_arch_reg : 1; | |
173 | u64 pebs_format : 4; | |
174 | u64 smm_freeze : 1; | |
175 | }; | |
176 | u64 capabilities; | |
177 | }; | |
178 | ||
241771ef | 179 | /* |
5f4ec28f | 180 | * struct x86_pmu - generic x86 pmu |
241771ef | 181 | */ |
5f4ec28f | 182 | struct x86_pmu { |
ca037701 PZ |
183 | /* |
184 | * Generic x86 PMC bits | |
185 | */ | |
faa28ae0 RR |
186 | const char *name; |
187 | int version; | |
a3288106 | 188 | int (*handle_irq)(struct pt_regs *); |
9e35ad38 PZ |
189 | void (*disable_all)(void); |
190 | void (*enable_all)(void); | |
aff3d91a PZ |
191 | void (*enable)(struct perf_event *); |
192 | void (*disable)(struct perf_event *); | |
a072738e CG |
193 | int (*hw_config)(struct perf_event_attr *attr, struct hw_perf_event *hwc); |
194 | int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign); | |
169e41eb JSR |
195 | unsigned eventsel; |
196 | unsigned perfctr; | |
b0f3f28e PZ |
197 | u64 (*event_map)(int); |
198 | u64 (*raw_event)(u64); | |
169e41eb | 199 | int max_events; |
cdd6c482 IM |
200 | int num_events; |
201 | int num_events_fixed; | |
202 | int event_bits; | |
203 | u64 event_mask; | |
04da8a43 | 204 | int apic; |
c619b8ff | 205 | u64 max_period; |
63b14649 PZ |
206 | struct event_constraint * |
207 | (*get_event_constraints)(struct cpu_hw_events *cpuc, | |
208 | struct perf_event *event); | |
209 | ||
c91e0f5d PZ |
210 | void (*put_event_constraints)(struct cpu_hw_events *cpuc, |
211 | struct perf_event *event); | |
63b14649 | 212 | struct event_constraint *event_constraints; |
3c44780b | 213 | void (*quirks)(void); |
3f6da390 PZ |
214 | |
215 | void (*cpu_prepare)(int cpu); | |
216 | void (*cpu_starting)(int cpu); | |
217 | void (*cpu_dying)(int cpu); | |
218 | void (*cpu_dead)(int cpu); | |
ca037701 PZ |
219 | |
220 | /* | |
221 | * Intel Arch Perfmon v2+ | |
222 | */ | |
8db909a7 PZ |
223 | u64 intel_ctrl; |
224 | union perf_capabilities intel_cap; | |
ca037701 PZ |
225 | |
226 | /* | |
227 | * Intel DebugStore bits | |
228 | */ | |
229 | int bts, pebs; | |
230 | int pebs_record_size; | |
231 | void (*drain_pebs)(struct pt_regs *regs); | |
232 | struct event_constraint *pebs_constraints; | |
caff2bef PZ |
233 | |
234 | /* | |
235 | * Intel LBR | |
236 | */ | |
237 | unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */ | |
238 | int lbr_nr; /* hardware stack size */ | |
b56a3802 JSR |
239 | }; |
240 | ||
4a06bd85 | 241 | static struct x86_pmu x86_pmu __read_mostly; |
b56a3802 | 242 | |
cdd6c482 | 243 | static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { |
b0f3f28e PZ |
244 | .enabled = 1, |
245 | }; | |
241771ef | 246 | |
07088edb | 247 | static int x86_perf_event_set_period(struct perf_event *event); |
b690081d | 248 | |
8326f44d | 249 | /* |
dfc65094 | 250 | * Generalized hw caching related hw_event table, filled |
8326f44d | 251 | * in on a per model basis. A value of 0 means |
dfc65094 IM |
252 | * 'not supported', -1 means 'hw_event makes no sense on |
253 | * this CPU', any other value means the raw hw_event | |
8326f44d IM |
254 | * ID. |
255 | */ | |
256 | ||
257 | #define C(x) PERF_COUNT_HW_CACHE_##x | |
258 | ||
259 | static u64 __read_mostly hw_cache_event_ids | |
260 | [PERF_COUNT_HW_CACHE_MAX] | |
261 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
262 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
263 | ||
ee06094f | 264 | /* |
cdd6c482 IM |
265 | * Propagate event elapsed time into the generic event. |
266 | * Can only be executed on the CPU where the event is active. | |
ee06094f IM |
267 | * Returns the delta events processed. |
268 | */ | |
4b7bfd0d | 269 | static u64 |
cc2ad4ba | 270 | x86_perf_event_update(struct perf_event *event) |
ee06094f | 271 | { |
cc2ad4ba | 272 | struct hw_perf_event *hwc = &event->hw; |
cdd6c482 | 273 | int shift = 64 - x86_pmu.event_bits; |
ec3232bd | 274 | u64 prev_raw_count, new_raw_count; |
cc2ad4ba | 275 | int idx = hwc->idx; |
ec3232bd | 276 | s64 delta; |
ee06094f | 277 | |
30dd568c MM |
278 | if (idx == X86_PMC_IDX_FIXED_BTS) |
279 | return 0; | |
280 | ||
ee06094f | 281 | /* |
cdd6c482 | 282 | * Careful: an NMI might modify the previous event value. |
ee06094f IM |
283 | * |
284 | * Our tactic to handle this is to first atomically read and | |
285 | * exchange a new raw count - then add that new-prev delta | |
cdd6c482 | 286 | * count to the generic event atomically: |
ee06094f IM |
287 | */ |
288 | again: | |
289 | prev_raw_count = atomic64_read(&hwc->prev_count); | |
cdd6c482 | 290 | rdmsrl(hwc->event_base + idx, new_raw_count); |
ee06094f IM |
291 | |
292 | if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count, | |
293 | new_raw_count) != prev_raw_count) | |
294 | goto again; | |
295 | ||
296 | /* | |
297 | * Now we have the new raw value and have updated the prev | |
298 | * timestamp already. We can now calculate the elapsed delta | |
cdd6c482 | 299 | * (event-)time and add that to the generic event. |
ee06094f IM |
300 | * |
301 | * Careful, not all hw sign-extends above the physical width | |
ec3232bd | 302 | * of the count. |
ee06094f | 303 | */ |
ec3232bd PZ |
304 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
305 | delta >>= shift; | |
ee06094f | 306 | |
cdd6c482 | 307 | atomic64_add(delta, &event->count); |
ee06094f | 308 | atomic64_sub(delta, &hwc->period_left); |
4b7bfd0d RR |
309 | |
310 | return new_raw_count; | |
ee06094f IM |
311 | } |
312 | ||
cdd6c482 | 313 | static atomic_t active_events; |
4e935e47 PZ |
314 | static DEFINE_MUTEX(pmc_reserve_mutex); |
315 | ||
316 | static bool reserve_pmc_hardware(void) | |
317 | { | |
04da8a43 | 318 | #ifdef CONFIG_X86_LOCAL_APIC |
4e935e47 PZ |
319 | int i; |
320 | ||
321 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
322 | disable_lapic_nmi_watchdog(); | |
323 | ||
cdd6c482 | 324 | for (i = 0; i < x86_pmu.num_events; i++) { |
4a06bd85 | 325 | if (!reserve_perfctr_nmi(x86_pmu.perfctr + i)) |
4e935e47 PZ |
326 | goto perfctr_fail; |
327 | } | |
328 | ||
cdd6c482 | 329 | for (i = 0; i < x86_pmu.num_events; i++) { |
4a06bd85 | 330 | if (!reserve_evntsel_nmi(x86_pmu.eventsel + i)) |
4e935e47 PZ |
331 | goto eventsel_fail; |
332 | } | |
04da8a43 | 333 | #endif |
4e935e47 PZ |
334 | |
335 | return true; | |
336 | ||
04da8a43 | 337 | #ifdef CONFIG_X86_LOCAL_APIC |
4e935e47 PZ |
338 | eventsel_fail: |
339 | for (i--; i >= 0; i--) | |
4a06bd85 | 340 | release_evntsel_nmi(x86_pmu.eventsel + i); |
4e935e47 | 341 | |
cdd6c482 | 342 | i = x86_pmu.num_events; |
4e935e47 PZ |
343 | |
344 | perfctr_fail: | |
345 | for (i--; i >= 0; i--) | |
4a06bd85 | 346 | release_perfctr_nmi(x86_pmu.perfctr + i); |
4e935e47 PZ |
347 | |
348 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
349 | enable_lapic_nmi_watchdog(); | |
350 | ||
351 | return false; | |
04da8a43 | 352 | #endif |
4e935e47 PZ |
353 | } |
354 | ||
355 | static void release_pmc_hardware(void) | |
356 | { | |
04da8a43 | 357 | #ifdef CONFIG_X86_LOCAL_APIC |
4e935e47 PZ |
358 | int i; |
359 | ||
cdd6c482 | 360 | for (i = 0; i < x86_pmu.num_events; i++) { |
4a06bd85 RR |
361 | release_perfctr_nmi(x86_pmu.perfctr + i); |
362 | release_evntsel_nmi(x86_pmu.eventsel + i); | |
4e935e47 PZ |
363 | } |
364 | ||
365 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
366 | enable_lapic_nmi_watchdog(); | |
04da8a43 | 367 | #endif |
4e935e47 PZ |
368 | } |
369 | ||
ca037701 PZ |
370 | static int reserve_ds_buffers(void); |
371 | static void release_ds_buffers(void); | |
30dd568c | 372 | |
cdd6c482 | 373 | static void hw_perf_event_destroy(struct perf_event *event) |
4e935e47 | 374 | { |
cdd6c482 | 375 | if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) { |
4e935e47 | 376 | release_pmc_hardware(); |
ca037701 | 377 | release_ds_buffers(); |
4e935e47 PZ |
378 | mutex_unlock(&pmc_reserve_mutex); |
379 | } | |
380 | } | |
381 | ||
85cf9dba RR |
382 | static inline int x86_pmu_initialized(void) |
383 | { | |
384 | return x86_pmu.handle_irq != NULL; | |
385 | } | |
386 | ||
8326f44d | 387 | static inline int |
cdd6c482 | 388 | set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr) |
8326f44d IM |
389 | { |
390 | unsigned int cache_type, cache_op, cache_result; | |
391 | u64 config, val; | |
392 | ||
393 | config = attr->config; | |
394 | ||
395 | cache_type = (config >> 0) & 0xff; | |
396 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
397 | return -EINVAL; | |
398 | ||
399 | cache_op = (config >> 8) & 0xff; | |
400 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
401 | return -EINVAL; | |
402 | ||
403 | cache_result = (config >> 16) & 0xff; | |
404 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
405 | return -EINVAL; | |
406 | ||
407 | val = hw_cache_event_ids[cache_type][cache_op][cache_result]; | |
408 | ||
409 | if (val == 0) | |
410 | return -ENOENT; | |
411 | ||
412 | if (val == -1) | |
413 | return -EINVAL; | |
414 | ||
415 | hwc->config |= val; | |
416 | ||
417 | return 0; | |
418 | } | |
419 | ||
a072738e CG |
420 | static int x86_hw_config(struct perf_event_attr *attr, struct hw_perf_event *hwc) |
421 | { | |
422 | /* | |
423 | * Generate PMC IRQs: | |
424 | * (keep 'enabled' bit clear for now) | |
425 | */ | |
426 | hwc->config = ARCH_PERFMON_EVENTSEL_INT; | |
427 | ||
428 | /* | |
429 | * Count user and OS events unless requested not to | |
430 | */ | |
431 | if (!attr->exclude_user) | |
432 | hwc->config |= ARCH_PERFMON_EVENTSEL_USR; | |
433 | if (!attr->exclude_kernel) | |
434 | hwc->config |= ARCH_PERFMON_EVENTSEL_OS; | |
435 | ||
436 | return 0; | |
437 | } | |
438 | ||
241771ef | 439 | /* |
0d48696f | 440 | * Setup the hardware configuration for a given attr_type |
241771ef | 441 | */ |
cdd6c482 | 442 | static int __hw_perf_event_init(struct perf_event *event) |
241771ef | 443 | { |
cdd6c482 IM |
444 | struct perf_event_attr *attr = &event->attr; |
445 | struct hw_perf_event *hwc = &event->hw; | |
9c74fb50 | 446 | u64 config; |
4e935e47 | 447 | int err; |
241771ef | 448 | |
85cf9dba RR |
449 | if (!x86_pmu_initialized()) |
450 | return -ENODEV; | |
241771ef | 451 | |
4e935e47 | 452 | err = 0; |
cdd6c482 | 453 | if (!atomic_inc_not_zero(&active_events)) { |
4e935e47 | 454 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 | 455 | if (atomic_read(&active_events) == 0) { |
30dd568c MM |
456 | if (!reserve_pmc_hardware()) |
457 | err = -EBUSY; | |
458 | else | |
ca037701 | 459 | err = reserve_ds_buffers(); |
30dd568c MM |
460 | } |
461 | if (!err) | |
cdd6c482 | 462 | atomic_inc(&active_events); |
4e935e47 PZ |
463 | mutex_unlock(&pmc_reserve_mutex); |
464 | } | |
465 | if (err) | |
466 | return err; | |
467 | ||
cdd6c482 | 468 | event->destroy = hw_perf_event_destroy; |
a1792cda | 469 | |
b690081d | 470 | hwc->idx = -1; |
447a194b SE |
471 | hwc->last_cpu = -1; |
472 | hwc->last_tag = ~0ULL; | |
b690081d | 473 | |
a072738e | 474 | /* Processor specifics */ |
984763cb RR |
475 | err = x86_pmu.hw_config(attr, hwc); |
476 | if (err) | |
477 | return err; | |
0475f9ea | 478 | |
bd2b5b12 | 479 | if (!hwc->sample_period) { |
b23f3325 | 480 | hwc->sample_period = x86_pmu.max_period; |
9e350de3 | 481 | hwc->last_period = hwc->sample_period; |
bd2b5b12 | 482 | atomic64_set(&hwc->period_left, hwc->sample_period); |
04da8a43 IM |
483 | } else { |
484 | /* | |
485 | * If we have a PMU initialized but no APIC | |
486 | * interrupts, we cannot sample hardware | |
cdd6c482 IM |
487 | * events (user-space has to fall back and |
488 | * sample via a hrtimer based software event): | |
04da8a43 IM |
489 | */ |
490 | if (!x86_pmu.apic) | |
491 | return -EOPNOTSUPP; | |
bd2b5b12 | 492 | } |
d2517a49 | 493 | |
241771ef | 494 | /* |
dfc65094 | 495 | * Raw hw_event type provide the config in the hw_event structure |
241771ef | 496 | */ |
a21ca2ca IM |
497 | if (attr->type == PERF_TYPE_RAW) { |
498 | hwc->config |= x86_pmu.raw_event(attr->config); | |
320ebf09 PZ |
499 | if ((hwc->config & ARCH_PERFMON_EVENTSEL_ANY) && |
500 | perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN)) | |
501 | return -EACCES; | |
8326f44d | 502 | return 0; |
241771ef | 503 | } |
241771ef | 504 | |
8326f44d IM |
505 | if (attr->type == PERF_TYPE_HW_CACHE) |
506 | return set_ext_hw_attr(hwc, attr); | |
507 | ||
508 | if (attr->config >= x86_pmu.max_events) | |
509 | return -EINVAL; | |
9c74fb50 | 510 | |
8326f44d IM |
511 | /* |
512 | * The generic map: | |
513 | */ | |
9c74fb50 PZ |
514 | config = x86_pmu.event_map(attr->config); |
515 | ||
516 | if (config == 0) | |
517 | return -ENOENT; | |
518 | ||
519 | if (config == -1LL) | |
520 | return -EINVAL; | |
521 | ||
747b50aa | 522 | /* |
523 | * Branch tracing: | |
524 | */ | |
525 | if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) && | |
1653192f | 526 | (hwc->sample_period == 1)) { |
527 | /* BTS is not supported by this architecture. */ | |
ca037701 | 528 | if (!x86_pmu.bts) |
1653192f | 529 | return -EOPNOTSUPP; |
530 | ||
531 | /* BTS is currently only allowed for user-mode. */ | |
a072738e | 532 | if (!attr->exclude_kernel) |
1653192f | 533 | return -EOPNOTSUPP; |
534 | } | |
747b50aa | 535 | |
9c74fb50 | 536 | hwc->config |= config; |
4e935e47 | 537 | |
241771ef IM |
538 | return 0; |
539 | } | |
540 | ||
8c48e444 | 541 | static void x86_pmu_disable_all(void) |
f87ad35d | 542 | { |
cdd6c482 | 543 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
9e35ad38 PZ |
544 | int idx; |
545 | ||
cdd6c482 | 546 | for (idx = 0; idx < x86_pmu.num_events; idx++) { |
b0f3f28e PZ |
547 | u64 val; |
548 | ||
43f6201a | 549 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 550 | continue; |
8c48e444 | 551 | rdmsrl(x86_pmu.eventsel + idx, val); |
bb1165d6 | 552 | if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE)) |
4295ee62 | 553 | continue; |
bb1165d6 | 554 | val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; |
8c48e444 | 555 | wrmsrl(x86_pmu.eventsel + idx, val); |
f87ad35d | 556 | } |
f87ad35d JSR |
557 | } |
558 | ||
9e35ad38 | 559 | void hw_perf_disable(void) |
b56a3802 | 560 | { |
1da53e02 SE |
561 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
562 | ||
85cf9dba | 563 | if (!x86_pmu_initialized()) |
9e35ad38 | 564 | return; |
1da53e02 | 565 | |
1a6e21f7 PZ |
566 | if (!cpuc->enabled) |
567 | return; | |
568 | ||
569 | cpuc->n_added = 0; | |
570 | cpuc->enabled = 0; | |
571 | barrier(); | |
1da53e02 SE |
572 | |
573 | x86_pmu.disable_all(); | |
b56a3802 | 574 | } |
241771ef | 575 | |
8c48e444 | 576 | static void x86_pmu_enable_all(void) |
f87ad35d | 577 | { |
cdd6c482 | 578 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
f87ad35d JSR |
579 | int idx; |
580 | ||
cdd6c482 IM |
581 | for (idx = 0; idx < x86_pmu.num_events; idx++) { |
582 | struct perf_event *event = cpuc->events[idx]; | |
4295ee62 | 583 | u64 val; |
b0f3f28e | 584 | |
43f6201a | 585 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 586 | continue; |
984b838c | 587 | |
cdd6c482 | 588 | val = event->hw.config; |
bb1165d6 | 589 | val |= ARCH_PERFMON_EVENTSEL_ENABLE; |
8c48e444 | 590 | wrmsrl(x86_pmu.eventsel + idx, val); |
f87ad35d JSR |
591 | } |
592 | } | |
593 | ||
1da53e02 SE |
594 | static const struct pmu pmu; |
595 | ||
596 | static inline int is_x86_event(struct perf_event *event) | |
597 | { | |
598 | return event->pmu == &pmu; | |
599 | } | |
600 | ||
601 | static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) | |
602 | { | |
63b14649 | 603 | struct event_constraint *c, *constraints[X86_PMC_IDX_MAX]; |
1da53e02 | 604 | unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
c933c1a6 | 605 | int i, j, w, wmax, num = 0; |
1da53e02 SE |
606 | struct hw_perf_event *hwc; |
607 | ||
608 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); | |
609 | ||
610 | for (i = 0; i < n; i++) { | |
b622d644 PZ |
611 | c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]); |
612 | constraints[i] = c; | |
1da53e02 SE |
613 | } |
614 | ||
8113070d SE |
615 | /* |
616 | * fastpath, try to reuse previous register | |
617 | */ | |
c933c1a6 | 618 | for (i = 0; i < n; i++) { |
8113070d | 619 | hwc = &cpuc->event_list[i]->hw; |
81269a08 | 620 | c = constraints[i]; |
8113070d SE |
621 | |
622 | /* never assigned */ | |
623 | if (hwc->idx == -1) | |
624 | break; | |
625 | ||
626 | /* constraint still honored */ | |
63b14649 | 627 | if (!test_bit(hwc->idx, c->idxmsk)) |
8113070d SE |
628 | break; |
629 | ||
630 | /* not already used */ | |
631 | if (test_bit(hwc->idx, used_mask)) | |
632 | break; | |
633 | ||
34538ee7 | 634 | __set_bit(hwc->idx, used_mask); |
8113070d SE |
635 | if (assign) |
636 | assign[i] = hwc->idx; | |
637 | } | |
c933c1a6 | 638 | if (i == n) |
8113070d SE |
639 | goto done; |
640 | ||
641 | /* | |
642 | * begin slow path | |
643 | */ | |
644 | ||
645 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); | |
646 | ||
1da53e02 SE |
647 | /* |
648 | * weight = number of possible counters | |
649 | * | |
650 | * 1 = most constrained, only works on one counter | |
651 | * wmax = least constrained, works on any counter | |
652 | * | |
653 | * assign events to counters starting with most | |
654 | * constrained events. | |
655 | */ | |
656 | wmax = x86_pmu.num_events; | |
657 | ||
658 | /* | |
659 | * when fixed event counters are present, | |
660 | * wmax is incremented by 1 to account | |
661 | * for one more choice | |
662 | */ | |
663 | if (x86_pmu.num_events_fixed) | |
664 | wmax++; | |
665 | ||
8113070d | 666 | for (w = 1, num = n; num && w <= wmax; w++) { |
1da53e02 | 667 | /* for each event */ |
8113070d | 668 | for (i = 0; num && i < n; i++) { |
81269a08 | 669 | c = constraints[i]; |
1da53e02 SE |
670 | hwc = &cpuc->event_list[i]->hw; |
671 | ||
272d30be | 672 | if (c->weight != w) |
1da53e02 SE |
673 | continue; |
674 | ||
984b3f57 | 675 | for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) { |
1da53e02 SE |
676 | if (!test_bit(j, used_mask)) |
677 | break; | |
678 | } | |
679 | ||
680 | if (j == X86_PMC_IDX_MAX) | |
681 | break; | |
1da53e02 | 682 | |
34538ee7 | 683 | __set_bit(j, used_mask); |
8113070d | 684 | |
1da53e02 SE |
685 | if (assign) |
686 | assign[i] = j; | |
687 | num--; | |
688 | } | |
689 | } | |
8113070d | 690 | done: |
1da53e02 SE |
691 | /* |
692 | * scheduling failed or is just a simulation, | |
693 | * free resources if necessary | |
694 | */ | |
695 | if (!assign || num) { | |
696 | for (i = 0; i < n; i++) { | |
697 | if (x86_pmu.put_event_constraints) | |
698 | x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]); | |
699 | } | |
700 | } | |
701 | return num ? -ENOSPC : 0; | |
702 | } | |
703 | ||
704 | /* | |
705 | * dogrp: true if must collect siblings events (group) | |
706 | * returns total number of events and error code | |
707 | */ | |
708 | static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp) | |
709 | { | |
710 | struct perf_event *event; | |
711 | int n, max_count; | |
712 | ||
713 | max_count = x86_pmu.num_events + x86_pmu.num_events_fixed; | |
714 | ||
715 | /* current number of events already accepted */ | |
716 | n = cpuc->n_events; | |
717 | ||
718 | if (is_x86_event(leader)) { | |
719 | if (n >= max_count) | |
720 | return -ENOSPC; | |
721 | cpuc->event_list[n] = leader; | |
722 | n++; | |
723 | } | |
724 | if (!dogrp) | |
725 | return n; | |
726 | ||
727 | list_for_each_entry(event, &leader->sibling_list, group_entry) { | |
728 | if (!is_x86_event(event) || | |
8113070d | 729 | event->state <= PERF_EVENT_STATE_OFF) |
1da53e02 SE |
730 | continue; |
731 | ||
732 | if (n >= max_count) | |
733 | return -ENOSPC; | |
734 | ||
735 | cpuc->event_list[n] = event; | |
736 | n++; | |
737 | } | |
738 | return n; | |
739 | } | |
740 | ||
1da53e02 | 741 | static inline void x86_assign_hw_event(struct perf_event *event, |
447a194b | 742 | struct cpu_hw_events *cpuc, int i) |
1da53e02 | 743 | { |
447a194b SE |
744 | struct hw_perf_event *hwc = &event->hw; |
745 | ||
746 | hwc->idx = cpuc->assign[i]; | |
747 | hwc->last_cpu = smp_processor_id(); | |
748 | hwc->last_tag = ++cpuc->tags[i]; | |
1da53e02 SE |
749 | |
750 | if (hwc->idx == X86_PMC_IDX_FIXED_BTS) { | |
751 | hwc->config_base = 0; | |
752 | hwc->event_base = 0; | |
753 | } else if (hwc->idx >= X86_PMC_IDX_FIXED) { | |
754 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; | |
755 | /* | |
756 | * We set it so that event_base + idx in wrmsr/rdmsr maps to | |
757 | * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2: | |
758 | */ | |
759 | hwc->event_base = | |
760 | MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED; | |
761 | } else { | |
762 | hwc->config_base = x86_pmu.eventsel; | |
763 | hwc->event_base = x86_pmu.perfctr; | |
764 | } | |
765 | } | |
766 | ||
447a194b SE |
767 | static inline int match_prev_assignment(struct hw_perf_event *hwc, |
768 | struct cpu_hw_events *cpuc, | |
769 | int i) | |
770 | { | |
771 | return hwc->idx == cpuc->assign[i] && | |
772 | hwc->last_cpu == smp_processor_id() && | |
773 | hwc->last_tag == cpuc->tags[i]; | |
774 | } | |
775 | ||
c08053e6 | 776 | static int x86_pmu_start(struct perf_event *event); |
d76a0812 | 777 | static void x86_pmu_stop(struct perf_event *event); |
2e841873 | 778 | |
9e35ad38 | 779 | void hw_perf_enable(void) |
ee06094f | 780 | { |
1da53e02 SE |
781 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
782 | struct perf_event *event; | |
783 | struct hw_perf_event *hwc; | |
784 | int i; | |
785 | ||
85cf9dba | 786 | if (!x86_pmu_initialized()) |
2b9ff0db | 787 | return; |
1a6e21f7 PZ |
788 | |
789 | if (cpuc->enabled) | |
790 | return; | |
791 | ||
1da53e02 | 792 | if (cpuc->n_added) { |
19925ce7 | 793 | int n_running = cpuc->n_events - cpuc->n_added; |
1da53e02 SE |
794 | /* |
795 | * apply assignment obtained either from | |
796 | * hw_perf_group_sched_in() or x86_pmu_enable() | |
797 | * | |
798 | * step1: save events moving to new counters | |
799 | * step2: reprogram moved events into new counters | |
800 | */ | |
19925ce7 | 801 | for (i = 0; i < n_running; i++) { |
1da53e02 SE |
802 | event = cpuc->event_list[i]; |
803 | hwc = &event->hw; | |
804 | ||
447a194b SE |
805 | /* |
806 | * we can avoid reprogramming counter if: | |
807 | * - assigned same counter as last time | |
808 | * - running on same CPU as last time | |
809 | * - no other event has used the counter since | |
810 | */ | |
811 | if (hwc->idx == -1 || | |
812 | match_prev_assignment(hwc, cpuc, i)) | |
1da53e02 SE |
813 | continue; |
814 | ||
d76a0812 | 815 | x86_pmu_stop(event); |
1da53e02 SE |
816 | } |
817 | ||
818 | for (i = 0; i < cpuc->n_events; i++) { | |
1da53e02 SE |
819 | event = cpuc->event_list[i]; |
820 | hwc = &event->hw; | |
821 | ||
45e16a68 | 822 | if (!match_prev_assignment(hwc, cpuc, i)) |
447a194b | 823 | x86_assign_hw_event(event, cpuc, i); |
45e16a68 PZ |
824 | else if (i < n_running) |
825 | continue; | |
1da53e02 | 826 | |
c08053e6 | 827 | x86_pmu_start(event); |
1da53e02 SE |
828 | } |
829 | cpuc->n_added = 0; | |
830 | perf_events_lapic_init(); | |
831 | } | |
1a6e21f7 PZ |
832 | |
833 | cpuc->enabled = 1; | |
834 | barrier(); | |
835 | ||
9e35ad38 | 836 | x86_pmu.enable_all(); |
ee06094f | 837 | } |
ee06094f | 838 | |
aff3d91a | 839 | static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc) |
b0f3f28e | 840 | { |
7645a24c | 841 | wrmsrl(hwc->config_base + hwc->idx, |
bb1165d6 | 842 | hwc->config | ARCH_PERFMON_EVENTSEL_ENABLE); |
b0f3f28e PZ |
843 | } |
844 | ||
aff3d91a | 845 | static inline void x86_pmu_disable_event(struct perf_event *event) |
b0f3f28e | 846 | { |
aff3d91a | 847 | struct hw_perf_event *hwc = &event->hw; |
7645a24c PZ |
848 | |
849 | wrmsrl(hwc->config_base + hwc->idx, hwc->config); | |
b0f3f28e PZ |
850 | } |
851 | ||
245b2e70 | 852 | static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); |
241771ef | 853 | |
ee06094f IM |
854 | /* |
855 | * Set the next IRQ period, based on the hwc->period_left value. | |
cdd6c482 | 856 | * To be called with the event disabled in hw: |
ee06094f | 857 | */ |
e4abb5d4 | 858 | static int |
07088edb | 859 | x86_perf_event_set_period(struct perf_event *event) |
241771ef | 860 | { |
07088edb | 861 | struct hw_perf_event *hwc = &event->hw; |
2f18d1e8 | 862 | s64 left = atomic64_read(&hwc->period_left); |
e4abb5d4 | 863 | s64 period = hwc->sample_period; |
7645a24c | 864 | int ret = 0, idx = hwc->idx; |
ee06094f | 865 | |
30dd568c MM |
866 | if (idx == X86_PMC_IDX_FIXED_BTS) |
867 | return 0; | |
868 | ||
ee06094f | 869 | /* |
af901ca1 | 870 | * If we are way outside a reasonable range then just skip forward: |
ee06094f IM |
871 | */ |
872 | if (unlikely(left <= -period)) { | |
873 | left = period; | |
874 | atomic64_set(&hwc->period_left, left); | |
9e350de3 | 875 | hwc->last_period = period; |
e4abb5d4 | 876 | ret = 1; |
ee06094f IM |
877 | } |
878 | ||
879 | if (unlikely(left <= 0)) { | |
880 | left += period; | |
881 | atomic64_set(&hwc->period_left, left); | |
9e350de3 | 882 | hwc->last_period = period; |
e4abb5d4 | 883 | ret = 1; |
ee06094f | 884 | } |
1c80f4b5 | 885 | /* |
dfc65094 | 886 | * Quirk: certain CPUs dont like it if just 1 hw_event is left: |
1c80f4b5 IM |
887 | */ |
888 | if (unlikely(left < 2)) | |
889 | left = 2; | |
241771ef | 890 | |
e4abb5d4 PZ |
891 | if (left > x86_pmu.max_period) |
892 | left = x86_pmu.max_period; | |
893 | ||
245b2e70 | 894 | per_cpu(pmc_prev_left[idx], smp_processor_id()) = left; |
ee06094f IM |
895 | |
896 | /* | |
cdd6c482 | 897 | * The hw event starts counting from this event offset, |
ee06094f IM |
898 | * mark it to be able to extra future deltas: |
899 | */ | |
2f18d1e8 | 900 | atomic64_set(&hwc->prev_count, (u64)-left); |
ee06094f | 901 | |
7645a24c PZ |
902 | wrmsrl(hwc->event_base + idx, |
903 | (u64)(-left) & x86_pmu.event_mask); | |
e4abb5d4 | 904 | |
cdd6c482 | 905 | perf_event_update_userpage(event); |
194002b2 | 906 | |
e4abb5d4 | 907 | return ret; |
2f18d1e8 IM |
908 | } |
909 | ||
aff3d91a | 910 | static void x86_pmu_enable_event(struct perf_event *event) |
7c90cc45 | 911 | { |
cdd6c482 | 912 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
7c90cc45 | 913 | if (cpuc->enabled) |
aff3d91a | 914 | __x86_pmu_enable_event(&event->hw); |
241771ef IM |
915 | } |
916 | ||
b690081d | 917 | /* |
1da53e02 SE |
918 | * activate a single event |
919 | * | |
920 | * The event is added to the group of enabled events | |
921 | * but only if it can be scehduled with existing events. | |
922 | * | |
923 | * Called with PMU disabled. If successful and return value 1, | |
924 | * then guaranteed to call perf_enable() and hw_perf_enable() | |
fe9081cc PZ |
925 | */ |
926 | static int x86_pmu_enable(struct perf_event *event) | |
927 | { | |
928 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1da53e02 SE |
929 | struct hw_perf_event *hwc; |
930 | int assign[X86_PMC_IDX_MAX]; | |
931 | int n, n0, ret; | |
fe9081cc | 932 | |
1da53e02 | 933 | hwc = &event->hw; |
fe9081cc | 934 | |
1da53e02 SE |
935 | n0 = cpuc->n_events; |
936 | n = collect_events(cpuc, event, false); | |
937 | if (n < 0) | |
938 | return n; | |
53b441a5 | 939 | |
a072738e | 940 | ret = x86_pmu.schedule_events(cpuc, n, assign); |
1da53e02 SE |
941 | if (ret) |
942 | return ret; | |
943 | /* | |
944 | * copy new assignment, now we know it is possible | |
945 | * will be used by hw_perf_enable() | |
946 | */ | |
947 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
7e2ae347 | 948 | |
1da53e02 | 949 | cpuc->n_events = n; |
356e1f2e | 950 | cpuc->n_added += n - n0; |
95cdd2e7 IM |
951 | |
952 | return 0; | |
241771ef IM |
953 | } |
954 | ||
d76a0812 SE |
955 | static int x86_pmu_start(struct perf_event *event) |
956 | { | |
c08053e6 PZ |
957 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
958 | int idx = event->hw.idx; | |
959 | ||
960 | if (idx == -1) | |
d76a0812 SE |
961 | return -EAGAIN; |
962 | ||
07088edb | 963 | x86_perf_event_set_period(event); |
c08053e6 PZ |
964 | cpuc->events[idx] = event; |
965 | __set_bit(idx, cpuc->active_mask); | |
aff3d91a | 966 | x86_pmu.enable(event); |
c08053e6 | 967 | perf_event_update_userpage(event); |
d76a0812 SE |
968 | |
969 | return 0; | |
970 | } | |
971 | ||
cdd6c482 | 972 | static void x86_pmu_unthrottle(struct perf_event *event) |
a78ac325 | 973 | { |
71e2d282 PZ |
974 | int ret = x86_pmu_start(event); |
975 | WARN_ON_ONCE(ret); | |
a78ac325 PZ |
976 | } |
977 | ||
cdd6c482 | 978 | void perf_event_print_debug(void) |
241771ef | 979 | { |
2f18d1e8 | 980 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
ca037701 | 981 | u64 pebs; |
cdd6c482 | 982 | struct cpu_hw_events *cpuc; |
5bb9efe3 | 983 | unsigned long flags; |
1e125676 IM |
984 | int cpu, idx; |
985 | ||
cdd6c482 | 986 | if (!x86_pmu.num_events) |
1e125676 | 987 | return; |
241771ef | 988 | |
5bb9efe3 | 989 | local_irq_save(flags); |
241771ef IM |
990 | |
991 | cpu = smp_processor_id(); | |
cdd6c482 | 992 | cpuc = &per_cpu(cpu_hw_events, cpu); |
241771ef | 993 | |
faa28ae0 | 994 | if (x86_pmu.version >= 2) { |
a1ef58f4 JSR |
995 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
996 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
997 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
998 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); | |
ca037701 | 999 | rdmsrl(MSR_IA32_PEBS_ENABLE, pebs); |
a1ef58f4 JSR |
1000 | |
1001 | pr_info("\n"); | |
1002 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
1003 | pr_info("CPU#%d: status: %016llx\n", cpu, status); | |
1004 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); | |
1005 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); | |
ca037701 | 1006 | pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs); |
f87ad35d | 1007 | } |
7645a24c | 1008 | pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); |
241771ef | 1009 | |
cdd6c482 | 1010 | for (idx = 0; idx < x86_pmu.num_events; idx++) { |
4a06bd85 RR |
1011 | rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl); |
1012 | rdmsrl(x86_pmu.perfctr + idx, pmc_count); | |
241771ef | 1013 | |
245b2e70 | 1014 | prev_left = per_cpu(pmc_prev_left[idx], cpu); |
241771ef | 1015 | |
a1ef58f4 | 1016 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 1017 | cpu, idx, pmc_ctrl); |
a1ef58f4 | 1018 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 1019 | cpu, idx, pmc_count); |
a1ef58f4 | 1020 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 1021 | cpu, idx, prev_left); |
241771ef | 1022 | } |
cdd6c482 | 1023 | for (idx = 0; idx < x86_pmu.num_events_fixed; idx++) { |
2f18d1e8 IM |
1024 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
1025 | ||
a1ef58f4 | 1026 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
2f18d1e8 IM |
1027 | cpu, idx, pmc_count); |
1028 | } | |
5bb9efe3 | 1029 | local_irq_restore(flags); |
241771ef IM |
1030 | } |
1031 | ||
d76a0812 | 1032 | static void x86_pmu_stop(struct perf_event *event) |
241771ef | 1033 | { |
d76a0812 | 1034 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
cdd6c482 | 1035 | struct hw_perf_event *hwc = &event->hw; |
2e841873 | 1036 | int idx = hwc->idx; |
241771ef | 1037 | |
71e2d282 PZ |
1038 | if (!__test_and_clear_bit(idx, cpuc->active_mask)) |
1039 | return; | |
1040 | ||
aff3d91a | 1041 | x86_pmu.disable(event); |
241771ef | 1042 | |
ee06094f | 1043 | /* |
cdd6c482 | 1044 | * Drain the remaining delta count out of a event |
ee06094f IM |
1045 | * that we are disabling: |
1046 | */ | |
cc2ad4ba | 1047 | x86_perf_event_update(event); |
30dd568c | 1048 | |
cdd6c482 | 1049 | cpuc->events[idx] = NULL; |
2e841873 PZ |
1050 | } |
1051 | ||
1052 | static void x86_pmu_disable(struct perf_event *event) | |
1053 | { | |
1054 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1055 | int i; | |
1056 | ||
d76a0812 | 1057 | x86_pmu_stop(event); |
194002b2 | 1058 | |
1da53e02 SE |
1059 | for (i = 0; i < cpuc->n_events; i++) { |
1060 | if (event == cpuc->event_list[i]) { | |
1061 | ||
1062 | if (x86_pmu.put_event_constraints) | |
1063 | x86_pmu.put_event_constraints(cpuc, event); | |
1064 | ||
1065 | while (++i < cpuc->n_events) | |
1066 | cpuc->event_list[i-1] = cpuc->event_list[i]; | |
1067 | ||
1068 | --cpuc->n_events; | |
6c9687ab | 1069 | break; |
1da53e02 SE |
1070 | } |
1071 | } | |
cdd6c482 | 1072 | perf_event_update_userpage(event); |
241771ef IM |
1073 | } |
1074 | ||
8c48e444 | 1075 | static int x86_pmu_handle_irq(struct pt_regs *regs) |
a29aa8a7 | 1076 | { |
df1a132b | 1077 | struct perf_sample_data data; |
cdd6c482 IM |
1078 | struct cpu_hw_events *cpuc; |
1079 | struct perf_event *event; | |
1080 | struct hw_perf_event *hwc; | |
11d1578f | 1081 | int idx, handled = 0; |
9029a5e3 IM |
1082 | u64 val; |
1083 | ||
dc1d628a | 1084 | perf_sample_data_init(&data, 0); |
df1a132b | 1085 | |
cdd6c482 | 1086 | cpuc = &__get_cpu_var(cpu_hw_events); |
962bf7a6 | 1087 | |
cdd6c482 | 1088 | for (idx = 0; idx < x86_pmu.num_events; idx++) { |
43f6201a | 1089 | if (!test_bit(idx, cpuc->active_mask)) |
a29aa8a7 | 1090 | continue; |
962bf7a6 | 1091 | |
cdd6c482 IM |
1092 | event = cpuc->events[idx]; |
1093 | hwc = &event->hw; | |
a4016a79 | 1094 | |
cc2ad4ba | 1095 | val = x86_perf_event_update(event); |
cdd6c482 | 1096 | if (val & (1ULL << (x86_pmu.event_bits - 1))) |
48e22d56 | 1097 | continue; |
962bf7a6 | 1098 | |
9e350de3 | 1099 | /* |
cdd6c482 | 1100 | * event overflow |
9e350de3 PZ |
1101 | */ |
1102 | handled = 1; | |
cdd6c482 | 1103 | data.period = event->hw.last_period; |
9e350de3 | 1104 | |
07088edb | 1105 | if (!x86_perf_event_set_period(event)) |
e4abb5d4 PZ |
1106 | continue; |
1107 | ||
cdd6c482 | 1108 | if (perf_event_overflow(event, 1, &data, regs)) |
71e2d282 | 1109 | x86_pmu_stop(event); |
a29aa8a7 | 1110 | } |
962bf7a6 | 1111 | |
9e350de3 PZ |
1112 | if (handled) |
1113 | inc_irq_stat(apic_perf_irqs); | |
1114 | ||
a29aa8a7 RR |
1115 | return handled; |
1116 | } | |
39d81eab | 1117 | |
b6276f35 PZ |
1118 | void smp_perf_pending_interrupt(struct pt_regs *regs) |
1119 | { | |
1120 | irq_enter(); | |
1121 | ack_APIC_irq(); | |
1122 | inc_irq_stat(apic_pending_irqs); | |
cdd6c482 | 1123 | perf_event_do_pending(); |
b6276f35 PZ |
1124 | irq_exit(); |
1125 | } | |
1126 | ||
cdd6c482 | 1127 | void set_perf_event_pending(void) |
b6276f35 | 1128 | { |
04da8a43 | 1129 | #ifdef CONFIG_X86_LOCAL_APIC |
7d428966 PZ |
1130 | if (!x86_pmu.apic || !x86_pmu_initialized()) |
1131 | return; | |
1132 | ||
b6276f35 | 1133 | apic->send_IPI_self(LOCAL_PENDING_VECTOR); |
04da8a43 | 1134 | #endif |
b6276f35 PZ |
1135 | } |
1136 | ||
cdd6c482 | 1137 | void perf_events_lapic_init(void) |
241771ef | 1138 | { |
04da8a43 IM |
1139 | #ifdef CONFIG_X86_LOCAL_APIC |
1140 | if (!x86_pmu.apic || !x86_pmu_initialized()) | |
241771ef | 1141 | return; |
85cf9dba | 1142 | |
241771ef | 1143 | /* |
c323d95f | 1144 | * Always use NMI for PMU |
241771ef | 1145 | */ |
c323d95f | 1146 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
04da8a43 | 1147 | #endif |
241771ef IM |
1148 | } |
1149 | ||
1150 | static int __kprobes | |
cdd6c482 | 1151 | perf_event_nmi_handler(struct notifier_block *self, |
241771ef IM |
1152 | unsigned long cmd, void *__args) |
1153 | { | |
1154 | struct die_args *args = __args; | |
1155 | struct pt_regs *regs; | |
b0f3f28e | 1156 | |
cdd6c482 | 1157 | if (!atomic_read(&active_events)) |
63a809a2 PZ |
1158 | return NOTIFY_DONE; |
1159 | ||
b0f3f28e PZ |
1160 | switch (cmd) { |
1161 | case DIE_NMI: | |
1162 | case DIE_NMI_IPI: | |
1163 | break; | |
241771ef | 1164 | |
b0f3f28e | 1165 | default: |
241771ef | 1166 | return NOTIFY_DONE; |
b0f3f28e | 1167 | } |
241771ef IM |
1168 | |
1169 | regs = args->regs; | |
1170 | ||
04da8a43 | 1171 | #ifdef CONFIG_X86_LOCAL_APIC |
241771ef | 1172 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
04da8a43 | 1173 | #endif |
a4016a79 PZ |
1174 | /* |
1175 | * Can't rely on the handled return value to say it was our NMI, two | |
cdd6c482 | 1176 | * events could trigger 'simultaneously' raising two back-to-back NMIs. |
a4016a79 PZ |
1177 | * |
1178 | * If the first NMI handles both, the latter will be empty and daze | |
1179 | * the CPU. | |
1180 | */ | |
a3288106 | 1181 | x86_pmu.handle_irq(regs); |
241771ef | 1182 | |
a4016a79 | 1183 | return NOTIFY_STOP; |
241771ef IM |
1184 | } |
1185 | ||
f22f54f4 PZ |
1186 | static __read_mostly struct notifier_block perf_event_nmi_notifier = { |
1187 | .notifier_call = perf_event_nmi_handler, | |
1188 | .next = NULL, | |
1189 | .priority = 1 | |
1190 | }; | |
1191 | ||
63b14649 | 1192 | static struct event_constraint unconstrained; |
38331f62 | 1193 | static struct event_constraint emptyconstraint; |
63b14649 | 1194 | |
63b14649 | 1195 | static struct event_constraint * |
f22f54f4 | 1196 | x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event) |
1da53e02 | 1197 | { |
63b14649 | 1198 | struct event_constraint *c; |
1da53e02 | 1199 | |
1da53e02 SE |
1200 | if (x86_pmu.event_constraints) { |
1201 | for_each_event_constraint(c, x86_pmu.event_constraints) { | |
63b14649 PZ |
1202 | if ((event->hw.config & c->cmask) == c->code) |
1203 | return c; | |
1da53e02 SE |
1204 | } |
1205 | } | |
63b14649 PZ |
1206 | |
1207 | return &unconstrained; | |
1da53e02 SE |
1208 | } |
1209 | ||
1da53e02 | 1210 | static int x86_event_sched_in(struct perf_event *event, |
6e37738a | 1211 | struct perf_cpu_context *cpuctx) |
1da53e02 SE |
1212 | { |
1213 | int ret = 0; | |
1214 | ||
1215 | event->state = PERF_EVENT_STATE_ACTIVE; | |
6e37738a | 1216 | event->oncpu = smp_processor_id(); |
1da53e02 SE |
1217 | event->tstamp_running += event->ctx->time - event->tstamp_stopped; |
1218 | ||
1219 | if (!is_x86_event(event)) | |
1220 | ret = event->pmu->enable(event); | |
1221 | ||
1222 | if (!ret && !is_software_event(event)) | |
1223 | cpuctx->active_oncpu++; | |
1224 | ||
1225 | if (!ret && event->attr.exclusive) | |
1226 | cpuctx->exclusive = 1; | |
1227 | ||
1228 | return ret; | |
1229 | } | |
1230 | ||
1231 | static void x86_event_sched_out(struct perf_event *event, | |
6e37738a | 1232 | struct perf_cpu_context *cpuctx) |
1da53e02 SE |
1233 | { |
1234 | event->state = PERF_EVENT_STATE_INACTIVE; | |
1235 | event->oncpu = -1; | |
1236 | ||
1237 | if (!is_x86_event(event)) | |
1238 | event->pmu->disable(event); | |
1239 | ||
1240 | event->tstamp_running -= event->ctx->time - event->tstamp_stopped; | |
1241 | ||
1242 | if (!is_software_event(event)) | |
1243 | cpuctx->active_oncpu--; | |
1244 | ||
1245 | if (event->attr.exclusive || !cpuctx->active_oncpu) | |
1246 | cpuctx->exclusive = 0; | |
1247 | } | |
1248 | ||
1249 | /* | |
1250 | * Called to enable a whole group of events. | |
1251 | * Returns 1 if the group was enabled, or -EAGAIN if it could not be. | |
1252 | * Assumes the caller has disabled interrupts and has | |
1253 | * frozen the PMU with hw_perf_save_disable. | |
1254 | * | |
1255 | * called with PMU disabled. If successful and return value 1, | |
1256 | * then guaranteed to call perf_enable() and hw_perf_enable() | |
1257 | */ | |
1258 | int hw_perf_group_sched_in(struct perf_event *leader, | |
1259 | struct perf_cpu_context *cpuctx, | |
6e37738a | 1260 | struct perf_event_context *ctx) |
1da53e02 | 1261 | { |
6e37738a | 1262 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
1da53e02 SE |
1263 | struct perf_event *sub; |
1264 | int assign[X86_PMC_IDX_MAX]; | |
1265 | int n0, n1, ret; | |
1266 | ||
0b861225 CG |
1267 | if (!x86_pmu_initialized()) |
1268 | return 0; | |
1269 | ||
1da53e02 SE |
1270 | /* n0 = total number of events */ |
1271 | n0 = collect_events(cpuc, leader, true); | |
1272 | if (n0 < 0) | |
1273 | return n0; | |
1274 | ||
a072738e | 1275 | ret = x86_pmu.schedule_events(cpuc, n0, assign); |
1da53e02 SE |
1276 | if (ret) |
1277 | return ret; | |
1278 | ||
6e37738a | 1279 | ret = x86_event_sched_in(leader, cpuctx); |
1da53e02 SE |
1280 | if (ret) |
1281 | return ret; | |
1282 | ||
1283 | n1 = 1; | |
1284 | list_for_each_entry(sub, &leader->sibling_list, group_entry) { | |
8113070d | 1285 | if (sub->state > PERF_EVENT_STATE_OFF) { |
6e37738a | 1286 | ret = x86_event_sched_in(sub, cpuctx); |
1da53e02 SE |
1287 | if (ret) |
1288 | goto undo; | |
1289 | ++n1; | |
1290 | } | |
1291 | } | |
1292 | /* | |
1293 | * copy new assignment, now we know it is possible | |
1294 | * will be used by hw_perf_enable() | |
1295 | */ | |
1296 | memcpy(cpuc->assign, assign, n0*sizeof(int)); | |
1297 | ||
1298 | cpuc->n_events = n0; | |
356e1f2e | 1299 | cpuc->n_added += n1; |
1da53e02 SE |
1300 | ctx->nr_active += n1; |
1301 | ||
1302 | /* | |
1303 | * 1 means successful and events are active | |
1304 | * This is not quite true because we defer | |
1305 | * actual activation until hw_perf_enable() but | |
1306 | * this way we* ensure caller won't try to enable | |
1307 | * individual events | |
1308 | */ | |
1309 | return 1; | |
1310 | undo: | |
6e37738a | 1311 | x86_event_sched_out(leader, cpuctx); |
1da53e02 SE |
1312 | n0 = 1; |
1313 | list_for_each_entry(sub, &leader->sibling_list, group_entry) { | |
1314 | if (sub->state == PERF_EVENT_STATE_ACTIVE) { | |
6e37738a | 1315 | x86_event_sched_out(sub, cpuctx); |
1da53e02 SE |
1316 | if (++n0 == n1) |
1317 | break; | |
1318 | } | |
1319 | } | |
1320 | return ret; | |
1321 | } | |
1322 | ||
f22f54f4 PZ |
1323 | #include "perf_event_amd.c" |
1324 | #include "perf_event_p6.c" | |
a072738e | 1325 | #include "perf_event_p4.c" |
caff2bef | 1326 | #include "perf_event_intel_lbr.c" |
ca037701 | 1327 | #include "perf_event_intel_ds.c" |
f22f54f4 | 1328 | #include "perf_event_intel.c" |
f87ad35d | 1329 | |
3f6da390 PZ |
1330 | static int __cpuinit |
1331 | x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) | |
1332 | { | |
1333 | unsigned int cpu = (long)hcpu; | |
1334 | ||
1335 | switch (action & ~CPU_TASKS_FROZEN) { | |
1336 | case CPU_UP_PREPARE: | |
1337 | if (x86_pmu.cpu_prepare) | |
1338 | x86_pmu.cpu_prepare(cpu); | |
1339 | break; | |
1340 | ||
1341 | case CPU_STARTING: | |
1342 | if (x86_pmu.cpu_starting) | |
1343 | x86_pmu.cpu_starting(cpu); | |
1344 | break; | |
1345 | ||
1346 | case CPU_DYING: | |
1347 | if (x86_pmu.cpu_dying) | |
1348 | x86_pmu.cpu_dying(cpu); | |
1349 | break; | |
1350 | ||
1351 | case CPU_DEAD: | |
1352 | if (x86_pmu.cpu_dead) | |
1353 | x86_pmu.cpu_dead(cpu); | |
1354 | break; | |
1355 | ||
1356 | default: | |
1357 | break; | |
1358 | } | |
1359 | ||
1360 | return NOTIFY_OK; | |
1361 | } | |
1362 | ||
12558038 CG |
1363 | static void __init pmu_check_apic(void) |
1364 | { | |
1365 | if (cpu_has_apic) | |
1366 | return; | |
1367 | ||
1368 | x86_pmu.apic = 0; | |
1369 | pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n"); | |
1370 | pr_info("no hardware sampling interrupt available.\n"); | |
1371 | } | |
1372 | ||
cdd6c482 | 1373 | void __init init_hw_perf_events(void) |
b56a3802 | 1374 | { |
b622d644 | 1375 | struct event_constraint *c; |
72eae04d RR |
1376 | int err; |
1377 | ||
cdd6c482 | 1378 | pr_info("Performance Events: "); |
1123e3ad | 1379 | |
b56a3802 JSR |
1380 | switch (boot_cpu_data.x86_vendor) { |
1381 | case X86_VENDOR_INTEL: | |
72eae04d | 1382 | err = intel_pmu_init(); |
b56a3802 | 1383 | break; |
f87ad35d | 1384 | case X86_VENDOR_AMD: |
72eae04d | 1385 | err = amd_pmu_init(); |
f87ad35d | 1386 | break; |
4138960a RR |
1387 | default: |
1388 | return; | |
b56a3802 | 1389 | } |
1123e3ad | 1390 | if (err != 0) { |
cdd6c482 | 1391 | pr_cont("no PMU driver, software events only.\n"); |
b56a3802 | 1392 | return; |
1123e3ad | 1393 | } |
b56a3802 | 1394 | |
12558038 CG |
1395 | pmu_check_apic(); |
1396 | ||
1123e3ad | 1397 | pr_cont("%s PMU driver.\n", x86_pmu.name); |
faa28ae0 | 1398 | |
3c44780b PZ |
1399 | if (x86_pmu.quirks) |
1400 | x86_pmu.quirks(); | |
1401 | ||
cdd6c482 IM |
1402 | if (x86_pmu.num_events > X86_PMC_MAX_GENERIC) { |
1403 | WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", | |
1404 | x86_pmu.num_events, X86_PMC_MAX_GENERIC); | |
1405 | x86_pmu.num_events = X86_PMC_MAX_GENERIC; | |
241771ef | 1406 | } |
cdd6c482 IM |
1407 | perf_event_mask = (1 << x86_pmu.num_events) - 1; |
1408 | perf_max_events = x86_pmu.num_events; | |
241771ef | 1409 | |
cdd6c482 IM |
1410 | if (x86_pmu.num_events_fixed > X86_PMC_MAX_FIXED) { |
1411 | WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", | |
1412 | x86_pmu.num_events_fixed, X86_PMC_MAX_FIXED); | |
1413 | x86_pmu.num_events_fixed = X86_PMC_MAX_FIXED; | |
703e937c | 1414 | } |
862a1a5f | 1415 | |
cdd6c482 IM |
1416 | perf_event_mask |= |
1417 | ((1LL << x86_pmu.num_events_fixed)-1) << X86_PMC_IDX_FIXED; | |
1418 | x86_pmu.intel_ctrl = perf_event_mask; | |
241771ef | 1419 | |
cdd6c482 IM |
1420 | perf_events_lapic_init(); |
1421 | register_die_notifier(&perf_event_nmi_notifier); | |
1123e3ad | 1422 | |
63b14649 | 1423 | unconstrained = (struct event_constraint) |
fce877e3 PZ |
1424 | __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_events) - 1, |
1425 | 0, x86_pmu.num_events); | |
63b14649 | 1426 | |
b622d644 PZ |
1427 | if (x86_pmu.event_constraints) { |
1428 | for_each_event_constraint(c, x86_pmu.event_constraints) { | |
1429 | if (c->cmask != INTEL_ARCH_FIXED_MASK) | |
1430 | continue; | |
1431 | ||
1432 | c->idxmsk64 |= (1ULL << x86_pmu.num_events) - 1; | |
1433 | c->weight += x86_pmu.num_events; | |
1434 | } | |
1435 | } | |
1436 | ||
57c0c15b IM |
1437 | pr_info("... version: %d\n", x86_pmu.version); |
1438 | pr_info("... bit width: %d\n", x86_pmu.event_bits); | |
1439 | pr_info("... generic registers: %d\n", x86_pmu.num_events); | |
1440 | pr_info("... value mask: %016Lx\n", x86_pmu.event_mask); | |
1441 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); | |
1442 | pr_info("... fixed-purpose events: %d\n", x86_pmu.num_events_fixed); | |
1443 | pr_info("... event mask: %016Lx\n", perf_event_mask); | |
3f6da390 PZ |
1444 | |
1445 | perf_cpu_notifier(x86_pmu_notifier); | |
241771ef | 1446 | } |
621a01ea | 1447 | |
cdd6c482 | 1448 | static inline void x86_pmu_read(struct perf_event *event) |
ee06094f | 1449 | { |
cc2ad4ba | 1450 | x86_perf_event_update(event); |
ee06094f IM |
1451 | } |
1452 | ||
4aeb0b42 RR |
1453 | static const struct pmu pmu = { |
1454 | .enable = x86_pmu_enable, | |
1455 | .disable = x86_pmu_disable, | |
d76a0812 SE |
1456 | .start = x86_pmu_start, |
1457 | .stop = x86_pmu_stop, | |
4aeb0b42 | 1458 | .read = x86_pmu_read, |
a78ac325 | 1459 | .unthrottle = x86_pmu_unthrottle, |
621a01ea IM |
1460 | }; |
1461 | ||
ca037701 PZ |
1462 | /* |
1463 | * validate that we can schedule this event | |
1464 | */ | |
1465 | static int validate_event(struct perf_event *event) | |
1466 | { | |
1467 | struct cpu_hw_events *fake_cpuc; | |
1468 | struct event_constraint *c; | |
1469 | int ret = 0; | |
1470 | ||
1471 | fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO); | |
1472 | if (!fake_cpuc) | |
1473 | return -ENOMEM; | |
1474 | ||
1475 | c = x86_pmu.get_event_constraints(fake_cpuc, event); | |
1476 | ||
1477 | if (!c || !c->weight) | |
1478 | ret = -ENOSPC; | |
1479 | ||
1480 | if (x86_pmu.put_event_constraints) | |
1481 | x86_pmu.put_event_constraints(fake_cpuc, event); | |
1482 | ||
1483 | kfree(fake_cpuc); | |
1484 | ||
1485 | return ret; | |
1486 | } | |
1487 | ||
1da53e02 SE |
1488 | /* |
1489 | * validate a single event group | |
1490 | * | |
1491 | * validation include: | |
184f412c IM |
1492 | * - check events are compatible which each other |
1493 | * - events do not compete for the same counter | |
1494 | * - number of events <= number of counters | |
1da53e02 SE |
1495 | * |
1496 | * validation ensures the group can be loaded onto the | |
1497 | * PMU if it was the only group available. | |
1498 | */ | |
fe9081cc PZ |
1499 | static int validate_group(struct perf_event *event) |
1500 | { | |
1da53e02 | 1501 | struct perf_event *leader = event->group_leader; |
502568d5 PZ |
1502 | struct cpu_hw_events *fake_cpuc; |
1503 | int ret, n; | |
fe9081cc | 1504 | |
502568d5 PZ |
1505 | ret = -ENOMEM; |
1506 | fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO); | |
1507 | if (!fake_cpuc) | |
1508 | goto out; | |
fe9081cc | 1509 | |
1da53e02 SE |
1510 | /* |
1511 | * the event is not yet connected with its | |
1512 | * siblings therefore we must first collect | |
1513 | * existing siblings, then add the new event | |
1514 | * before we can simulate the scheduling | |
1515 | */ | |
502568d5 PZ |
1516 | ret = -ENOSPC; |
1517 | n = collect_events(fake_cpuc, leader, true); | |
1da53e02 | 1518 | if (n < 0) |
502568d5 | 1519 | goto out_free; |
fe9081cc | 1520 | |
502568d5 PZ |
1521 | fake_cpuc->n_events = n; |
1522 | n = collect_events(fake_cpuc, event, false); | |
1da53e02 | 1523 | if (n < 0) |
502568d5 | 1524 | goto out_free; |
fe9081cc | 1525 | |
502568d5 | 1526 | fake_cpuc->n_events = n; |
1da53e02 | 1527 | |
a072738e | 1528 | ret = x86_pmu.schedule_events(fake_cpuc, n, NULL); |
502568d5 PZ |
1529 | |
1530 | out_free: | |
1531 | kfree(fake_cpuc); | |
1532 | out: | |
1533 | return ret; | |
fe9081cc PZ |
1534 | } |
1535 | ||
cdd6c482 | 1536 | const struct pmu *hw_perf_event_init(struct perf_event *event) |
621a01ea | 1537 | { |
8113070d | 1538 | const struct pmu *tmp; |
621a01ea IM |
1539 | int err; |
1540 | ||
cdd6c482 | 1541 | err = __hw_perf_event_init(event); |
fe9081cc | 1542 | if (!err) { |
8113070d SE |
1543 | /* |
1544 | * we temporarily connect event to its pmu | |
1545 | * such that validate_group() can classify | |
1546 | * it as an x86 event using is_x86_event() | |
1547 | */ | |
1548 | tmp = event->pmu; | |
1549 | event->pmu = &pmu; | |
1550 | ||
fe9081cc PZ |
1551 | if (event->group_leader != event) |
1552 | err = validate_group(event); | |
ca037701 PZ |
1553 | else |
1554 | err = validate_event(event); | |
8113070d SE |
1555 | |
1556 | event->pmu = tmp; | |
fe9081cc | 1557 | } |
a1792cda | 1558 | if (err) { |
cdd6c482 IM |
1559 | if (event->destroy) |
1560 | event->destroy(event); | |
9ea98e19 | 1561 | return ERR_PTR(err); |
a1792cda | 1562 | } |
621a01ea | 1563 | |
4aeb0b42 | 1564 | return &pmu; |
621a01ea | 1565 | } |
d7d59fb3 PZ |
1566 | |
1567 | /* | |
1568 | * callchain support | |
1569 | */ | |
1570 | ||
1571 | static inline | |
f9188e02 | 1572 | void callchain_store(struct perf_callchain_entry *entry, u64 ip) |
d7d59fb3 | 1573 | { |
f9188e02 | 1574 | if (entry->nr < PERF_MAX_STACK_DEPTH) |
d7d59fb3 PZ |
1575 | entry->ip[entry->nr++] = ip; |
1576 | } | |
1577 | ||
245b2e70 TH |
1578 | static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry); |
1579 | static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_nmi_entry); | |
d7d59fb3 PZ |
1580 | |
1581 | ||
1582 | static void | |
1583 | backtrace_warning_symbol(void *data, char *msg, unsigned long symbol) | |
1584 | { | |
1585 | /* Ignore warnings */ | |
1586 | } | |
1587 | ||
1588 | static void backtrace_warning(void *data, char *msg) | |
1589 | { | |
1590 | /* Ignore warnings */ | |
1591 | } | |
1592 | ||
1593 | static int backtrace_stack(void *data, char *name) | |
1594 | { | |
038e836e | 1595 | return 0; |
d7d59fb3 PZ |
1596 | } |
1597 | ||
1598 | static void backtrace_address(void *data, unsigned long addr, int reliable) | |
1599 | { | |
1600 | struct perf_callchain_entry *entry = data; | |
1601 | ||
1602 | if (reliable) | |
1603 | callchain_store(entry, addr); | |
1604 | } | |
1605 | ||
1606 | static const struct stacktrace_ops backtrace_ops = { | |
1607 | .warning = backtrace_warning, | |
1608 | .warning_symbol = backtrace_warning_symbol, | |
1609 | .stack = backtrace_stack, | |
1610 | .address = backtrace_address, | |
06d65bda | 1611 | .walk_stack = print_context_stack_bp, |
d7d59fb3 PZ |
1612 | }; |
1613 | ||
038e836e IM |
1614 | #include "../dumpstack.h" |
1615 | ||
d7d59fb3 PZ |
1616 | static void |
1617 | perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1618 | { | |
f9188e02 | 1619 | callchain_store(entry, PERF_CONTEXT_KERNEL); |
038e836e | 1620 | callchain_store(entry, regs->ip); |
d7d59fb3 | 1621 | |
48b5ba9c | 1622 | dump_trace(NULL, regs, NULL, regs->bp, &backtrace_ops, entry); |
d7d59fb3 PZ |
1623 | } |
1624 | ||
74193ef0 PZ |
1625 | static int copy_stack_frame(const void __user *fp, struct stack_frame *frame) |
1626 | { | |
1627 | unsigned long bytes; | |
1628 | ||
1629 | bytes = copy_from_user_nmi(frame, fp, sizeof(*frame)); | |
1630 | ||
1631 | return bytes == sizeof(*frame); | |
d7d59fb3 PZ |
1632 | } |
1633 | ||
1634 | static void | |
1635 | perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1636 | { | |
1637 | struct stack_frame frame; | |
1638 | const void __user *fp; | |
1639 | ||
5a6cec3a IM |
1640 | if (!user_mode(regs)) |
1641 | regs = task_pt_regs(current); | |
1642 | ||
74193ef0 | 1643 | fp = (void __user *)regs->bp; |
d7d59fb3 | 1644 | |
f9188e02 | 1645 | callchain_store(entry, PERF_CONTEXT_USER); |
d7d59fb3 PZ |
1646 | callchain_store(entry, regs->ip); |
1647 | ||
f9188e02 | 1648 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
038e836e | 1649 | frame.next_frame = NULL; |
d7d59fb3 PZ |
1650 | frame.return_address = 0; |
1651 | ||
1652 | if (!copy_stack_frame(fp, &frame)) | |
1653 | break; | |
1654 | ||
5a6cec3a | 1655 | if ((unsigned long)fp < regs->sp) |
d7d59fb3 PZ |
1656 | break; |
1657 | ||
1658 | callchain_store(entry, frame.return_address); | |
038e836e | 1659 | fp = frame.next_frame; |
d7d59fb3 PZ |
1660 | } |
1661 | } | |
1662 | ||
1663 | static void | |
1664 | perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1665 | { | |
1666 | int is_user; | |
1667 | ||
1668 | if (!regs) | |
1669 | return; | |
1670 | ||
1671 | is_user = user_mode(regs); | |
1672 | ||
d7d59fb3 PZ |
1673 | if (is_user && current->state != TASK_RUNNING) |
1674 | return; | |
1675 | ||
1676 | if (!is_user) | |
1677 | perf_callchain_kernel(regs, entry); | |
1678 | ||
1679 | if (current->mm) | |
1680 | perf_callchain_user(regs, entry); | |
1681 | } | |
1682 | ||
1683 | struct perf_callchain_entry *perf_callchain(struct pt_regs *regs) | |
1684 | { | |
1685 | struct perf_callchain_entry *entry; | |
1686 | ||
1687 | if (in_nmi()) | |
245b2e70 | 1688 | entry = &__get_cpu_var(pmc_nmi_entry); |
d7d59fb3 | 1689 | else |
245b2e70 | 1690 | entry = &__get_cpu_var(pmc_irq_entry); |
d7d59fb3 PZ |
1691 | |
1692 | entry->nr = 0; | |
1693 | ||
1694 | perf_do_callchain(regs, entry); | |
1695 | ||
1696 | return entry; | |
1697 | } | |
5331d7b8 | 1698 | |
1d199b1a | 1699 | #ifdef CONFIG_EVENT_TRACING |
5331d7b8 FW |
1700 | void perf_arch_fetch_caller_regs(struct pt_regs *regs, unsigned long ip, int skip) |
1701 | { | |
1702 | regs->ip = ip; | |
1703 | /* | |
1704 | * perf_arch_fetch_caller_regs adds another call, we need to increment | |
1705 | * the skip level | |
1706 | */ | |
1707 | regs->bp = rewind_frame_pointer(skip + 1); | |
1708 | regs->cs = __KERNEL_CS; | |
1709 | local_save_flags(regs->flags); | |
1710 | } | |
1d199b1a | 1711 | #endif |