Commit | Line | Data |
---|---|---|
241771ef | 1 | /* |
cdd6c482 | 2 | * Performance events x86 architecture code |
241771ef | 3 | * |
98144511 IM |
4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> | |
30dd568c | 9 | * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> |
1da53e02 | 10 | * Copyright (C) 2009 Google, Inc., Stephane Eranian |
241771ef IM |
11 | * |
12 | * For licencing details see kernel-base/COPYING | |
13 | */ | |
14 | ||
cdd6c482 | 15 | #include <linux/perf_event.h> |
241771ef IM |
16 | #include <linux/capability.h> |
17 | #include <linux/notifier.h> | |
18 | #include <linux/hardirq.h> | |
19 | #include <linux/kprobes.h> | |
4ac13294 | 20 | #include <linux/module.h> |
241771ef IM |
21 | #include <linux/kdebug.h> |
22 | #include <linux/sched.h> | |
d7d59fb3 | 23 | #include <linux/uaccess.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
30dd568c | 25 | #include <linux/cpu.h> |
272d30be | 26 | #include <linux/bitops.h> |
0c9d42ed | 27 | #include <linux/device.h> |
241771ef | 28 | |
241771ef | 29 | #include <asm/apic.h> |
d7d59fb3 | 30 | #include <asm/stacktrace.h> |
4e935e47 | 31 | #include <asm/nmi.h> |
69092624 | 32 | #include <asm/smp.h> |
c8e5910e | 33 | #include <asm/alternative.h> |
7911d3f7 | 34 | #include <asm/mmu_context.h> |
375074cc | 35 | #include <asm/tlbflush.h> |
e3f3541c | 36 | #include <asm/timer.h> |
d07bdfd3 PZ |
37 | #include <asm/desc.h> |
38 | #include <asm/ldt.h> | |
241771ef | 39 | |
de0428a7 KW |
40 | #include "perf_event.h" |
41 | ||
de0428a7 | 42 | struct x86_pmu x86_pmu __read_mostly; |
efc9f05d | 43 | |
de0428a7 | 44 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { |
b0f3f28e PZ |
45 | .enabled = 1, |
46 | }; | |
241771ef | 47 | |
a6673429 AL |
48 | struct static_key rdpmc_always_available = STATIC_KEY_INIT_FALSE; |
49 | ||
de0428a7 | 50 | u64 __read_mostly hw_cache_event_ids |
8326f44d IM |
51 | [PERF_COUNT_HW_CACHE_MAX] |
52 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
53 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
de0428a7 | 54 | u64 __read_mostly hw_cache_extra_regs |
e994d7d2 AK |
55 | [PERF_COUNT_HW_CACHE_MAX] |
56 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
57 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
8326f44d | 58 | |
ee06094f | 59 | /* |
cdd6c482 IM |
60 | * Propagate event elapsed time into the generic event. |
61 | * Can only be executed on the CPU where the event is active. | |
ee06094f IM |
62 | * Returns the delta events processed. |
63 | */ | |
de0428a7 | 64 | u64 x86_perf_event_update(struct perf_event *event) |
ee06094f | 65 | { |
cc2ad4ba | 66 | struct hw_perf_event *hwc = &event->hw; |
948b1bb8 | 67 | int shift = 64 - x86_pmu.cntval_bits; |
ec3232bd | 68 | u64 prev_raw_count, new_raw_count; |
cc2ad4ba | 69 | int idx = hwc->idx; |
ec3232bd | 70 | s64 delta; |
ee06094f | 71 | |
15c7ad51 | 72 | if (idx == INTEL_PMC_IDX_FIXED_BTS) |
30dd568c MM |
73 | return 0; |
74 | ||
ee06094f | 75 | /* |
cdd6c482 | 76 | * Careful: an NMI might modify the previous event value. |
ee06094f IM |
77 | * |
78 | * Our tactic to handle this is to first atomically read and | |
79 | * exchange a new raw count - then add that new-prev delta | |
cdd6c482 | 80 | * count to the generic event atomically: |
ee06094f IM |
81 | */ |
82 | again: | |
e7850595 | 83 | prev_raw_count = local64_read(&hwc->prev_count); |
c48b6053 | 84 | rdpmcl(hwc->event_base_rdpmc, new_raw_count); |
ee06094f | 85 | |
e7850595 | 86 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
ee06094f IM |
87 | new_raw_count) != prev_raw_count) |
88 | goto again; | |
89 | ||
90 | /* | |
91 | * Now we have the new raw value and have updated the prev | |
92 | * timestamp already. We can now calculate the elapsed delta | |
cdd6c482 | 93 | * (event-)time and add that to the generic event. |
ee06094f IM |
94 | * |
95 | * Careful, not all hw sign-extends above the physical width | |
ec3232bd | 96 | * of the count. |
ee06094f | 97 | */ |
ec3232bd PZ |
98 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
99 | delta >>= shift; | |
ee06094f | 100 | |
e7850595 PZ |
101 | local64_add(delta, &event->count); |
102 | local64_sub(delta, &hwc->period_left); | |
4b7bfd0d RR |
103 | |
104 | return new_raw_count; | |
ee06094f IM |
105 | } |
106 | ||
a7e3ed1e AK |
107 | /* |
108 | * Find and validate any extra registers to set up. | |
109 | */ | |
110 | static int x86_pmu_extra_regs(u64 config, struct perf_event *event) | |
111 | { | |
efc9f05d | 112 | struct hw_perf_event_extra *reg; |
a7e3ed1e AK |
113 | struct extra_reg *er; |
114 | ||
efc9f05d | 115 | reg = &event->hw.extra_reg; |
a7e3ed1e AK |
116 | |
117 | if (!x86_pmu.extra_regs) | |
118 | return 0; | |
119 | ||
120 | for (er = x86_pmu.extra_regs; er->msr; er++) { | |
121 | if (er->event != (config & er->config_mask)) | |
122 | continue; | |
123 | if (event->attr.config1 & ~er->valid_mask) | |
124 | return -EINVAL; | |
338b522c KL |
125 | /* Check if the extra msrs can be safely accessed*/ |
126 | if (!er->extra_msr_access) | |
127 | return -ENXIO; | |
efc9f05d SE |
128 | |
129 | reg->idx = er->idx; | |
130 | reg->config = event->attr.config1; | |
131 | reg->reg = er->msr; | |
a7e3ed1e AK |
132 | break; |
133 | } | |
134 | return 0; | |
135 | } | |
136 | ||
cdd6c482 | 137 | static atomic_t active_events; |
4e935e47 PZ |
138 | static DEFINE_MUTEX(pmc_reserve_mutex); |
139 | ||
b27ea29c RR |
140 | #ifdef CONFIG_X86_LOCAL_APIC |
141 | ||
4e935e47 PZ |
142 | static bool reserve_pmc_hardware(void) |
143 | { | |
144 | int i; | |
145 | ||
948b1bb8 | 146 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 | 147 | if (!reserve_perfctr_nmi(x86_pmu_event_addr(i))) |
4e935e47 PZ |
148 | goto perfctr_fail; |
149 | } | |
150 | ||
948b1bb8 | 151 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 | 152 | if (!reserve_evntsel_nmi(x86_pmu_config_addr(i))) |
4e935e47 PZ |
153 | goto eventsel_fail; |
154 | } | |
155 | ||
156 | return true; | |
157 | ||
158 | eventsel_fail: | |
159 | for (i--; i >= 0; i--) | |
41bf4989 | 160 | release_evntsel_nmi(x86_pmu_config_addr(i)); |
4e935e47 | 161 | |
948b1bb8 | 162 | i = x86_pmu.num_counters; |
4e935e47 PZ |
163 | |
164 | perfctr_fail: | |
165 | for (i--; i >= 0; i--) | |
41bf4989 | 166 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
4e935e47 | 167 | |
4e935e47 PZ |
168 | return false; |
169 | } | |
170 | ||
171 | static void release_pmc_hardware(void) | |
172 | { | |
173 | int i; | |
174 | ||
948b1bb8 | 175 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 RR |
176 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
177 | release_evntsel_nmi(x86_pmu_config_addr(i)); | |
4e935e47 | 178 | } |
4e935e47 PZ |
179 | } |
180 | ||
b27ea29c RR |
181 | #else |
182 | ||
183 | static bool reserve_pmc_hardware(void) { return true; } | |
184 | static void release_pmc_hardware(void) {} | |
185 | ||
186 | #endif | |
187 | ||
33c6d6a7 DZ |
188 | static bool check_hw_exists(void) |
189 | { | |
a5ebe0ba GD |
190 | u64 val, val_fail, val_new= ~0; |
191 | int i, reg, reg_fail, ret = 0; | |
192 | int bios_fail = 0; | |
68ab7476 | 193 | int reg_safe = -1; |
33c6d6a7 | 194 | |
4407204c PZ |
195 | /* |
196 | * Check to see if the BIOS enabled any of the counters, if so | |
197 | * complain and bail. | |
198 | */ | |
199 | for (i = 0; i < x86_pmu.num_counters; i++) { | |
41bf4989 | 200 | reg = x86_pmu_config_addr(i); |
4407204c PZ |
201 | ret = rdmsrl_safe(reg, &val); |
202 | if (ret) | |
203 | goto msr_fail; | |
a5ebe0ba GD |
204 | if (val & ARCH_PERFMON_EVENTSEL_ENABLE) { |
205 | bios_fail = 1; | |
206 | val_fail = val; | |
207 | reg_fail = reg; | |
68ab7476 DZ |
208 | } else { |
209 | reg_safe = i; | |
a5ebe0ba | 210 | } |
4407204c PZ |
211 | } |
212 | ||
213 | if (x86_pmu.num_counters_fixed) { | |
214 | reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; | |
215 | ret = rdmsrl_safe(reg, &val); | |
216 | if (ret) | |
217 | goto msr_fail; | |
218 | for (i = 0; i < x86_pmu.num_counters_fixed; i++) { | |
a5ebe0ba GD |
219 | if (val & (0x03 << i*4)) { |
220 | bios_fail = 1; | |
221 | val_fail = val; | |
222 | reg_fail = reg; | |
223 | } | |
4407204c PZ |
224 | } |
225 | } | |
226 | ||
68ab7476 DZ |
227 | /* |
228 | * If all the counters are enabled, the below test will always | |
229 | * fail. The tools will also become useless in this scenario. | |
230 | * Just fail and disable the hardware counters. | |
231 | */ | |
232 | ||
233 | if (reg_safe == -1) { | |
234 | reg = reg_safe; | |
235 | goto msr_fail; | |
236 | } | |
237 | ||
4407204c | 238 | /* |
bffd5fc2 AP |
239 | * Read the current value, change it and read it back to see if it |
240 | * matches, this is needed to detect certain hardware emulators | |
241 | * (qemu/kvm) that don't trap on the MSR access and always return 0s. | |
4407204c | 242 | */ |
68ab7476 | 243 | reg = x86_pmu_event_addr(reg_safe); |
bffd5fc2 AP |
244 | if (rdmsrl_safe(reg, &val)) |
245 | goto msr_fail; | |
246 | val ^= 0xffffUL; | |
f285f92f RR |
247 | ret = wrmsrl_safe(reg, val); |
248 | ret |= rdmsrl_safe(reg, &val_new); | |
33c6d6a7 | 249 | if (ret || val != val_new) |
4407204c | 250 | goto msr_fail; |
33c6d6a7 | 251 | |
45daae57 IM |
252 | /* |
253 | * We still allow the PMU driver to operate: | |
254 | */ | |
a5ebe0ba GD |
255 | if (bios_fail) { |
256 | printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n"); | |
257 | printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg_fail, val_fail); | |
258 | } | |
45daae57 IM |
259 | |
260 | return true; | |
4407204c PZ |
261 | |
262 | msr_fail: | |
263 | printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n"); | |
65d71fe1 PZI |
264 | printk("%sFailed to access perfctr msr (MSR %x is %Lx)\n", |
265 | boot_cpu_has(X86_FEATURE_HYPERVISOR) ? KERN_INFO : KERN_ERR, | |
266 | reg, val_new); | |
45daae57 | 267 | |
4407204c | 268 | return false; |
33c6d6a7 DZ |
269 | } |
270 | ||
cdd6c482 | 271 | static void hw_perf_event_destroy(struct perf_event *event) |
4e935e47 | 272 | { |
cdd6c482 | 273 | if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) { |
4e935e47 | 274 | release_pmc_hardware(); |
ca037701 | 275 | release_ds_buffers(); |
4e935e47 PZ |
276 | mutex_unlock(&pmc_reserve_mutex); |
277 | } | |
278 | } | |
279 | ||
48070342 AS |
280 | void hw_perf_lbr_event_destroy(struct perf_event *event) |
281 | { | |
282 | hw_perf_event_destroy(event); | |
283 | ||
284 | /* undo the lbr/bts event accounting */ | |
285 | x86_del_exclusive(x86_lbr_exclusive_lbr); | |
286 | } | |
287 | ||
85cf9dba RR |
288 | static inline int x86_pmu_initialized(void) |
289 | { | |
290 | return x86_pmu.handle_irq != NULL; | |
291 | } | |
292 | ||
8326f44d | 293 | static inline int |
e994d7d2 | 294 | set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event) |
8326f44d | 295 | { |
e994d7d2 | 296 | struct perf_event_attr *attr = &event->attr; |
8326f44d IM |
297 | unsigned int cache_type, cache_op, cache_result; |
298 | u64 config, val; | |
299 | ||
300 | config = attr->config; | |
301 | ||
302 | cache_type = (config >> 0) & 0xff; | |
303 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
304 | return -EINVAL; | |
305 | ||
306 | cache_op = (config >> 8) & 0xff; | |
307 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
308 | return -EINVAL; | |
309 | ||
310 | cache_result = (config >> 16) & 0xff; | |
311 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
312 | return -EINVAL; | |
313 | ||
314 | val = hw_cache_event_ids[cache_type][cache_op][cache_result]; | |
315 | ||
316 | if (val == 0) | |
317 | return -ENOENT; | |
318 | ||
319 | if (val == -1) | |
320 | return -EINVAL; | |
321 | ||
322 | hwc->config |= val; | |
e994d7d2 AK |
323 | attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result]; |
324 | return x86_pmu_extra_regs(val, event); | |
8326f44d IM |
325 | } |
326 | ||
48070342 AS |
327 | /* |
328 | * Check if we can create event of a certain type (that no conflicting events | |
329 | * are present). | |
330 | */ | |
331 | int x86_add_exclusive(unsigned int what) | |
332 | { | |
333 | int ret = -EBUSY, i; | |
334 | ||
335 | if (atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) | |
336 | return 0; | |
337 | ||
338 | mutex_lock(&pmc_reserve_mutex); | |
339 | for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++) | |
340 | if (i != what && atomic_read(&x86_pmu.lbr_exclusive[i])) | |
341 | goto out; | |
342 | ||
343 | atomic_inc(&x86_pmu.lbr_exclusive[what]); | |
344 | ret = 0; | |
345 | ||
346 | out: | |
347 | mutex_unlock(&pmc_reserve_mutex); | |
348 | return ret; | |
349 | } | |
350 | ||
351 | void x86_del_exclusive(unsigned int what) | |
352 | { | |
353 | atomic_dec(&x86_pmu.lbr_exclusive[what]); | |
354 | } | |
355 | ||
de0428a7 | 356 | int x86_setup_perfctr(struct perf_event *event) |
c1726f34 RR |
357 | { |
358 | struct perf_event_attr *attr = &event->attr; | |
359 | struct hw_perf_event *hwc = &event->hw; | |
360 | u64 config; | |
361 | ||
6c7e550f | 362 | if (!is_sampling_event(event)) { |
c1726f34 RR |
363 | hwc->sample_period = x86_pmu.max_period; |
364 | hwc->last_period = hwc->sample_period; | |
e7850595 | 365 | local64_set(&hwc->period_left, hwc->sample_period); |
c1726f34 RR |
366 | } |
367 | ||
368 | if (attr->type == PERF_TYPE_RAW) | |
ed13ec58 | 369 | return x86_pmu_extra_regs(event->attr.config, event); |
c1726f34 RR |
370 | |
371 | if (attr->type == PERF_TYPE_HW_CACHE) | |
e994d7d2 | 372 | return set_ext_hw_attr(hwc, event); |
c1726f34 RR |
373 | |
374 | if (attr->config >= x86_pmu.max_events) | |
375 | return -EINVAL; | |
376 | ||
377 | /* | |
378 | * The generic map: | |
379 | */ | |
380 | config = x86_pmu.event_map(attr->config); | |
381 | ||
382 | if (config == 0) | |
383 | return -ENOENT; | |
384 | ||
385 | if (config == -1LL) | |
386 | return -EINVAL; | |
387 | ||
388 | /* | |
389 | * Branch tracing: | |
390 | */ | |
18a073a3 PZ |
391 | if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS && |
392 | !attr->freq && hwc->sample_period == 1) { | |
c1726f34 | 393 | /* BTS is not supported by this architecture. */ |
6809b6ea | 394 | if (!x86_pmu.bts_active) |
c1726f34 RR |
395 | return -EOPNOTSUPP; |
396 | ||
397 | /* BTS is currently only allowed for user-mode. */ | |
398 | if (!attr->exclude_kernel) | |
399 | return -EOPNOTSUPP; | |
48070342 AS |
400 | |
401 | /* disallow bts if conflicting events are present */ | |
402 | if (x86_add_exclusive(x86_lbr_exclusive_lbr)) | |
403 | return -EBUSY; | |
404 | ||
405 | event->destroy = hw_perf_lbr_event_destroy; | |
c1726f34 RR |
406 | } |
407 | ||
408 | hwc->config |= config; | |
409 | ||
410 | return 0; | |
411 | } | |
4261e0e0 | 412 | |
ff3fb511 SE |
413 | /* |
414 | * check that branch_sample_type is compatible with | |
415 | * settings needed for precise_ip > 1 which implies | |
416 | * using the LBR to capture ALL taken branches at the | |
417 | * priv levels of the measurement | |
418 | */ | |
419 | static inline int precise_br_compat(struct perf_event *event) | |
420 | { | |
421 | u64 m = event->attr.branch_sample_type; | |
422 | u64 b = 0; | |
423 | ||
424 | /* must capture all branches */ | |
425 | if (!(m & PERF_SAMPLE_BRANCH_ANY)) | |
426 | return 0; | |
427 | ||
428 | m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER; | |
429 | ||
430 | if (!event->attr.exclude_user) | |
431 | b |= PERF_SAMPLE_BRANCH_USER; | |
432 | ||
433 | if (!event->attr.exclude_kernel) | |
434 | b |= PERF_SAMPLE_BRANCH_KERNEL; | |
435 | ||
436 | /* | |
437 | * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86 | |
438 | */ | |
439 | ||
440 | return m == b; | |
441 | } | |
442 | ||
de0428a7 | 443 | int x86_pmu_hw_config(struct perf_event *event) |
a072738e | 444 | { |
ab608344 PZ |
445 | if (event->attr.precise_ip) { |
446 | int precise = 0; | |
447 | ||
448 | /* Support for constant skid */ | |
c93dc84c | 449 | if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) { |
ab608344 PZ |
450 | precise++; |
451 | ||
5553be26 | 452 | /* Support for IP fixup */ |
03de874a | 453 | if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2) |
5553be26 PZ |
454 | precise++; |
455 | } | |
ab608344 PZ |
456 | |
457 | if (event->attr.precise_ip > precise) | |
458 | return -EOPNOTSUPP; | |
4b854900 YZ |
459 | } |
460 | /* | |
461 | * check that PEBS LBR correction does not conflict with | |
462 | * whatever the user is asking with attr->branch_sample_type | |
463 | */ | |
464 | if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) { | |
465 | u64 *br_type = &event->attr.branch_sample_type; | |
466 | ||
467 | if (has_branch_stack(event)) { | |
468 | if (!precise_br_compat(event)) | |
469 | return -EOPNOTSUPP; | |
470 | ||
471 | /* branch_sample_type is compatible */ | |
472 | ||
473 | } else { | |
474 | /* | |
475 | * user did not specify branch_sample_type | |
476 | * | |
477 | * For PEBS fixups, we capture all | |
478 | * the branches at the priv level of the | |
479 | * event. | |
480 | */ | |
481 | *br_type = PERF_SAMPLE_BRANCH_ANY; | |
482 | ||
483 | if (!event->attr.exclude_user) | |
484 | *br_type |= PERF_SAMPLE_BRANCH_USER; | |
485 | ||
486 | if (!event->attr.exclude_kernel) | |
487 | *br_type |= PERF_SAMPLE_BRANCH_KERNEL; | |
ff3fb511 | 488 | } |
ab608344 PZ |
489 | } |
490 | ||
e18bf526 YZ |
491 | if (event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_CALL_STACK) |
492 | event->attach_state |= PERF_ATTACH_TASK_DATA; | |
493 | ||
a072738e CG |
494 | /* |
495 | * Generate PMC IRQs: | |
496 | * (keep 'enabled' bit clear for now) | |
497 | */ | |
b4cdc5c2 | 498 | event->hw.config = ARCH_PERFMON_EVENTSEL_INT; |
a072738e CG |
499 | |
500 | /* | |
501 | * Count user and OS events unless requested not to | |
502 | */ | |
b4cdc5c2 PZ |
503 | if (!event->attr.exclude_user) |
504 | event->hw.config |= ARCH_PERFMON_EVENTSEL_USR; | |
505 | if (!event->attr.exclude_kernel) | |
506 | event->hw.config |= ARCH_PERFMON_EVENTSEL_OS; | |
a072738e | 507 | |
b4cdc5c2 PZ |
508 | if (event->attr.type == PERF_TYPE_RAW) |
509 | event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK; | |
a072738e | 510 | |
294fe0f5 AK |
511 | if (event->attr.sample_period && x86_pmu.limit_period) { |
512 | if (x86_pmu.limit_period(event, event->attr.sample_period) > | |
513 | event->attr.sample_period) | |
514 | return -EINVAL; | |
515 | } | |
516 | ||
9d0fcba6 | 517 | return x86_setup_perfctr(event); |
a098f448 RR |
518 | } |
519 | ||
241771ef | 520 | /* |
0d48696f | 521 | * Setup the hardware configuration for a given attr_type |
241771ef | 522 | */ |
b0a873eb | 523 | static int __x86_pmu_event_init(struct perf_event *event) |
241771ef | 524 | { |
4e935e47 | 525 | int err; |
241771ef | 526 | |
85cf9dba RR |
527 | if (!x86_pmu_initialized()) |
528 | return -ENODEV; | |
241771ef | 529 | |
4e935e47 | 530 | err = 0; |
cdd6c482 | 531 | if (!atomic_inc_not_zero(&active_events)) { |
4e935e47 | 532 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 | 533 | if (atomic_read(&active_events) == 0) { |
30dd568c MM |
534 | if (!reserve_pmc_hardware()) |
535 | err = -EBUSY; | |
f80c9e30 PZ |
536 | else |
537 | reserve_ds_buffers(); | |
30dd568c MM |
538 | } |
539 | if (!err) | |
cdd6c482 | 540 | atomic_inc(&active_events); |
4e935e47 PZ |
541 | mutex_unlock(&pmc_reserve_mutex); |
542 | } | |
543 | if (err) | |
544 | return err; | |
545 | ||
cdd6c482 | 546 | event->destroy = hw_perf_event_destroy; |
a1792cda | 547 | |
4261e0e0 RR |
548 | event->hw.idx = -1; |
549 | event->hw.last_cpu = -1; | |
550 | event->hw.last_tag = ~0ULL; | |
b690081d | 551 | |
efc9f05d SE |
552 | /* mark unused */ |
553 | event->hw.extra_reg.idx = EXTRA_REG_NONE; | |
b36817e8 SE |
554 | event->hw.branch_reg.idx = EXTRA_REG_NONE; |
555 | ||
9d0fcba6 | 556 | return x86_pmu.hw_config(event); |
4261e0e0 RR |
557 | } |
558 | ||
de0428a7 | 559 | void x86_pmu_disable_all(void) |
f87ad35d | 560 | { |
89cbc767 | 561 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
9e35ad38 PZ |
562 | int idx; |
563 | ||
948b1bb8 | 564 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
b0f3f28e PZ |
565 | u64 val; |
566 | ||
43f6201a | 567 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 568 | continue; |
41bf4989 | 569 | rdmsrl(x86_pmu_config_addr(idx), val); |
bb1165d6 | 570 | if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE)) |
4295ee62 | 571 | continue; |
bb1165d6 | 572 | val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; |
41bf4989 | 573 | wrmsrl(x86_pmu_config_addr(idx), val); |
f87ad35d | 574 | } |
f87ad35d JSR |
575 | } |
576 | ||
a4eaf7f1 | 577 | static void x86_pmu_disable(struct pmu *pmu) |
b56a3802 | 578 | { |
89cbc767 | 579 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
1da53e02 | 580 | |
85cf9dba | 581 | if (!x86_pmu_initialized()) |
9e35ad38 | 582 | return; |
1da53e02 | 583 | |
1a6e21f7 PZ |
584 | if (!cpuc->enabled) |
585 | return; | |
586 | ||
587 | cpuc->n_added = 0; | |
588 | cpuc->enabled = 0; | |
589 | barrier(); | |
1da53e02 SE |
590 | |
591 | x86_pmu.disable_all(); | |
b56a3802 | 592 | } |
241771ef | 593 | |
de0428a7 | 594 | void x86_pmu_enable_all(int added) |
f87ad35d | 595 | { |
89cbc767 | 596 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
f87ad35d JSR |
597 | int idx; |
598 | ||
948b1bb8 | 599 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
d45dd923 | 600 | struct hw_perf_event *hwc = &cpuc->events[idx]->hw; |
b0f3f28e | 601 | |
43f6201a | 602 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 603 | continue; |
984b838c | 604 | |
d45dd923 | 605 | __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); |
f87ad35d JSR |
606 | } |
607 | } | |
608 | ||
51b0fe39 | 609 | static struct pmu pmu; |
1da53e02 SE |
610 | |
611 | static inline int is_x86_event(struct perf_event *event) | |
612 | { | |
613 | return event->pmu == &pmu; | |
614 | } | |
615 | ||
1e2ad28f RR |
616 | /* |
617 | * Event scheduler state: | |
618 | * | |
619 | * Assign events iterating over all events and counters, beginning | |
620 | * with events with least weights first. Keep the current iterator | |
621 | * state in struct sched_state. | |
622 | */ | |
623 | struct sched_state { | |
624 | int weight; | |
625 | int event; /* event index */ | |
626 | int counter; /* counter index */ | |
627 | int unassigned; /* number of events to be assigned left */ | |
cc1790cf | 628 | int nr_gp; /* number of GP counters used */ |
1e2ad28f RR |
629 | unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
630 | }; | |
631 | ||
bc1738f6 RR |
632 | /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */ |
633 | #define SCHED_STATES_MAX 2 | |
634 | ||
1e2ad28f RR |
635 | struct perf_sched { |
636 | int max_weight; | |
637 | int max_events; | |
cc1790cf PZ |
638 | int max_gp; |
639 | int saved_states; | |
b371b594 | 640 | struct event_constraint **constraints; |
1e2ad28f | 641 | struct sched_state state; |
bc1738f6 | 642 | struct sched_state saved[SCHED_STATES_MAX]; |
1e2ad28f RR |
643 | }; |
644 | ||
645 | /* | |
646 | * Initialize interator that runs through all events and counters. | |
647 | */ | |
b371b594 | 648 | static void perf_sched_init(struct perf_sched *sched, struct event_constraint **constraints, |
cc1790cf | 649 | int num, int wmin, int wmax, int gpmax) |
1e2ad28f RR |
650 | { |
651 | int idx; | |
652 | ||
653 | memset(sched, 0, sizeof(*sched)); | |
654 | sched->max_events = num; | |
655 | sched->max_weight = wmax; | |
cc1790cf | 656 | sched->max_gp = gpmax; |
b371b594 | 657 | sched->constraints = constraints; |
1e2ad28f RR |
658 | |
659 | for (idx = 0; idx < num; idx++) { | |
b371b594 | 660 | if (constraints[idx]->weight == wmin) |
1e2ad28f RR |
661 | break; |
662 | } | |
663 | ||
664 | sched->state.event = idx; /* start with min weight */ | |
665 | sched->state.weight = wmin; | |
666 | sched->state.unassigned = num; | |
667 | } | |
668 | ||
bc1738f6 RR |
669 | static void perf_sched_save_state(struct perf_sched *sched) |
670 | { | |
671 | if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX)) | |
672 | return; | |
673 | ||
674 | sched->saved[sched->saved_states] = sched->state; | |
675 | sched->saved_states++; | |
676 | } | |
677 | ||
678 | static bool perf_sched_restore_state(struct perf_sched *sched) | |
679 | { | |
680 | if (!sched->saved_states) | |
681 | return false; | |
682 | ||
683 | sched->saved_states--; | |
684 | sched->state = sched->saved[sched->saved_states]; | |
685 | ||
686 | /* continue with next counter: */ | |
687 | clear_bit(sched->state.counter++, sched->state.used); | |
688 | ||
689 | return true; | |
690 | } | |
691 | ||
1e2ad28f RR |
692 | /* |
693 | * Select a counter for the current event to schedule. Return true on | |
694 | * success. | |
695 | */ | |
bc1738f6 | 696 | static bool __perf_sched_find_counter(struct perf_sched *sched) |
1e2ad28f RR |
697 | { |
698 | struct event_constraint *c; | |
699 | int idx; | |
700 | ||
701 | if (!sched->state.unassigned) | |
702 | return false; | |
703 | ||
704 | if (sched->state.event >= sched->max_events) | |
705 | return false; | |
706 | ||
b371b594 | 707 | c = sched->constraints[sched->state.event]; |
4defea85 | 708 | /* Prefer fixed purpose counters */ |
15c7ad51 RR |
709 | if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) { |
710 | idx = INTEL_PMC_IDX_FIXED; | |
307b1cd7 | 711 | for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) { |
4defea85 PZ |
712 | if (!__test_and_set_bit(idx, sched->state.used)) |
713 | goto done; | |
714 | } | |
715 | } | |
cc1790cf | 716 | |
1e2ad28f RR |
717 | /* Grab the first unused counter starting with idx */ |
718 | idx = sched->state.counter; | |
15c7ad51 | 719 | for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) { |
cc1790cf PZ |
720 | if (!__test_and_set_bit(idx, sched->state.used)) { |
721 | if (sched->state.nr_gp++ >= sched->max_gp) | |
722 | return false; | |
723 | ||
4defea85 | 724 | goto done; |
cc1790cf | 725 | } |
1e2ad28f | 726 | } |
1e2ad28f | 727 | |
4defea85 PZ |
728 | return false; |
729 | ||
730 | done: | |
731 | sched->state.counter = idx; | |
1e2ad28f | 732 | |
bc1738f6 RR |
733 | if (c->overlap) |
734 | perf_sched_save_state(sched); | |
735 | ||
736 | return true; | |
737 | } | |
738 | ||
739 | static bool perf_sched_find_counter(struct perf_sched *sched) | |
740 | { | |
741 | while (!__perf_sched_find_counter(sched)) { | |
742 | if (!perf_sched_restore_state(sched)) | |
743 | return false; | |
744 | } | |
745 | ||
1e2ad28f RR |
746 | return true; |
747 | } | |
748 | ||
749 | /* | |
750 | * Go through all unassigned events and find the next one to schedule. | |
751 | * Take events with the least weight first. Return true on success. | |
752 | */ | |
753 | static bool perf_sched_next_event(struct perf_sched *sched) | |
754 | { | |
755 | struct event_constraint *c; | |
756 | ||
757 | if (!sched->state.unassigned || !--sched->state.unassigned) | |
758 | return false; | |
759 | ||
760 | do { | |
761 | /* next event */ | |
762 | sched->state.event++; | |
763 | if (sched->state.event >= sched->max_events) { | |
764 | /* next weight */ | |
765 | sched->state.event = 0; | |
766 | sched->state.weight++; | |
767 | if (sched->state.weight > sched->max_weight) | |
768 | return false; | |
769 | } | |
b371b594 | 770 | c = sched->constraints[sched->state.event]; |
1e2ad28f RR |
771 | } while (c->weight != sched->state.weight); |
772 | ||
773 | sched->state.counter = 0; /* start with first counter */ | |
774 | ||
775 | return true; | |
776 | } | |
777 | ||
778 | /* | |
779 | * Assign a counter for each event. | |
780 | */ | |
b371b594 | 781 | int perf_assign_events(struct event_constraint **constraints, int n, |
cc1790cf | 782 | int wmin, int wmax, int gpmax, int *assign) |
1e2ad28f RR |
783 | { |
784 | struct perf_sched sched; | |
785 | ||
cc1790cf | 786 | perf_sched_init(&sched, constraints, n, wmin, wmax, gpmax); |
1e2ad28f RR |
787 | |
788 | do { | |
789 | if (!perf_sched_find_counter(&sched)) | |
790 | break; /* failed */ | |
791 | if (assign) | |
792 | assign[sched.state.event] = sched.state.counter; | |
793 | } while (perf_sched_next_event(&sched)); | |
794 | ||
795 | return sched.state.unassigned; | |
796 | } | |
4a3dc121 | 797 | EXPORT_SYMBOL_GPL(perf_assign_events); |
1e2ad28f | 798 | |
de0428a7 | 799 | int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) |
1da53e02 | 800 | { |
43b45780 | 801 | struct event_constraint *c; |
1da53e02 | 802 | unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
2f7f73a5 | 803 | struct perf_event *e; |
e979121b | 804 | int i, wmin, wmax, unsched = 0; |
1da53e02 SE |
805 | struct hw_perf_event *hwc; |
806 | ||
807 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); | |
808 | ||
c5362c0c MD |
809 | if (x86_pmu.start_scheduling) |
810 | x86_pmu.start_scheduling(cpuc); | |
811 | ||
1e2ad28f | 812 | for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) { |
b371b594 | 813 | cpuc->event_constraint[i] = NULL; |
79cba822 | 814 | c = x86_pmu.get_event_constraints(cpuc, i, cpuc->event_list[i]); |
b371b594 | 815 | cpuc->event_constraint[i] = c; |
43b45780 | 816 | |
1e2ad28f RR |
817 | wmin = min(wmin, c->weight); |
818 | wmax = max(wmax, c->weight); | |
1da53e02 SE |
819 | } |
820 | ||
8113070d SE |
821 | /* |
822 | * fastpath, try to reuse previous register | |
823 | */ | |
c933c1a6 | 824 | for (i = 0; i < n; i++) { |
8113070d | 825 | hwc = &cpuc->event_list[i]->hw; |
b371b594 | 826 | c = cpuc->event_constraint[i]; |
8113070d SE |
827 | |
828 | /* never assigned */ | |
829 | if (hwc->idx == -1) | |
830 | break; | |
831 | ||
832 | /* constraint still honored */ | |
63b14649 | 833 | if (!test_bit(hwc->idx, c->idxmsk)) |
8113070d SE |
834 | break; |
835 | ||
836 | /* not already used */ | |
837 | if (test_bit(hwc->idx, used_mask)) | |
838 | break; | |
839 | ||
34538ee7 | 840 | __set_bit(hwc->idx, used_mask); |
8113070d SE |
841 | if (assign) |
842 | assign[i] = hwc->idx; | |
843 | } | |
8113070d | 844 | |
1e2ad28f | 845 | /* slow path */ |
b371b594 | 846 | if (i != n) { |
cc1790cf PZ |
847 | int gpmax = x86_pmu.num_counters; |
848 | ||
849 | /* | |
850 | * Do not allow scheduling of more than half the available | |
851 | * generic counters. | |
852 | * | |
853 | * This helps avoid counter starvation of sibling thread by | |
854 | * ensuring at most half the counters cannot be in exclusive | |
855 | * mode. There is no designated counters for the limits. Any | |
856 | * N/2 counters can be used. This helps with events with | |
857 | * specific counter constraints. | |
858 | */ | |
859 | if (is_ht_workaround_enabled() && !cpuc->is_fake && | |
860 | READ_ONCE(cpuc->excl_cntrs->exclusive_present)) | |
861 | gpmax /= 2; | |
862 | ||
b371b594 | 863 | unsched = perf_assign_events(cpuc->event_constraint, n, wmin, |
cc1790cf | 864 | wmax, gpmax, assign); |
b371b594 | 865 | } |
8113070d | 866 | |
2f7f73a5 | 867 | /* |
e979121b MD |
868 | * In case of success (unsched = 0), mark events as committed, |
869 | * so we do not put_constraint() in case new events are added | |
870 | * and fail to be scheduled | |
871 | * | |
872 | * We invoke the lower level commit callback to lock the resource | |
873 | * | |
874 | * We do not need to do all of this in case we are called to | |
875 | * validate an event group (assign == NULL) | |
2f7f73a5 | 876 | */ |
e979121b | 877 | if (!unsched && assign) { |
2f7f73a5 SE |
878 | for (i = 0; i < n; i++) { |
879 | e = cpuc->event_list[i]; | |
880 | e->hw.flags |= PERF_X86_EVENT_COMMITTED; | |
c5362c0c | 881 | if (x86_pmu.commit_scheduling) |
b371b594 | 882 | x86_pmu.commit_scheduling(cpuc, i, assign[i]); |
2f7f73a5 SE |
883 | } |
884 | } | |
e979121b MD |
885 | |
886 | if (!assign || unsched) { | |
1da53e02 | 887 | for (i = 0; i < n; i++) { |
2f7f73a5 SE |
888 | e = cpuc->event_list[i]; |
889 | /* | |
890 | * do not put_constraint() on comitted events, | |
891 | * because they are good to go | |
892 | */ | |
893 | if ((e->hw.flags & PERF_X86_EVENT_COMMITTED)) | |
894 | continue; | |
895 | ||
e979121b MD |
896 | /* |
897 | * release events that failed scheduling | |
898 | */ | |
1da53e02 | 899 | if (x86_pmu.put_event_constraints) |
2f7f73a5 | 900 | x86_pmu.put_event_constraints(cpuc, e); |
1da53e02 SE |
901 | } |
902 | } | |
c5362c0c MD |
903 | |
904 | if (x86_pmu.stop_scheduling) | |
905 | x86_pmu.stop_scheduling(cpuc); | |
906 | ||
e979121b | 907 | return unsched ? -EINVAL : 0; |
1da53e02 SE |
908 | } |
909 | ||
910 | /* | |
911 | * dogrp: true if must collect siblings events (group) | |
912 | * returns total number of events and error code | |
913 | */ | |
914 | static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp) | |
915 | { | |
916 | struct perf_event *event; | |
917 | int n, max_count; | |
918 | ||
948b1bb8 | 919 | max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed; |
1da53e02 SE |
920 | |
921 | /* current number of events already accepted */ | |
922 | n = cpuc->n_events; | |
923 | ||
924 | if (is_x86_event(leader)) { | |
925 | if (n >= max_count) | |
aa2bc1ad | 926 | return -EINVAL; |
1da53e02 SE |
927 | cpuc->event_list[n] = leader; |
928 | n++; | |
929 | } | |
930 | if (!dogrp) | |
931 | return n; | |
932 | ||
933 | list_for_each_entry(event, &leader->sibling_list, group_entry) { | |
934 | if (!is_x86_event(event) || | |
8113070d | 935 | event->state <= PERF_EVENT_STATE_OFF) |
1da53e02 SE |
936 | continue; |
937 | ||
938 | if (n >= max_count) | |
aa2bc1ad | 939 | return -EINVAL; |
1da53e02 SE |
940 | |
941 | cpuc->event_list[n] = event; | |
942 | n++; | |
943 | } | |
944 | return n; | |
945 | } | |
946 | ||
1da53e02 | 947 | static inline void x86_assign_hw_event(struct perf_event *event, |
447a194b | 948 | struct cpu_hw_events *cpuc, int i) |
1da53e02 | 949 | { |
447a194b SE |
950 | struct hw_perf_event *hwc = &event->hw; |
951 | ||
952 | hwc->idx = cpuc->assign[i]; | |
953 | hwc->last_cpu = smp_processor_id(); | |
954 | hwc->last_tag = ++cpuc->tags[i]; | |
1da53e02 | 955 | |
15c7ad51 | 956 | if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) { |
1da53e02 SE |
957 | hwc->config_base = 0; |
958 | hwc->event_base = 0; | |
15c7ad51 | 959 | } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) { |
1da53e02 | 960 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; |
15c7ad51 RR |
961 | hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED); |
962 | hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30; | |
1da53e02 | 963 | } else { |
73d6e522 RR |
964 | hwc->config_base = x86_pmu_config_addr(hwc->idx); |
965 | hwc->event_base = x86_pmu_event_addr(hwc->idx); | |
0fbdad07 | 966 | hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx); |
1da53e02 SE |
967 | } |
968 | } | |
969 | ||
447a194b SE |
970 | static inline int match_prev_assignment(struct hw_perf_event *hwc, |
971 | struct cpu_hw_events *cpuc, | |
972 | int i) | |
973 | { | |
974 | return hwc->idx == cpuc->assign[i] && | |
975 | hwc->last_cpu == smp_processor_id() && | |
976 | hwc->last_tag == cpuc->tags[i]; | |
977 | } | |
978 | ||
a4eaf7f1 | 979 | static void x86_pmu_start(struct perf_event *event, int flags); |
2e841873 | 980 | |
a4eaf7f1 | 981 | static void x86_pmu_enable(struct pmu *pmu) |
ee06094f | 982 | { |
89cbc767 | 983 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
1da53e02 SE |
984 | struct perf_event *event; |
985 | struct hw_perf_event *hwc; | |
11164cd4 | 986 | int i, added = cpuc->n_added; |
1da53e02 | 987 | |
85cf9dba | 988 | if (!x86_pmu_initialized()) |
2b9ff0db | 989 | return; |
1a6e21f7 PZ |
990 | |
991 | if (cpuc->enabled) | |
992 | return; | |
993 | ||
1da53e02 | 994 | if (cpuc->n_added) { |
19925ce7 | 995 | int n_running = cpuc->n_events - cpuc->n_added; |
1da53e02 SE |
996 | /* |
997 | * apply assignment obtained either from | |
998 | * hw_perf_group_sched_in() or x86_pmu_enable() | |
999 | * | |
1000 | * step1: save events moving to new counters | |
1da53e02 | 1001 | */ |
19925ce7 | 1002 | for (i = 0; i < n_running; i++) { |
1da53e02 SE |
1003 | event = cpuc->event_list[i]; |
1004 | hwc = &event->hw; | |
1005 | ||
447a194b SE |
1006 | /* |
1007 | * we can avoid reprogramming counter if: | |
1008 | * - assigned same counter as last time | |
1009 | * - running on same CPU as last time | |
1010 | * - no other event has used the counter since | |
1011 | */ | |
1012 | if (hwc->idx == -1 || | |
1013 | match_prev_assignment(hwc, cpuc, i)) | |
1da53e02 SE |
1014 | continue; |
1015 | ||
a4eaf7f1 PZ |
1016 | /* |
1017 | * Ensure we don't accidentally enable a stopped | |
1018 | * counter simply because we rescheduled. | |
1019 | */ | |
1020 | if (hwc->state & PERF_HES_STOPPED) | |
1021 | hwc->state |= PERF_HES_ARCH; | |
1022 | ||
1023 | x86_pmu_stop(event, PERF_EF_UPDATE); | |
1da53e02 SE |
1024 | } |
1025 | ||
c347a2f1 PZ |
1026 | /* |
1027 | * step2: reprogram moved events into new counters | |
1028 | */ | |
1da53e02 | 1029 | for (i = 0; i < cpuc->n_events; i++) { |
1da53e02 SE |
1030 | event = cpuc->event_list[i]; |
1031 | hwc = &event->hw; | |
1032 | ||
45e16a68 | 1033 | if (!match_prev_assignment(hwc, cpuc, i)) |
447a194b | 1034 | x86_assign_hw_event(event, cpuc, i); |
45e16a68 PZ |
1035 | else if (i < n_running) |
1036 | continue; | |
1da53e02 | 1037 | |
a4eaf7f1 PZ |
1038 | if (hwc->state & PERF_HES_ARCH) |
1039 | continue; | |
1040 | ||
1041 | x86_pmu_start(event, PERF_EF_RELOAD); | |
1da53e02 SE |
1042 | } |
1043 | cpuc->n_added = 0; | |
1044 | perf_events_lapic_init(); | |
1045 | } | |
1a6e21f7 PZ |
1046 | |
1047 | cpuc->enabled = 1; | |
1048 | barrier(); | |
1049 | ||
11164cd4 | 1050 | x86_pmu.enable_all(added); |
ee06094f | 1051 | } |
ee06094f | 1052 | |
245b2e70 | 1053 | static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); |
241771ef | 1054 | |
ee06094f IM |
1055 | /* |
1056 | * Set the next IRQ period, based on the hwc->period_left value. | |
cdd6c482 | 1057 | * To be called with the event disabled in hw: |
ee06094f | 1058 | */ |
de0428a7 | 1059 | int x86_perf_event_set_period(struct perf_event *event) |
241771ef | 1060 | { |
07088edb | 1061 | struct hw_perf_event *hwc = &event->hw; |
e7850595 | 1062 | s64 left = local64_read(&hwc->period_left); |
e4abb5d4 | 1063 | s64 period = hwc->sample_period; |
7645a24c | 1064 | int ret = 0, idx = hwc->idx; |
ee06094f | 1065 | |
15c7ad51 | 1066 | if (idx == INTEL_PMC_IDX_FIXED_BTS) |
30dd568c MM |
1067 | return 0; |
1068 | ||
ee06094f | 1069 | /* |
af901ca1 | 1070 | * If we are way outside a reasonable range then just skip forward: |
ee06094f IM |
1071 | */ |
1072 | if (unlikely(left <= -period)) { | |
1073 | left = period; | |
e7850595 | 1074 | local64_set(&hwc->period_left, left); |
9e350de3 | 1075 | hwc->last_period = period; |
e4abb5d4 | 1076 | ret = 1; |
ee06094f IM |
1077 | } |
1078 | ||
1079 | if (unlikely(left <= 0)) { | |
1080 | left += period; | |
e7850595 | 1081 | local64_set(&hwc->period_left, left); |
9e350de3 | 1082 | hwc->last_period = period; |
e4abb5d4 | 1083 | ret = 1; |
ee06094f | 1084 | } |
1c80f4b5 | 1085 | /* |
dfc65094 | 1086 | * Quirk: certain CPUs dont like it if just 1 hw_event is left: |
1c80f4b5 IM |
1087 | */ |
1088 | if (unlikely(left < 2)) | |
1089 | left = 2; | |
241771ef | 1090 | |
e4abb5d4 PZ |
1091 | if (left > x86_pmu.max_period) |
1092 | left = x86_pmu.max_period; | |
1093 | ||
294fe0f5 AK |
1094 | if (x86_pmu.limit_period) |
1095 | left = x86_pmu.limit_period(event, left); | |
1096 | ||
245b2e70 | 1097 | per_cpu(pmc_prev_left[idx], smp_processor_id()) = left; |
ee06094f IM |
1098 | |
1099 | /* | |
cdd6c482 | 1100 | * The hw event starts counting from this event offset, |
ee06094f IM |
1101 | * mark it to be able to extra future deltas: |
1102 | */ | |
e7850595 | 1103 | local64_set(&hwc->prev_count, (u64)-left); |
ee06094f | 1104 | |
73d6e522 | 1105 | wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac CG |
1106 | |
1107 | /* | |
1108 | * Due to erratum on certan cpu we need | |
1109 | * a second write to be sure the register | |
1110 | * is updated properly | |
1111 | */ | |
1112 | if (x86_pmu.perfctr_second_write) { | |
73d6e522 | 1113 | wrmsrl(hwc->event_base, |
948b1bb8 | 1114 | (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac | 1115 | } |
e4abb5d4 | 1116 | |
cdd6c482 | 1117 | perf_event_update_userpage(event); |
194002b2 | 1118 | |
e4abb5d4 | 1119 | return ret; |
2f18d1e8 IM |
1120 | } |
1121 | ||
de0428a7 | 1122 | void x86_pmu_enable_event(struct perf_event *event) |
7c90cc45 | 1123 | { |
0a3aee0d | 1124 | if (__this_cpu_read(cpu_hw_events.enabled)) |
31fa58af RR |
1125 | __x86_pmu_enable_event(&event->hw, |
1126 | ARCH_PERFMON_EVENTSEL_ENABLE); | |
241771ef IM |
1127 | } |
1128 | ||
b690081d | 1129 | /* |
a4eaf7f1 | 1130 | * Add a single event to the PMU. |
1da53e02 SE |
1131 | * |
1132 | * The event is added to the group of enabled events | |
1133 | * but only if it can be scehduled with existing events. | |
fe9081cc | 1134 | */ |
a4eaf7f1 | 1135 | static int x86_pmu_add(struct perf_event *event, int flags) |
fe9081cc | 1136 | { |
89cbc767 | 1137 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
1da53e02 SE |
1138 | struct hw_perf_event *hwc; |
1139 | int assign[X86_PMC_IDX_MAX]; | |
1140 | int n, n0, ret; | |
fe9081cc | 1141 | |
1da53e02 | 1142 | hwc = &event->hw; |
fe9081cc | 1143 | |
1da53e02 | 1144 | n0 = cpuc->n_events; |
24cd7f54 PZ |
1145 | ret = n = collect_events(cpuc, event, false); |
1146 | if (ret < 0) | |
1147 | goto out; | |
53b441a5 | 1148 | |
a4eaf7f1 PZ |
1149 | hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; |
1150 | if (!(flags & PERF_EF_START)) | |
1151 | hwc->state |= PERF_HES_ARCH; | |
1152 | ||
4d1c52b0 LM |
1153 | /* |
1154 | * If group events scheduling transaction was started, | |
0d2eb44f | 1155 | * skip the schedulability test here, it will be performed |
c347a2f1 | 1156 | * at commit time (->commit_txn) as a whole. |
4d1c52b0 | 1157 | */ |
8d2cacbb | 1158 | if (cpuc->group_flag & PERF_EVENT_TXN) |
24cd7f54 | 1159 | goto done_collect; |
4d1c52b0 | 1160 | |
a072738e | 1161 | ret = x86_pmu.schedule_events(cpuc, n, assign); |
1da53e02 | 1162 | if (ret) |
24cd7f54 | 1163 | goto out; |
1da53e02 SE |
1164 | /* |
1165 | * copy new assignment, now we know it is possible | |
1166 | * will be used by hw_perf_enable() | |
1167 | */ | |
1168 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
7e2ae347 | 1169 | |
24cd7f54 | 1170 | done_collect: |
c347a2f1 PZ |
1171 | /* |
1172 | * Commit the collect_events() state. See x86_pmu_del() and | |
1173 | * x86_pmu_*_txn(). | |
1174 | */ | |
1da53e02 | 1175 | cpuc->n_events = n; |
356e1f2e | 1176 | cpuc->n_added += n - n0; |
90151c35 | 1177 | cpuc->n_txn += n - n0; |
95cdd2e7 | 1178 | |
24cd7f54 PZ |
1179 | ret = 0; |
1180 | out: | |
24cd7f54 | 1181 | return ret; |
241771ef IM |
1182 | } |
1183 | ||
a4eaf7f1 | 1184 | static void x86_pmu_start(struct perf_event *event, int flags) |
d76a0812 | 1185 | { |
89cbc767 | 1186 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
c08053e6 PZ |
1187 | int idx = event->hw.idx; |
1188 | ||
a4eaf7f1 PZ |
1189 | if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) |
1190 | return; | |
1191 | ||
1192 | if (WARN_ON_ONCE(idx == -1)) | |
1193 | return; | |
1194 | ||
1195 | if (flags & PERF_EF_RELOAD) { | |
1196 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); | |
1197 | x86_perf_event_set_period(event); | |
1198 | } | |
1199 | ||
1200 | event->hw.state = 0; | |
d76a0812 | 1201 | |
c08053e6 PZ |
1202 | cpuc->events[idx] = event; |
1203 | __set_bit(idx, cpuc->active_mask); | |
63e6be6d | 1204 | __set_bit(idx, cpuc->running); |
aff3d91a | 1205 | x86_pmu.enable(event); |
c08053e6 | 1206 | perf_event_update_userpage(event); |
a78ac325 PZ |
1207 | } |
1208 | ||
cdd6c482 | 1209 | void perf_event_print_debug(void) |
241771ef | 1210 | { |
2f18d1e8 | 1211 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
da3e606d | 1212 | u64 pebs, debugctl; |
cdd6c482 | 1213 | struct cpu_hw_events *cpuc; |
5bb9efe3 | 1214 | unsigned long flags; |
1e125676 IM |
1215 | int cpu, idx; |
1216 | ||
948b1bb8 | 1217 | if (!x86_pmu.num_counters) |
1e125676 | 1218 | return; |
241771ef | 1219 | |
5bb9efe3 | 1220 | local_irq_save(flags); |
241771ef IM |
1221 | |
1222 | cpu = smp_processor_id(); | |
cdd6c482 | 1223 | cpuc = &per_cpu(cpu_hw_events, cpu); |
241771ef | 1224 | |
faa28ae0 | 1225 | if (x86_pmu.version >= 2) { |
a1ef58f4 JSR |
1226 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
1227 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
1228 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
1229 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); | |
1230 | ||
1231 | pr_info("\n"); | |
1232 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
1233 | pr_info("CPU#%d: status: %016llx\n", cpu, status); | |
1234 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); | |
1235 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); | |
15fde110 AK |
1236 | if (x86_pmu.pebs_constraints) { |
1237 | rdmsrl(MSR_IA32_PEBS_ENABLE, pebs); | |
1238 | pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs); | |
1239 | } | |
da3e606d AK |
1240 | if (x86_pmu.lbr_nr) { |
1241 | rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); | |
1242 | pr_info("CPU#%d: debugctl: %016llx\n", cpu, debugctl); | |
1243 | } | |
f87ad35d | 1244 | } |
7645a24c | 1245 | pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); |
241771ef | 1246 | |
948b1bb8 | 1247 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
41bf4989 RR |
1248 | rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl); |
1249 | rdmsrl(x86_pmu_event_addr(idx), pmc_count); | |
241771ef | 1250 | |
245b2e70 | 1251 | prev_left = per_cpu(pmc_prev_left[idx], cpu); |
241771ef | 1252 | |
a1ef58f4 | 1253 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 1254 | cpu, idx, pmc_ctrl); |
a1ef58f4 | 1255 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 1256 | cpu, idx, pmc_count); |
a1ef58f4 | 1257 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 1258 | cpu, idx, prev_left); |
241771ef | 1259 | } |
948b1bb8 | 1260 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { |
2f18d1e8 IM |
1261 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
1262 | ||
a1ef58f4 | 1263 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
2f18d1e8 IM |
1264 | cpu, idx, pmc_count); |
1265 | } | |
5bb9efe3 | 1266 | local_irq_restore(flags); |
241771ef IM |
1267 | } |
1268 | ||
de0428a7 | 1269 | void x86_pmu_stop(struct perf_event *event, int flags) |
241771ef | 1270 | { |
89cbc767 | 1271 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
cdd6c482 | 1272 | struct hw_perf_event *hwc = &event->hw; |
241771ef | 1273 | |
a4eaf7f1 PZ |
1274 | if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) { |
1275 | x86_pmu.disable(event); | |
1276 | cpuc->events[hwc->idx] = NULL; | |
1277 | WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); | |
1278 | hwc->state |= PERF_HES_STOPPED; | |
1279 | } | |
30dd568c | 1280 | |
a4eaf7f1 PZ |
1281 | if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { |
1282 | /* | |
1283 | * Drain the remaining delta count out of a event | |
1284 | * that we are disabling: | |
1285 | */ | |
1286 | x86_perf_event_update(event); | |
1287 | hwc->state |= PERF_HES_UPTODATE; | |
1288 | } | |
2e841873 PZ |
1289 | } |
1290 | ||
a4eaf7f1 | 1291 | static void x86_pmu_del(struct perf_event *event, int flags) |
2e841873 | 1292 | { |
89cbc767 | 1293 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
2e841873 PZ |
1294 | int i; |
1295 | ||
2f7f73a5 SE |
1296 | /* |
1297 | * event is descheduled | |
1298 | */ | |
1299 | event->hw.flags &= ~PERF_X86_EVENT_COMMITTED; | |
1300 | ||
90151c35 SE |
1301 | /* |
1302 | * If we're called during a txn, we don't need to do anything. | |
1303 | * The events never got scheduled and ->cancel_txn will truncate | |
1304 | * the event_list. | |
c347a2f1 PZ |
1305 | * |
1306 | * XXX assumes any ->del() called during a TXN will only be on | |
1307 | * an event added during that same TXN. | |
90151c35 | 1308 | */ |
8d2cacbb | 1309 | if (cpuc->group_flag & PERF_EVENT_TXN) |
90151c35 SE |
1310 | return; |
1311 | ||
c347a2f1 PZ |
1312 | /* |
1313 | * Not a TXN, therefore cleanup properly. | |
1314 | */ | |
a4eaf7f1 | 1315 | x86_pmu_stop(event, PERF_EF_UPDATE); |
194002b2 | 1316 | |
1da53e02 | 1317 | for (i = 0; i < cpuc->n_events; i++) { |
c347a2f1 PZ |
1318 | if (event == cpuc->event_list[i]) |
1319 | break; | |
1320 | } | |
1da53e02 | 1321 | |
c347a2f1 PZ |
1322 | if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */ |
1323 | return; | |
26e61e89 | 1324 | |
c347a2f1 PZ |
1325 | /* If we have a newly added event; make sure to decrease n_added. */ |
1326 | if (i >= cpuc->n_events - cpuc->n_added) | |
1327 | --cpuc->n_added; | |
1da53e02 | 1328 | |
c347a2f1 PZ |
1329 | if (x86_pmu.put_event_constraints) |
1330 | x86_pmu.put_event_constraints(cpuc, event); | |
1331 | ||
1332 | /* Delete the array entry. */ | |
b371b594 | 1333 | while (++i < cpuc->n_events) { |
c347a2f1 | 1334 | cpuc->event_list[i-1] = cpuc->event_list[i]; |
b371b594 PZ |
1335 | cpuc->event_constraint[i-1] = cpuc->event_constraint[i]; |
1336 | } | |
c347a2f1 | 1337 | --cpuc->n_events; |
1da53e02 | 1338 | |
cdd6c482 | 1339 | perf_event_update_userpage(event); |
241771ef IM |
1340 | } |
1341 | ||
de0428a7 | 1342 | int x86_pmu_handle_irq(struct pt_regs *regs) |
a29aa8a7 | 1343 | { |
df1a132b | 1344 | struct perf_sample_data data; |
cdd6c482 IM |
1345 | struct cpu_hw_events *cpuc; |
1346 | struct perf_event *event; | |
11d1578f | 1347 | int idx, handled = 0; |
9029a5e3 IM |
1348 | u64 val; |
1349 | ||
89cbc767 | 1350 | cpuc = this_cpu_ptr(&cpu_hw_events); |
962bf7a6 | 1351 | |
2bce5dac DZ |
1352 | /* |
1353 | * Some chipsets need to unmask the LVTPC in a particular spot | |
1354 | * inside the nmi handler. As a result, the unmasking was pushed | |
1355 | * into all the nmi handlers. | |
1356 | * | |
1357 | * This generic handler doesn't seem to have any issues where the | |
1358 | * unmasking occurs so it was left at the top. | |
1359 | */ | |
1360 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
1361 | ||
948b1bb8 | 1362 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
63e6be6d RR |
1363 | if (!test_bit(idx, cpuc->active_mask)) { |
1364 | /* | |
1365 | * Though we deactivated the counter some cpus | |
1366 | * might still deliver spurious interrupts still | |
1367 | * in flight. Catch them: | |
1368 | */ | |
1369 | if (__test_and_clear_bit(idx, cpuc->running)) | |
1370 | handled++; | |
a29aa8a7 | 1371 | continue; |
63e6be6d | 1372 | } |
962bf7a6 | 1373 | |
cdd6c482 | 1374 | event = cpuc->events[idx]; |
a4016a79 | 1375 | |
cc2ad4ba | 1376 | val = x86_perf_event_update(event); |
948b1bb8 | 1377 | if (val & (1ULL << (x86_pmu.cntval_bits - 1))) |
48e22d56 | 1378 | continue; |
962bf7a6 | 1379 | |
9e350de3 | 1380 | /* |
cdd6c482 | 1381 | * event overflow |
9e350de3 | 1382 | */ |
4177c42a | 1383 | handled++; |
fd0d000b | 1384 | perf_sample_data_init(&data, 0, event->hw.last_period); |
9e350de3 | 1385 | |
07088edb | 1386 | if (!x86_perf_event_set_period(event)) |
e4abb5d4 PZ |
1387 | continue; |
1388 | ||
a8b0ca17 | 1389 | if (perf_event_overflow(event, &data, regs)) |
a4eaf7f1 | 1390 | x86_pmu_stop(event, 0); |
a29aa8a7 | 1391 | } |
962bf7a6 | 1392 | |
9e350de3 PZ |
1393 | if (handled) |
1394 | inc_irq_stat(apic_perf_irqs); | |
1395 | ||
a29aa8a7 RR |
1396 | return handled; |
1397 | } | |
39d81eab | 1398 | |
cdd6c482 | 1399 | void perf_events_lapic_init(void) |
241771ef | 1400 | { |
04da8a43 | 1401 | if (!x86_pmu.apic || !x86_pmu_initialized()) |
241771ef | 1402 | return; |
85cf9dba | 1403 | |
241771ef | 1404 | /* |
c323d95f | 1405 | * Always use NMI for PMU |
241771ef | 1406 | */ |
c323d95f | 1407 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
241771ef IM |
1408 | } |
1409 | ||
9326638c | 1410 | static int |
9c48f1c6 | 1411 | perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs) |
241771ef | 1412 | { |
14c63f17 DH |
1413 | u64 start_clock; |
1414 | u64 finish_clock; | |
e8a923cc | 1415 | int ret; |
14c63f17 | 1416 | |
cdd6c482 | 1417 | if (!atomic_read(&active_events)) |
9c48f1c6 | 1418 | return NMI_DONE; |
4177c42a | 1419 | |
e8a923cc | 1420 | start_clock = sched_clock(); |
14c63f17 | 1421 | ret = x86_pmu.handle_irq(regs); |
e8a923cc | 1422 | finish_clock = sched_clock(); |
14c63f17 DH |
1423 | |
1424 | perf_sample_event_took(finish_clock - start_clock); | |
1425 | ||
1426 | return ret; | |
241771ef | 1427 | } |
9326638c | 1428 | NOKPROBE_SYMBOL(perf_event_nmi_handler); |
241771ef | 1429 | |
de0428a7 KW |
1430 | struct event_constraint emptyconstraint; |
1431 | struct event_constraint unconstrained; | |
f87ad35d | 1432 | |
148f9bb8 | 1433 | static int |
3f6da390 PZ |
1434 | x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) |
1435 | { | |
1436 | unsigned int cpu = (long)hcpu; | |
7fdba1ca | 1437 | struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); |
90413464 | 1438 | int i, ret = NOTIFY_OK; |
3f6da390 PZ |
1439 | |
1440 | switch (action & ~CPU_TASKS_FROZEN) { | |
1441 | case CPU_UP_PREPARE: | |
90413464 SE |
1442 | for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) |
1443 | cpuc->kfree_on_online[i] = NULL; | |
3f6da390 | 1444 | if (x86_pmu.cpu_prepare) |
b38b24ea | 1445 | ret = x86_pmu.cpu_prepare(cpu); |
3f6da390 PZ |
1446 | break; |
1447 | ||
1448 | case CPU_STARTING: | |
1449 | if (x86_pmu.cpu_starting) | |
1450 | x86_pmu.cpu_starting(cpu); | |
1451 | break; | |
1452 | ||
7fdba1ca | 1453 | case CPU_ONLINE: |
90413464 SE |
1454 | for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) { |
1455 | kfree(cpuc->kfree_on_online[i]); | |
1456 | cpuc->kfree_on_online[i] = NULL; | |
1457 | } | |
7fdba1ca PZ |
1458 | break; |
1459 | ||
3f6da390 PZ |
1460 | case CPU_DYING: |
1461 | if (x86_pmu.cpu_dying) | |
1462 | x86_pmu.cpu_dying(cpu); | |
1463 | break; | |
1464 | ||
b38b24ea | 1465 | case CPU_UP_CANCELED: |
3f6da390 PZ |
1466 | case CPU_DEAD: |
1467 | if (x86_pmu.cpu_dead) | |
1468 | x86_pmu.cpu_dead(cpu); | |
1469 | break; | |
1470 | ||
1471 | default: | |
1472 | break; | |
1473 | } | |
1474 | ||
b38b24ea | 1475 | return ret; |
3f6da390 PZ |
1476 | } |
1477 | ||
12558038 CG |
1478 | static void __init pmu_check_apic(void) |
1479 | { | |
1480 | if (cpu_has_apic) | |
1481 | return; | |
1482 | ||
1483 | x86_pmu.apic = 0; | |
1484 | pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n"); | |
1485 | pr_info("no hardware sampling interrupt available.\n"); | |
c184c980 VW |
1486 | |
1487 | /* | |
1488 | * If we have a PMU initialized but no APIC | |
1489 | * interrupts, we cannot sample hardware | |
1490 | * events (user-space has to fall back and | |
1491 | * sample via a hrtimer based software event): | |
1492 | */ | |
1493 | pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT; | |
1494 | ||
12558038 CG |
1495 | } |
1496 | ||
641cc938 JO |
1497 | static struct attribute_group x86_pmu_format_group = { |
1498 | .name = "format", | |
1499 | .attrs = NULL, | |
1500 | }; | |
1501 | ||
8300daa2 JO |
1502 | /* |
1503 | * Remove all undefined events (x86_pmu.event_map(id) == 0) | |
1504 | * out of events_attr attributes. | |
1505 | */ | |
1506 | static void __init filter_events(struct attribute **attrs) | |
1507 | { | |
3a54aaa0 SE |
1508 | struct device_attribute *d; |
1509 | struct perf_pmu_events_attr *pmu_attr; | |
8300daa2 JO |
1510 | int i, j; |
1511 | ||
1512 | for (i = 0; attrs[i]; i++) { | |
3a54aaa0 SE |
1513 | d = (struct device_attribute *)attrs[i]; |
1514 | pmu_attr = container_of(d, struct perf_pmu_events_attr, attr); | |
1515 | /* str trumps id */ | |
1516 | if (pmu_attr->event_str) | |
1517 | continue; | |
8300daa2 JO |
1518 | if (x86_pmu.event_map(i)) |
1519 | continue; | |
1520 | ||
1521 | for (j = i; attrs[j]; j++) | |
1522 | attrs[j] = attrs[j + 1]; | |
1523 | ||
1524 | /* Check the shifted attr. */ | |
1525 | i--; | |
1526 | } | |
1527 | } | |
1528 | ||
1a6461b1 AK |
1529 | /* Merge two pointer arrays */ |
1530 | static __init struct attribute **merge_attr(struct attribute **a, struct attribute **b) | |
1531 | { | |
1532 | struct attribute **new; | |
1533 | int j, i; | |
1534 | ||
1535 | for (j = 0; a[j]; j++) | |
1536 | ; | |
1537 | for (i = 0; b[i]; i++) | |
1538 | j++; | |
1539 | j++; | |
1540 | ||
1541 | new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL); | |
1542 | if (!new) | |
1543 | return NULL; | |
1544 | ||
1545 | j = 0; | |
1546 | for (i = 0; a[i]; i++) | |
1547 | new[j++] = a[i]; | |
1548 | for (i = 0; b[i]; i++) | |
1549 | new[j++] = b[i]; | |
1550 | new[j] = NULL; | |
1551 | ||
1552 | return new; | |
1553 | } | |
1554 | ||
f20093ee | 1555 | ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, |
a4747393 JO |
1556 | char *page) |
1557 | { | |
1558 | struct perf_pmu_events_attr *pmu_attr = \ | |
1559 | container_of(attr, struct perf_pmu_events_attr, attr); | |
a4747393 | 1560 | u64 config = x86_pmu.event_map(pmu_attr->id); |
a4747393 | 1561 | |
3a54aaa0 SE |
1562 | /* string trumps id */ |
1563 | if (pmu_attr->event_str) | |
1564 | return sprintf(page, "%s", pmu_attr->event_str); | |
a4747393 | 1565 | |
3a54aaa0 SE |
1566 | return x86_pmu.events_sysfs_show(page, config); |
1567 | } | |
a4747393 JO |
1568 | |
1569 | EVENT_ATTR(cpu-cycles, CPU_CYCLES ); | |
1570 | EVENT_ATTR(instructions, INSTRUCTIONS ); | |
1571 | EVENT_ATTR(cache-references, CACHE_REFERENCES ); | |
1572 | EVENT_ATTR(cache-misses, CACHE_MISSES ); | |
1573 | EVENT_ATTR(branch-instructions, BRANCH_INSTRUCTIONS ); | |
1574 | EVENT_ATTR(branch-misses, BRANCH_MISSES ); | |
1575 | EVENT_ATTR(bus-cycles, BUS_CYCLES ); | |
1576 | EVENT_ATTR(stalled-cycles-frontend, STALLED_CYCLES_FRONTEND ); | |
1577 | EVENT_ATTR(stalled-cycles-backend, STALLED_CYCLES_BACKEND ); | |
1578 | EVENT_ATTR(ref-cycles, REF_CPU_CYCLES ); | |
1579 | ||
1580 | static struct attribute *empty_attrs; | |
1581 | ||
95d18aa2 | 1582 | static struct attribute *events_attr[] = { |
a4747393 JO |
1583 | EVENT_PTR(CPU_CYCLES), |
1584 | EVENT_PTR(INSTRUCTIONS), | |
1585 | EVENT_PTR(CACHE_REFERENCES), | |
1586 | EVENT_PTR(CACHE_MISSES), | |
1587 | EVENT_PTR(BRANCH_INSTRUCTIONS), | |
1588 | EVENT_PTR(BRANCH_MISSES), | |
1589 | EVENT_PTR(BUS_CYCLES), | |
1590 | EVENT_PTR(STALLED_CYCLES_FRONTEND), | |
1591 | EVENT_PTR(STALLED_CYCLES_BACKEND), | |
1592 | EVENT_PTR(REF_CPU_CYCLES), | |
1593 | NULL, | |
1594 | }; | |
1595 | ||
1596 | static struct attribute_group x86_pmu_events_group = { | |
1597 | .name = "events", | |
1598 | .attrs = events_attr, | |
1599 | }; | |
1600 | ||
0bf79d44 | 1601 | ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event) |
43c032fe | 1602 | { |
43c032fe JO |
1603 | u64 umask = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8; |
1604 | u64 cmask = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24; | |
1605 | bool edge = (config & ARCH_PERFMON_EVENTSEL_EDGE); | |
1606 | bool pc = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL); | |
1607 | bool any = (config & ARCH_PERFMON_EVENTSEL_ANY); | |
1608 | bool inv = (config & ARCH_PERFMON_EVENTSEL_INV); | |
1609 | ssize_t ret; | |
1610 | ||
1611 | /* | |
1612 | * We have whole page size to spend and just little data | |
1613 | * to write, so we can safely use sprintf. | |
1614 | */ | |
1615 | ret = sprintf(page, "event=0x%02llx", event); | |
1616 | ||
1617 | if (umask) | |
1618 | ret += sprintf(page + ret, ",umask=0x%02llx", umask); | |
1619 | ||
1620 | if (edge) | |
1621 | ret += sprintf(page + ret, ",edge"); | |
1622 | ||
1623 | if (pc) | |
1624 | ret += sprintf(page + ret, ",pc"); | |
1625 | ||
1626 | if (any) | |
1627 | ret += sprintf(page + ret, ",any"); | |
1628 | ||
1629 | if (inv) | |
1630 | ret += sprintf(page + ret, ",inv"); | |
1631 | ||
1632 | if (cmask) | |
1633 | ret += sprintf(page + ret, ",cmask=0x%02llx", cmask); | |
1634 | ||
1635 | ret += sprintf(page + ret, "\n"); | |
1636 | ||
1637 | return ret; | |
1638 | } | |
1639 | ||
dda99116 | 1640 | static int __init init_hw_perf_events(void) |
b56a3802 | 1641 | { |
c1d6f42f | 1642 | struct x86_pmu_quirk *quirk; |
72eae04d RR |
1643 | int err; |
1644 | ||
cdd6c482 | 1645 | pr_info("Performance Events: "); |
1123e3ad | 1646 | |
b56a3802 JSR |
1647 | switch (boot_cpu_data.x86_vendor) { |
1648 | case X86_VENDOR_INTEL: | |
72eae04d | 1649 | err = intel_pmu_init(); |
b56a3802 | 1650 | break; |
f87ad35d | 1651 | case X86_VENDOR_AMD: |
72eae04d | 1652 | err = amd_pmu_init(); |
f87ad35d | 1653 | break; |
4138960a | 1654 | default: |
8a3da6c7 | 1655 | err = -ENOTSUPP; |
b56a3802 | 1656 | } |
1123e3ad | 1657 | if (err != 0) { |
cdd6c482 | 1658 | pr_cont("no PMU driver, software events only.\n"); |
004417a6 | 1659 | return 0; |
1123e3ad | 1660 | } |
b56a3802 | 1661 | |
12558038 CG |
1662 | pmu_check_apic(); |
1663 | ||
33c6d6a7 | 1664 | /* sanity check that the hardware exists or is emulated */ |
4407204c | 1665 | if (!check_hw_exists()) |
004417a6 | 1666 | return 0; |
33c6d6a7 | 1667 | |
1123e3ad | 1668 | pr_cont("%s PMU driver.\n", x86_pmu.name); |
faa28ae0 | 1669 | |
e97df763 PZ |
1670 | x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */ |
1671 | ||
c1d6f42f PZ |
1672 | for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next) |
1673 | quirk->func(); | |
3c44780b | 1674 | |
a1eac7ac RR |
1675 | if (!x86_pmu.intel_ctrl) |
1676 | x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1; | |
241771ef | 1677 | |
cdd6c482 | 1678 | perf_events_lapic_init(); |
9c48f1c6 | 1679 | register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI"); |
1123e3ad | 1680 | |
63b14649 | 1681 | unconstrained = (struct event_constraint) |
948b1bb8 | 1682 | __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1, |
9fac2cf3 | 1683 | 0, x86_pmu.num_counters, 0, 0); |
63b14649 | 1684 | |
641cc938 | 1685 | x86_pmu_format_group.attrs = x86_pmu.format_attrs; |
0c9d42ed | 1686 | |
f20093ee SE |
1687 | if (x86_pmu.event_attrs) |
1688 | x86_pmu_events_group.attrs = x86_pmu.event_attrs; | |
1689 | ||
a4747393 JO |
1690 | if (!x86_pmu.events_sysfs_show) |
1691 | x86_pmu_events_group.attrs = &empty_attrs; | |
8300daa2 JO |
1692 | else |
1693 | filter_events(x86_pmu_events_group.attrs); | |
a4747393 | 1694 | |
1a6461b1 AK |
1695 | if (x86_pmu.cpu_events) { |
1696 | struct attribute **tmp; | |
1697 | ||
1698 | tmp = merge_attr(x86_pmu_events_group.attrs, x86_pmu.cpu_events); | |
1699 | if (!WARN_ON(!tmp)) | |
1700 | x86_pmu_events_group.attrs = tmp; | |
1701 | } | |
1702 | ||
57c0c15b | 1703 | pr_info("... version: %d\n", x86_pmu.version); |
948b1bb8 RR |
1704 | pr_info("... bit width: %d\n", x86_pmu.cntval_bits); |
1705 | pr_info("... generic registers: %d\n", x86_pmu.num_counters); | |
1706 | pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask); | |
57c0c15b | 1707 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); |
948b1bb8 | 1708 | pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed); |
d6dc0b4e | 1709 | pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl); |
3f6da390 | 1710 | |
2e80a82a | 1711 | perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); |
3f6da390 | 1712 | perf_cpu_notifier(x86_pmu_notifier); |
004417a6 PZ |
1713 | |
1714 | return 0; | |
241771ef | 1715 | } |
004417a6 | 1716 | early_initcall(init_hw_perf_events); |
621a01ea | 1717 | |
cdd6c482 | 1718 | static inline void x86_pmu_read(struct perf_event *event) |
ee06094f | 1719 | { |
cc2ad4ba | 1720 | x86_perf_event_update(event); |
ee06094f IM |
1721 | } |
1722 | ||
4d1c52b0 LM |
1723 | /* |
1724 | * Start group events scheduling transaction | |
1725 | * Set the flag to make pmu::enable() not perform the | |
1726 | * schedulability test, it will be performed at commit time | |
1727 | */ | |
51b0fe39 | 1728 | static void x86_pmu_start_txn(struct pmu *pmu) |
4d1c52b0 | 1729 | { |
33696fc0 | 1730 | perf_pmu_disable(pmu); |
0a3aee0d TH |
1731 | __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN); |
1732 | __this_cpu_write(cpu_hw_events.n_txn, 0); | |
4d1c52b0 LM |
1733 | } |
1734 | ||
1735 | /* | |
1736 | * Stop group events scheduling transaction | |
1737 | * Clear the flag and pmu::enable() will perform the | |
1738 | * schedulability test. | |
1739 | */ | |
51b0fe39 | 1740 | static void x86_pmu_cancel_txn(struct pmu *pmu) |
4d1c52b0 | 1741 | { |
0a3aee0d | 1742 | __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN); |
90151c35 | 1743 | /* |
c347a2f1 PZ |
1744 | * Truncate collected array by the number of events added in this |
1745 | * transaction. See x86_pmu_add() and x86_pmu_*_txn(). | |
90151c35 | 1746 | */ |
0a3aee0d TH |
1747 | __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn)); |
1748 | __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn)); | |
33696fc0 | 1749 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1750 | } |
1751 | ||
1752 | /* | |
1753 | * Commit group events scheduling transaction | |
1754 | * Perform the group schedulability test as a whole | |
1755 | * Return 0 if success | |
c347a2f1 PZ |
1756 | * |
1757 | * Does not cancel the transaction on failure; expects the caller to do this. | |
4d1c52b0 | 1758 | */ |
51b0fe39 | 1759 | static int x86_pmu_commit_txn(struct pmu *pmu) |
4d1c52b0 | 1760 | { |
89cbc767 | 1761 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
4d1c52b0 LM |
1762 | int assign[X86_PMC_IDX_MAX]; |
1763 | int n, ret; | |
1764 | ||
1765 | n = cpuc->n_events; | |
1766 | ||
1767 | if (!x86_pmu_initialized()) | |
1768 | return -EAGAIN; | |
1769 | ||
1770 | ret = x86_pmu.schedule_events(cpuc, n, assign); | |
1771 | if (ret) | |
1772 | return ret; | |
1773 | ||
1774 | /* | |
1775 | * copy new assignment, now we know it is possible | |
1776 | * will be used by hw_perf_enable() | |
1777 | */ | |
1778 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
1779 | ||
8d2cacbb | 1780 | cpuc->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 1781 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1782 | return 0; |
1783 | } | |
cd8a38d3 SE |
1784 | /* |
1785 | * a fake_cpuc is used to validate event groups. Due to | |
1786 | * the extra reg logic, we need to also allocate a fake | |
1787 | * per_core and per_cpu structure. Otherwise, group events | |
1788 | * using extra reg may conflict without the kernel being | |
1789 | * able to catch this when the last event gets added to | |
1790 | * the group. | |
1791 | */ | |
1792 | static void free_fake_cpuc(struct cpu_hw_events *cpuc) | |
1793 | { | |
1794 | kfree(cpuc->shared_regs); | |
1795 | kfree(cpuc); | |
1796 | } | |
1797 | ||
1798 | static struct cpu_hw_events *allocate_fake_cpuc(void) | |
1799 | { | |
1800 | struct cpu_hw_events *cpuc; | |
1801 | int cpu = raw_smp_processor_id(); | |
1802 | ||
1803 | cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL); | |
1804 | if (!cpuc) | |
1805 | return ERR_PTR(-ENOMEM); | |
1806 | ||
1807 | /* only needed, if we have extra_regs */ | |
1808 | if (x86_pmu.extra_regs) { | |
1809 | cpuc->shared_regs = allocate_shared_regs(cpu); | |
1810 | if (!cpuc->shared_regs) | |
1811 | goto error; | |
1812 | } | |
b430f7c4 | 1813 | cpuc->is_fake = 1; |
cd8a38d3 SE |
1814 | return cpuc; |
1815 | error: | |
1816 | free_fake_cpuc(cpuc); | |
1817 | return ERR_PTR(-ENOMEM); | |
1818 | } | |
4d1c52b0 | 1819 | |
ca037701 PZ |
1820 | /* |
1821 | * validate that we can schedule this event | |
1822 | */ | |
1823 | static int validate_event(struct perf_event *event) | |
1824 | { | |
1825 | struct cpu_hw_events *fake_cpuc; | |
1826 | struct event_constraint *c; | |
1827 | int ret = 0; | |
1828 | ||
cd8a38d3 SE |
1829 | fake_cpuc = allocate_fake_cpuc(); |
1830 | if (IS_ERR(fake_cpuc)) | |
1831 | return PTR_ERR(fake_cpuc); | |
ca037701 | 1832 | |
79cba822 | 1833 | c = x86_pmu.get_event_constraints(fake_cpuc, -1, event); |
ca037701 PZ |
1834 | |
1835 | if (!c || !c->weight) | |
aa2bc1ad | 1836 | ret = -EINVAL; |
ca037701 PZ |
1837 | |
1838 | if (x86_pmu.put_event_constraints) | |
1839 | x86_pmu.put_event_constraints(fake_cpuc, event); | |
1840 | ||
cd8a38d3 | 1841 | free_fake_cpuc(fake_cpuc); |
ca037701 PZ |
1842 | |
1843 | return ret; | |
1844 | } | |
1845 | ||
1da53e02 SE |
1846 | /* |
1847 | * validate a single event group | |
1848 | * | |
1849 | * validation include: | |
184f412c IM |
1850 | * - check events are compatible which each other |
1851 | * - events do not compete for the same counter | |
1852 | * - number of events <= number of counters | |
1da53e02 SE |
1853 | * |
1854 | * validation ensures the group can be loaded onto the | |
1855 | * PMU if it was the only group available. | |
1856 | */ | |
fe9081cc PZ |
1857 | static int validate_group(struct perf_event *event) |
1858 | { | |
1da53e02 | 1859 | struct perf_event *leader = event->group_leader; |
502568d5 | 1860 | struct cpu_hw_events *fake_cpuc; |
aa2bc1ad | 1861 | int ret = -EINVAL, n; |
fe9081cc | 1862 | |
cd8a38d3 SE |
1863 | fake_cpuc = allocate_fake_cpuc(); |
1864 | if (IS_ERR(fake_cpuc)) | |
1865 | return PTR_ERR(fake_cpuc); | |
1da53e02 SE |
1866 | /* |
1867 | * the event is not yet connected with its | |
1868 | * siblings therefore we must first collect | |
1869 | * existing siblings, then add the new event | |
1870 | * before we can simulate the scheduling | |
1871 | */ | |
502568d5 | 1872 | n = collect_events(fake_cpuc, leader, true); |
1da53e02 | 1873 | if (n < 0) |
cd8a38d3 | 1874 | goto out; |
fe9081cc | 1875 | |
502568d5 PZ |
1876 | fake_cpuc->n_events = n; |
1877 | n = collect_events(fake_cpuc, event, false); | |
1da53e02 | 1878 | if (n < 0) |
cd8a38d3 | 1879 | goto out; |
fe9081cc | 1880 | |
502568d5 | 1881 | fake_cpuc->n_events = n; |
1da53e02 | 1882 | |
a072738e | 1883 | ret = x86_pmu.schedule_events(fake_cpuc, n, NULL); |
502568d5 | 1884 | |
502568d5 | 1885 | out: |
cd8a38d3 | 1886 | free_fake_cpuc(fake_cpuc); |
502568d5 | 1887 | return ret; |
fe9081cc PZ |
1888 | } |
1889 | ||
dda99116 | 1890 | static int x86_pmu_event_init(struct perf_event *event) |
621a01ea | 1891 | { |
51b0fe39 | 1892 | struct pmu *tmp; |
621a01ea IM |
1893 | int err; |
1894 | ||
b0a873eb PZ |
1895 | switch (event->attr.type) { |
1896 | case PERF_TYPE_RAW: | |
1897 | case PERF_TYPE_HARDWARE: | |
1898 | case PERF_TYPE_HW_CACHE: | |
1899 | break; | |
1900 | ||
1901 | default: | |
1902 | return -ENOENT; | |
1903 | } | |
1904 | ||
1905 | err = __x86_pmu_event_init(event); | |
fe9081cc | 1906 | if (!err) { |
8113070d SE |
1907 | /* |
1908 | * we temporarily connect event to its pmu | |
1909 | * such that validate_group() can classify | |
1910 | * it as an x86 event using is_x86_event() | |
1911 | */ | |
1912 | tmp = event->pmu; | |
1913 | event->pmu = &pmu; | |
1914 | ||
fe9081cc PZ |
1915 | if (event->group_leader != event) |
1916 | err = validate_group(event); | |
ca037701 PZ |
1917 | else |
1918 | err = validate_event(event); | |
8113070d SE |
1919 | |
1920 | event->pmu = tmp; | |
fe9081cc | 1921 | } |
a1792cda | 1922 | if (err) { |
cdd6c482 IM |
1923 | if (event->destroy) |
1924 | event->destroy(event); | |
a1792cda | 1925 | } |
621a01ea | 1926 | |
7911d3f7 AL |
1927 | if (ACCESS_ONCE(x86_pmu.attr_rdpmc)) |
1928 | event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED; | |
1929 | ||
b0a873eb | 1930 | return err; |
621a01ea | 1931 | } |
d7d59fb3 | 1932 | |
7911d3f7 AL |
1933 | static void refresh_pce(void *ignored) |
1934 | { | |
1935 | if (current->mm) | |
1936 | load_mm_cr4(current->mm); | |
1937 | } | |
1938 | ||
1939 | static void x86_pmu_event_mapped(struct perf_event *event) | |
1940 | { | |
1941 | if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED)) | |
1942 | return; | |
1943 | ||
1944 | if (atomic_inc_return(¤t->mm->context.perf_rdpmc_allowed) == 1) | |
1945 | on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1); | |
1946 | } | |
1947 | ||
1948 | static void x86_pmu_event_unmapped(struct perf_event *event) | |
1949 | { | |
1950 | if (!current->mm) | |
1951 | return; | |
1952 | ||
1953 | if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED)) | |
1954 | return; | |
1955 | ||
1956 | if (atomic_dec_and_test(¤t->mm->context.perf_rdpmc_allowed)) | |
1957 | on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1); | |
1958 | } | |
1959 | ||
fe4a3308 PZ |
1960 | static int x86_pmu_event_idx(struct perf_event *event) |
1961 | { | |
1962 | int idx = event->hw.idx; | |
1963 | ||
7911d3f7 | 1964 | if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED)) |
c7206205 PZ |
1965 | return 0; |
1966 | ||
15c7ad51 RR |
1967 | if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) { |
1968 | idx -= INTEL_PMC_IDX_FIXED; | |
fe4a3308 PZ |
1969 | idx |= 1 << 30; |
1970 | } | |
1971 | ||
1972 | return idx + 1; | |
1973 | } | |
1974 | ||
0c9d42ed PZ |
1975 | static ssize_t get_attr_rdpmc(struct device *cdev, |
1976 | struct device_attribute *attr, | |
1977 | char *buf) | |
1978 | { | |
1979 | return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc); | |
1980 | } | |
1981 | ||
0c9d42ed PZ |
1982 | static ssize_t set_attr_rdpmc(struct device *cdev, |
1983 | struct device_attribute *attr, | |
1984 | const char *buf, size_t count) | |
1985 | { | |
e2b297fc SK |
1986 | unsigned long val; |
1987 | ssize_t ret; | |
1988 | ||
1989 | ret = kstrtoul(buf, 0, &val); | |
1990 | if (ret) | |
1991 | return ret; | |
e97df763 | 1992 | |
a6673429 AL |
1993 | if (val > 2) |
1994 | return -EINVAL; | |
1995 | ||
e97df763 PZ |
1996 | if (x86_pmu.attr_rdpmc_broken) |
1997 | return -ENOTSUPP; | |
0c9d42ed | 1998 | |
a6673429 AL |
1999 | if ((val == 2) != (x86_pmu.attr_rdpmc == 2)) { |
2000 | /* | |
2001 | * Changing into or out of always available, aka | |
2002 | * perf-event-bypassing mode. This path is extremely slow, | |
2003 | * but only root can trigger it, so it's okay. | |
2004 | */ | |
2005 | if (val == 2) | |
2006 | static_key_slow_inc(&rdpmc_always_available); | |
2007 | else | |
2008 | static_key_slow_dec(&rdpmc_always_available); | |
2009 | on_each_cpu(refresh_pce, NULL, 1); | |
2010 | } | |
2011 | ||
2012 | x86_pmu.attr_rdpmc = val; | |
2013 | ||
0c9d42ed PZ |
2014 | return count; |
2015 | } | |
2016 | ||
2017 | static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc); | |
2018 | ||
2019 | static struct attribute *x86_pmu_attrs[] = { | |
2020 | &dev_attr_rdpmc.attr, | |
2021 | NULL, | |
2022 | }; | |
2023 | ||
2024 | static struct attribute_group x86_pmu_attr_group = { | |
2025 | .attrs = x86_pmu_attrs, | |
2026 | }; | |
2027 | ||
2028 | static const struct attribute_group *x86_pmu_attr_groups[] = { | |
2029 | &x86_pmu_attr_group, | |
641cc938 | 2030 | &x86_pmu_format_group, |
a4747393 | 2031 | &x86_pmu_events_group, |
0c9d42ed PZ |
2032 | NULL, |
2033 | }; | |
2034 | ||
ba532500 | 2035 | static void x86_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) |
d010b332 | 2036 | { |
ba532500 YZ |
2037 | if (x86_pmu.sched_task) |
2038 | x86_pmu.sched_task(ctx, sched_in); | |
d010b332 SE |
2039 | } |
2040 | ||
c93dc84c PZ |
2041 | void perf_check_microcode(void) |
2042 | { | |
2043 | if (x86_pmu.check_microcode) | |
2044 | x86_pmu.check_microcode(); | |
2045 | } | |
2046 | EXPORT_SYMBOL_GPL(perf_check_microcode); | |
2047 | ||
b0a873eb | 2048 | static struct pmu pmu = { |
d010b332 SE |
2049 | .pmu_enable = x86_pmu_enable, |
2050 | .pmu_disable = x86_pmu_disable, | |
a4eaf7f1 | 2051 | |
c93dc84c | 2052 | .attr_groups = x86_pmu_attr_groups, |
0c9d42ed | 2053 | |
c93dc84c | 2054 | .event_init = x86_pmu_event_init, |
a4eaf7f1 | 2055 | |
7911d3f7 AL |
2056 | .event_mapped = x86_pmu_event_mapped, |
2057 | .event_unmapped = x86_pmu_event_unmapped, | |
2058 | ||
d010b332 SE |
2059 | .add = x86_pmu_add, |
2060 | .del = x86_pmu_del, | |
2061 | .start = x86_pmu_start, | |
2062 | .stop = x86_pmu_stop, | |
2063 | .read = x86_pmu_read, | |
a4eaf7f1 | 2064 | |
c93dc84c PZ |
2065 | .start_txn = x86_pmu_start_txn, |
2066 | .cancel_txn = x86_pmu_cancel_txn, | |
2067 | .commit_txn = x86_pmu_commit_txn, | |
fe4a3308 | 2068 | |
c93dc84c | 2069 | .event_idx = x86_pmu_event_idx, |
ba532500 | 2070 | .sched_task = x86_pmu_sched_task, |
e18bf526 | 2071 | .task_ctx_size = sizeof(struct x86_perf_task_context), |
b0a873eb PZ |
2072 | }; |
2073 | ||
c1317ec2 AL |
2074 | void arch_perf_update_userpage(struct perf_event *event, |
2075 | struct perf_event_mmap_page *userpg, u64 now) | |
e3f3541c | 2076 | { |
20d1c86a PZ |
2077 | struct cyc2ns_data *data; |
2078 | ||
fa731587 PZ |
2079 | userpg->cap_user_time = 0; |
2080 | userpg->cap_user_time_zero = 0; | |
7911d3f7 AL |
2081 | userpg->cap_user_rdpmc = |
2082 | !!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED); | |
c7206205 PZ |
2083 | userpg->pmc_width = x86_pmu.cntval_bits; |
2084 | ||
35af99e6 | 2085 | if (!sched_clock_stable()) |
e3f3541c PZ |
2086 | return; |
2087 | ||
20d1c86a PZ |
2088 | data = cyc2ns_read_begin(); |
2089 | ||
34f43927 PZ |
2090 | /* |
2091 | * Internal timekeeping for enabled/running/stopped times | |
2092 | * is always in the local_clock domain. | |
2093 | */ | |
fa731587 | 2094 | userpg->cap_user_time = 1; |
20d1c86a PZ |
2095 | userpg->time_mult = data->cyc2ns_mul; |
2096 | userpg->time_shift = data->cyc2ns_shift; | |
2097 | userpg->time_offset = data->cyc2ns_offset - now; | |
c73deb6a | 2098 | |
34f43927 PZ |
2099 | /* |
2100 | * cap_user_time_zero doesn't make sense when we're using a different | |
2101 | * time base for the records. | |
2102 | */ | |
2103 | if (event->clock == &local_clock) { | |
2104 | userpg->cap_user_time_zero = 1; | |
2105 | userpg->time_zero = data->cyc2ns_offset; | |
2106 | } | |
20d1c86a PZ |
2107 | |
2108 | cyc2ns_read_end(data); | |
e3f3541c PZ |
2109 | } |
2110 | ||
d7d59fb3 PZ |
2111 | /* |
2112 | * callchain support | |
2113 | */ | |
2114 | ||
d7d59fb3 PZ |
2115 | static int backtrace_stack(void *data, char *name) |
2116 | { | |
038e836e | 2117 | return 0; |
d7d59fb3 PZ |
2118 | } |
2119 | ||
2120 | static void backtrace_address(void *data, unsigned long addr, int reliable) | |
2121 | { | |
2122 | struct perf_callchain_entry *entry = data; | |
2123 | ||
70791ce9 | 2124 | perf_callchain_store(entry, addr); |
d7d59fb3 PZ |
2125 | } |
2126 | ||
2127 | static const struct stacktrace_ops backtrace_ops = { | |
d7d59fb3 PZ |
2128 | .stack = backtrace_stack, |
2129 | .address = backtrace_address, | |
06d65bda | 2130 | .walk_stack = print_context_stack_bp, |
d7d59fb3 PZ |
2131 | }; |
2132 | ||
56962b44 FW |
2133 | void |
2134 | perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 | 2135 | { |
927c7a9e FW |
2136 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
2137 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 2138 | return; |
927c7a9e FW |
2139 | } |
2140 | ||
70791ce9 | 2141 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 2142 | |
e8e999cf | 2143 | dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry); |
d7d59fb3 PZ |
2144 | } |
2145 | ||
bc6ca7b3 AS |
2146 | static inline int |
2147 | valid_user_frame(const void __user *fp, unsigned long size) | |
2148 | { | |
2149 | return (__range_not_ok(fp, size, TASK_SIZE) == 0); | |
2150 | } | |
2151 | ||
d07bdfd3 PZ |
2152 | static unsigned long get_segment_base(unsigned int segment) |
2153 | { | |
2154 | struct desc_struct *desc; | |
2155 | int idx = segment >> 3; | |
2156 | ||
2157 | if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) { | |
2158 | if (idx > LDT_ENTRIES) | |
2159 | return 0; | |
2160 | ||
2161 | if (idx > current->active_mm->context.size) | |
2162 | return 0; | |
2163 | ||
2164 | desc = current->active_mm->context.ldt; | |
2165 | } else { | |
2166 | if (idx > GDT_ENTRIES) | |
2167 | return 0; | |
2168 | ||
89cbc767 | 2169 | desc = raw_cpu_ptr(gdt_page.gdt); |
d07bdfd3 PZ |
2170 | } |
2171 | ||
2172 | return get_desc_base(desc + idx); | |
2173 | } | |
2174 | ||
257ef9d2 | 2175 | #ifdef CONFIG_COMPAT |
d1a797f3 PA |
2176 | |
2177 | #include <asm/compat.h> | |
2178 | ||
257ef9d2 TE |
2179 | static inline int |
2180 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
74193ef0 | 2181 | { |
257ef9d2 | 2182 | /* 32-bit process in 64-bit kernel. */ |
d07bdfd3 | 2183 | unsigned long ss_base, cs_base; |
257ef9d2 TE |
2184 | struct stack_frame_ia32 frame; |
2185 | const void __user *fp; | |
74193ef0 | 2186 | |
257ef9d2 TE |
2187 | if (!test_thread_flag(TIF_IA32)) |
2188 | return 0; | |
2189 | ||
d07bdfd3 PZ |
2190 | cs_base = get_segment_base(regs->cs); |
2191 | ss_base = get_segment_base(regs->ss); | |
2192 | ||
2193 | fp = compat_ptr(ss_base + regs->bp); | |
257ef9d2 TE |
2194 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
2195 | unsigned long bytes; | |
2196 | frame.next_frame = 0; | |
2197 | frame.return_address = 0; | |
2198 | ||
2199 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); | |
0a196848 | 2200 | if (bytes != 0) |
257ef9d2 | 2201 | break; |
74193ef0 | 2202 | |
bc6ca7b3 AS |
2203 | if (!valid_user_frame(fp, sizeof(frame))) |
2204 | break; | |
2205 | ||
d07bdfd3 PZ |
2206 | perf_callchain_store(entry, cs_base + frame.return_address); |
2207 | fp = compat_ptr(ss_base + frame.next_frame); | |
257ef9d2 TE |
2208 | } |
2209 | return 1; | |
d7d59fb3 | 2210 | } |
257ef9d2 TE |
2211 | #else |
2212 | static inline int | |
2213 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
2214 | { | |
2215 | return 0; | |
2216 | } | |
2217 | #endif | |
d7d59fb3 | 2218 | |
56962b44 FW |
2219 | void |
2220 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 PZ |
2221 | { |
2222 | struct stack_frame frame; | |
2223 | const void __user *fp; | |
2224 | ||
927c7a9e FW |
2225 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
2226 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 2227 | return; |
927c7a9e | 2228 | } |
5a6cec3a | 2229 | |
d07bdfd3 PZ |
2230 | /* |
2231 | * We don't know what to do with VM86 stacks.. ignore them for now. | |
2232 | */ | |
2233 | if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM)) | |
2234 | return; | |
2235 | ||
74193ef0 | 2236 | fp = (void __user *)regs->bp; |
d7d59fb3 | 2237 | |
70791ce9 | 2238 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 2239 | |
20afc60f AV |
2240 | if (!current->mm) |
2241 | return; | |
2242 | ||
257ef9d2 TE |
2243 | if (perf_callchain_user32(regs, entry)) |
2244 | return; | |
2245 | ||
f9188e02 | 2246 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
257ef9d2 | 2247 | unsigned long bytes; |
038e836e | 2248 | frame.next_frame = NULL; |
d7d59fb3 PZ |
2249 | frame.return_address = 0; |
2250 | ||
257ef9d2 | 2251 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); |
0a196848 | 2252 | if (bytes != 0) |
d7d59fb3 PZ |
2253 | break; |
2254 | ||
bc6ca7b3 AS |
2255 | if (!valid_user_frame(fp, sizeof(frame))) |
2256 | break; | |
2257 | ||
70791ce9 | 2258 | perf_callchain_store(entry, frame.return_address); |
038e836e | 2259 | fp = frame.next_frame; |
d7d59fb3 PZ |
2260 | } |
2261 | } | |
2262 | ||
d07bdfd3 PZ |
2263 | /* |
2264 | * Deal with code segment offsets for the various execution modes: | |
2265 | * | |
2266 | * VM86 - the good olde 16 bit days, where the linear address is | |
2267 | * 20 bits and we use regs->ip + 0x10 * regs->cs. | |
2268 | * | |
2269 | * IA32 - Where we need to look at GDT/LDT segment descriptor tables | |
2270 | * to figure out what the 32bit base address is. | |
2271 | * | |
2272 | * X32 - has TIF_X32 set, but is running in x86_64 | |
2273 | * | |
2274 | * X86_64 - CS,DS,SS,ES are all zero based. | |
2275 | */ | |
2276 | static unsigned long code_segment_base(struct pt_regs *regs) | |
39447b38 | 2277 | { |
383f3af3 AL |
2278 | /* |
2279 | * For IA32 we look at the GDT/LDT segment base to convert the | |
2280 | * effective IP to a linear address. | |
2281 | */ | |
2282 | ||
2283 | #ifdef CONFIG_X86_32 | |
d07bdfd3 PZ |
2284 | /* |
2285 | * If we are in VM86 mode, add the segment offset to convert to a | |
2286 | * linear address. | |
2287 | */ | |
2288 | if (regs->flags & X86_VM_MASK) | |
2289 | return 0x10 * regs->cs; | |
2290 | ||
55474c48 | 2291 | if (user_mode(regs) && regs->cs != __USER_CS) |
d07bdfd3 PZ |
2292 | return get_segment_base(regs->cs); |
2293 | #else | |
c56716af AL |
2294 | if (user_mode(regs) && !user_64bit_mode(regs) && |
2295 | regs->cs != __USER32_CS) | |
2296 | return get_segment_base(regs->cs); | |
d07bdfd3 PZ |
2297 | #endif |
2298 | return 0; | |
2299 | } | |
dcf46b94 | 2300 | |
d07bdfd3 PZ |
2301 | unsigned long perf_instruction_pointer(struct pt_regs *regs) |
2302 | { | |
39447b38 | 2303 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) |
d07bdfd3 | 2304 | return perf_guest_cbs->get_guest_ip(); |
dcf46b94 | 2305 | |
d07bdfd3 | 2306 | return regs->ip + code_segment_base(regs); |
39447b38 ZY |
2307 | } |
2308 | ||
2309 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
2310 | { | |
2311 | int misc = 0; | |
dcf46b94 | 2312 | |
39447b38 | 2313 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
dcf46b94 ZY |
2314 | if (perf_guest_cbs->is_user_mode()) |
2315 | misc |= PERF_RECORD_MISC_GUEST_USER; | |
2316 | else | |
2317 | misc |= PERF_RECORD_MISC_GUEST_KERNEL; | |
2318 | } else { | |
d07bdfd3 | 2319 | if (user_mode(regs)) |
dcf46b94 ZY |
2320 | misc |= PERF_RECORD_MISC_USER; |
2321 | else | |
2322 | misc |= PERF_RECORD_MISC_KERNEL; | |
2323 | } | |
2324 | ||
39447b38 | 2325 | if (regs->flags & PERF_EFLAGS_EXACT) |
ab608344 | 2326 | misc |= PERF_RECORD_MISC_EXACT_IP; |
39447b38 ZY |
2327 | |
2328 | return misc; | |
2329 | } | |
b3d9468a GN |
2330 | |
2331 | void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap) | |
2332 | { | |
2333 | cap->version = x86_pmu.version; | |
2334 | cap->num_counters_gp = x86_pmu.num_counters; | |
2335 | cap->num_counters_fixed = x86_pmu.num_counters_fixed; | |
2336 | cap->bit_width_gp = x86_pmu.cntval_bits; | |
2337 | cap->bit_width_fixed = x86_pmu.cntval_bits; | |
2338 | cap->events_mask = (unsigned int)x86_pmu.events_maskl; | |
2339 | cap->events_mask_len = x86_pmu.events_mask_len; | |
2340 | } | |
2341 | EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability); |