Commit | Line | Data |
---|---|---|
241771ef | 1 | /* |
cdd6c482 | 2 | * Performance events x86 architecture code |
241771ef | 3 | * |
98144511 IM |
4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> | |
30dd568c | 9 | * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> |
1da53e02 | 10 | * Copyright (C) 2009 Google, Inc., Stephane Eranian |
241771ef IM |
11 | * |
12 | * For licencing details see kernel-base/COPYING | |
13 | */ | |
14 | ||
cdd6c482 | 15 | #include <linux/perf_event.h> |
241771ef IM |
16 | #include <linux/capability.h> |
17 | #include <linux/notifier.h> | |
18 | #include <linux/hardirq.h> | |
19 | #include <linux/kprobes.h> | |
4ac13294 | 20 | #include <linux/module.h> |
241771ef IM |
21 | #include <linux/kdebug.h> |
22 | #include <linux/sched.h> | |
d7d59fb3 | 23 | #include <linux/uaccess.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
30dd568c | 25 | #include <linux/cpu.h> |
272d30be | 26 | #include <linux/bitops.h> |
0c9d42ed | 27 | #include <linux/device.h> |
241771ef | 28 | |
241771ef | 29 | #include <asm/apic.h> |
d7d59fb3 | 30 | #include <asm/stacktrace.h> |
4e935e47 | 31 | #include <asm/nmi.h> |
69092624 | 32 | #include <asm/smp.h> |
c8e5910e | 33 | #include <asm/alternative.h> |
e3f3541c | 34 | #include <asm/timer.h> |
d07bdfd3 PZ |
35 | #include <asm/desc.h> |
36 | #include <asm/ldt.h> | |
241771ef | 37 | |
de0428a7 KW |
38 | #include "perf_event.h" |
39 | ||
de0428a7 | 40 | struct x86_pmu x86_pmu __read_mostly; |
efc9f05d | 41 | |
de0428a7 | 42 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { |
b0f3f28e PZ |
43 | .enabled = 1, |
44 | }; | |
241771ef | 45 | |
de0428a7 | 46 | u64 __read_mostly hw_cache_event_ids |
8326f44d IM |
47 | [PERF_COUNT_HW_CACHE_MAX] |
48 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
49 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
de0428a7 | 50 | u64 __read_mostly hw_cache_extra_regs |
e994d7d2 AK |
51 | [PERF_COUNT_HW_CACHE_MAX] |
52 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
53 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
8326f44d | 54 | |
ee06094f | 55 | /* |
cdd6c482 IM |
56 | * Propagate event elapsed time into the generic event. |
57 | * Can only be executed on the CPU where the event is active. | |
ee06094f IM |
58 | * Returns the delta events processed. |
59 | */ | |
de0428a7 | 60 | u64 x86_perf_event_update(struct perf_event *event) |
ee06094f | 61 | { |
cc2ad4ba | 62 | struct hw_perf_event *hwc = &event->hw; |
948b1bb8 | 63 | int shift = 64 - x86_pmu.cntval_bits; |
ec3232bd | 64 | u64 prev_raw_count, new_raw_count; |
cc2ad4ba | 65 | int idx = hwc->idx; |
ec3232bd | 66 | s64 delta; |
ee06094f | 67 | |
15c7ad51 | 68 | if (idx == INTEL_PMC_IDX_FIXED_BTS) |
30dd568c MM |
69 | return 0; |
70 | ||
ee06094f | 71 | /* |
cdd6c482 | 72 | * Careful: an NMI might modify the previous event value. |
ee06094f IM |
73 | * |
74 | * Our tactic to handle this is to first atomically read and | |
75 | * exchange a new raw count - then add that new-prev delta | |
cdd6c482 | 76 | * count to the generic event atomically: |
ee06094f IM |
77 | */ |
78 | again: | |
e7850595 | 79 | prev_raw_count = local64_read(&hwc->prev_count); |
c48b6053 | 80 | rdpmcl(hwc->event_base_rdpmc, new_raw_count); |
ee06094f | 81 | |
e7850595 | 82 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
ee06094f IM |
83 | new_raw_count) != prev_raw_count) |
84 | goto again; | |
85 | ||
86 | /* | |
87 | * Now we have the new raw value and have updated the prev | |
88 | * timestamp already. We can now calculate the elapsed delta | |
cdd6c482 | 89 | * (event-)time and add that to the generic event. |
ee06094f IM |
90 | * |
91 | * Careful, not all hw sign-extends above the physical width | |
ec3232bd | 92 | * of the count. |
ee06094f | 93 | */ |
ec3232bd PZ |
94 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
95 | delta >>= shift; | |
ee06094f | 96 | |
e7850595 PZ |
97 | local64_add(delta, &event->count); |
98 | local64_sub(delta, &hwc->period_left); | |
4b7bfd0d RR |
99 | |
100 | return new_raw_count; | |
ee06094f IM |
101 | } |
102 | ||
a7e3ed1e AK |
103 | /* |
104 | * Find and validate any extra registers to set up. | |
105 | */ | |
106 | static int x86_pmu_extra_regs(u64 config, struct perf_event *event) | |
107 | { | |
efc9f05d | 108 | struct hw_perf_event_extra *reg; |
a7e3ed1e AK |
109 | struct extra_reg *er; |
110 | ||
efc9f05d | 111 | reg = &event->hw.extra_reg; |
a7e3ed1e AK |
112 | |
113 | if (!x86_pmu.extra_regs) | |
114 | return 0; | |
115 | ||
116 | for (er = x86_pmu.extra_regs; er->msr; er++) { | |
117 | if (er->event != (config & er->config_mask)) | |
118 | continue; | |
119 | if (event->attr.config1 & ~er->valid_mask) | |
120 | return -EINVAL; | |
efc9f05d SE |
121 | |
122 | reg->idx = er->idx; | |
123 | reg->config = event->attr.config1; | |
124 | reg->reg = er->msr; | |
a7e3ed1e AK |
125 | break; |
126 | } | |
127 | return 0; | |
128 | } | |
129 | ||
cdd6c482 | 130 | static atomic_t active_events; |
4e935e47 PZ |
131 | static DEFINE_MUTEX(pmc_reserve_mutex); |
132 | ||
b27ea29c RR |
133 | #ifdef CONFIG_X86_LOCAL_APIC |
134 | ||
4e935e47 PZ |
135 | static bool reserve_pmc_hardware(void) |
136 | { | |
137 | int i; | |
138 | ||
948b1bb8 | 139 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 | 140 | if (!reserve_perfctr_nmi(x86_pmu_event_addr(i))) |
4e935e47 PZ |
141 | goto perfctr_fail; |
142 | } | |
143 | ||
948b1bb8 | 144 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 | 145 | if (!reserve_evntsel_nmi(x86_pmu_config_addr(i))) |
4e935e47 PZ |
146 | goto eventsel_fail; |
147 | } | |
148 | ||
149 | return true; | |
150 | ||
151 | eventsel_fail: | |
152 | for (i--; i >= 0; i--) | |
41bf4989 | 153 | release_evntsel_nmi(x86_pmu_config_addr(i)); |
4e935e47 | 154 | |
948b1bb8 | 155 | i = x86_pmu.num_counters; |
4e935e47 PZ |
156 | |
157 | perfctr_fail: | |
158 | for (i--; i >= 0; i--) | |
41bf4989 | 159 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
4e935e47 | 160 | |
4e935e47 PZ |
161 | return false; |
162 | } | |
163 | ||
164 | static void release_pmc_hardware(void) | |
165 | { | |
166 | int i; | |
167 | ||
948b1bb8 | 168 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 RR |
169 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
170 | release_evntsel_nmi(x86_pmu_config_addr(i)); | |
4e935e47 | 171 | } |
4e935e47 PZ |
172 | } |
173 | ||
b27ea29c RR |
174 | #else |
175 | ||
176 | static bool reserve_pmc_hardware(void) { return true; } | |
177 | static void release_pmc_hardware(void) {} | |
178 | ||
179 | #endif | |
180 | ||
33c6d6a7 DZ |
181 | static bool check_hw_exists(void) |
182 | { | |
a5ebe0ba GD |
183 | u64 val, val_fail, val_new= ~0; |
184 | int i, reg, reg_fail, ret = 0; | |
185 | int bios_fail = 0; | |
33c6d6a7 | 186 | |
4407204c PZ |
187 | /* |
188 | * Check to see if the BIOS enabled any of the counters, if so | |
189 | * complain and bail. | |
190 | */ | |
191 | for (i = 0; i < x86_pmu.num_counters; i++) { | |
41bf4989 | 192 | reg = x86_pmu_config_addr(i); |
4407204c PZ |
193 | ret = rdmsrl_safe(reg, &val); |
194 | if (ret) | |
195 | goto msr_fail; | |
a5ebe0ba GD |
196 | if (val & ARCH_PERFMON_EVENTSEL_ENABLE) { |
197 | bios_fail = 1; | |
198 | val_fail = val; | |
199 | reg_fail = reg; | |
200 | } | |
4407204c PZ |
201 | } |
202 | ||
203 | if (x86_pmu.num_counters_fixed) { | |
204 | reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; | |
205 | ret = rdmsrl_safe(reg, &val); | |
206 | if (ret) | |
207 | goto msr_fail; | |
208 | for (i = 0; i < x86_pmu.num_counters_fixed; i++) { | |
a5ebe0ba GD |
209 | if (val & (0x03 << i*4)) { |
210 | bios_fail = 1; | |
211 | val_fail = val; | |
212 | reg_fail = reg; | |
213 | } | |
4407204c PZ |
214 | } |
215 | } | |
216 | ||
217 | /* | |
bffd5fc2 AP |
218 | * Read the current value, change it and read it back to see if it |
219 | * matches, this is needed to detect certain hardware emulators | |
220 | * (qemu/kvm) that don't trap on the MSR access and always return 0s. | |
4407204c | 221 | */ |
f285f92f | 222 | reg = x86_pmu_event_addr(0); |
bffd5fc2 AP |
223 | if (rdmsrl_safe(reg, &val)) |
224 | goto msr_fail; | |
225 | val ^= 0xffffUL; | |
f285f92f RR |
226 | ret = wrmsrl_safe(reg, val); |
227 | ret |= rdmsrl_safe(reg, &val_new); | |
33c6d6a7 | 228 | if (ret || val != val_new) |
4407204c | 229 | goto msr_fail; |
33c6d6a7 | 230 | |
45daae57 IM |
231 | /* |
232 | * We still allow the PMU driver to operate: | |
233 | */ | |
a5ebe0ba GD |
234 | if (bios_fail) { |
235 | printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n"); | |
236 | printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg_fail, val_fail); | |
237 | } | |
45daae57 IM |
238 | |
239 | return true; | |
4407204c PZ |
240 | |
241 | msr_fail: | |
242 | printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n"); | |
f285f92f | 243 | printk(KERN_ERR "Failed to access perfctr msr (MSR %x is %Lx)\n", reg, val_new); |
45daae57 | 244 | |
4407204c | 245 | return false; |
33c6d6a7 DZ |
246 | } |
247 | ||
cdd6c482 | 248 | static void hw_perf_event_destroy(struct perf_event *event) |
4e935e47 | 249 | { |
cdd6c482 | 250 | if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) { |
4e935e47 | 251 | release_pmc_hardware(); |
ca037701 | 252 | release_ds_buffers(); |
4e935e47 PZ |
253 | mutex_unlock(&pmc_reserve_mutex); |
254 | } | |
255 | } | |
256 | ||
85cf9dba RR |
257 | static inline int x86_pmu_initialized(void) |
258 | { | |
259 | return x86_pmu.handle_irq != NULL; | |
260 | } | |
261 | ||
8326f44d | 262 | static inline int |
e994d7d2 | 263 | set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event) |
8326f44d | 264 | { |
e994d7d2 | 265 | struct perf_event_attr *attr = &event->attr; |
8326f44d IM |
266 | unsigned int cache_type, cache_op, cache_result; |
267 | u64 config, val; | |
268 | ||
269 | config = attr->config; | |
270 | ||
271 | cache_type = (config >> 0) & 0xff; | |
272 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
273 | return -EINVAL; | |
274 | ||
275 | cache_op = (config >> 8) & 0xff; | |
276 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
277 | return -EINVAL; | |
278 | ||
279 | cache_result = (config >> 16) & 0xff; | |
280 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
281 | return -EINVAL; | |
282 | ||
283 | val = hw_cache_event_ids[cache_type][cache_op][cache_result]; | |
284 | ||
285 | if (val == 0) | |
286 | return -ENOENT; | |
287 | ||
288 | if (val == -1) | |
289 | return -EINVAL; | |
290 | ||
291 | hwc->config |= val; | |
e994d7d2 AK |
292 | attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result]; |
293 | return x86_pmu_extra_regs(val, event); | |
8326f44d IM |
294 | } |
295 | ||
de0428a7 | 296 | int x86_setup_perfctr(struct perf_event *event) |
c1726f34 RR |
297 | { |
298 | struct perf_event_attr *attr = &event->attr; | |
299 | struct hw_perf_event *hwc = &event->hw; | |
300 | u64 config; | |
301 | ||
6c7e550f | 302 | if (!is_sampling_event(event)) { |
c1726f34 RR |
303 | hwc->sample_period = x86_pmu.max_period; |
304 | hwc->last_period = hwc->sample_period; | |
e7850595 | 305 | local64_set(&hwc->period_left, hwc->sample_period); |
c1726f34 RR |
306 | } |
307 | ||
308 | if (attr->type == PERF_TYPE_RAW) | |
ed13ec58 | 309 | return x86_pmu_extra_regs(event->attr.config, event); |
c1726f34 RR |
310 | |
311 | if (attr->type == PERF_TYPE_HW_CACHE) | |
e994d7d2 | 312 | return set_ext_hw_attr(hwc, event); |
c1726f34 RR |
313 | |
314 | if (attr->config >= x86_pmu.max_events) | |
315 | return -EINVAL; | |
316 | ||
317 | /* | |
318 | * The generic map: | |
319 | */ | |
320 | config = x86_pmu.event_map(attr->config); | |
321 | ||
322 | if (config == 0) | |
323 | return -ENOENT; | |
324 | ||
325 | if (config == -1LL) | |
326 | return -EINVAL; | |
327 | ||
328 | /* | |
329 | * Branch tracing: | |
330 | */ | |
18a073a3 PZ |
331 | if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS && |
332 | !attr->freq && hwc->sample_period == 1) { | |
c1726f34 | 333 | /* BTS is not supported by this architecture. */ |
6809b6ea | 334 | if (!x86_pmu.bts_active) |
c1726f34 RR |
335 | return -EOPNOTSUPP; |
336 | ||
337 | /* BTS is currently only allowed for user-mode. */ | |
338 | if (!attr->exclude_kernel) | |
339 | return -EOPNOTSUPP; | |
340 | } | |
341 | ||
342 | hwc->config |= config; | |
343 | ||
344 | return 0; | |
345 | } | |
4261e0e0 | 346 | |
ff3fb511 SE |
347 | /* |
348 | * check that branch_sample_type is compatible with | |
349 | * settings needed for precise_ip > 1 which implies | |
350 | * using the LBR to capture ALL taken branches at the | |
351 | * priv levels of the measurement | |
352 | */ | |
353 | static inline int precise_br_compat(struct perf_event *event) | |
354 | { | |
355 | u64 m = event->attr.branch_sample_type; | |
356 | u64 b = 0; | |
357 | ||
358 | /* must capture all branches */ | |
359 | if (!(m & PERF_SAMPLE_BRANCH_ANY)) | |
360 | return 0; | |
361 | ||
362 | m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER; | |
363 | ||
364 | if (!event->attr.exclude_user) | |
365 | b |= PERF_SAMPLE_BRANCH_USER; | |
366 | ||
367 | if (!event->attr.exclude_kernel) | |
368 | b |= PERF_SAMPLE_BRANCH_KERNEL; | |
369 | ||
370 | /* | |
371 | * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86 | |
372 | */ | |
373 | ||
374 | return m == b; | |
375 | } | |
376 | ||
de0428a7 | 377 | int x86_pmu_hw_config(struct perf_event *event) |
a072738e | 378 | { |
ab608344 PZ |
379 | if (event->attr.precise_ip) { |
380 | int precise = 0; | |
381 | ||
382 | /* Support for constant skid */ | |
c93dc84c | 383 | if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) { |
ab608344 PZ |
384 | precise++; |
385 | ||
5553be26 PZ |
386 | /* Support for IP fixup */ |
387 | if (x86_pmu.lbr_nr) | |
388 | precise++; | |
389 | } | |
ab608344 PZ |
390 | |
391 | if (event->attr.precise_ip > precise) | |
392 | return -EOPNOTSUPP; | |
ff3fb511 SE |
393 | /* |
394 | * check that PEBS LBR correction does not conflict with | |
395 | * whatever the user is asking with attr->branch_sample_type | |
396 | */ | |
130768b8 AK |
397 | if (event->attr.precise_ip > 1 && |
398 | x86_pmu.intel_cap.pebs_format < 2) { | |
ff3fb511 SE |
399 | u64 *br_type = &event->attr.branch_sample_type; |
400 | ||
401 | if (has_branch_stack(event)) { | |
402 | if (!precise_br_compat(event)) | |
403 | return -EOPNOTSUPP; | |
404 | ||
405 | /* branch_sample_type is compatible */ | |
406 | ||
407 | } else { | |
408 | /* | |
409 | * user did not specify branch_sample_type | |
410 | * | |
411 | * For PEBS fixups, we capture all | |
412 | * the branches at the priv level of the | |
413 | * event. | |
414 | */ | |
415 | *br_type = PERF_SAMPLE_BRANCH_ANY; | |
416 | ||
417 | if (!event->attr.exclude_user) | |
418 | *br_type |= PERF_SAMPLE_BRANCH_USER; | |
419 | ||
420 | if (!event->attr.exclude_kernel) | |
421 | *br_type |= PERF_SAMPLE_BRANCH_KERNEL; | |
422 | } | |
423 | } | |
ab608344 PZ |
424 | } |
425 | ||
a072738e CG |
426 | /* |
427 | * Generate PMC IRQs: | |
428 | * (keep 'enabled' bit clear for now) | |
429 | */ | |
b4cdc5c2 | 430 | event->hw.config = ARCH_PERFMON_EVENTSEL_INT; |
a072738e CG |
431 | |
432 | /* | |
433 | * Count user and OS events unless requested not to | |
434 | */ | |
b4cdc5c2 PZ |
435 | if (!event->attr.exclude_user) |
436 | event->hw.config |= ARCH_PERFMON_EVENTSEL_USR; | |
437 | if (!event->attr.exclude_kernel) | |
438 | event->hw.config |= ARCH_PERFMON_EVENTSEL_OS; | |
a072738e | 439 | |
b4cdc5c2 PZ |
440 | if (event->attr.type == PERF_TYPE_RAW) |
441 | event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK; | |
a072738e | 442 | |
9d0fcba6 | 443 | return x86_setup_perfctr(event); |
a098f448 RR |
444 | } |
445 | ||
241771ef | 446 | /* |
0d48696f | 447 | * Setup the hardware configuration for a given attr_type |
241771ef | 448 | */ |
b0a873eb | 449 | static int __x86_pmu_event_init(struct perf_event *event) |
241771ef | 450 | { |
4e935e47 | 451 | int err; |
241771ef | 452 | |
85cf9dba RR |
453 | if (!x86_pmu_initialized()) |
454 | return -ENODEV; | |
241771ef | 455 | |
4e935e47 | 456 | err = 0; |
cdd6c482 | 457 | if (!atomic_inc_not_zero(&active_events)) { |
4e935e47 | 458 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 | 459 | if (atomic_read(&active_events) == 0) { |
30dd568c MM |
460 | if (!reserve_pmc_hardware()) |
461 | err = -EBUSY; | |
f80c9e30 PZ |
462 | else |
463 | reserve_ds_buffers(); | |
30dd568c MM |
464 | } |
465 | if (!err) | |
cdd6c482 | 466 | atomic_inc(&active_events); |
4e935e47 PZ |
467 | mutex_unlock(&pmc_reserve_mutex); |
468 | } | |
469 | if (err) | |
470 | return err; | |
471 | ||
cdd6c482 | 472 | event->destroy = hw_perf_event_destroy; |
a1792cda | 473 | |
4261e0e0 RR |
474 | event->hw.idx = -1; |
475 | event->hw.last_cpu = -1; | |
476 | event->hw.last_tag = ~0ULL; | |
b690081d | 477 | |
efc9f05d SE |
478 | /* mark unused */ |
479 | event->hw.extra_reg.idx = EXTRA_REG_NONE; | |
b36817e8 SE |
480 | event->hw.branch_reg.idx = EXTRA_REG_NONE; |
481 | ||
9d0fcba6 | 482 | return x86_pmu.hw_config(event); |
4261e0e0 RR |
483 | } |
484 | ||
de0428a7 | 485 | void x86_pmu_disable_all(void) |
f87ad35d | 486 | { |
cdd6c482 | 487 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
9e35ad38 PZ |
488 | int idx; |
489 | ||
948b1bb8 | 490 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
b0f3f28e PZ |
491 | u64 val; |
492 | ||
43f6201a | 493 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 494 | continue; |
41bf4989 | 495 | rdmsrl(x86_pmu_config_addr(idx), val); |
bb1165d6 | 496 | if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE)) |
4295ee62 | 497 | continue; |
bb1165d6 | 498 | val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; |
41bf4989 | 499 | wrmsrl(x86_pmu_config_addr(idx), val); |
f87ad35d | 500 | } |
f87ad35d JSR |
501 | } |
502 | ||
a4eaf7f1 | 503 | static void x86_pmu_disable(struct pmu *pmu) |
b56a3802 | 504 | { |
1da53e02 SE |
505 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
506 | ||
85cf9dba | 507 | if (!x86_pmu_initialized()) |
9e35ad38 | 508 | return; |
1da53e02 | 509 | |
1a6e21f7 PZ |
510 | if (!cpuc->enabled) |
511 | return; | |
512 | ||
513 | cpuc->n_added = 0; | |
514 | cpuc->enabled = 0; | |
515 | barrier(); | |
1da53e02 SE |
516 | |
517 | x86_pmu.disable_all(); | |
b56a3802 | 518 | } |
241771ef | 519 | |
de0428a7 | 520 | void x86_pmu_enable_all(int added) |
f87ad35d | 521 | { |
cdd6c482 | 522 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
f87ad35d JSR |
523 | int idx; |
524 | ||
948b1bb8 | 525 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
d45dd923 | 526 | struct hw_perf_event *hwc = &cpuc->events[idx]->hw; |
b0f3f28e | 527 | |
43f6201a | 528 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 529 | continue; |
984b838c | 530 | |
d45dd923 | 531 | __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); |
f87ad35d JSR |
532 | } |
533 | } | |
534 | ||
51b0fe39 | 535 | static struct pmu pmu; |
1da53e02 SE |
536 | |
537 | static inline int is_x86_event(struct perf_event *event) | |
538 | { | |
539 | return event->pmu == &pmu; | |
540 | } | |
541 | ||
1e2ad28f RR |
542 | /* |
543 | * Event scheduler state: | |
544 | * | |
545 | * Assign events iterating over all events and counters, beginning | |
546 | * with events with least weights first. Keep the current iterator | |
547 | * state in struct sched_state. | |
548 | */ | |
549 | struct sched_state { | |
550 | int weight; | |
551 | int event; /* event index */ | |
552 | int counter; /* counter index */ | |
553 | int unassigned; /* number of events to be assigned left */ | |
554 | unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
555 | }; | |
556 | ||
bc1738f6 RR |
557 | /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */ |
558 | #define SCHED_STATES_MAX 2 | |
559 | ||
1e2ad28f RR |
560 | struct perf_sched { |
561 | int max_weight; | |
562 | int max_events; | |
43b45780 | 563 | struct perf_event **events; |
1e2ad28f | 564 | struct sched_state state; |
bc1738f6 RR |
565 | int saved_states; |
566 | struct sched_state saved[SCHED_STATES_MAX]; | |
1e2ad28f RR |
567 | }; |
568 | ||
569 | /* | |
570 | * Initialize interator that runs through all events and counters. | |
571 | */ | |
43b45780 | 572 | static void perf_sched_init(struct perf_sched *sched, struct perf_event **events, |
1e2ad28f RR |
573 | int num, int wmin, int wmax) |
574 | { | |
575 | int idx; | |
576 | ||
577 | memset(sched, 0, sizeof(*sched)); | |
578 | sched->max_events = num; | |
579 | sched->max_weight = wmax; | |
43b45780 | 580 | sched->events = events; |
1e2ad28f RR |
581 | |
582 | for (idx = 0; idx < num; idx++) { | |
43b45780 | 583 | if (events[idx]->hw.constraint->weight == wmin) |
1e2ad28f RR |
584 | break; |
585 | } | |
586 | ||
587 | sched->state.event = idx; /* start with min weight */ | |
588 | sched->state.weight = wmin; | |
589 | sched->state.unassigned = num; | |
590 | } | |
591 | ||
bc1738f6 RR |
592 | static void perf_sched_save_state(struct perf_sched *sched) |
593 | { | |
594 | if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX)) | |
595 | return; | |
596 | ||
597 | sched->saved[sched->saved_states] = sched->state; | |
598 | sched->saved_states++; | |
599 | } | |
600 | ||
601 | static bool perf_sched_restore_state(struct perf_sched *sched) | |
602 | { | |
603 | if (!sched->saved_states) | |
604 | return false; | |
605 | ||
606 | sched->saved_states--; | |
607 | sched->state = sched->saved[sched->saved_states]; | |
608 | ||
609 | /* continue with next counter: */ | |
610 | clear_bit(sched->state.counter++, sched->state.used); | |
611 | ||
612 | return true; | |
613 | } | |
614 | ||
1e2ad28f RR |
615 | /* |
616 | * Select a counter for the current event to schedule. Return true on | |
617 | * success. | |
618 | */ | |
bc1738f6 | 619 | static bool __perf_sched_find_counter(struct perf_sched *sched) |
1e2ad28f RR |
620 | { |
621 | struct event_constraint *c; | |
622 | int idx; | |
623 | ||
624 | if (!sched->state.unassigned) | |
625 | return false; | |
626 | ||
627 | if (sched->state.event >= sched->max_events) | |
628 | return false; | |
629 | ||
43b45780 | 630 | c = sched->events[sched->state.event]->hw.constraint; |
4defea85 | 631 | /* Prefer fixed purpose counters */ |
15c7ad51 RR |
632 | if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) { |
633 | idx = INTEL_PMC_IDX_FIXED; | |
307b1cd7 | 634 | for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) { |
4defea85 PZ |
635 | if (!__test_and_set_bit(idx, sched->state.used)) |
636 | goto done; | |
637 | } | |
638 | } | |
1e2ad28f RR |
639 | /* Grab the first unused counter starting with idx */ |
640 | idx = sched->state.counter; | |
15c7ad51 | 641 | for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) { |
1e2ad28f | 642 | if (!__test_and_set_bit(idx, sched->state.used)) |
4defea85 | 643 | goto done; |
1e2ad28f | 644 | } |
1e2ad28f | 645 | |
4defea85 PZ |
646 | return false; |
647 | ||
648 | done: | |
649 | sched->state.counter = idx; | |
1e2ad28f | 650 | |
bc1738f6 RR |
651 | if (c->overlap) |
652 | perf_sched_save_state(sched); | |
653 | ||
654 | return true; | |
655 | } | |
656 | ||
657 | static bool perf_sched_find_counter(struct perf_sched *sched) | |
658 | { | |
659 | while (!__perf_sched_find_counter(sched)) { | |
660 | if (!perf_sched_restore_state(sched)) | |
661 | return false; | |
662 | } | |
663 | ||
1e2ad28f RR |
664 | return true; |
665 | } | |
666 | ||
667 | /* | |
668 | * Go through all unassigned events and find the next one to schedule. | |
669 | * Take events with the least weight first. Return true on success. | |
670 | */ | |
671 | static bool perf_sched_next_event(struct perf_sched *sched) | |
672 | { | |
673 | struct event_constraint *c; | |
674 | ||
675 | if (!sched->state.unassigned || !--sched->state.unassigned) | |
676 | return false; | |
677 | ||
678 | do { | |
679 | /* next event */ | |
680 | sched->state.event++; | |
681 | if (sched->state.event >= sched->max_events) { | |
682 | /* next weight */ | |
683 | sched->state.event = 0; | |
684 | sched->state.weight++; | |
685 | if (sched->state.weight > sched->max_weight) | |
686 | return false; | |
687 | } | |
43b45780 | 688 | c = sched->events[sched->state.event]->hw.constraint; |
1e2ad28f RR |
689 | } while (c->weight != sched->state.weight); |
690 | ||
691 | sched->state.counter = 0; /* start with first counter */ | |
692 | ||
693 | return true; | |
694 | } | |
695 | ||
696 | /* | |
697 | * Assign a counter for each event. | |
698 | */ | |
43b45780 | 699 | int perf_assign_events(struct perf_event **events, int n, |
4b4969b1 | 700 | int wmin, int wmax, int *assign) |
1e2ad28f RR |
701 | { |
702 | struct perf_sched sched; | |
703 | ||
43b45780 | 704 | perf_sched_init(&sched, events, n, wmin, wmax); |
1e2ad28f RR |
705 | |
706 | do { | |
707 | if (!perf_sched_find_counter(&sched)) | |
708 | break; /* failed */ | |
709 | if (assign) | |
710 | assign[sched.state.event] = sched.state.counter; | |
711 | } while (perf_sched_next_event(&sched)); | |
712 | ||
713 | return sched.state.unassigned; | |
714 | } | |
4a3dc121 | 715 | EXPORT_SYMBOL_GPL(perf_assign_events); |
1e2ad28f | 716 | |
de0428a7 | 717 | int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) |
1da53e02 | 718 | { |
43b45780 | 719 | struct event_constraint *c; |
1da53e02 | 720 | unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
2f7f73a5 | 721 | struct perf_event *e; |
1e2ad28f | 722 | int i, wmin, wmax, num = 0; |
1da53e02 SE |
723 | struct hw_perf_event *hwc; |
724 | ||
725 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); | |
726 | ||
1e2ad28f | 727 | for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) { |
43b45780 | 728 | hwc = &cpuc->event_list[i]->hw; |
b622d644 | 729 | c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]); |
43b45780 AH |
730 | hwc->constraint = c; |
731 | ||
1e2ad28f RR |
732 | wmin = min(wmin, c->weight); |
733 | wmax = max(wmax, c->weight); | |
1da53e02 SE |
734 | } |
735 | ||
8113070d SE |
736 | /* |
737 | * fastpath, try to reuse previous register | |
738 | */ | |
c933c1a6 | 739 | for (i = 0; i < n; i++) { |
8113070d | 740 | hwc = &cpuc->event_list[i]->hw; |
43b45780 | 741 | c = hwc->constraint; |
8113070d SE |
742 | |
743 | /* never assigned */ | |
744 | if (hwc->idx == -1) | |
745 | break; | |
746 | ||
747 | /* constraint still honored */ | |
63b14649 | 748 | if (!test_bit(hwc->idx, c->idxmsk)) |
8113070d SE |
749 | break; |
750 | ||
751 | /* not already used */ | |
752 | if (test_bit(hwc->idx, used_mask)) | |
753 | break; | |
754 | ||
34538ee7 | 755 | __set_bit(hwc->idx, used_mask); |
8113070d SE |
756 | if (assign) |
757 | assign[i] = hwc->idx; | |
758 | } | |
8113070d | 759 | |
1e2ad28f RR |
760 | /* slow path */ |
761 | if (i != n) | |
43b45780 AH |
762 | num = perf_assign_events(cpuc->event_list, n, wmin, |
763 | wmax, assign); | |
8113070d | 764 | |
2f7f73a5 SE |
765 | /* |
766 | * Mark the event as committed, so we do not put_constraint() | |
767 | * in case new events are added and fail scheduling. | |
768 | */ | |
769 | if (!num && assign) { | |
770 | for (i = 0; i < n; i++) { | |
771 | e = cpuc->event_list[i]; | |
772 | e->hw.flags |= PERF_X86_EVENT_COMMITTED; | |
773 | } | |
774 | } | |
1da53e02 SE |
775 | /* |
776 | * scheduling failed or is just a simulation, | |
777 | * free resources if necessary | |
778 | */ | |
779 | if (!assign || num) { | |
780 | for (i = 0; i < n; i++) { | |
2f7f73a5 SE |
781 | e = cpuc->event_list[i]; |
782 | /* | |
783 | * do not put_constraint() on comitted events, | |
784 | * because they are good to go | |
785 | */ | |
786 | if ((e->hw.flags & PERF_X86_EVENT_COMMITTED)) | |
787 | continue; | |
788 | ||
1da53e02 | 789 | if (x86_pmu.put_event_constraints) |
2f7f73a5 | 790 | x86_pmu.put_event_constraints(cpuc, e); |
1da53e02 SE |
791 | } |
792 | } | |
aa2bc1ad | 793 | return num ? -EINVAL : 0; |
1da53e02 SE |
794 | } |
795 | ||
796 | /* | |
797 | * dogrp: true if must collect siblings events (group) | |
798 | * returns total number of events and error code | |
799 | */ | |
800 | static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp) | |
801 | { | |
802 | struct perf_event *event; | |
803 | int n, max_count; | |
804 | ||
948b1bb8 | 805 | max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed; |
1da53e02 SE |
806 | |
807 | /* current number of events already accepted */ | |
808 | n = cpuc->n_events; | |
809 | ||
810 | if (is_x86_event(leader)) { | |
811 | if (n >= max_count) | |
aa2bc1ad | 812 | return -EINVAL; |
1da53e02 SE |
813 | cpuc->event_list[n] = leader; |
814 | n++; | |
815 | } | |
816 | if (!dogrp) | |
817 | return n; | |
818 | ||
819 | list_for_each_entry(event, &leader->sibling_list, group_entry) { | |
820 | if (!is_x86_event(event) || | |
8113070d | 821 | event->state <= PERF_EVENT_STATE_OFF) |
1da53e02 SE |
822 | continue; |
823 | ||
824 | if (n >= max_count) | |
aa2bc1ad | 825 | return -EINVAL; |
1da53e02 SE |
826 | |
827 | cpuc->event_list[n] = event; | |
828 | n++; | |
829 | } | |
830 | return n; | |
831 | } | |
832 | ||
1da53e02 | 833 | static inline void x86_assign_hw_event(struct perf_event *event, |
447a194b | 834 | struct cpu_hw_events *cpuc, int i) |
1da53e02 | 835 | { |
447a194b SE |
836 | struct hw_perf_event *hwc = &event->hw; |
837 | ||
838 | hwc->idx = cpuc->assign[i]; | |
839 | hwc->last_cpu = smp_processor_id(); | |
840 | hwc->last_tag = ++cpuc->tags[i]; | |
1da53e02 | 841 | |
15c7ad51 | 842 | if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) { |
1da53e02 SE |
843 | hwc->config_base = 0; |
844 | hwc->event_base = 0; | |
15c7ad51 | 845 | } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) { |
1da53e02 | 846 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; |
15c7ad51 RR |
847 | hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED); |
848 | hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30; | |
1da53e02 | 849 | } else { |
73d6e522 RR |
850 | hwc->config_base = x86_pmu_config_addr(hwc->idx); |
851 | hwc->event_base = x86_pmu_event_addr(hwc->idx); | |
0fbdad07 | 852 | hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx); |
1da53e02 SE |
853 | } |
854 | } | |
855 | ||
447a194b SE |
856 | static inline int match_prev_assignment(struct hw_perf_event *hwc, |
857 | struct cpu_hw_events *cpuc, | |
858 | int i) | |
859 | { | |
860 | return hwc->idx == cpuc->assign[i] && | |
861 | hwc->last_cpu == smp_processor_id() && | |
862 | hwc->last_tag == cpuc->tags[i]; | |
863 | } | |
864 | ||
a4eaf7f1 | 865 | static void x86_pmu_start(struct perf_event *event, int flags); |
2e841873 | 866 | |
a4eaf7f1 | 867 | static void x86_pmu_enable(struct pmu *pmu) |
ee06094f | 868 | { |
1da53e02 SE |
869 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
870 | struct perf_event *event; | |
871 | struct hw_perf_event *hwc; | |
11164cd4 | 872 | int i, added = cpuc->n_added; |
1da53e02 | 873 | |
85cf9dba | 874 | if (!x86_pmu_initialized()) |
2b9ff0db | 875 | return; |
1a6e21f7 PZ |
876 | |
877 | if (cpuc->enabled) | |
878 | return; | |
879 | ||
1da53e02 | 880 | if (cpuc->n_added) { |
19925ce7 | 881 | int n_running = cpuc->n_events - cpuc->n_added; |
1da53e02 SE |
882 | /* |
883 | * apply assignment obtained either from | |
884 | * hw_perf_group_sched_in() or x86_pmu_enable() | |
885 | * | |
886 | * step1: save events moving to new counters | |
1da53e02 | 887 | */ |
19925ce7 | 888 | for (i = 0; i < n_running; i++) { |
1da53e02 SE |
889 | event = cpuc->event_list[i]; |
890 | hwc = &event->hw; | |
891 | ||
447a194b SE |
892 | /* |
893 | * we can avoid reprogramming counter if: | |
894 | * - assigned same counter as last time | |
895 | * - running on same CPU as last time | |
896 | * - no other event has used the counter since | |
897 | */ | |
898 | if (hwc->idx == -1 || | |
899 | match_prev_assignment(hwc, cpuc, i)) | |
1da53e02 SE |
900 | continue; |
901 | ||
a4eaf7f1 PZ |
902 | /* |
903 | * Ensure we don't accidentally enable a stopped | |
904 | * counter simply because we rescheduled. | |
905 | */ | |
906 | if (hwc->state & PERF_HES_STOPPED) | |
907 | hwc->state |= PERF_HES_ARCH; | |
908 | ||
909 | x86_pmu_stop(event, PERF_EF_UPDATE); | |
1da53e02 SE |
910 | } |
911 | ||
c347a2f1 PZ |
912 | /* |
913 | * step2: reprogram moved events into new counters | |
914 | */ | |
1da53e02 | 915 | for (i = 0; i < cpuc->n_events; i++) { |
1da53e02 SE |
916 | event = cpuc->event_list[i]; |
917 | hwc = &event->hw; | |
918 | ||
45e16a68 | 919 | if (!match_prev_assignment(hwc, cpuc, i)) |
447a194b | 920 | x86_assign_hw_event(event, cpuc, i); |
45e16a68 PZ |
921 | else if (i < n_running) |
922 | continue; | |
1da53e02 | 923 | |
a4eaf7f1 PZ |
924 | if (hwc->state & PERF_HES_ARCH) |
925 | continue; | |
926 | ||
927 | x86_pmu_start(event, PERF_EF_RELOAD); | |
1da53e02 SE |
928 | } |
929 | cpuc->n_added = 0; | |
930 | perf_events_lapic_init(); | |
931 | } | |
1a6e21f7 PZ |
932 | |
933 | cpuc->enabled = 1; | |
934 | barrier(); | |
935 | ||
11164cd4 | 936 | x86_pmu.enable_all(added); |
ee06094f | 937 | } |
ee06094f | 938 | |
245b2e70 | 939 | static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); |
241771ef | 940 | |
ee06094f IM |
941 | /* |
942 | * Set the next IRQ period, based on the hwc->period_left value. | |
cdd6c482 | 943 | * To be called with the event disabled in hw: |
ee06094f | 944 | */ |
de0428a7 | 945 | int x86_perf_event_set_period(struct perf_event *event) |
241771ef | 946 | { |
07088edb | 947 | struct hw_perf_event *hwc = &event->hw; |
e7850595 | 948 | s64 left = local64_read(&hwc->period_left); |
e4abb5d4 | 949 | s64 period = hwc->sample_period; |
7645a24c | 950 | int ret = 0, idx = hwc->idx; |
ee06094f | 951 | |
15c7ad51 | 952 | if (idx == INTEL_PMC_IDX_FIXED_BTS) |
30dd568c MM |
953 | return 0; |
954 | ||
ee06094f | 955 | /* |
af901ca1 | 956 | * If we are way outside a reasonable range then just skip forward: |
ee06094f IM |
957 | */ |
958 | if (unlikely(left <= -period)) { | |
959 | left = period; | |
e7850595 | 960 | local64_set(&hwc->period_left, left); |
9e350de3 | 961 | hwc->last_period = period; |
e4abb5d4 | 962 | ret = 1; |
ee06094f IM |
963 | } |
964 | ||
965 | if (unlikely(left <= 0)) { | |
966 | left += period; | |
e7850595 | 967 | local64_set(&hwc->period_left, left); |
9e350de3 | 968 | hwc->last_period = period; |
e4abb5d4 | 969 | ret = 1; |
ee06094f | 970 | } |
1c80f4b5 | 971 | /* |
dfc65094 | 972 | * Quirk: certain CPUs dont like it if just 1 hw_event is left: |
1c80f4b5 IM |
973 | */ |
974 | if (unlikely(left < 2)) | |
975 | left = 2; | |
241771ef | 976 | |
e4abb5d4 PZ |
977 | if (left > x86_pmu.max_period) |
978 | left = x86_pmu.max_period; | |
979 | ||
245b2e70 | 980 | per_cpu(pmc_prev_left[idx], smp_processor_id()) = left; |
ee06094f IM |
981 | |
982 | /* | |
cdd6c482 | 983 | * The hw event starts counting from this event offset, |
ee06094f IM |
984 | * mark it to be able to extra future deltas: |
985 | */ | |
e7850595 | 986 | local64_set(&hwc->prev_count, (u64)-left); |
ee06094f | 987 | |
73d6e522 | 988 | wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac CG |
989 | |
990 | /* | |
991 | * Due to erratum on certan cpu we need | |
992 | * a second write to be sure the register | |
993 | * is updated properly | |
994 | */ | |
995 | if (x86_pmu.perfctr_second_write) { | |
73d6e522 | 996 | wrmsrl(hwc->event_base, |
948b1bb8 | 997 | (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac | 998 | } |
e4abb5d4 | 999 | |
cdd6c482 | 1000 | perf_event_update_userpage(event); |
194002b2 | 1001 | |
e4abb5d4 | 1002 | return ret; |
2f18d1e8 IM |
1003 | } |
1004 | ||
de0428a7 | 1005 | void x86_pmu_enable_event(struct perf_event *event) |
7c90cc45 | 1006 | { |
0a3aee0d | 1007 | if (__this_cpu_read(cpu_hw_events.enabled)) |
31fa58af RR |
1008 | __x86_pmu_enable_event(&event->hw, |
1009 | ARCH_PERFMON_EVENTSEL_ENABLE); | |
241771ef IM |
1010 | } |
1011 | ||
b690081d | 1012 | /* |
a4eaf7f1 | 1013 | * Add a single event to the PMU. |
1da53e02 SE |
1014 | * |
1015 | * The event is added to the group of enabled events | |
1016 | * but only if it can be scehduled with existing events. | |
fe9081cc | 1017 | */ |
a4eaf7f1 | 1018 | static int x86_pmu_add(struct perf_event *event, int flags) |
fe9081cc PZ |
1019 | { |
1020 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1da53e02 SE |
1021 | struct hw_perf_event *hwc; |
1022 | int assign[X86_PMC_IDX_MAX]; | |
1023 | int n, n0, ret; | |
fe9081cc | 1024 | |
1da53e02 | 1025 | hwc = &event->hw; |
fe9081cc | 1026 | |
33696fc0 | 1027 | perf_pmu_disable(event->pmu); |
1da53e02 | 1028 | n0 = cpuc->n_events; |
24cd7f54 PZ |
1029 | ret = n = collect_events(cpuc, event, false); |
1030 | if (ret < 0) | |
1031 | goto out; | |
53b441a5 | 1032 | |
a4eaf7f1 PZ |
1033 | hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; |
1034 | if (!(flags & PERF_EF_START)) | |
1035 | hwc->state |= PERF_HES_ARCH; | |
1036 | ||
4d1c52b0 LM |
1037 | /* |
1038 | * If group events scheduling transaction was started, | |
0d2eb44f | 1039 | * skip the schedulability test here, it will be performed |
c347a2f1 | 1040 | * at commit time (->commit_txn) as a whole. |
4d1c52b0 | 1041 | */ |
8d2cacbb | 1042 | if (cpuc->group_flag & PERF_EVENT_TXN) |
24cd7f54 | 1043 | goto done_collect; |
4d1c52b0 | 1044 | |
a072738e | 1045 | ret = x86_pmu.schedule_events(cpuc, n, assign); |
1da53e02 | 1046 | if (ret) |
24cd7f54 | 1047 | goto out; |
1da53e02 SE |
1048 | /* |
1049 | * copy new assignment, now we know it is possible | |
1050 | * will be used by hw_perf_enable() | |
1051 | */ | |
1052 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
7e2ae347 | 1053 | |
24cd7f54 | 1054 | done_collect: |
c347a2f1 PZ |
1055 | /* |
1056 | * Commit the collect_events() state. See x86_pmu_del() and | |
1057 | * x86_pmu_*_txn(). | |
1058 | */ | |
1da53e02 | 1059 | cpuc->n_events = n; |
356e1f2e | 1060 | cpuc->n_added += n - n0; |
90151c35 | 1061 | cpuc->n_txn += n - n0; |
95cdd2e7 | 1062 | |
24cd7f54 PZ |
1063 | ret = 0; |
1064 | out: | |
33696fc0 | 1065 | perf_pmu_enable(event->pmu); |
24cd7f54 | 1066 | return ret; |
241771ef IM |
1067 | } |
1068 | ||
a4eaf7f1 | 1069 | static void x86_pmu_start(struct perf_event *event, int flags) |
d76a0812 | 1070 | { |
c08053e6 PZ |
1071 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
1072 | int idx = event->hw.idx; | |
1073 | ||
a4eaf7f1 PZ |
1074 | if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) |
1075 | return; | |
1076 | ||
1077 | if (WARN_ON_ONCE(idx == -1)) | |
1078 | return; | |
1079 | ||
1080 | if (flags & PERF_EF_RELOAD) { | |
1081 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); | |
1082 | x86_perf_event_set_period(event); | |
1083 | } | |
1084 | ||
1085 | event->hw.state = 0; | |
d76a0812 | 1086 | |
c08053e6 PZ |
1087 | cpuc->events[idx] = event; |
1088 | __set_bit(idx, cpuc->active_mask); | |
63e6be6d | 1089 | __set_bit(idx, cpuc->running); |
aff3d91a | 1090 | x86_pmu.enable(event); |
c08053e6 | 1091 | perf_event_update_userpage(event); |
a78ac325 PZ |
1092 | } |
1093 | ||
cdd6c482 | 1094 | void perf_event_print_debug(void) |
241771ef | 1095 | { |
2f18d1e8 | 1096 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
ca037701 | 1097 | u64 pebs; |
cdd6c482 | 1098 | struct cpu_hw_events *cpuc; |
5bb9efe3 | 1099 | unsigned long flags; |
1e125676 IM |
1100 | int cpu, idx; |
1101 | ||
948b1bb8 | 1102 | if (!x86_pmu.num_counters) |
1e125676 | 1103 | return; |
241771ef | 1104 | |
5bb9efe3 | 1105 | local_irq_save(flags); |
241771ef IM |
1106 | |
1107 | cpu = smp_processor_id(); | |
cdd6c482 | 1108 | cpuc = &per_cpu(cpu_hw_events, cpu); |
241771ef | 1109 | |
faa28ae0 | 1110 | if (x86_pmu.version >= 2) { |
a1ef58f4 JSR |
1111 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
1112 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
1113 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
1114 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); | |
ca037701 | 1115 | rdmsrl(MSR_IA32_PEBS_ENABLE, pebs); |
a1ef58f4 JSR |
1116 | |
1117 | pr_info("\n"); | |
1118 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
1119 | pr_info("CPU#%d: status: %016llx\n", cpu, status); | |
1120 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); | |
1121 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); | |
ca037701 | 1122 | pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs); |
f87ad35d | 1123 | } |
7645a24c | 1124 | pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); |
241771ef | 1125 | |
948b1bb8 | 1126 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
41bf4989 RR |
1127 | rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl); |
1128 | rdmsrl(x86_pmu_event_addr(idx), pmc_count); | |
241771ef | 1129 | |
245b2e70 | 1130 | prev_left = per_cpu(pmc_prev_left[idx], cpu); |
241771ef | 1131 | |
a1ef58f4 | 1132 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 1133 | cpu, idx, pmc_ctrl); |
a1ef58f4 | 1134 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 1135 | cpu, idx, pmc_count); |
a1ef58f4 | 1136 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 1137 | cpu, idx, prev_left); |
241771ef | 1138 | } |
948b1bb8 | 1139 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { |
2f18d1e8 IM |
1140 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
1141 | ||
a1ef58f4 | 1142 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
2f18d1e8 IM |
1143 | cpu, idx, pmc_count); |
1144 | } | |
5bb9efe3 | 1145 | local_irq_restore(flags); |
241771ef IM |
1146 | } |
1147 | ||
de0428a7 | 1148 | void x86_pmu_stop(struct perf_event *event, int flags) |
241771ef | 1149 | { |
d76a0812 | 1150 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
cdd6c482 | 1151 | struct hw_perf_event *hwc = &event->hw; |
241771ef | 1152 | |
a4eaf7f1 PZ |
1153 | if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) { |
1154 | x86_pmu.disable(event); | |
1155 | cpuc->events[hwc->idx] = NULL; | |
1156 | WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); | |
1157 | hwc->state |= PERF_HES_STOPPED; | |
1158 | } | |
30dd568c | 1159 | |
a4eaf7f1 PZ |
1160 | if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { |
1161 | /* | |
1162 | * Drain the remaining delta count out of a event | |
1163 | * that we are disabling: | |
1164 | */ | |
1165 | x86_perf_event_update(event); | |
1166 | hwc->state |= PERF_HES_UPTODATE; | |
1167 | } | |
2e841873 PZ |
1168 | } |
1169 | ||
a4eaf7f1 | 1170 | static void x86_pmu_del(struct perf_event *event, int flags) |
2e841873 PZ |
1171 | { |
1172 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1173 | int i; | |
1174 | ||
2f7f73a5 SE |
1175 | /* |
1176 | * event is descheduled | |
1177 | */ | |
1178 | event->hw.flags &= ~PERF_X86_EVENT_COMMITTED; | |
1179 | ||
90151c35 SE |
1180 | /* |
1181 | * If we're called during a txn, we don't need to do anything. | |
1182 | * The events never got scheduled and ->cancel_txn will truncate | |
1183 | * the event_list. | |
c347a2f1 PZ |
1184 | * |
1185 | * XXX assumes any ->del() called during a TXN will only be on | |
1186 | * an event added during that same TXN. | |
90151c35 | 1187 | */ |
8d2cacbb | 1188 | if (cpuc->group_flag & PERF_EVENT_TXN) |
90151c35 SE |
1189 | return; |
1190 | ||
c347a2f1 PZ |
1191 | /* |
1192 | * Not a TXN, therefore cleanup properly. | |
1193 | */ | |
a4eaf7f1 | 1194 | x86_pmu_stop(event, PERF_EF_UPDATE); |
194002b2 | 1195 | |
1da53e02 | 1196 | for (i = 0; i < cpuc->n_events; i++) { |
c347a2f1 PZ |
1197 | if (event == cpuc->event_list[i]) |
1198 | break; | |
1199 | } | |
1da53e02 | 1200 | |
c347a2f1 PZ |
1201 | if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */ |
1202 | return; | |
26e61e89 | 1203 | |
c347a2f1 PZ |
1204 | /* If we have a newly added event; make sure to decrease n_added. */ |
1205 | if (i >= cpuc->n_events - cpuc->n_added) | |
1206 | --cpuc->n_added; | |
1da53e02 | 1207 | |
c347a2f1 PZ |
1208 | if (x86_pmu.put_event_constraints) |
1209 | x86_pmu.put_event_constraints(cpuc, event); | |
1210 | ||
1211 | /* Delete the array entry. */ | |
1212 | while (++i < cpuc->n_events) | |
1213 | cpuc->event_list[i-1] = cpuc->event_list[i]; | |
1214 | --cpuc->n_events; | |
1da53e02 | 1215 | |
cdd6c482 | 1216 | perf_event_update_userpage(event); |
241771ef IM |
1217 | } |
1218 | ||
de0428a7 | 1219 | int x86_pmu_handle_irq(struct pt_regs *regs) |
a29aa8a7 | 1220 | { |
df1a132b | 1221 | struct perf_sample_data data; |
cdd6c482 IM |
1222 | struct cpu_hw_events *cpuc; |
1223 | struct perf_event *event; | |
11d1578f | 1224 | int idx, handled = 0; |
9029a5e3 IM |
1225 | u64 val; |
1226 | ||
cdd6c482 | 1227 | cpuc = &__get_cpu_var(cpu_hw_events); |
962bf7a6 | 1228 | |
2bce5dac DZ |
1229 | /* |
1230 | * Some chipsets need to unmask the LVTPC in a particular spot | |
1231 | * inside the nmi handler. As a result, the unmasking was pushed | |
1232 | * into all the nmi handlers. | |
1233 | * | |
1234 | * This generic handler doesn't seem to have any issues where the | |
1235 | * unmasking occurs so it was left at the top. | |
1236 | */ | |
1237 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
1238 | ||
948b1bb8 | 1239 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
63e6be6d RR |
1240 | if (!test_bit(idx, cpuc->active_mask)) { |
1241 | /* | |
1242 | * Though we deactivated the counter some cpus | |
1243 | * might still deliver spurious interrupts still | |
1244 | * in flight. Catch them: | |
1245 | */ | |
1246 | if (__test_and_clear_bit(idx, cpuc->running)) | |
1247 | handled++; | |
a29aa8a7 | 1248 | continue; |
63e6be6d | 1249 | } |
962bf7a6 | 1250 | |
cdd6c482 | 1251 | event = cpuc->events[idx]; |
a4016a79 | 1252 | |
cc2ad4ba | 1253 | val = x86_perf_event_update(event); |
948b1bb8 | 1254 | if (val & (1ULL << (x86_pmu.cntval_bits - 1))) |
48e22d56 | 1255 | continue; |
962bf7a6 | 1256 | |
9e350de3 | 1257 | /* |
cdd6c482 | 1258 | * event overflow |
9e350de3 | 1259 | */ |
4177c42a | 1260 | handled++; |
fd0d000b | 1261 | perf_sample_data_init(&data, 0, event->hw.last_period); |
9e350de3 | 1262 | |
07088edb | 1263 | if (!x86_perf_event_set_period(event)) |
e4abb5d4 PZ |
1264 | continue; |
1265 | ||
a8b0ca17 | 1266 | if (perf_event_overflow(event, &data, regs)) |
a4eaf7f1 | 1267 | x86_pmu_stop(event, 0); |
a29aa8a7 | 1268 | } |
962bf7a6 | 1269 | |
9e350de3 PZ |
1270 | if (handled) |
1271 | inc_irq_stat(apic_perf_irqs); | |
1272 | ||
a29aa8a7 RR |
1273 | return handled; |
1274 | } | |
39d81eab | 1275 | |
cdd6c482 | 1276 | void perf_events_lapic_init(void) |
241771ef | 1277 | { |
04da8a43 | 1278 | if (!x86_pmu.apic || !x86_pmu_initialized()) |
241771ef | 1279 | return; |
85cf9dba | 1280 | |
241771ef | 1281 | /* |
c323d95f | 1282 | * Always use NMI for PMU |
241771ef | 1283 | */ |
c323d95f | 1284 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
241771ef IM |
1285 | } |
1286 | ||
9326638c | 1287 | static int |
9c48f1c6 | 1288 | perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs) |
241771ef | 1289 | { |
14c63f17 DH |
1290 | u64 start_clock; |
1291 | u64 finish_clock; | |
e8a923cc | 1292 | int ret; |
14c63f17 | 1293 | |
cdd6c482 | 1294 | if (!atomic_read(&active_events)) |
9c48f1c6 | 1295 | return NMI_DONE; |
4177c42a | 1296 | |
e8a923cc | 1297 | start_clock = sched_clock(); |
14c63f17 | 1298 | ret = x86_pmu.handle_irq(regs); |
e8a923cc | 1299 | finish_clock = sched_clock(); |
14c63f17 DH |
1300 | |
1301 | perf_sample_event_took(finish_clock - start_clock); | |
1302 | ||
1303 | return ret; | |
241771ef | 1304 | } |
9326638c | 1305 | NOKPROBE_SYMBOL(perf_event_nmi_handler); |
241771ef | 1306 | |
de0428a7 KW |
1307 | struct event_constraint emptyconstraint; |
1308 | struct event_constraint unconstrained; | |
f87ad35d | 1309 | |
148f9bb8 | 1310 | static int |
3f6da390 PZ |
1311 | x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) |
1312 | { | |
1313 | unsigned int cpu = (long)hcpu; | |
7fdba1ca | 1314 | struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); |
b38b24ea | 1315 | int ret = NOTIFY_OK; |
3f6da390 PZ |
1316 | |
1317 | switch (action & ~CPU_TASKS_FROZEN) { | |
1318 | case CPU_UP_PREPARE: | |
7fdba1ca | 1319 | cpuc->kfree_on_online = NULL; |
3f6da390 | 1320 | if (x86_pmu.cpu_prepare) |
b38b24ea | 1321 | ret = x86_pmu.cpu_prepare(cpu); |
3f6da390 PZ |
1322 | break; |
1323 | ||
1324 | case CPU_STARTING: | |
0c9d42ed PZ |
1325 | if (x86_pmu.attr_rdpmc) |
1326 | set_in_cr4(X86_CR4_PCE); | |
3f6da390 PZ |
1327 | if (x86_pmu.cpu_starting) |
1328 | x86_pmu.cpu_starting(cpu); | |
1329 | break; | |
1330 | ||
7fdba1ca PZ |
1331 | case CPU_ONLINE: |
1332 | kfree(cpuc->kfree_on_online); | |
1333 | break; | |
1334 | ||
3f6da390 PZ |
1335 | case CPU_DYING: |
1336 | if (x86_pmu.cpu_dying) | |
1337 | x86_pmu.cpu_dying(cpu); | |
1338 | break; | |
1339 | ||
b38b24ea | 1340 | case CPU_UP_CANCELED: |
3f6da390 PZ |
1341 | case CPU_DEAD: |
1342 | if (x86_pmu.cpu_dead) | |
1343 | x86_pmu.cpu_dead(cpu); | |
1344 | break; | |
1345 | ||
1346 | default: | |
1347 | break; | |
1348 | } | |
1349 | ||
b38b24ea | 1350 | return ret; |
3f6da390 PZ |
1351 | } |
1352 | ||
12558038 CG |
1353 | static void __init pmu_check_apic(void) |
1354 | { | |
1355 | if (cpu_has_apic) | |
1356 | return; | |
1357 | ||
1358 | x86_pmu.apic = 0; | |
1359 | pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n"); | |
1360 | pr_info("no hardware sampling interrupt available.\n"); | |
c184c980 VW |
1361 | |
1362 | /* | |
1363 | * If we have a PMU initialized but no APIC | |
1364 | * interrupts, we cannot sample hardware | |
1365 | * events (user-space has to fall back and | |
1366 | * sample via a hrtimer based software event): | |
1367 | */ | |
1368 | pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT; | |
1369 | ||
12558038 CG |
1370 | } |
1371 | ||
641cc938 JO |
1372 | static struct attribute_group x86_pmu_format_group = { |
1373 | .name = "format", | |
1374 | .attrs = NULL, | |
1375 | }; | |
1376 | ||
8300daa2 JO |
1377 | /* |
1378 | * Remove all undefined events (x86_pmu.event_map(id) == 0) | |
1379 | * out of events_attr attributes. | |
1380 | */ | |
1381 | static void __init filter_events(struct attribute **attrs) | |
1382 | { | |
3a54aaa0 SE |
1383 | struct device_attribute *d; |
1384 | struct perf_pmu_events_attr *pmu_attr; | |
8300daa2 JO |
1385 | int i, j; |
1386 | ||
1387 | for (i = 0; attrs[i]; i++) { | |
3a54aaa0 SE |
1388 | d = (struct device_attribute *)attrs[i]; |
1389 | pmu_attr = container_of(d, struct perf_pmu_events_attr, attr); | |
1390 | /* str trumps id */ | |
1391 | if (pmu_attr->event_str) | |
1392 | continue; | |
8300daa2 JO |
1393 | if (x86_pmu.event_map(i)) |
1394 | continue; | |
1395 | ||
1396 | for (j = i; attrs[j]; j++) | |
1397 | attrs[j] = attrs[j + 1]; | |
1398 | ||
1399 | /* Check the shifted attr. */ | |
1400 | i--; | |
1401 | } | |
1402 | } | |
1403 | ||
1a6461b1 AK |
1404 | /* Merge two pointer arrays */ |
1405 | static __init struct attribute **merge_attr(struct attribute **a, struct attribute **b) | |
1406 | { | |
1407 | struct attribute **new; | |
1408 | int j, i; | |
1409 | ||
1410 | for (j = 0; a[j]; j++) | |
1411 | ; | |
1412 | for (i = 0; b[i]; i++) | |
1413 | j++; | |
1414 | j++; | |
1415 | ||
1416 | new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL); | |
1417 | if (!new) | |
1418 | return NULL; | |
1419 | ||
1420 | j = 0; | |
1421 | for (i = 0; a[i]; i++) | |
1422 | new[j++] = a[i]; | |
1423 | for (i = 0; b[i]; i++) | |
1424 | new[j++] = b[i]; | |
1425 | new[j] = NULL; | |
1426 | ||
1427 | return new; | |
1428 | } | |
1429 | ||
f20093ee | 1430 | ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, |
a4747393 JO |
1431 | char *page) |
1432 | { | |
1433 | struct perf_pmu_events_attr *pmu_attr = \ | |
1434 | container_of(attr, struct perf_pmu_events_attr, attr); | |
a4747393 | 1435 | u64 config = x86_pmu.event_map(pmu_attr->id); |
a4747393 | 1436 | |
3a54aaa0 SE |
1437 | /* string trumps id */ |
1438 | if (pmu_attr->event_str) | |
1439 | return sprintf(page, "%s", pmu_attr->event_str); | |
a4747393 | 1440 | |
3a54aaa0 SE |
1441 | return x86_pmu.events_sysfs_show(page, config); |
1442 | } | |
a4747393 JO |
1443 | |
1444 | EVENT_ATTR(cpu-cycles, CPU_CYCLES ); | |
1445 | EVENT_ATTR(instructions, INSTRUCTIONS ); | |
1446 | EVENT_ATTR(cache-references, CACHE_REFERENCES ); | |
1447 | EVENT_ATTR(cache-misses, CACHE_MISSES ); | |
1448 | EVENT_ATTR(branch-instructions, BRANCH_INSTRUCTIONS ); | |
1449 | EVENT_ATTR(branch-misses, BRANCH_MISSES ); | |
1450 | EVENT_ATTR(bus-cycles, BUS_CYCLES ); | |
1451 | EVENT_ATTR(stalled-cycles-frontend, STALLED_CYCLES_FRONTEND ); | |
1452 | EVENT_ATTR(stalled-cycles-backend, STALLED_CYCLES_BACKEND ); | |
1453 | EVENT_ATTR(ref-cycles, REF_CPU_CYCLES ); | |
1454 | ||
1455 | static struct attribute *empty_attrs; | |
1456 | ||
95d18aa2 | 1457 | static struct attribute *events_attr[] = { |
a4747393 JO |
1458 | EVENT_PTR(CPU_CYCLES), |
1459 | EVENT_PTR(INSTRUCTIONS), | |
1460 | EVENT_PTR(CACHE_REFERENCES), | |
1461 | EVENT_PTR(CACHE_MISSES), | |
1462 | EVENT_PTR(BRANCH_INSTRUCTIONS), | |
1463 | EVENT_PTR(BRANCH_MISSES), | |
1464 | EVENT_PTR(BUS_CYCLES), | |
1465 | EVENT_PTR(STALLED_CYCLES_FRONTEND), | |
1466 | EVENT_PTR(STALLED_CYCLES_BACKEND), | |
1467 | EVENT_PTR(REF_CPU_CYCLES), | |
1468 | NULL, | |
1469 | }; | |
1470 | ||
1471 | static struct attribute_group x86_pmu_events_group = { | |
1472 | .name = "events", | |
1473 | .attrs = events_attr, | |
1474 | }; | |
1475 | ||
0bf79d44 | 1476 | ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event) |
43c032fe | 1477 | { |
43c032fe JO |
1478 | u64 umask = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8; |
1479 | u64 cmask = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24; | |
1480 | bool edge = (config & ARCH_PERFMON_EVENTSEL_EDGE); | |
1481 | bool pc = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL); | |
1482 | bool any = (config & ARCH_PERFMON_EVENTSEL_ANY); | |
1483 | bool inv = (config & ARCH_PERFMON_EVENTSEL_INV); | |
1484 | ssize_t ret; | |
1485 | ||
1486 | /* | |
1487 | * We have whole page size to spend and just little data | |
1488 | * to write, so we can safely use sprintf. | |
1489 | */ | |
1490 | ret = sprintf(page, "event=0x%02llx", event); | |
1491 | ||
1492 | if (umask) | |
1493 | ret += sprintf(page + ret, ",umask=0x%02llx", umask); | |
1494 | ||
1495 | if (edge) | |
1496 | ret += sprintf(page + ret, ",edge"); | |
1497 | ||
1498 | if (pc) | |
1499 | ret += sprintf(page + ret, ",pc"); | |
1500 | ||
1501 | if (any) | |
1502 | ret += sprintf(page + ret, ",any"); | |
1503 | ||
1504 | if (inv) | |
1505 | ret += sprintf(page + ret, ",inv"); | |
1506 | ||
1507 | if (cmask) | |
1508 | ret += sprintf(page + ret, ",cmask=0x%02llx", cmask); | |
1509 | ||
1510 | ret += sprintf(page + ret, "\n"); | |
1511 | ||
1512 | return ret; | |
1513 | } | |
1514 | ||
dda99116 | 1515 | static int __init init_hw_perf_events(void) |
b56a3802 | 1516 | { |
c1d6f42f | 1517 | struct x86_pmu_quirk *quirk; |
72eae04d RR |
1518 | int err; |
1519 | ||
cdd6c482 | 1520 | pr_info("Performance Events: "); |
1123e3ad | 1521 | |
b56a3802 JSR |
1522 | switch (boot_cpu_data.x86_vendor) { |
1523 | case X86_VENDOR_INTEL: | |
72eae04d | 1524 | err = intel_pmu_init(); |
b56a3802 | 1525 | break; |
f87ad35d | 1526 | case X86_VENDOR_AMD: |
72eae04d | 1527 | err = amd_pmu_init(); |
f87ad35d | 1528 | break; |
4138960a | 1529 | default: |
8a3da6c7 | 1530 | err = -ENOTSUPP; |
b56a3802 | 1531 | } |
1123e3ad | 1532 | if (err != 0) { |
cdd6c482 | 1533 | pr_cont("no PMU driver, software events only.\n"); |
004417a6 | 1534 | return 0; |
1123e3ad | 1535 | } |
b56a3802 | 1536 | |
12558038 CG |
1537 | pmu_check_apic(); |
1538 | ||
33c6d6a7 | 1539 | /* sanity check that the hardware exists or is emulated */ |
4407204c | 1540 | if (!check_hw_exists()) |
004417a6 | 1541 | return 0; |
33c6d6a7 | 1542 | |
1123e3ad | 1543 | pr_cont("%s PMU driver.\n", x86_pmu.name); |
faa28ae0 | 1544 | |
e97df763 PZ |
1545 | x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */ |
1546 | ||
c1d6f42f PZ |
1547 | for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next) |
1548 | quirk->func(); | |
3c44780b | 1549 | |
a1eac7ac RR |
1550 | if (!x86_pmu.intel_ctrl) |
1551 | x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1; | |
241771ef | 1552 | |
cdd6c482 | 1553 | perf_events_lapic_init(); |
9c48f1c6 | 1554 | register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI"); |
1123e3ad | 1555 | |
63b14649 | 1556 | unconstrained = (struct event_constraint) |
948b1bb8 | 1557 | __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1, |
9fac2cf3 | 1558 | 0, x86_pmu.num_counters, 0, 0); |
63b14649 | 1559 | |
641cc938 | 1560 | x86_pmu_format_group.attrs = x86_pmu.format_attrs; |
0c9d42ed | 1561 | |
f20093ee SE |
1562 | if (x86_pmu.event_attrs) |
1563 | x86_pmu_events_group.attrs = x86_pmu.event_attrs; | |
1564 | ||
a4747393 JO |
1565 | if (!x86_pmu.events_sysfs_show) |
1566 | x86_pmu_events_group.attrs = &empty_attrs; | |
8300daa2 JO |
1567 | else |
1568 | filter_events(x86_pmu_events_group.attrs); | |
a4747393 | 1569 | |
1a6461b1 AK |
1570 | if (x86_pmu.cpu_events) { |
1571 | struct attribute **tmp; | |
1572 | ||
1573 | tmp = merge_attr(x86_pmu_events_group.attrs, x86_pmu.cpu_events); | |
1574 | if (!WARN_ON(!tmp)) | |
1575 | x86_pmu_events_group.attrs = tmp; | |
1576 | } | |
1577 | ||
57c0c15b | 1578 | pr_info("... version: %d\n", x86_pmu.version); |
948b1bb8 RR |
1579 | pr_info("... bit width: %d\n", x86_pmu.cntval_bits); |
1580 | pr_info("... generic registers: %d\n", x86_pmu.num_counters); | |
1581 | pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask); | |
57c0c15b | 1582 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); |
948b1bb8 | 1583 | pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed); |
d6dc0b4e | 1584 | pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl); |
3f6da390 | 1585 | |
2e80a82a | 1586 | perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); |
3f6da390 | 1587 | perf_cpu_notifier(x86_pmu_notifier); |
004417a6 PZ |
1588 | |
1589 | return 0; | |
241771ef | 1590 | } |
004417a6 | 1591 | early_initcall(init_hw_perf_events); |
621a01ea | 1592 | |
cdd6c482 | 1593 | static inline void x86_pmu_read(struct perf_event *event) |
ee06094f | 1594 | { |
cc2ad4ba | 1595 | x86_perf_event_update(event); |
ee06094f IM |
1596 | } |
1597 | ||
4d1c52b0 LM |
1598 | /* |
1599 | * Start group events scheduling transaction | |
1600 | * Set the flag to make pmu::enable() not perform the | |
1601 | * schedulability test, it will be performed at commit time | |
1602 | */ | |
51b0fe39 | 1603 | static void x86_pmu_start_txn(struct pmu *pmu) |
4d1c52b0 | 1604 | { |
33696fc0 | 1605 | perf_pmu_disable(pmu); |
0a3aee0d TH |
1606 | __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN); |
1607 | __this_cpu_write(cpu_hw_events.n_txn, 0); | |
4d1c52b0 LM |
1608 | } |
1609 | ||
1610 | /* | |
1611 | * Stop group events scheduling transaction | |
1612 | * Clear the flag and pmu::enable() will perform the | |
1613 | * schedulability test. | |
1614 | */ | |
51b0fe39 | 1615 | static void x86_pmu_cancel_txn(struct pmu *pmu) |
4d1c52b0 | 1616 | { |
0a3aee0d | 1617 | __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN); |
90151c35 | 1618 | /* |
c347a2f1 PZ |
1619 | * Truncate collected array by the number of events added in this |
1620 | * transaction. See x86_pmu_add() and x86_pmu_*_txn(). | |
90151c35 | 1621 | */ |
0a3aee0d TH |
1622 | __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn)); |
1623 | __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn)); | |
33696fc0 | 1624 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1625 | } |
1626 | ||
1627 | /* | |
1628 | * Commit group events scheduling transaction | |
1629 | * Perform the group schedulability test as a whole | |
1630 | * Return 0 if success | |
c347a2f1 PZ |
1631 | * |
1632 | * Does not cancel the transaction on failure; expects the caller to do this. | |
4d1c52b0 | 1633 | */ |
51b0fe39 | 1634 | static int x86_pmu_commit_txn(struct pmu *pmu) |
4d1c52b0 LM |
1635 | { |
1636 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1637 | int assign[X86_PMC_IDX_MAX]; | |
1638 | int n, ret; | |
1639 | ||
1640 | n = cpuc->n_events; | |
1641 | ||
1642 | if (!x86_pmu_initialized()) | |
1643 | return -EAGAIN; | |
1644 | ||
1645 | ret = x86_pmu.schedule_events(cpuc, n, assign); | |
1646 | if (ret) | |
1647 | return ret; | |
1648 | ||
1649 | /* | |
1650 | * copy new assignment, now we know it is possible | |
1651 | * will be used by hw_perf_enable() | |
1652 | */ | |
1653 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
1654 | ||
8d2cacbb | 1655 | cpuc->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 1656 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1657 | return 0; |
1658 | } | |
cd8a38d3 SE |
1659 | /* |
1660 | * a fake_cpuc is used to validate event groups. Due to | |
1661 | * the extra reg logic, we need to also allocate a fake | |
1662 | * per_core and per_cpu structure. Otherwise, group events | |
1663 | * using extra reg may conflict without the kernel being | |
1664 | * able to catch this when the last event gets added to | |
1665 | * the group. | |
1666 | */ | |
1667 | static void free_fake_cpuc(struct cpu_hw_events *cpuc) | |
1668 | { | |
1669 | kfree(cpuc->shared_regs); | |
1670 | kfree(cpuc); | |
1671 | } | |
1672 | ||
1673 | static struct cpu_hw_events *allocate_fake_cpuc(void) | |
1674 | { | |
1675 | struct cpu_hw_events *cpuc; | |
1676 | int cpu = raw_smp_processor_id(); | |
1677 | ||
1678 | cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL); | |
1679 | if (!cpuc) | |
1680 | return ERR_PTR(-ENOMEM); | |
1681 | ||
1682 | /* only needed, if we have extra_regs */ | |
1683 | if (x86_pmu.extra_regs) { | |
1684 | cpuc->shared_regs = allocate_shared_regs(cpu); | |
1685 | if (!cpuc->shared_regs) | |
1686 | goto error; | |
1687 | } | |
b430f7c4 | 1688 | cpuc->is_fake = 1; |
cd8a38d3 SE |
1689 | return cpuc; |
1690 | error: | |
1691 | free_fake_cpuc(cpuc); | |
1692 | return ERR_PTR(-ENOMEM); | |
1693 | } | |
4d1c52b0 | 1694 | |
ca037701 PZ |
1695 | /* |
1696 | * validate that we can schedule this event | |
1697 | */ | |
1698 | static int validate_event(struct perf_event *event) | |
1699 | { | |
1700 | struct cpu_hw_events *fake_cpuc; | |
1701 | struct event_constraint *c; | |
1702 | int ret = 0; | |
1703 | ||
cd8a38d3 SE |
1704 | fake_cpuc = allocate_fake_cpuc(); |
1705 | if (IS_ERR(fake_cpuc)) | |
1706 | return PTR_ERR(fake_cpuc); | |
ca037701 PZ |
1707 | |
1708 | c = x86_pmu.get_event_constraints(fake_cpuc, event); | |
1709 | ||
1710 | if (!c || !c->weight) | |
aa2bc1ad | 1711 | ret = -EINVAL; |
ca037701 PZ |
1712 | |
1713 | if (x86_pmu.put_event_constraints) | |
1714 | x86_pmu.put_event_constraints(fake_cpuc, event); | |
1715 | ||
cd8a38d3 | 1716 | free_fake_cpuc(fake_cpuc); |
ca037701 PZ |
1717 | |
1718 | return ret; | |
1719 | } | |
1720 | ||
1da53e02 SE |
1721 | /* |
1722 | * validate a single event group | |
1723 | * | |
1724 | * validation include: | |
184f412c IM |
1725 | * - check events are compatible which each other |
1726 | * - events do not compete for the same counter | |
1727 | * - number of events <= number of counters | |
1da53e02 SE |
1728 | * |
1729 | * validation ensures the group can be loaded onto the | |
1730 | * PMU if it was the only group available. | |
1731 | */ | |
fe9081cc PZ |
1732 | static int validate_group(struct perf_event *event) |
1733 | { | |
1da53e02 | 1734 | struct perf_event *leader = event->group_leader; |
502568d5 | 1735 | struct cpu_hw_events *fake_cpuc; |
aa2bc1ad | 1736 | int ret = -EINVAL, n; |
fe9081cc | 1737 | |
cd8a38d3 SE |
1738 | fake_cpuc = allocate_fake_cpuc(); |
1739 | if (IS_ERR(fake_cpuc)) | |
1740 | return PTR_ERR(fake_cpuc); | |
1da53e02 SE |
1741 | /* |
1742 | * the event is not yet connected with its | |
1743 | * siblings therefore we must first collect | |
1744 | * existing siblings, then add the new event | |
1745 | * before we can simulate the scheduling | |
1746 | */ | |
502568d5 | 1747 | n = collect_events(fake_cpuc, leader, true); |
1da53e02 | 1748 | if (n < 0) |
cd8a38d3 | 1749 | goto out; |
fe9081cc | 1750 | |
502568d5 PZ |
1751 | fake_cpuc->n_events = n; |
1752 | n = collect_events(fake_cpuc, event, false); | |
1da53e02 | 1753 | if (n < 0) |
cd8a38d3 | 1754 | goto out; |
fe9081cc | 1755 | |
502568d5 | 1756 | fake_cpuc->n_events = n; |
1da53e02 | 1757 | |
a072738e | 1758 | ret = x86_pmu.schedule_events(fake_cpuc, n, NULL); |
502568d5 | 1759 | |
502568d5 | 1760 | out: |
cd8a38d3 | 1761 | free_fake_cpuc(fake_cpuc); |
502568d5 | 1762 | return ret; |
fe9081cc PZ |
1763 | } |
1764 | ||
dda99116 | 1765 | static int x86_pmu_event_init(struct perf_event *event) |
621a01ea | 1766 | { |
51b0fe39 | 1767 | struct pmu *tmp; |
621a01ea IM |
1768 | int err; |
1769 | ||
b0a873eb PZ |
1770 | switch (event->attr.type) { |
1771 | case PERF_TYPE_RAW: | |
1772 | case PERF_TYPE_HARDWARE: | |
1773 | case PERF_TYPE_HW_CACHE: | |
1774 | break; | |
1775 | ||
1776 | default: | |
1777 | return -ENOENT; | |
1778 | } | |
1779 | ||
1780 | err = __x86_pmu_event_init(event); | |
fe9081cc | 1781 | if (!err) { |
8113070d SE |
1782 | /* |
1783 | * we temporarily connect event to its pmu | |
1784 | * such that validate_group() can classify | |
1785 | * it as an x86 event using is_x86_event() | |
1786 | */ | |
1787 | tmp = event->pmu; | |
1788 | event->pmu = &pmu; | |
1789 | ||
fe9081cc PZ |
1790 | if (event->group_leader != event) |
1791 | err = validate_group(event); | |
ca037701 PZ |
1792 | else |
1793 | err = validate_event(event); | |
8113070d SE |
1794 | |
1795 | event->pmu = tmp; | |
fe9081cc | 1796 | } |
a1792cda | 1797 | if (err) { |
cdd6c482 IM |
1798 | if (event->destroy) |
1799 | event->destroy(event); | |
a1792cda | 1800 | } |
621a01ea | 1801 | |
b0a873eb | 1802 | return err; |
621a01ea | 1803 | } |
d7d59fb3 | 1804 | |
fe4a3308 PZ |
1805 | static int x86_pmu_event_idx(struct perf_event *event) |
1806 | { | |
1807 | int idx = event->hw.idx; | |
1808 | ||
c7206205 PZ |
1809 | if (!x86_pmu.attr_rdpmc) |
1810 | return 0; | |
1811 | ||
15c7ad51 RR |
1812 | if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) { |
1813 | idx -= INTEL_PMC_IDX_FIXED; | |
fe4a3308 PZ |
1814 | idx |= 1 << 30; |
1815 | } | |
1816 | ||
1817 | return idx + 1; | |
1818 | } | |
1819 | ||
0c9d42ed PZ |
1820 | static ssize_t get_attr_rdpmc(struct device *cdev, |
1821 | struct device_attribute *attr, | |
1822 | char *buf) | |
1823 | { | |
1824 | return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc); | |
1825 | } | |
1826 | ||
1827 | static void change_rdpmc(void *info) | |
1828 | { | |
1829 | bool enable = !!(unsigned long)info; | |
1830 | ||
1831 | if (enable) | |
1832 | set_in_cr4(X86_CR4_PCE); | |
1833 | else | |
1834 | clear_in_cr4(X86_CR4_PCE); | |
1835 | } | |
1836 | ||
1837 | static ssize_t set_attr_rdpmc(struct device *cdev, | |
1838 | struct device_attribute *attr, | |
1839 | const char *buf, size_t count) | |
1840 | { | |
e2b297fc SK |
1841 | unsigned long val; |
1842 | ssize_t ret; | |
1843 | ||
1844 | ret = kstrtoul(buf, 0, &val); | |
1845 | if (ret) | |
1846 | return ret; | |
e97df763 PZ |
1847 | |
1848 | if (x86_pmu.attr_rdpmc_broken) | |
1849 | return -ENOTSUPP; | |
0c9d42ed PZ |
1850 | |
1851 | if (!!val != !!x86_pmu.attr_rdpmc) { | |
1852 | x86_pmu.attr_rdpmc = !!val; | |
0e9f2204 | 1853 | on_each_cpu(change_rdpmc, (void *)val, 1); |
0c9d42ed PZ |
1854 | } |
1855 | ||
1856 | return count; | |
1857 | } | |
1858 | ||
1859 | static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc); | |
1860 | ||
1861 | static struct attribute *x86_pmu_attrs[] = { | |
1862 | &dev_attr_rdpmc.attr, | |
1863 | NULL, | |
1864 | }; | |
1865 | ||
1866 | static struct attribute_group x86_pmu_attr_group = { | |
1867 | .attrs = x86_pmu_attrs, | |
1868 | }; | |
1869 | ||
1870 | static const struct attribute_group *x86_pmu_attr_groups[] = { | |
1871 | &x86_pmu_attr_group, | |
641cc938 | 1872 | &x86_pmu_format_group, |
a4747393 | 1873 | &x86_pmu_events_group, |
0c9d42ed PZ |
1874 | NULL, |
1875 | }; | |
1876 | ||
d010b332 SE |
1877 | static void x86_pmu_flush_branch_stack(void) |
1878 | { | |
1879 | if (x86_pmu.flush_branch_stack) | |
1880 | x86_pmu.flush_branch_stack(); | |
1881 | } | |
1882 | ||
c93dc84c PZ |
1883 | void perf_check_microcode(void) |
1884 | { | |
1885 | if (x86_pmu.check_microcode) | |
1886 | x86_pmu.check_microcode(); | |
1887 | } | |
1888 | EXPORT_SYMBOL_GPL(perf_check_microcode); | |
1889 | ||
b0a873eb | 1890 | static struct pmu pmu = { |
d010b332 SE |
1891 | .pmu_enable = x86_pmu_enable, |
1892 | .pmu_disable = x86_pmu_disable, | |
a4eaf7f1 | 1893 | |
c93dc84c | 1894 | .attr_groups = x86_pmu_attr_groups, |
0c9d42ed | 1895 | |
c93dc84c | 1896 | .event_init = x86_pmu_event_init, |
a4eaf7f1 | 1897 | |
d010b332 SE |
1898 | .add = x86_pmu_add, |
1899 | .del = x86_pmu_del, | |
1900 | .start = x86_pmu_start, | |
1901 | .stop = x86_pmu_stop, | |
1902 | .read = x86_pmu_read, | |
a4eaf7f1 | 1903 | |
c93dc84c PZ |
1904 | .start_txn = x86_pmu_start_txn, |
1905 | .cancel_txn = x86_pmu_cancel_txn, | |
1906 | .commit_txn = x86_pmu_commit_txn, | |
fe4a3308 | 1907 | |
c93dc84c | 1908 | .event_idx = x86_pmu_event_idx, |
d010b332 | 1909 | .flush_branch_stack = x86_pmu_flush_branch_stack, |
b0a873eb PZ |
1910 | }; |
1911 | ||
c7206205 | 1912 | void arch_perf_update_userpage(struct perf_event_mmap_page *userpg, u64 now) |
e3f3541c | 1913 | { |
20d1c86a PZ |
1914 | struct cyc2ns_data *data; |
1915 | ||
fa731587 PZ |
1916 | userpg->cap_user_time = 0; |
1917 | userpg->cap_user_time_zero = 0; | |
1918 | userpg->cap_user_rdpmc = x86_pmu.attr_rdpmc; | |
c7206205 PZ |
1919 | userpg->pmc_width = x86_pmu.cntval_bits; |
1920 | ||
35af99e6 | 1921 | if (!sched_clock_stable()) |
e3f3541c PZ |
1922 | return; |
1923 | ||
20d1c86a PZ |
1924 | data = cyc2ns_read_begin(); |
1925 | ||
fa731587 | 1926 | userpg->cap_user_time = 1; |
20d1c86a PZ |
1927 | userpg->time_mult = data->cyc2ns_mul; |
1928 | userpg->time_shift = data->cyc2ns_shift; | |
1929 | userpg->time_offset = data->cyc2ns_offset - now; | |
c73deb6a | 1930 | |
d8b11a0c | 1931 | userpg->cap_user_time_zero = 1; |
20d1c86a PZ |
1932 | userpg->time_zero = data->cyc2ns_offset; |
1933 | ||
1934 | cyc2ns_read_end(data); | |
e3f3541c PZ |
1935 | } |
1936 | ||
d7d59fb3 PZ |
1937 | /* |
1938 | * callchain support | |
1939 | */ | |
1940 | ||
d7d59fb3 PZ |
1941 | static int backtrace_stack(void *data, char *name) |
1942 | { | |
038e836e | 1943 | return 0; |
d7d59fb3 PZ |
1944 | } |
1945 | ||
1946 | static void backtrace_address(void *data, unsigned long addr, int reliable) | |
1947 | { | |
1948 | struct perf_callchain_entry *entry = data; | |
1949 | ||
70791ce9 | 1950 | perf_callchain_store(entry, addr); |
d7d59fb3 PZ |
1951 | } |
1952 | ||
1953 | static const struct stacktrace_ops backtrace_ops = { | |
d7d59fb3 PZ |
1954 | .stack = backtrace_stack, |
1955 | .address = backtrace_address, | |
06d65bda | 1956 | .walk_stack = print_context_stack_bp, |
d7d59fb3 PZ |
1957 | }; |
1958 | ||
56962b44 FW |
1959 | void |
1960 | perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 | 1961 | { |
927c7a9e FW |
1962 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
1963 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 1964 | return; |
927c7a9e FW |
1965 | } |
1966 | ||
70791ce9 | 1967 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 1968 | |
e8e999cf | 1969 | dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry); |
d7d59fb3 PZ |
1970 | } |
1971 | ||
bc6ca7b3 AS |
1972 | static inline int |
1973 | valid_user_frame(const void __user *fp, unsigned long size) | |
1974 | { | |
1975 | return (__range_not_ok(fp, size, TASK_SIZE) == 0); | |
1976 | } | |
1977 | ||
d07bdfd3 PZ |
1978 | static unsigned long get_segment_base(unsigned int segment) |
1979 | { | |
1980 | struct desc_struct *desc; | |
1981 | int idx = segment >> 3; | |
1982 | ||
1983 | if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) { | |
1984 | if (idx > LDT_ENTRIES) | |
1985 | return 0; | |
1986 | ||
1987 | if (idx > current->active_mm->context.size) | |
1988 | return 0; | |
1989 | ||
1990 | desc = current->active_mm->context.ldt; | |
1991 | } else { | |
1992 | if (idx > GDT_ENTRIES) | |
1993 | return 0; | |
1994 | ||
1995 | desc = __this_cpu_ptr(&gdt_page.gdt[0]); | |
1996 | } | |
1997 | ||
1998 | return get_desc_base(desc + idx); | |
1999 | } | |
2000 | ||
257ef9d2 | 2001 | #ifdef CONFIG_COMPAT |
d1a797f3 PA |
2002 | |
2003 | #include <asm/compat.h> | |
2004 | ||
257ef9d2 TE |
2005 | static inline int |
2006 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
74193ef0 | 2007 | { |
257ef9d2 | 2008 | /* 32-bit process in 64-bit kernel. */ |
d07bdfd3 | 2009 | unsigned long ss_base, cs_base; |
257ef9d2 TE |
2010 | struct stack_frame_ia32 frame; |
2011 | const void __user *fp; | |
74193ef0 | 2012 | |
257ef9d2 TE |
2013 | if (!test_thread_flag(TIF_IA32)) |
2014 | return 0; | |
2015 | ||
d07bdfd3 PZ |
2016 | cs_base = get_segment_base(regs->cs); |
2017 | ss_base = get_segment_base(regs->ss); | |
2018 | ||
2019 | fp = compat_ptr(ss_base + regs->bp); | |
257ef9d2 TE |
2020 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
2021 | unsigned long bytes; | |
2022 | frame.next_frame = 0; | |
2023 | frame.return_address = 0; | |
2024 | ||
2025 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); | |
0a196848 | 2026 | if (bytes != 0) |
257ef9d2 | 2027 | break; |
74193ef0 | 2028 | |
bc6ca7b3 AS |
2029 | if (!valid_user_frame(fp, sizeof(frame))) |
2030 | break; | |
2031 | ||
d07bdfd3 PZ |
2032 | perf_callchain_store(entry, cs_base + frame.return_address); |
2033 | fp = compat_ptr(ss_base + frame.next_frame); | |
257ef9d2 TE |
2034 | } |
2035 | return 1; | |
d7d59fb3 | 2036 | } |
257ef9d2 TE |
2037 | #else |
2038 | static inline int | |
2039 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
2040 | { | |
2041 | return 0; | |
2042 | } | |
2043 | #endif | |
d7d59fb3 | 2044 | |
56962b44 FW |
2045 | void |
2046 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 PZ |
2047 | { |
2048 | struct stack_frame frame; | |
2049 | const void __user *fp; | |
2050 | ||
927c7a9e FW |
2051 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
2052 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 2053 | return; |
927c7a9e | 2054 | } |
5a6cec3a | 2055 | |
d07bdfd3 PZ |
2056 | /* |
2057 | * We don't know what to do with VM86 stacks.. ignore them for now. | |
2058 | */ | |
2059 | if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM)) | |
2060 | return; | |
2061 | ||
74193ef0 | 2062 | fp = (void __user *)regs->bp; |
d7d59fb3 | 2063 | |
70791ce9 | 2064 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 2065 | |
20afc60f AV |
2066 | if (!current->mm) |
2067 | return; | |
2068 | ||
257ef9d2 TE |
2069 | if (perf_callchain_user32(regs, entry)) |
2070 | return; | |
2071 | ||
f9188e02 | 2072 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
257ef9d2 | 2073 | unsigned long bytes; |
038e836e | 2074 | frame.next_frame = NULL; |
d7d59fb3 PZ |
2075 | frame.return_address = 0; |
2076 | ||
257ef9d2 | 2077 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); |
0a196848 | 2078 | if (bytes != 0) |
d7d59fb3 PZ |
2079 | break; |
2080 | ||
bc6ca7b3 AS |
2081 | if (!valid_user_frame(fp, sizeof(frame))) |
2082 | break; | |
2083 | ||
70791ce9 | 2084 | perf_callchain_store(entry, frame.return_address); |
038e836e | 2085 | fp = frame.next_frame; |
d7d59fb3 PZ |
2086 | } |
2087 | } | |
2088 | ||
d07bdfd3 PZ |
2089 | /* |
2090 | * Deal with code segment offsets for the various execution modes: | |
2091 | * | |
2092 | * VM86 - the good olde 16 bit days, where the linear address is | |
2093 | * 20 bits and we use regs->ip + 0x10 * regs->cs. | |
2094 | * | |
2095 | * IA32 - Where we need to look at GDT/LDT segment descriptor tables | |
2096 | * to figure out what the 32bit base address is. | |
2097 | * | |
2098 | * X32 - has TIF_X32 set, but is running in x86_64 | |
2099 | * | |
2100 | * X86_64 - CS,DS,SS,ES are all zero based. | |
2101 | */ | |
2102 | static unsigned long code_segment_base(struct pt_regs *regs) | |
39447b38 | 2103 | { |
d07bdfd3 PZ |
2104 | /* |
2105 | * If we are in VM86 mode, add the segment offset to convert to a | |
2106 | * linear address. | |
2107 | */ | |
2108 | if (regs->flags & X86_VM_MASK) | |
2109 | return 0x10 * regs->cs; | |
2110 | ||
2111 | /* | |
2112 | * For IA32 we look at the GDT/LDT segment base to convert the | |
2113 | * effective IP to a linear address. | |
2114 | */ | |
2115 | #ifdef CONFIG_X86_32 | |
2116 | if (user_mode(regs) && regs->cs != __USER_CS) | |
2117 | return get_segment_base(regs->cs); | |
2118 | #else | |
2119 | if (test_thread_flag(TIF_IA32)) { | |
2120 | if (user_mode(regs) && regs->cs != __USER32_CS) | |
2121 | return get_segment_base(regs->cs); | |
2122 | } | |
2123 | #endif | |
2124 | return 0; | |
2125 | } | |
dcf46b94 | 2126 | |
d07bdfd3 PZ |
2127 | unsigned long perf_instruction_pointer(struct pt_regs *regs) |
2128 | { | |
39447b38 | 2129 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) |
d07bdfd3 | 2130 | return perf_guest_cbs->get_guest_ip(); |
dcf46b94 | 2131 | |
d07bdfd3 | 2132 | return regs->ip + code_segment_base(regs); |
39447b38 ZY |
2133 | } |
2134 | ||
2135 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
2136 | { | |
2137 | int misc = 0; | |
dcf46b94 | 2138 | |
39447b38 | 2139 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
dcf46b94 ZY |
2140 | if (perf_guest_cbs->is_user_mode()) |
2141 | misc |= PERF_RECORD_MISC_GUEST_USER; | |
2142 | else | |
2143 | misc |= PERF_RECORD_MISC_GUEST_KERNEL; | |
2144 | } else { | |
d07bdfd3 | 2145 | if (user_mode(regs)) |
dcf46b94 ZY |
2146 | misc |= PERF_RECORD_MISC_USER; |
2147 | else | |
2148 | misc |= PERF_RECORD_MISC_KERNEL; | |
2149 | } | |
2150 | ||
39447b38 | 2151 | if (regs->flags & PERF_EFLAGS_EXACT) |
ab608344 | 2152 | misc |= PERF_RECORD_MISC_EXACT_IP; |
39447b38 ZY |
2153 | |
2154 | return misc; | |
2155 | } | |
b3d9468a GN |
2156 | |
2157 | void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap) | |
2158 | { | |
2159 | cap->version = x86_pmu.version; | |
2160 | cap->num_counters_gp = x86_pmu.num_counters; | |
2161 | cap->num_counters_fixed = x86_pmu.num_counters_fixed; | |
2162 | cap->bit_width_gp = x86_pmu.cntval_bits; | |
2163 | cap->bit_width_fixed = x86_pmu.cntval_bits; | |
2164 | cap->events_mask = (unsigned int)x86_pmu.events_maskl; | |
2165 | cap->events_mask_len = x86_pmu.events_mask_len; | |
2166 | } | |
2167 | EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability); |