Commit | Line | Data |
---|---|---|
241771ef | 1 | /* |
cdd6c482 | 2 | * Performance events x86 architecture code |
241771ef | 3 | * |
98144511 IM |
4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> | |
30dd568c | 9 | * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> |
1da53e02 | 10 | * Copyright (C) 2009 Google, Inc., Stephane Eranian |
241771ef IM |
11 | * |
12 | * For licencing details see kernel-base/COPYING | |
13 | */ | |
14 | ||
cdd6c482 | 15 | #include <linux/perf_event.h> |
241771ef IM |
16 | #include <linux/capability.h> |
17 | #include <linux/notifier.h> | |
18 | #include <linux/hardirq.h> | |
19 | #include <linux/kprobes.h> | |
4ac13294 | 20 | #include <linux/module.h> |
241771ef IM |
21 | #include <linux/kdebug.h> |
22 | #include <linux/sched.h> | |
d7d59fb3 | 23 | #include <linux/uaccess.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
74193ef0 | 25 | #include <linux/highmem.h> |
30dd568c | 26 | #include <linux/cpu.h> |
272d30be | 27 | #include <linux/bitops.h> |
241771ef | 28 | |
241771ef | 29 | #include <asm/apic.h> |
d7d59fb3 | 30 | #include <asm/stacktrace.h> |
4e935e47 | 31 | #include <asm/nmi.h> |
257ef9d2 | 32 | #include <asm/compat.h> |
241771ef | 33 | |
7645a24c PZ |
34 | #if 0 |
35 | #undef wrmsrl | |
36 | #define wrmsrl(msr, val) \ | |
37 | do { \ | |
38 | trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\ | |
39 | (unsigned long)(val)); \ | |
40 | native_write_msr((msr), (u32)((u64)(val)), \ | |
41 | (u32)((u64)(val) >> 32)); \ | |
42 | } while (0) | |
43 | #endif | |
44 | ||
ef21f683 PZ |
45 | /* |
46 | * best effort, GUP based copy_from_user() that assumes IRQ or NMI context | |
47 | */ | |
48 | static unsigned long | |
49 | copy_from_user_nmi(void *to, const void __user *from, unsigned long n) | |
50 | { | |
51 | unsigned long offset, addr = (unsigned long)from; | |
52 | int type = in_nmi() ? KM_NMI : KM_IRQ0; | |
53 | unsigned long size, len = 0; | |
54 | struct page *page; | |
55 | void *map; | |
56 | int ret; | |
57 | ||
58 | do { | |
59 | ret = __get_user_pages_fast(addr, 1, 0, &page); | |
60 | if (!ret) | |
61 | break; | |
62 | ||
63 | offset = addr & (PAGE_SIZE - 1); | |
64 | size = min(PAGE_SIZE - offset, n - len); | |
65 | ||
66 | map = kmap_atomic(page, type); | |
67 | memcpy(to, map+offset, size); | |
68 | kunmap_atomic(map, type); | |
69 | put_page(page); | |
70 | ||
71 | len += size; | |
72 | to += size; | |
73 | addr += size; | |
74 | ||
75 | } while (len < n); | |
76 | ||
77 | return len; | |
78 | } | |
79 | ||
1da53e02 | 80 | struct event_constraint { |
c91e0f5d PZ |
81 | union { |
82 | unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
b622d644 | 83 | u64 idxmsk64; |
c91e0f5d | 84 | }; |
b622d644 PZ |
85 | u64 code; |
86 | u64 cmask; | |
272d30be | 87 | int weight; |
1da53e02 SE |
88 | }; |
89 | ||
38331f62 SE |
90 | struct amd_nb { |
91 | int nb_id; /* NorthBridge id */ | |
92 | int refcnt; /* reference count */ | |
93 | struct perf_event *owners[X86_PMC_IDX_MAX]; | |
94 | struct event_constraint event_constraints[X86_PMC_IDX_MAX]; | |
95 | }; | |
96 | ||
caff2bef PZ |
97 | #define MAX_LBR_ENTRIES 16 |
98 | ||
cdd6c482 | 99 | struct cpu_hw_events { |
ca037701 PZ |
100 | /* |
101 | * Generic x86 PMC bits | |
102 | */ | |
1da53e02 | 103 | struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */ |
43f6201a | 104 | unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
b0f3f28e | 105 | int enabled; |
241771ef | 106 | |
1da53e02 SE |
107 | int n_events; |
108 | int n_added; | |
90151c35 | 109 | int n_txn; |
1da53e02 | 110 | int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */ |
447a194b | 111 | u64 tags[X86_PMC_IDX_MAX]; |
1da53e02 | 112 | struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */ |
ca037701 | 113 | |
4d1c52b0 LM |
114 | unsigned int group_flag; |
115 | ||
ca037701 PZ |
116 | /* |
117 | * Intel DebugStore bits | |
118 | */ | |
119 | struct debug_store *ds; | |
120 | u64 pebs_enabled; | |
121 | ||
caff2bef PZ |
122 | /* |
123 | * Intel LBR bits | |
124 | */ | |
125 | int lbr_users; | |
126 | void *lbr_context; | |
127 | struct perf_branch_stack lbr_stack; | |
128 | struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES]; | |
129 | ||
ca037701 PZ |
130 | /* |
131 | * AMD specific bits | |
132 | */ | |
38331f62 | 133 | struct amd_nb *amd_nb; |
b690081d SE |
134 | }; |
135 | ||
fce877e3 | 136 | #define __EVENT_CONSTRAINT(c, n, m, w) {\ |
b622d644 | 137 | { .idxmsk64 = (n) }, \ |
c91e0f5d PZ |
138 | .code = (c), \ |
139 | .cmask = (m), \ | |
fce877e3 | 140 | .weight = (w), \ |
c91e0f5d | 141 | } |
b690081d | 142 | |
fce877e3 PZ |
143 | #define EVENT_CONSTRAINT(c, n, m) \ |
144 | __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n)) | |
145 | ||
ca037701 PZ |
146 | /* |
147 | * Constraint on the Event code. | |
148 | */ | |
ed8777fc | 149 | #define INTEL_EVENT_CONSTRAINT(c, n) \ |
a098f448 | 150 | EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT) |
8433be11 | 151 | |
ca037701 PZ |
152 | /* |
153 | * Constraint on the Event code + UMask + fixed-mask | |
a098f448 RR |
154 | * |
155 | * filter mask to validate fixed counter events. | |
156 | * the following filters disqualify for fixed counters: | |
157 | * - inv | |
158 | * - edge | |
159 | * - cnt-mask | |
160 | * The other filters are supported by fixed counters. | |
161 | * The any-thread option is supported starting with v3. | |
ca037701 | 162 | */ |
ed8777fc | 163 | #define FIXED_EVENT_CONSTRAINT(c, n) \ |
a098f448 | 164 | EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK) |
8433be11 | 165 | |
ca037701 PZ |
166 | /* |
167 | * Constraint on the Event code + UMask | |
168 | */ | |
169 | #define PEBS_EVENT_CONSTRAINT(c, n) \ | |
170 | EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK) | |
171 | ||
ed8777fc PZ |
172 | #define EVENT_CONSTRAINT_END \ |
173 | EVENT_CONSTRAINT(0, 0, 0) | |
174 | ||
175 | #define for_each_event_constraint(e, c) \ | |
a1f2b70a | 176 | for ((e) = (c); (e)->weight; (e)++) |
b690081d | 177 | |
8db909a7 PZ |
178 | union perf_capabilities { |
179 | struct { | |
180 | u64 lbr_format : 6; | |
181 | u64 pebs_trap : 1; | |
182 | u64 pebs_arch_reg : 1; | |
183 | u64 pebs_format : 4; | |
184 | u64 smm_freeze : 1; | |
185 | }; | |
186 | u64 capabilities; | |
187 | }; | |
188 | ||
241771ef | 189 | /* |
5f4ec28f | 190 | * struct x86_pmu - generic x86 pmu |
241771ef | 191 | */ |
5f4ec28f | 192 | struct x86_pmu { |
ca037701 PZ |
193 | /* |
194 | * Generic x86 PMC bits | |
195 | */ | |
faa28ae0 RR |
196 | const char *name; |
197 | int version; | |
a3288106 | 198 | int (*handle_irq)(struct pt_regs *); |
9e35ad38 | 199 | void (*disable_all)(void); |
11164cd4 | 200 | void (*enable_all)(int added); |
aff3d91a PZ |
201 | void (*enable)(struct perf_event *); |
202 | void (*disable)(struct perf_event *); | |
b4cdc5c2 | 203 | int (*hw_config)(struct perf_event *event); |
a072738e | 204 | int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign); |
169e41eb JSR |
205 | unsigned eventsel; |
206 | unsigned perfctr; | |
b0f3f28e | 207 | u64 (*event_map)(int); |
169e41eb | 208 | int max_events; |
948b1bb8 RR |
209 | int num_counters; |
210 | int num_counters_fixed; | |
211 | int cntval_bits; | |
212 | u64 cntval_mask; | |
04da8a43 | 213 | int apic; |
c619b8ff | 214 | u64 max_period; |
63b14649 PZ |
215 | struct event_constraint * |
216 | (*get_event_constraints)(struct cpu_hw_events *cpuc, | |
217 | struct perf_event *event); | |
218 | ||
c91e0f5d PZ |
219 | void (*put_event_constraints)(struct cpu_hw_events *cpuc, |
220 | struct perf_event *event); | |
63b14649 | 221 | struct event_constraint *event_constraints; |
3c44780b | 222 | void (*quirks)(void); |
68aa00ac | 223 | int perfctr_second_write; |
3f6da390 | 224 | |
b38b24ea | 225 | int (*cpu_prepare)(int cpu); |
3f6da390 PZ |
226 | void (*cpu_starting)(int cpu); |
227 | void (*cpu_dying)(int cpu); | |
228 | void (*cpu_dead)(int cpu); | |
ca037701 PZ |
229 | |
230 | /* | |
231 | * Intel Arch Perfmon v2+ | |
232 | */ | |
8db909a7 PZ |
233 | u64 intel_ctrl; |
234 | union perf_capabilities intel_cap; | |
ca037701 PZ |
235 | |
236 | /* | |
237 | * Intel DebugStore bits | |
238 | */ | |
239 | int bts, pebs; | |
240 | int pebs_record_size; | |
241 | void (*drain_pebs)(struct pt_regs *regs); | |
242 | struct event_constraint *pebs_constraints; | |
caff2bef PZ |
243 | |
244 | /* | |
245 | * Intel LBR | |
246 | */ | |
247 | unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */ | |
248 | int lbr_nr; /* hardware stack size */ | |
b56a3802 JSR |
249 | }; |
250 | ||
4a06bd85 | 251 | static struct x86_pmu x86_pmu __read_mostly; |
b56a3802 | 252 | |
cdd6c482 | 253 | static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { |
b0f3f28e PZ |
254 | .enabled = 1, |
255 | }; | |
241771ef | 256 | |
07088edb | 257 | static int x86_perf_event_set_period(struct perf_event *event); |
b690081d | 258 | |
8326f44d | 259 | /* |
dfc65094 | 260 | * Generalized hw caching related hw_event table, filled |
8326f44d | 261 | * in on a per model basis. A value of 0 means |
dfc65094 IM |
262 | * 'not supported', -1 means 'hw_event makes no sense on |
263 | * this CPU', any other value means the raw hw_event | |
8326f44d IM |
264 | * ID. |
265 | */ | |
266 | ||
267 | #define C(x) PERF_COUNT_HW_CACHE_##x | |
268 | ||
269 | static u64 __read_mostly hw_cache_event_ids | |
270 | [PERF_COUNT_HW_CACHE_MAX] | |
271 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
272 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
273 | ||
ee06094f | 274 | /* |
cdd6c482 IM |
275 | * Propagate event elapsed time into the generic event. |
276 | * Can only be executed on the CPU where the event is active. | |
ee06094f IM |
277 | * Returns the delta events processed. |
278 | */ | |
4b7bfd0d | 279 | static u64 |
cc2ad4ba | 280 | x86_perf_event_update(struct perf_event *event) |
ee06094f | 281 | { |
cc2ad4ba | 282 | struct hw_perf_event *hwc = &event->hw; |
948b1bb8 | 283 | int shift = 64 - x86_pmu.cntval_bits; |
ec3232bd | 284 | u64 prev_raw_count, new_raw_count; |
cc2ad4ba | 285 | int idx = hwc->idx; |
ec3232bd | 286 | s64 delta; |
ee06094f | 287 | |
30dd568c MM |
288 | if (idx == X86_PMC_IDX_FIXED_BTS) |
289 | return 0; | |
290 | ||
ee06094f | 291 | /* |
cdd6c482 | 292 | * Careful: an NMI might modify the previous event value. |
ee06094f IM |
293 | * |
294 | * Our tactic to handle this is to first atomically read and | |
295 | * exchange a new raw count - then add that new-prev delta | |
cdd6c482 | 296 | * count to the generic event atomically: |
ee06094f IM |
297 | */ |
298 | again: | |
e7850595 | 299 | prev_raw_count = local64_read(&hwc->prev_count); |
cdd6c482 | 300 | rdmsrl(hwc->event_base + idx, new_raw_count); |
ee06094f | 301 | |
e7850595 | 302 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
ee06094f IM |
303 | new_raw_count) != prev_raw_count) |
304 | goto again; | |
305 | ||
306 | /* | |
307 | * Now we have the new raw value and have updated the prev | |
308 | * timestamp already. We can now calculate the elapsed delta | |
cdd6c482 | 309 | * (event-)time and add that to the generic event. |
ee06094f IM |
310 | * |
311 | * Careful, not all hw sign-extends above the physical width | |
ec3232bd | 312 | * of the count. |
ee06094f | 313 | */ |
ec3232bd PZ |
314 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
315 | delta >>= shift; | |
ee06094f | 316 | |
e7850595 PZ |
317 | local64_add(delta, &event->count); |
318 | local64_sub(delta, &hwc->period_left); | |
4b7bfd0d RR |
319 | |
320 | return new_raw_count; | |
ee06094f IM |
321 | } |
322 | ||
cdd6c482 | 323 | static atomic_t active_events; |
4e935e47 PZ |
324 | static DEFINE_MUTEX(pmc_reserve_mutex); |
325 | ||
b27ea29c RR |
326 | #ifdef CONFIG_X86_LOCAL_APIC |
327 | ||
4e935e47 PZ |
328 | static bool reserve_pmc_hardware(void) |
329 | { | |
330 | int i; | |
331 | ||
332 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
333 | disable_lapic_nmi_watchdog(); | |
334 | ||
948b1bb8 | 335 | for (i = 0; i < x86_pmu.num_counters; i++) { |
4a06bd85 | 336 | if (!reserve_perfctr_nmi(x86_pmu.perfctr + i)) |
4e935e47 PZ |
337 | goto perfctr_fail; |
338 | } | |
339 | ||
948b1bb8 | 340 | for (i = 0; i < x86_pmu.num_counters; i++) { |
4a06bd85 | 341 | if (!reserve_evntsel_nmi(x86_pmu.eventsel + i)) |
4e935e47 PZ |
342 | goto eventsel_fail; |
343 | } | |
344 | ||
345 | return true; | |
346 | ||
347 | eventsel_fail: | |
348 | for (i--; i >= 0; i--) | |
4a06bd85 | 349 | release_evntsel_nmi(x86_pmu.eventsel + i); |
4e935e47 | 350 | |
948b1bb8 | 351 | i = x86_pmu.num_counters; |
4e935e47 PZ |
352 | |
353 | perfctr_fail: | |
354 | for (i--; i >= 0; i--) | |
4a06bd85 | 355 | release_perfctr_nmi(x86_pmu.perfctr + i); |
4e935e47 PZ |
356 | |
357 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
358 | enable_lapic_nmi_watchdog(); | |
359 | ||
360 | return false; | |
361 | } | |
362 | ||
363 | static void release_pmc_hardware(void) | |
364 | { | |
365 | int i; | |
366 | ||
948b1bb8 | 367 | for (i = 0; i < x86_pmu.num_counters; i++) { |
4a06bd85 RR |
368 | release_perfctr_nmi(x86_pmu.perfctr + i); |
369 | release_evntsel_nmi(x86_pmu.eventsel + i); | |
4e935e47 PZ |
370 | } |
371 | ||
372 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
373 | enable_lapic_nmi_watchdog(); | |
374 | } | |
375 | ||
b27ea29c RR |
376 | #else |
377 | ||
378 | static bool reserve_pmc_hardware(void) { return true; } | |
379 | static void release_pmc_hardware(void) {} | |
380 | ||
381 | #endif | |
382 | ||
ca037701 PZ |
383 | static int reserve_ds_buffers(void); |
384 | static void release_ds_buffers(void); | |
30dd568c | 385 | |
cdd6c482 | 386 | static void hw_perf_event_destroy(struct perf_event *event) |
4e935e47 | 387 | { |
cdd6c482 | 388 | if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) { |
4e935e47 | 389 | release_pmc_hardware(); |
ca037701 | 390 | release_ds_buffers(); |
4e935e47 PZ |
391 | mutex_unlock(&pmc_reserve_mutex); |
392 | } | |
393 | } | |
394 | ||
85cf9dba RR |
395 | static inline int x86_pmu_initialized(void) |
396 | { | |
397 | return x86_pmu.handle_irq != NULL; | |
398 | } | |
399 | ||
8326f44d | 400 | static inline int |
cdd6c482 | 401 | set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr) |
8326f44d IM |
402 | { |
403 | unsigned int cache_type, cache_op, cache_result; | |
404 | u64 config, val; | |
405 | ||
406 | config = attr->config; | |
407 | ||
408 | cache_type = (config >> 0) & 0xff; | |
409 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
410 | return -EINVAL; | |
411 | ||
412 | cache_op = (config >> 8) & 0xff; | |
413 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
414 | return -EINVAL; | |
415 | ||
416 | cache_result = (config >> 16) & 0xff; | |
417 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
418 | return -EINVAL; | |
419 | ||
420 | val = hw_cache_event_ids[cache_type][cache_op][cache_result]; | |
421 | ||
422 | if (val == 0) | |
423 | return -ENOENT; | |
424 | ||
425 | if (val == -1) | |
426 | return -EINVAL; | |
427 | ||
428 | hwc->config |= val; | |
429 | ||
430 | return 0; | |
431 | } | |
432 | ||
c1726f34 RR |
433 | static int x86_setup_perfctr(struct perf_event *event) |
434 | { | |
435 | struct perf_event_attr *attr = &event->attr; | |
436 | struct hw_perf_event *hwc = &event->hw; | |
437 | u64 config; | |
438 | ||
439 | if (!hwc->sample_period) { | |
440 | hwc->sample_period = x86_pmu.max_period; | |
441 | hwc->last_period = hwc->sample_period; | |
e7850595 | 442 | local64_set(&hwc->period_left, hwc->sample_period); |
c1726f34 RR |
443 | } else { |
444 | /* | |
445 | * If we have a PMU initialized but no APIC | |
446 | * interrupts, we cannot sample hardware | |
447 | * events (user-space has to fall back and | |
448 | * sample via a hrtimer based software event): | |
449 | */ | |
450 | if (!x86_pmu.apic) | |
451 | return -EOPNOTSUPP; | |
452 | } | |
453 | ||
454 | if (attr->type == PERF_TYPE_RAW) | |
455 | return 0; | |
456 | ||
457 | if (attr->type == PERF_TYPE_HW_CACHE) | |
458 | return set_ext_hw_attr(hwc, attr); | |
459 | ||
460 | if (attr->config >= x86_pmu.max_events) | |
461 | return -EINVAL; | |
462 | ||
463 | /* | |
464 | * The generic map: | |
465 | */ | |
466 | config = x86_pmu.event_map(attr->config); | |
467 | ||
468 | if (config == 0) | |
469 | return -ENOENT; | |
470 | ||
471 | if (config == -1LL) | |
472 | return -EINVAL; | |
473 | ||
474 | /* | |
475 | * Branch tracing: | |
476 | */ | |
477 | if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) && | |
478 | (hwc->sample_period == 1)) { | |
479 | /* BTS is not supported by this architecture. */ | |
480 | if (!x86_pmu.bts) | |
481 | return -EOPNOTSUPP; | |
482 | ||
483 | /* BTS is currently only allowed for user-mode. */ | |
484 | if (!attr->exclude_kernel) | |
485 | return -EOPNOTSUPP; | |
486 | } | |
487 | ||
488 | hwc->config |= config; | |
489 | ||
490 | return 0; | |
491 | } | |
4261e0e0 | 492 | |
b4cdc5c2 | 493 | static int x86_pmu_hw_config(struct perf_event *event) |
a072738e | 494 | { |
ab608344 PZ |
495 | if (event->attr.precise_ip) { |
496 | int precise = 0; | |
497 | ||
498 | /* Support for constant skid */ | |
499 | if (x86_pmu.pebs) | |
500 | precise++; | |
501 | ||
502 | /* Support for IP fixup */ | |
503 | if (x86_pmu.lbr_nr) | |
504 | precise++; | |
505 | ||
506 | if (event->attr.precise_ip > precise) | |
507 | return -EOPNOTSUPP; | |
508 | } | |
509 | ||
a072738e CG |
510 | /* |
511 | * Generate PMC IRQs: | |
512 | * (keep 'enabled' bit clear for now) | |
513 | */ | |
b4cdc5c2 | 514 | event->hw.config = ARCH_PERFMON_EVENTSEL_INT; |
a072738e CG |
515 | |
516 | /* | |
517 | * Count user and OS events unless requested not to | |
518 | */ | |
b4cdc5c2 PZ |
519 | if (!event->attr.exclude_user) |
520 | event->hw.config |= ARCH_PERFMON_EVENTSEL_USR; | |
521 | if (!event->attr.exclude_kernel) | |
522 | event->hw.config |= ARCH_PERFMON_EVENTSEL_OS; | |
a072738e | 523 | |
b4cdc5c2 PZ |
524 | if (event->attr.type == PERF_TYPE_RAW) |
525 | event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK; | |
a072738e | 526 | |
9d0fcba6 | 527 | return x86_setup_perfctr(event); |
a098f448 RR |
528 | } |
529 | ||
241771ef | 530 | /* |
0d48696f | 531 | * Setup the hardware configuration for a given attr_type |
241771ef | 532 | */ |
b0a873eb | 533 | static int __x86_pmu_event_init(struct perf_event *event) |
241771ef | 534 | { |
4e935e47 | 535 | int err; |
241771ef | 536 | |
85cf9dba RR |
537 | if (!x86_pmu_initialized()) |
538 | return -ENODEV; | |
241771ef | 539 | |
4e935e47 | 540 | err = 0; |
cdd6c482 | 541 | if (!atomic_inc_not_zero(&active_events)) { |
4e935e47 | 542 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 | 543 | if (atomic_read(&active_events) == 0) { |
30dd568c MM |
544 | if (!reserve_pmc_hardware()) |
545 | err = -EBUSY; | |
4b24a88b | 546 | else { |
ca037701 | 547 | err = reserve_ds_buffers(); |
4b24a88b SE |
548 | if (err) |
549 | release_pmc_hardware(); | |
550 | } | |
30dd568c MM |
551 | } |
552 | if (!err) | |
cdd6c482 | 553 | atomic_inc(&active_events); |
4e935e47 PZ |
554 | mutex_unlock(&pmc_reserve_mutex); |
555 | } | |
556 | if (err) | |
557 | return err; | |
558 | ||
cdd6c482 | 559 | event->destroy = hw_perf_event_destroy; |
a1792cda | 560 | |
4261e0e0 RR |
561 | event->hw.idx = -1; |
562 | event->hw.last_cpu = -1; | |
563 | event->hw.last_tag = ~0ULL; | |
b690081d | 564 | |
9d0fcba6 | 565 | return x86_pmu.hw_config(event); |
4261e0e0 RR |
566 | } |
567 | ||
8c48e444 | 568 | static void x86_pmu_disable_all(void) |
f87ad35d | 569 | { |
cdd6c482 | 570 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
9e35ad38 PZ |
571 | int idx; |
572 | ||
948b1bb8 | 573 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
b0f3f28e PZ |
574 | u64 val; |
575 | ||
43f6201a | 576 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 577 | continue; |
8c48e444 | 578 | rdmsrl(x86_pmu.eventsel + idx, val); |
bb1165d6 | 579 | if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE)) |
4295ee62 | 580 | continue; |
bb1165d6 | 581 | val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; |
8c48e444 | 582 | wrmsrl(x86_pmu.eventsel + idx, val); |
f87ad35d | 583 | } |
f87ad35d JSR |
584 | } |
585 | ||
9e35ad38 | 586 | void hw_perf_disable(void) |
b56a3802 | 587 | { |
1da53e02 SE |
588 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
589 | ||
85cf9dba | 590 | if (!x86_pmu_initialized()) |
9e35ad38 | 591 | return; |
1da53e02 | 592 | |
1a6e21f7 PZ |
593 | if (!cpuc->enabled) |
594 | return; | |
595 | ||
596 | cpuc->n_added = 0; | |
597 | cpuc->enabled = 0; | |
598 | barrier(); | |
1da53e02 SE |
599 | |
600 | x86_pmu.disable_all(); | |
b56a3802 | 601 | } |
241771ef | 602 | |
11164cd4 | 603 | static void x86_pmu_enable_all(int added) |
f87ad35d | 604 | { |
cdd6c482 | 605 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
f87ad35d JSR |
606 | int idx; |
607 | ||
948b1bb8 | 608 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
cdd6c482 | 609 | struct perf_event *event = cpuc->events[idx]; |
4295ee62 | 610 | u64 val; |
b0f3f28e | 611 | |
43f6201a | 612 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 613 | continue; |
984b838c | 614 | |
cdd6c482 | 615 | val = event->hw.config; |
bb1165d6 | 616 | val |= ARCH_PERFMON_EVENTSEL_ENABLE; |
8c48e444 | 617 | wrmsrl(x86_pmu.eventsel + idx, val); |
f87ad35d JSR |
618 | } |
619 | } | |
620 | ||
51b0fe39 | 621 | static struct pmu pmu; |
1da53e02 SE |
622 | |
623 | static inline int is_x86_event(struct perf_event *event) | |
624 | { | |
625 | return event->pmu == &pmu; | |
626 | } | |
627 | ||
628 | static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) | |
629 | { | |
63b14649 | 630 | struct event_constraint *c, *constraints[X86_PMC_IDX_MAX]; |
1da53e02 | 631 | unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
c933c1a6 | 632 | int i, j, w, wmax, num = 0; |
1da53e02 SE |
633 | struct hw_perf_event *hwc; |
634 | ||
635 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); | |
636 | ||
637 | for (i = 0; i < n; i++) { | |
b622d644 PZ |
638 | c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]); |
639 | constraints[i] = c; | |
1da53e02 SE |
640 | } |
641 | ||
8113070d SE |
642 | /* |
643 | * fastpath, try to reuse previous register | |
644 | */ | |
c933c1a6 | 645 | for (i = 0; i < n; i++) { |
8113070d | 646 | hwc = &cpuc->event_list[i]->hw; |
81269a08 | 647 | c = constraints[i]; |
8113070d SE |
648 | |
649 | /* never assigned */ | |
650 | if (hwc->idx == -1) | |
651 | break; | |
652 | ||
653 | /* constraint still honored */ | |
63b14649 | 654 | if (!test_bit(hwc->idx, c->idxmsk)) |
8113070d SE |
655 | break; |
656 | ||
657 | /* not already used */ | |
658 | if (test_bit(hwc->idx, used_mask)) | |
659 | break; | |
660 | ||
34538ee7 | 661 | __set_bit(hwc->idx, used_mask); |
8113070d SE |
662 | if (assign) |
663 | assign[i] = hwc->idx; | |
664 | } | |
c933c1a6 | 665 | if (i == n) |
8113070d SE |
666 | goto done; |
667 | ||
668 | /* | |
669 | * begin slow path | |
670 | */ | |
671 | ||
672 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); | |
673 | ||
1da53e02 SE |
674 | /* |
675 | * weight = number of possible counters | |
676 | * | |
677 | * 1 = most constrained, only works on one counter | |
678 | * wmax = least constrained, works on any counter | |
679 | * | |
680 | * assign events to counters starting with most | |
681 | * constrained events. | |
682 | */ | |
948b1bb8 | 683 | wmax = x86_pmu.num_counters; |
1da53e02 SE |
684 | |
685 | /* | |
686 | * when fixed event counters are present, | |
687 | * wmax is incremented by 1 to account | |
688 | * for one more choice | |
689 | */ | |
948b1bb8 | 690 | if (x86_pmu.num_counters_fixed) |
1da53e02 SE |
691 | wmax++; |
692 | ||
8113070d | 693 | for (w = 1, num = n; num && w <= wmax; w++) { |
1da53e02 | 694 | /* for each event */ |
8113070d | 695 | for (i = 0; num && i < n; i++) { |
81269a08 | 696 | c = constraints[i]; |
1da53e02 SE |
697 | hwc = &cpuc->event_list[i]->hw; |
698 | ||
272d30be | 699 | if (c->weight != w) |
1da53e02 SE |
700 | continue; |
701 | ||
984b3f57 | 702 | for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) { |
1da53e02 SE |
703 | if (!test_bit(j, used_mask)) |
704 | break; | |
705 | } | |
706 | ||
707 | if (j == X86_PMC_IDX_MAX) | |
708 | break; | |
1da53e02 | 709 | |
34538ee7 | 710 | __set_bit(j, used_mask); |
8113070d | 711 | |
1da53e02 SE |
712 | if (assign) |
713 | assign[i] = j; | |
714 | num--; | |
715 | } | |
716 | } | |
8113070d | 717 | done: |
1da53e02 SE |
718 | /* |
719 | * scheduling failed or is just a simulation, | |
720 | * free resources if necessary | |
721 | */ | |
722 | if (!assign || num) { | |
723 | for (i = 0; i < n; i++) { | |
724 | if (x86_pmu.put_event_constraints) | |
725 | x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]); | |
726 | } | |
727 | } | |
728 | return num ? -ENOSPC : 0; | |
729 | } | |
730 | ||
731 | /* | |
732 | * dogrp: true if must collect siblings events (group) | |
733 | * returns total number of events and error code | |
734 | */ | |
735 | static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp) | |
736 | { | |
737 | struct perf_event *event; | |
738 | int n, max_count; | |
739 | ||
948b1bb8 | 740 | max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed; |
1da53e02 SE |
741 | |
742 | /* current number of events already accepted */ | |
743 | n = cpuc->n_events; | |
744 | ||
745 | if (is_x86_event(leader)) { | |
746 | if (n >= max_count) | |
747 | return -ENOSPC; | |
748 | cpuc->event_list[n] = leader; | |
749 | n++; | |
750 | } | |
751 | if (!dogrp) | |
752 | return n; | |
753 | ||
754 | list_for_each_entry(event, &leader->sibling_list, group_entry) { | |
755 | if (!is_x86_event(event) || | |
8113070d | 756 | event->state <= PERF_EVENT_STATE_OFF) |
1da53e02 SE |
757 | continue; |
758 | ||
759 | if (n >= max_count) | |
760 | return -ENOSPC; | |
761 | ||
762 | cpuc->event_list[n] = event; | |
763 | n++; | |
764 | } | |
765 | return n; | |
766 | } | |
767 | ||
1da53e02 | 768 | static inline void x86_assign_hw_event(struct perf_event *event, |
447a194b | 769 | struct cpu_hw_events *cpuc, int i) |
1da53e02 | 770 | { |
447a194b SE |
771 | struct hw_perf_event *hwc = &event->hw; |
772 | ||
773 | hwc->idx = cpuc->assign[i]; | |
774 | hwc->last_cpu = smp_processor_id(); | |
775 | hwc->last_tag = ++cpuc->tags[i]; | |
1da53e02 SE |
776 | |
777 | if (hwc->idx == X86_PMC_IDX_FIXED_BTS) { | |
778 | hwc->config_base = 0; | |
779 | hwc->event_base = 0; | |
780 | } else if (hwc->idx >= X86_PMC_IDX_FIXED) { | |
781 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; | |
782 | /* | |
783 | * We set it so that event_base + idx in wrmsr/rdmsr maps to | |
784 | * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2: | |
785 | */ | |
786 | hwc->event_base = | |
787 | MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED; | |
788 | } else { | |
789 | hwc->config_base = x86_pmu.eventsel; | |
790 | hwc->event_base = x86_pmu.perfctr; | |
791 | } | |
792 | } | |
793 | ||
447a194b SE |
794 | static inline int match_prev_assignment(struct hw_perf_event *hwc, |
795 | struct cpu_hw_events *cpuc, | |
796 | int i) | |
797 | { | |
798 | return hwc->idx == cpuc->assign[i] && | |
799 | hwc->last_cpu == smp_processor_id() && | |
800 | hwc->last_tag == cpuc->tags[i]; | |
801 | } | |
802 | ||
c08053e6 | 803 | static int x86_pmu_start(struct perf_event *event); |
d76a0812 | 804 | static void x86_pmu_stop(struct perf_event *event); |
2e841873 | 805 | |
9e35ad38 | 806 | void hw_perf_enable(void) |
ee06094f | 807 | { |
1da53e02 SE |
808 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
809 | struct perf_event *event; | |
810 | struct hw_perf_event *hwc; | |
11164cd4 | 811 | int i, added = cpuc->n_added; |
1da53e02 | 812 | |
85cf9dba | 813 | if (!x86_pmu_initialized()) |
2b9ff0db | 814 | return; |
1a6e21f7 PZ |
815 | |
816 | if (cpuc->enabled) | |
817 | return; | |
818 | ||
1da53e02 | 819 | if (cpuc->n_added) { |
19925ce7 | 820 | int n_running = cpuc->n_events - cpuc->n_added; |
1da53e02 SE |
821 | /* |
822 | * apply assignment obtained either from | |
823 | * hw_perf_group_sched_in() or x86_pmu_enable() | |
824 | * | |
825 | * step1: save events moving to new counters | |
826 | * step2: reprogram moved events into new counters | |
827 | */ | |
19925ce7 | 828 | for (i = 0; i < n_running; i++) { |
1da53e02 SE |
829 | event = cpuc->event_list[i]; |
830 | hwc = &event->hw; | |
831 | ||
447a194b SE |
832 | /* |
833 | * we can avoid reprogramming counter if: | |
834 | * - assigned same counter as last time | |
835 | * - running on same CPU as last time | |
836 | * - no other event has used the counter since | |
837 | */ | |
838 | if (hwc->idx == -1 || | |
839 | match_prev_assignment(hwc, cpuc, i)) | |
1da53e02 SE |
840 | continue; |
841 | ||
d76a0812 | 842 | x86_pmu_stop(event); |
1da53e02 SE |
843 | } |
844 | ||
845 | for (i = 0; i < cpuc->n_events; i++) { | |
1da53e02 SE |
846 | event = cpuc->event_list[i]; |
847 | hwc = &event->hw; | |
848 | ||
45e16a68 | 849 | if (!match_prev_assignment(hwc, cpuc, i)) |
447a194b | 850 | x86_assign_hw_event(event, cpuc, i); |
45e16a68 PZ |
851 | else if (i < n_running) |
852 | continue; | |
1da53e02 | 853 | |
c08053e6 | 854 | x86_pmu_start(event); |
1da53e02 SE |
855 | } |
856 | cpuc->n_added = 0; | |
857 | perf_events_lapic_init(); | |
858 | } | |
1a6e21f7 PZ |
859 | |
860 | cpuc->enabled = 1; | |
861 | barrier(); | |
862 | ||
11164cd4 | 863 | x86_pmu.enable_all(added); |
ee06094f | 864 | } |
ee06094f | 865 | |
31fa58af RR |
866 | static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, |
867 | u64 enable_mask) | |
b0f3f28e | 868 | { |
31fa58af | 869 | wrmsrl(hwc->config_base + hwc->idx, hwc->config | enable_mask); |
b0f3f28e PZ |
870 | } |
871 | ||
aff3d91a | 872 | static inline void x86_pmu_disable_event(struct perf_event *event) |
b0f3f28e | 873 | { |
aff3d91a | 874 | struct hw_perf_event *hwc = &event->hw; |
7645a24c PZ |
875 | |
876 | wrmsrl(hwc->config_base + hwc->idx, hwc->config); | |
b0f3f28e PZ |
877 | } |
878 | ||
245b2e70 | 879 | static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); |
241771ef | 880 | |
ee06094f IM |
881 | /* |
882 | * Set the next IRQ period, based on the hwc->period_left value. | |
cdd6c482 | 883 | * To be called with the event disabled in hw: |
ee06094f | 884 | */ |
e4abb5d4 | 885 | static int |
07088edb | 886 | x86_perf_event_set_period(struct perf_event *event) |
241771ef | 887 | { |
07088edb | 888 | struct hw_perf_event *hwc = &event->hw; |
e7850595 | 889 | s64 left = local64_read(&hwc->period_left); |
e4abb5d4 | 890 | s64 period = hwc->sample_period; |
7645a24c | 891 | int ret = 0, idx = hwc->idx; |
ee06094f | 892 | |
30dd568c MM |
893 | if (idx == X86_PMC_IDX_FIXED_BTS) |
894 | return 0; | |
895 | ||
ee06094f | 896 | /* |
af901ca1 | 897 | * If we are way outside a reasonable range then just skip forward: |
ee06094f IM |
898 | */ |
899 | if (unlikely(left <= -period)) { | |
900 | left = period; | |
e7850595 | 901 | local64_set(&hwc->period_left, left); |
9e350de3 | 902 | hwc->last_period = period; |
e4abb5d4 | 903 | ret = 1; |
ee06094f IM |
904 | } |
905 | ||
906 | if (unlikely(left <= 0)) { | |
907 | left += period; | |
e7850595 | 908 | local64_set(&hwc->period_left, left); |
9e350de3 | 909 | hwc->last_period = period; |
e4abb5d4 | 910 | ret = 1; |
ee06094f | 911 | } |
1c80f4b5 | 912 | /* |
dfc65094 | 913 | * Quirk: certain CPUs dont like it if just 1 hw_event is left: |
1c80f4b5 IM |
914 | */ |
915 | if (unlikely(left < 2)) | |
916 | left = 2; | |
241771ef | 917 | |
e4abb5d4 PZ |
918 | if (left > x86_pmu.max_period) |
919 | left = x86_pmu.max_period; | |
920 | ||
245b2e70 | 921 | per_cpu(pmc_prev_left[idx], smp_processor_id()) = left; |
ee06094f IM |
922 | |
923 | /* | |
cdd6c482 | 924 | * The hw event starts counting from this event offset, |
ee06094f IM |
925 | * mark it to be able to extra future deltas: |
926 | */ | |
e7850595 | 927 | local64_set(&hwc->prev_count, (u64)-left); |
ee06094f | 928 | |
68aa00ac CG |
929 | wrmsrl(hwc->event_base + idx, (u64)(-left) & x86_pmu.cntval_mask); |
930 | ||
931 | /* | |
932 | * Due to erratum on certan cpu we need | |
933 | * a second write to be sure the register | |
934 | * is updated properly | |
935 | */ | |
936 | if (x86_pmu.perfctr_second_write) { | |
937 | wrmsrl(hwc->event_base + idx, | |
948b1bb8 | 938 | (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac | 939 | } |
e4abb5d4 | 940 | |
cdd6c482 | 941 | perf_event_update_userpage(event); |
194002b2 | 942 | |
e4abb5d4 | 943 | return ret; |
2f18d1e8 IM |
944 | } |
945 | ||
aff3d91a | 946 | static void x86_pmu_enable_event(struct perf_event *event) |
7c90cc45 | 947 | { |
cdd6c482 | 948 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
7c90cc45 | 949 | if (cpuc->enabled) |
31fa58af RR |
950 | __x86_pmu_enable_event(&event->hw, |
951 | ARCH_PERFMON_EVENTSEL_ENABLE); | |
241771ef IM |
952 | } |
953 | ||
b690081d | 954 | /* |
1da53e02 SE |
955 | * activate a single event |
956 | * | |
957 | * The event is added to the group of enabled events | |
958 | * but only if it can be scehduled with existing events. | |
959 | * | |
960 | * Called with PMU disabled. If successful and return value 1, | |
961 | * then guaranteed to call perf_enable() and hw_perf_enable() | |
fe9081cc PZ |
962 | */ |
963 | static int x86_pmu_enable(struct perf_event *event) | |
964 | { | |
965 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1da53e02 SE |
966 | struct hw_perf_event *hwc; |
967 | int assign[X86_PMC_IDX_MAX]; | |
968 | int n, n0, ret; | |
fe9081cc | 969 | |
1da53e02 | 970 | hwc = &event->hw; |
fe9081cc | 971 | |
1da53e02 SE |
972 | n0 = cpuc->n_events; |
973 | n = collect_events(cpuc, event, false); | |
974 | if (n < 0) | |
975 | return n; | |
53b441a5 | 976 | |
4d1c52b0 LM |
977 | /* |
978 | * If group events scheduling transaction was started, | |
979 | * skip the schedulability test here, it will be peformed | |
980 | * at commit time(->commit_txn) as a whole | |
981 | */ | |
8d2cacbb | 982 | if (cpuc->group_flag & PERF_EVENT_TXN) |
4d1c52b0 LM |
983 | goto out; |
984 | ||
a072738e | 985 | ret = x86_pmu.schedule_events(cpuc, n, assign); |
1da53e02 SE |
986 | if (ret) |
987 | return ret; | |
988 | /* | |
989 | * copy new assignment, now we know it is possible | |
990 | * will be used by hw_perf_enable() | |
991 | */ | |
992 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
7e2ae347 | 993 | |
4d1c52b0 | 994 | out: |
1da53e02 | 995 | cpuc->n_events = n; |
356e1f2e | 996 | cpuc->n_added += n - n0; |
90151c35 | 997 | cpuc->n_txn += n - n0; |
95cdd2e7 IM |
998 | |
999 | return 0; | |
241771ef IM |
1000 | } |
1001 | ||
d76a0812 SE |
1002 | static int x86_pmu_start(struct perf_event *event) |
1003 | { | |
c08053e6 PZ |
1004 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
1005 | int idx = event->hw.idx; | |
1006 | ||
1007 | if (idx == -1) | |
d76a0812 SE |
1008 | return -EAGAIN; |
1009 | ||
07088edb | 1010 | x86_perf_event_set_period(event); |
c08053e6 PZ |
1011 | cpuc->events[idx] = event; |
1012 | __set_bit(idx, cpuc->active_mask); | |
aff3d91a | 1013 | x86_pmu.enable(event); |
c08053e6 | 1014 | perf_event_update_userpage(event); |
d76a0812 SE |
1015 | |
1016 | return 0; | |
1017 | } | |
1018 | ||
cdd6c482 | 1019 | static void x86_pmu_unthrottle(struct perf_event *event) |
a78ac325 | 1020 | { |
71e2d282 PZ |
1021 | int ret = x86_pmu_start(event); |
1022 | WARN_ON_ONCE(ret); | |
a78ac325 PZ |
1023 | } |
1024 | ||
cdd6c482 | 1025 | void perf_event_print_debug(void) |
241771ef | 1026 | { |
2f18d1e8 | 1027 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
ca037701 | 1028 | u64 pebs; |
cdd6c482 | 1029 | struct cpu_hw_events *cpuc; |
5bb9efe3 | 1030 | unsigned long flags; |
1e125676 IM |
1031 | int cpu, idx; |
1032 | ||
948b1bb8 | 1033 | if (!x86_pmu.num_counters) |
1e125676 | 1034 | return; |
241771ef | 1035 | |
5bb9efe3 | 1036 | local_irq_save(flags); |
241771ef IM |
1037 | |
1038 | cpu = smp_processor_id(); | |
cdd6c482 | 1039 | cpuc = &per_cpu(cpu_hw_events, cpu); |
241771ef | 1040 | |
faa28ae0 | 1041 | if (x86_pmu.version >= 2) { |
a1ef58f4 JSR |
1042 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
1043 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
1044 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
1045 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); | |
ca037701 | 1046 | rdmsrl(MSR_IA32_PEBS_ENABLE, pebs); |
a1ef58f4 JSR |
1047 | |
1048 | pr_info("\n"); | |
1049 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
1050 | pr_info("CPU#%d: status: %016llx\n", cpu, status); | |
1051 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); | |
1052 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); | |
ca037701 | 1053 | pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs); |
f87ad35d | 1054 | } |
7645a24c | 1055 | pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); |
241771ef | 1056 | |
948b1bb8 | 1057 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
4a06bd85 RR |
1058 | rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl); |
1059 | rdmsrl(x86_pmu.perfctr + idx, pmc_count); | |
241771ef | 1060 | |
245b2e70 | 1061 | prev_left = per_cpu(pmc_prev_left[idx], cpu); |
241771ef | 1062 | |
a1ef58f4 | 1063 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 1064 | cpu, idx, pmc_ctrl); |
a1ef58f4 | 1065 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 1066 | cpu, idx, pmc_count); |
a1ef58f4 | 1067 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 1068 | cpu, idx, prev_left); |
241771ef | 1069 | } |
948b1bb8 | 1070 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { |
2f18d1e8 IM |
1071 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
1072 | ||
a1ef58f4 | 1073 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
2f18d1e8 IM |
1074 | cpu, idx, pmc_count); |
1075 | } | |
5bb9efe3 | 1076 | local_irq_restore(flags); |
241771ef IM |
1077 | } |
1078 | ||
d76a0812 | 1079 | static void x86_pmu_stop(struct perf_event *event) |
241771ef | 1080 | { |
d76a0812 | 1081 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
cdd6c482 | 1082 | struct hw_perf_event *hwc = &event->hw; |
2e841873 | 1083 | int idx = hwc->idx; |
241771ef | 1084 | |
71e2d282 PZ |
1085 | if (!__test_and_clear_bit(idx, cpuc->active_mask)) |
1086 | return; | |
1087 | ||
aff3d91a | 1088 | x86_pmu.disable(event); |
241771ef | 1089 | |
ee06094f | 1090 | /* |
cdd6c482 | 1091 | * Drain the remaining delta count out of a event |
ee06094f IM |
1092 | * that we are disabling: |
1093 | */ | |
cc2ad4ba | 1094 | x86_perf_event_update(event); |
30dd568c | 1095 | |
cdd6c482 | 1096 | cpuc->events[idx] = NULL; |
2e841873 PZ |
1097 | } |
1098 | ||
1099 | static void x86_pmu_disable(struct perf_event *event) | |
1100 | { | |
1101 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1102 | int i; | |
1103 | ||
90151c35 SE |
1104 | /* |
1105 | * If we're called during a txn, we don't need to do anything. | |
1106 | * The events never got scheduled and ->cancel_txn will truncate | |
1107 | * the event_list. | |
1108 | */ | |
8d2cacbb | 1109 | if (cpuc->group_flag & PERF_EVENT_TXN) |
90151c35 SE |
1110 | return; |
1111 | ||
d76a0812 | 1112 | x86_pmu_stop(event); |
194002b2 | 1113 | |
1da53e02 SE |
1114 | for (i = 0; i < cpuc->n_events; i++) { |
1115 | if (event == cpuc->event_list[i]) { | |
1116 | ||
1117 | if (x86_pmu.put_event_constraints) | |
1118 | x86_pmu.put_event_constraints(cpuc, event); | |
1119 | ||
1120 | while (++i < cpuc->n_events) | |
1121 | cpuc->event_list[i-1] = cpuc->event_list[i]; | |
1122 | ||
1123 | --cpuc->n_events; | |
6c9687ab | 1124 | break; |
1da53e02 SE |
1125 | } |
1126 | } | |
cdd6c482 | 1127 | perf_event_update_userpage(event); |
241771ef IM |
1128 | } |
1129 | ||
8c48e444 | 1130 | static int x86_pmu_handle_irq(struct pt_regs *regs) |
a29aa8a7 | 1131 | { |
df1a132b | 1132 | struct perf_sample_data data; |
cdd6c482 IM |
1133 | struct cpu_hw_events *cpuc; |
1134 | struct perf_event *event; | |
1135 | struct hw_perf_event *hwc; | |
11d1578f | 1136 | int idx, handled = 0; |
9029a5e3 IM |
1137 | u64 val; |
1138 | ||
dc1d628a | 1139 | perf_sample_data_init(&data, 0); |
df1a132b | 1140 | |
cdd6c482 | 1141 | cpuc = &__get_cpu_var(cpu_hw_events); |
962bf7a6 | 1142 | |
948b1bb8 | 1143 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
43f6201a | 1144 | if (!test_bit(idx, cpuc->active_mask)) |
a29aa8a7 | 1145 | continue; |
962bf7a6 | 1146 | |
cdd6c482 IM |
1147 | event = cpuc->events[idx]; |
1148 | hwc = &event->hw; | |
a4016a79 | 1149 | |
cc2ad4ba | 1150 | val = x86_perf_event_update(event); |
948b1bb8 | 1151 | if (val & (1ULL << (x86_pmu.cntval_bits - 1))) |
48e22d56 | 1152 | continue; |
962bf7a6 | 1153 | |
9e350de3 | 1154 | /* |
cdd6c482 | 1155 | * event overflow |
9e350de3 | 1156 | */ |
4177c42a | 1157 | handled++; |
cdd6c482 | 1158 | data.period = event->hw.last_period; |
9e350de3 | 1159 | |
07088edb | 1160 | if (!x86_perf_event_set_period(event)) |
e4abb5d4 PZ |
1161 | continue; |
1162 | ||
cdd6c482 | 1163 | if (perf_event_overflow(event, 1, &data, regs)) |
71e2d282 | 1164 | x86_pmu_stop(event); |
a29aa8a7 | 1165 | } |
962bf7a6 | 1166 | |
9e350de3 PZ |
1167 | if (handled) |
1168 | inc_irq_stat(apic_perf_irqs); | |
1169 | ||
a29aa8a7 RR |
1170 | return handled; |
1171 | } | |
39d81eab | 1172 | |
b6276f35 PZ |
1173 | void smp_perf_pending_interrupt(struct pt_regs *regs) |
1174 | { | |
1175 | irq_enter(); | |
1176 | ack_APIC_irq(); | |
1177 | inc_irq_stat(apic_pending_irqs); | |
cdd6c482 | 1178 | perf_event_do_pending(); |
b6276f35 PZ |
1179 | irq_exit(); |
1180 | } | |
1181 | ||
cdd6c482 | 1182 | void set_perf_event_pending(void) |
b6276f35 | 1183 | { |
04da8a43 | 1184 | #ifdef CONFIG_X86_LOCAL_APIC |
7d428966 PZ |
1185 | if (!x86_pmu.apic || !x86_pmu_initialized()) |
1186 | return; | |
1187 | ||
b6276f35 | 1188 | apic->send_IPI_self(LOCAL_PENDING_VECTOR); |
04da8a43 | 1189 | #endif |
b6276f35 PZ |
1190 | } |
1191 | ||
cdd6c482 | 1192 | void perf_events_lapic_init(void) |
241771ef | 1193 | { |
04da8a43 | 1194 | if (!x86_pmu.apic || !x86_pmu_initialized()) |
241771ef | 1195 | return; |
85cf9dba | 1196 | |
241771ef | 1197 | /* |
c323d95f | 1198 | * Always use NMI for PMU |
241771ef | 1199 | */ |
c323d95f | 1200 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
241771ef IM |
1201 | } |
1202 | ||
4177c42a RR |
1203 | struct pmu_nmi_state { |
1204 | unsigned int marked; | |
1205 | int handled; | |
1206 | }; | |
1207 | ||
1208 | static DEFINE_PER_CPU(struct pmu_nmi_state, pmu_nmi); | |
1209 | ||
241771ef | 1210 | static int __kprobes |
cdd6c482 | 1211 | perf_event_nmi_handler(struct notifier_block *self, |
241771ef IM |
1212 | unsigned long cmd, void *__args) |
1213 | { | |
1214 | struct die_args *args = __args; | |
4177c42a RR |
1215 | unsigned int this_nmi; |
1216 | int handled; | |
b0f3f28e | 1217 | |
cdd6c482 | 1218 | if (!atomic_read(&active_events)) |
63a809a2 PZ |
1219 | return NOTIFY_DONE; |
1220 | ||
b0f3f28e PZ |
1221 | switch (cmd) { |
1222 | case DIE_NMI: | |
1223 | case DIE_NMI_IPI: | |
1224 | break; | |
4177c42a RR |
1225 | case DIE_NMIUNKNOWN: |
1226 | this_nmi = percpu_read(irq_stat.__nmi_count); | |
1227 | if (this_nmi != __get_cpu_var(pmu_nmi).marked) | |
1228 | /* let the kernel handle the unknown nmi */ | |
1229 | return NOTIFY_DONE; | |
1230 | /* | |
1231 | * This one is a PMU back-to-back nmi. Two events | |
1232 | * trigger 'simultaneously' raising two back-to-back | |
1233 | * NMIs. If the first NMI handles both, the latter | |
1234 | * will be empty and daze the CPU. So, we drop it to | |
1235 | * avoid false-positive 'unknown nmi' messages. | |
1236 | */ | |
1237 | return NOTIFY_STOP; | |
b0f3f28e | 1238 | default: |
241771ef | 1239 | return NOTIFY_DONE; |
b0f3f28e | 1240 | } |
241771ef | 1241 | |
241771ef | 1242 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
4177c42a RR |
1243 | |
1244 | handled = x86_pmu.handle_irq(args->regs); | |
1245 | if (!handled) | |
1246 | return NOTIFY_DONE; | |
1247 | ||
1248 | this_nmi = percpu_read(irq_stat.__nmi_count); | |
1249 | if ((handled > 1) || | |
1250 | /* the next nmi could be a back-to-back nmi */ | |
1251 | ((__get_cpu_var(pmu_nmi).marked == this_nmi) && | |
1252 | (__get_cpu_var(pmu_nmi).handled > 1))) { | |
1253 | /* | |
1254 | * We could have two subsequent back-to-back nmis: The | |
1255 | * first handles more than one counter, the 2nd | |
1256 | * handles only one counter and the 3rd handles no | |
1257 | * counter. | |
1258 | * | |
1259 | * This is the 2nd nmi because the previous was | |
1260 | * handling more than one counter. We will mark the | |
1261 | * next (3rd) and then drop it if unhandled. | |
1262 | */ | |
1263 | __get_cpu_var(pmu_nmi).marked = this_nmi + 1; | |
1264 | __get_cpu_var(pmu_nmi).handled = handled; | |
1265 | } | |
241771ef | 1266 | |
a4016a79 | 1267 | return NOTIFY_STOP; |
241771ef IM |
1268 | } |
1269 | ||
f22f54f4 PZ |
1270 | static __read_mostly struct notifier_block perf_event_nmi_notifier = { |
1271 | .notifier_call = perf_event_nmi_handler, | |
1272 | .next = NULL, | |
1273 | .priority = 1 | |
1274 | }; | |
1275 | ||
63b14649 | 1276 | static struct event_constraint unconstrained; |
38331f62 | 1277 | static struct event_constraint emptyconstraint; |
63b14649 | 1278 | |
63b14649 | 1279 | static struct event_constraint * |
f22f54f4 | 1280 | x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event) |
1da53e02 | 1281 | { |
63b14649 | 1282 | struct event_constraint *c; |
1da53e02 | 1283 | |
1da53e02 SE |
1284 | if (x86_pmu.event_constraints) { |
1285 | for_each_event_constraint(c, x86_pmu.event_constraints) { | |
63b14649 PZ |
1286 | if ((event->hw.config & c->cmask) == c->code) |
1287 | return c; | |
1da53e02 SE |
1288 | } |
1289 | } | |
63b14649 PZ |
1290 | |
1291 | return &unconstrained; | |
1da53e02 SE |
1292 | } |
1293 | ||
f22f54f4 PZ |
1294 | #include "perf_event_amd.c" |
1295 | #include "perf_event_p6.c" | |
a072738e | 1296 | #include "perf_event_p4.c" |
caff2bef | 1297 | #include "perf_event_intel_lbr.c" |
ca037701 | 1298 | #include "perf_event_intel_ds.c" |
f22f54f4 | 1299 | #include "perf_event_intel.c" |
f87ad35d | 1300 | |
3f6da390 PZ |
1301 | static int __cpuinit |
1302 | x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) | |
1303 | { | |
1304 | unsigned int cpu = (long)hcpu; | |
b38b24ea | 1305 | int ret = NOTIFY_OK; |
3f6da390 PZ |
1306 | |
1307 | switch (action & ~CPU_TASKS_FROZEN) { | |
1308 | case CPU_UP_PREPARE: | |
1309 | if (x86_pmu.cpu_prepare) | |
b38b24ea | 1310 | ret = x86_pmu.cpu_prepare(cpu); |
3f6da390 PZ |
1311 | break; |
1312 | ||
1313 | case CPU_STARTING: | |
1314 | if (x86_pmu.cpu_starting) | |
1315 | x86_pmu.cpu_starting(cpu); | |
1316 | break; | |
1317 | ||
1318 | case CPU_DYING: | |
1319 | if (x86_pmu.cpu_dying) | |
1320 | x86_pmu.cpu_dying(cpu); | |
1321 | break; | |
1322 | ||
b38b24ea | 1323 | case CPU_UP_CANCELED: |
3f6da390 PZ |
1324 | case CPU_DEAD: |
1325 | if (x86_pmu.cpu_dead) | |
1326 | x86_pmu.cpu_dead(cpu); | |
1327 | break; | |
1328 | ||
1329 | default: | |
1330 | break; | |
1331 | } | |
1332 | ||
b38b24ea | 1333 | return ret; |
3f6da390 PZ |
1334 | } |
1335 | ||
12558038 CG |
1336 | static void __init pmu_check_apic(void) |
1337 | { | |
1338 | if (cpu_has_apic) | |
1339 | return; | |
1340 | ||
1341 | x86_pmu.apic = 0; | |
1342 | pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n"); | |
1343 | pr_info("no hardware sampling interrupt available.\n"); | |
1344 | } | |
1345 | ||
cdd6c482 | 1346 | void __init init_hw_perf_events(void) |
b56a3802 | 1347 | { |
b622d644 | 1348 | struct event_constraint *c; |
72eae04d RR |
1349 | int err; |
1350 | ||
cdd6c482 | 1351 | pr_info("Performance Events: "); |
1123e3ad | 1352 | |
b56a3802 JSR |
1353 | switch (boot_cpu_data.x86_vendor) { |
1354 | case X86_VENDOR_INTEL: | |
72eae04d | 1355 | err = intel_pmu_init(); |
b56a3802 | 1356 | break; |
f87ad35d | 1357 | case X86_VENDOR_AMD: |
72eae04d | 1358 | err = amd_pmu_init(); |
f87ad35d | 1359 | break; |
4138960a RR |
1360 | default: |
1361 | return; | |
b56a3802 | 1362 | } |
1123e3ad | 1363 | if (err != 0) { |
cdd6c482 | 1364 | pr_cont("no PMU driver, software events only.\n"); |
b56a3802 | 1365 | return; |
1123e3ad | 1366 | } |
b56a3802 | 1367 | |
12558038 CG |
1368 | pmu_check_apic(); |
1369 | ||
1123e3ad | 1370 | pr_cont("%s PMU driver.\n", x86_pmu.name); |
faa28ae0 | 1371 | |
3c44780b PZ |
1372 | if (x86_pmu.quirks) |
1373 | x86_pmu.quirks(); | |
1374 | ||
948b1bb8 | 1375 | if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) { |
cdd6c482 | 1376 | WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", |
948b1bb8 RR |
1377 | x86_pmu.num_counters, X86_PMC_MAX_GENERIC); |
1378 | x86_pmu.num_counters = X86_PMC_MAX_GENERIC; | |
241771ef | 1379 | } |
948b1bb8 RR |
1380 | x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1; |
1381 | perf_max_events = x86_pmu.num_counters; | |
241771ef | 1382 | |
948b1bb8 | 1383 | if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) { |
cdd6c482 | 1384 | WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", |
948b1bb8 RR |
1385 | x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED); |
1386 | x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED; | |
703e937c | 1387 | } |
862a1a5f | 1388 | |
d6dc0b4e | 1389 | x86_pmu.intel_ctrl |= |
948b1bb8 | 1390 | ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED; |
241771ef | 1391 | |
cdd6c482 IM |
1392 | perf_events_lapic_init(); |
1393 | register_die_notifier(&perf_event_nmi_notifier); | |
1123e3ad | 1394 | |
63b14649 | 1395 | unconstrained = (struct event_constraint) |
948b1bb8 RR |
1396 | __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1, |
1397 | 0, x86_pmu.num_counters); | |
63b14649 | 1398 | |
b622d644 PZ |
1399 | if (x86_pmu.event_constraints) { |
1400 | for_each_event_constraint(c, x86_pmu.event_constraints) { | |
a098f448 | 1401 | if (c->cmask != X86_RAW_EVENT_MASK) |
b622d644 PZ |
1402 | continue; |
1403 | ||
948b1bb8 RR |
1404 | c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1; |
1405 | c->weight += x86_pmu.num_counters; | |
b622d644 PZ |
1406 | } |
1407 | } | |
1408 | ||
57c0c15b | 1409 | pr_info("... version: %d\n", x86_pmu.version); |
948b1bb8 RR |
1410 | pr_info("... bit width: %d\n", x86_pmu.cntval_bits); |
1411 | pr_info("... generic registers: %d\n", x86_pmu.num_counters); | |
1412 | pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask); | |
57c0c15b | 1413 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); |
948b1bb8 | 1414 | pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed); |
d6dc0b4e | 1415 | pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl); |
3f6da390 | 1416 | |
b0a873eb | 1417 | perf_pmu_register(&pmu); |
3f6da390 | 1418 | perf_cpu_notifier(x86_pmu_notifier); |
241771ef | 1419 | } |
621a01ea | 1420 | |
cdd6c482 | 1421 | static inline void x86_pmu_read(struct perf_event *event) |
ee06094f | 1422 | { |
cc2ad4ba | 1423 | x86_perf_event_update(event); |
ee06094f IM |
1424 | } |
1425 | ||
4d1c52b0 LM |
1426 | /* |
1427 | * Start group events scheduling transaction | |
1428 | * Set the flag to make pmu::enable() not perform the | |
1429 | * schedulability test, it will be performed at commit time | |
1430 | */ | |
51b0fe39 | 1431 | static void x86_pmu_start_txn(struct pmu *pmu) |
4d1c52b0 LM |
1432 | { |
1433 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1434 | ||
8d2cacbb | 1435 | cpuc->group_flag |= PERF_EVENT_TXN; |
90151c35 | 1436 | cpuc->n_txn = 0; |
4d1c52b0 LM |
1437 | } |
1438 | ||
1439 | /* | |
1440 | * Stop group events scheduling transaction | |
1441 | * Clear the flag and pmu::enable() will perform the | |
1442 | * schedulability test. | |
1443 | */ | |
51b0fe39 | 1444 | static void x86_pmu_cancel_txn(struct pmu *pmu) |
4d1c52b0 LM |
1445 | { |
1446 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1447 | ||
8d2cacbb | 1448 | cpuc->group_flag &= ~PERF_EVENT_TXN; |
90151c35 SE |
1449 | /* |
1450 | * Truncate the collected events. | |
1451 | */ | |
1452 | cpuc->n_added -= cpuc->n_txn; | |
1453 | cpuc->n_events -= cpuc->n_txn; | |
4d1c52b0 LM |
1454 | } |
1455 | ||
1456 | /* | |
1457 | * Commit group events scheduling transaction | |
1458 | * Perform the group schedulability test as a whole | |
1459 | * Return 0 if success | |
1460 | */ | |
51b0fe39 | 1461 | static int x86_pmu_commit_txn(struct pmu *pmu) |
4d1c52b0 LM |
1462 | { |
1463 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1464 | int assign[X86_PMC_IDX_MAX]; | |
1465 | int n, ret; | |
1466 | ||
1467 | n = cpuc->n_events; | |
1468 | ||
1469 | if (!x86_pmu_initialized()) | |
1470 | return -EAGAIN; | |
1471 | ||
1472 | ret = x86_pmu.schedule_events(cpuc, n, assign); | |
1473 | if (ret) | |
1474 | return ret; | |
1475 | ||
1476 | /* | |
1477 | * copy new assignment, now we know it is possible | |
1478 | * will be used by hw_perf_enable() | |
1479 | */ | |
1480 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
1481 | ||
8d2cacbb | 1482 | cpuc->group_flag &= ~PERF_EVENT_TXN; |
90151c35 | 1483 | |
4d1c52b0 LM |
1484 | return 0; |
1485 | } | |
1486 | ||
ca037701 PZ |
1487 | /* |
1488 | * validate that we can schedule this event | |
1489 | */ | |
1490 | static int validate_event(struct perf_event *event) | |
1491 | { | |
1492 | struct cpu_hw_events *fake_cpuc; | |
1493 | struct event_constraint *c; | |
1494 | int ret = 0; | |
1495 | ||
1496 | fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO); | |
1497 | if (!fake_cpuc) | |
1498 | return -ENOMEM; | |
1499 | ||
1500 | c = x86_pmu.get_event_constraints(fake_cpuc, event); | |
1501 | ||
1502 | if (!c || !c->weight) | |
1503 | ret = -ENOSPC; | |
1504 | ||
1505 | if (x86_pmu.put_event_constraints) | |
1506 | x86_pmu.put_event_constraints(fake_cpuc, event); | |
1507 | ||
1508 | kfree(fake_cpuc); | |
1509 | ||
1510 | return ret; | |
1511 | } | |
1512 | ||
1da53e02 SE |
1513 | /* |
1514 | * validate a single event group | |
1515 | * | |
1516 | * validation include: | |
184f412c IM |
1517 | * - check events are compatible which each other |
1518 | * - events do not compete for the same counter | |
1519 | * - number of events <= number of counters | |
1da53e02 SE |
1520 | * |
1521 | * validation ensures the group can be loaded onto the | |
1522 | * PMU if it was the only group available. | |
1523 | */ | |
fe9081cc PZ |
1524 | static int validate_group(struct perf_event *event) |
1525 | { | |
1da53e02 | 1526 | struct perf_event *leader = event->group_leader; |
502568d5 PZ |
1527 | struct cpu_hw_events *fake_cpuc; |
1528 | int ret, n; | |
fe9081cc | 1529 | |
502568d5 PZ |
1530 | ret = -ENOMEM; |
1531 | fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO); | |
1532 | if (!fake_cpuc) | |
1533 | goto out; | |
fe9081cc | 1534 | |
1da53e02 SE |
1535 | /* |
1536 | * the event is not yet connected with its | |
1537 | * siblings therefore we must first collect | |
1538 | * existing siblings, then add the new event | |
1539 | * before we can simulate the scheduling | |
1540 | */ | |
502568d5 PZ |
1541 | ret = -ENOSPC; |
1542 | n = collect_events(fake_cpuc, leader, true); | |
1da53e02 | 1543 | if (n < 0) |
502568d5 | 1544 | goto out_free; |
fe9081cc | 1545 | |
502568d5 PZ |
1546 | fake_cpuc->n_events = n; |
1547 | n = collect_events(fake_cpuc, event, false); | |
1da53e02 | 1548 | if (n < 0) |
502568d5 | 1549 | goto out_free; |
fe9081cc | 1550 | |
502568d5 | 1551 | fake_cpuc->n_events = n; |
1da53e02 | 1552 | |
a072738e | 1553 | ret = x86_pmu.schedule_events(fake_cpuc, n, NULL); |
502568d5 PZ |
1554 | |
1555 | out_free: | |
1556 | kfree(fake_cpuc); | |
1557 | out: | |
1558 | return ret; | |
fe9081cc PZ |
1559 | } |
1560 | ||
b0a873eb | 1561 | int x86_pmu_event_init(struct perf_event *event) |
621a01ea | 1562 | { |
51b0fe39 | 1563 | struct pmu *tmp; |
621a01ea IM |
1564 | int err; |
1565 | ||
b0a873eb PZ |
1566 | switch (event->attr.type) { |
1567 | case PERF_TYPE_RAW: | |
1568 | case PERF_TYPE_HARDWARE: | |
1569 | case PERF_TYPE_HW_CACHE: | |
1570 | break; | |
1571 | ||
1572 | default: | |
1573 | return -ENOENT; | |
1574 | } | |
1575 | ||
1576 | err = __x86_pmu_event_init(event); | |
fe9081cc | 1577 | if (!err) { |
8113070d SE |
1578 | /* |
1579 | * we temporarily connect event to its pmu | |
1580 | * such that validate_group() can classify | |
1581 | * it as an x86 event using is_x86_event() | |
1582 | */ | |
1583 | tmp = event->pmu; | |
1584 | event->pmu = &pmu; | |
1585 | ||
fe9081cc PZ |
1586 | if (event->group_leader != event) |
1587 | err = validate_group(event); | |
ca037701 PZ |
1588 | else |
1589 | err = validate_event(event); | |
8113070d SE |
1590 | |
1591 | event->pmu = tmp; | |
fe9081cc | 1592 | } |
a1792cda | 1593 | if (err) { |
cdd6c482 IM |
1594 | if (event->destroy) |
1595 | event->destroy(event); | |
a1792cda | 1596 | } |
621a01ea | 1597 | |
b0a873eb | 1598 | return err; |
621a01ea | 1599 | } |
d7d59fb3 | 1600 | |
b0a873eb PZ |
1601 | static struct pmu pmu = { |
1602 | .event_init = x86_pmu_event_init, | |
1603 | .enable = x86_pmu_enable, | |
1604 | .disable = x86_pmu_disable, | |
1605 | .start = x86_pmu_start, | |
1606 | .stop = x86_pmu_stop, | |
1607 | .read = x86_pmu_read, | |
1608 | .unthrottle = x86_pmu_unthrottle, | |
1609 | .start_txn = x86_pmu_start_txn, | |
1610 | .cancel_txn = x86_pmu_cancel_txn, | |
1611 | .commit_txn = x86_pmu_commit_txn, | |
1612 | }; | |
1613 | ||
d7d59fb3 PZ |
1614 | /* |
1615 | * callchain support | |
1616 | */ | |
1617 | ||
d7d59fb3 PZ |
1618 | static void |
1619 | backtrace_warning_symbol(void *data, char *msg, unsigned long symbol) | |
1620 | { | |
1621 | /* Ignore warnings */ | |
1622 | } | |
1623 | ||
1624 | static void backtrace_warning(void *data, char *msg) | |
1625 | { | |
1626 | /* Ignore warnings */ | |
1627 | } | |
1628 | ||
1629 | static int backtrace_stack(void *data, char *name) | |
1630 | { | |
038e836e | 1631 | return 0; |
d7d59fb3 PZ |
1632 | } |
1633 | ||
1634 | static void backtrace_address(void *data, unsigned long addr, int reliable) | |
1635 | { | |
1636 | struct perf_callchain_entry *entry = data; | |
1637 | ||
70791ce9 | 1638 | perf_callchain_store(entry, addr); |
d7d59fb3 PZ |
1639 | } |
1640 | ||
1641 | static const struct stacktrace_ops backtrace_ops = { | |
1642 | .warning = backtrace_warning, | |
1643 | .warning_symbol = backtrace_warning_symbol, | |
1644 | .stack = backtrace_stack, | |
1645 | .address = backtrace_address, | |
06d65bda | 1646 | .walk_stack = print_context_stack_bp, |
d7d59fb3 PZ |
1647 | }; |
1648 | ||
56962b44 FW |
1649 | void |
1650 | perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 | 1651 | { |
927c7a9e FW |
1652 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
1653 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 1654 | return; |
927c7a9e FW |
1655 | } |
1656 | ||
70791ce9 | 1657 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 1658 | |
48b5ba9c | 1659 | dump_trace(NULL, regs, NULL, regs->bp, &backtrace_ops, entry); |
d7d59fb3 PZ |
1660 | } |
1661 | ||
257ef9d2 TE |
1662 | #ifdef CONFIG_COMPAT |
1663 | static inline int | |
1664 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
74193ef0 | 1665 | { |
257ef9d2 TE |
1666 | /* 32-bit process in 64-bit kernel. */ |
1667 | struct stack_frame_ia32 frame; | |
1668 | const void __user *fp; | |
74193ef0 | 1669 | |
257ef9d2 TE |
1670 | if (!test_thread_flag(TIF_IA32)) |
1671 | return 0; | |
1672 | ||
1673 | fp = compat_ptr(regs->bp); | |
1674 | while (entry->nr < PERF_MAX_STACK_DEPTH) { | |
1675 | unsigned long bytes; | |
1676 | frame.next_frame = 0; | |
1677 | frame.return_address = 0; | |
1678 | ||
1679 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); | |
1680 | if (bytes != sizeof(frame)) | |
1681 | break; | |
74193ef0 | 1682 | |
257ef9d2 TE |
1683 | if (fp < compat_ptr(regs->sp)) |
1684 | break; | |
74193ef0 | 1685 | |
70791ce9 | 1686 | perf_callchain_store(entry, frame.return_address); |
257ef9d2 TE |
1687 | fp = compat_ptr(frame.next_frame); |
1688 | } | |
1689 | return 1; | |
d7d59fb3 | 1690 | } |
257ef9d2 TE |
1691 | #else |
1692 | static inline int | |
1693 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1694 | { | |
1695 | return 0; | |
1696 | } | |
1697 | #endif | |
d7d59fb3 | 1698 | |
56962b44 FW |
1699 | void |
1700 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 PZ |
1701 | { |
1702 | struct stack_frame frame; | |
1703 | const void __user *fp; | |
1704 | ||
927c7a9e FW |
1705 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
1706 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 1707 | return; |
927c7a9e | 1708 | } |
5a6cec3a | 1709 | |
74193ef0 | 1710 | fp = (void __user *)regs->bp; |
d7d59fb3 | 1711 | |
70791ce9 | 1712 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 1713 | |
257ef9d2 TE |
1714 | if (perf_callchain_user32(regs, entry)) |
1715 | return; | |
1716 | ||
f9188e02 | 1717 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
257ef9d2 | 1718 | unsigned long bytes; |
038e836e | 1719 | frame.next_frame = NULL; |
d7d59fb3 PZ |
1720 | frame.return_address = 0; |
1721 | ||
257ef9d2 TE |
1722 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); |
1723 | if (bytes != sizeof(frame)) | |
d7d59fb3 PZ |
1724 | break; |
1725 | ||
5a6cec3a | 1726 | if ((unsigned long)fp < regs->sp) |
d7d59fb3 PZ |
1727 | break; |
1728 | ||
70791ce9 | 1729 | perf_callchain_store(entry, frame.return_address); |
038e836e | 1730 | fp = frame.next_frame; |
d7d59fb3 PZ |
1731 | } |
1732 | } | |
1733 | ||
39447b38 ZY |
1734 | unsigned long perf_instruction_pointer(struct pt_regs *regs) |
1735 | { | |
1736 | unsigned long ip; | |
dcf46b94 | 1737 | |
39447b38 ZY |
1738 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) |
1739 | ip = perf_guest_cbs->get_guest_ip(); | |
1740 | else | |
1741 | ip = instruction_pointer(regs); | |
dcf46b94 | 1742 | |
39447b38 ZY |
1743 | return ip; |
1744 | } | |
1745 | ||
1746 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
1747 | { | |
1748 | int misc = 0; | |
dcf46b94 | 1749 | |
39447b38 | 1750 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
dcf46b94 ZY |
1751 | if (perf_guest_cbs->is_user_mode()) |
1752 | misc |= PERF_RECORD_MISC_GUEST_USER; | |
1753 | else | |
1754 | misc |= PERF_RECORD_MISC_GUEST_KERNEL; | |
1755 | } else { | |
1756 | if (user_mode(regs)) | |
1757 | misc |= PERF_RECORD_MISC_USER; | |
1758 | else | |
1759 | misc |= PERF_RECORD_MISC_KERNEL; | |
1760 | } | |
1761 | ||
39447b38 | 1762 | if (regs->flags & PERF_EFLAGS_EXACT) |
ab608344 | 1763 | misc |= PERF_RECORD_MISC_EXACT_IP; |
39447b38 ZY |
1764 | |
1765 | return misc; | |
1766 | } |