Commit | Line | Data |
---|---|---|
241771ef | 1 | /* |
cdd6c482 | 2 | * Performance events x86 architecture code |
241771ef | 3 | * |
98144511 IM |
4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> | |
30dd568c | 9 | * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> |
1da53e02 | 10 | * Copyright (C) 2009 Google, Inc., Stephane Eranian |
241771ef IM |
11 | * |
12 | * For licencing details see kernel-base/COPYING | |
13 | */ | |
14 | ||
cdd6c482 | 15 | #include <linux/perf_event.h> |
241771ef IM |
16 | #include <linux/capability.h> |
17 | #include <linux/notifier.h> | |
18 | #include <linux/hardirq.h> | |
19 | #include <linux/kprobes.h> | |
4ac13294 | 20 | #include <linux/module.h> |
241771ef IM |
21 | #include <linux/kdebug.h> |
22 | #include <linux/sched.h> | |
d7d59fb3 | 23 | #include <linux/uaccess.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
74193ef0 | 25 | #include <linux/highmem.h> |
30dd568c | 26 | #include <linux/cpu.h> |
272d30be | 27 | #include <linux/bitops.h> |
241771ef | 28 | |
241771ef | 29 | #include <asm/apic.h> |
d7d59fb3 | 30 | #include <asm/stacktrace.h> |
4e935e47 | 31 | #include <asm/nmi.h> |
257ef9d2 | 32 | #include <asm/compat.h> |
69092624 | 33 | #include <asm/smp.h> |
241771ef | 34 | |
7645a24c PZ |
35 | #if 0 |
36 | #undef wrmsrl | |
37 | #define wrmsrl(msr, val) \ | |
38 | do { \ | |
39 | trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\ | |
40 | (unsigned long)(val)); \ | |
41 | native_write_msr((msr), (u32)((u64)(val)), \ | |
42 | (u32)((u64)(val) >> 32)); \ | |
43 | } while (0) | |
44 | #endif | |
45 | ||
ef21f683 PZ |
46 | /* |
47 | * best effort, GUP based copy_from_user() that assumes IRQ or NMI context | |
48 | */ | |
49 | static unsigned long | |
50 | copy_from_user_nmi(void *to, const void __user *from, unsigned long n) | |
51 | { | |
52 | unsigned long offset, addr = (unsigned long)from; | |
ef21f683 PZ |
53 | unsigned long size, len = 0; |
54 | struct page *page; | |
55 | void *map; | |
56 | int ret; | |
57 | ||
58 | do { | |
59 | ret = __get_user_pages_fast(addr, 1, 0, &page); | |
60 | if (!ret) | |
61 | break; | |
62 | ||
63 | offset = addr & (PAGE_SIZE - 1); | |
64 | size = min(PAGE_SIZE - offset, n - len); | |
65 | ||
7a837d1b | 66 | map = kmap_atomic(page); |
ef21f683 | 67 | memcpy(to, map+offset, size); |
7a837d1b | 68 | kunmap_atomic(map); |
ef21f683 PZ |
69 | put_page(page); |
70 | ||
71 | len += size; | |
72 | to += size; | |
73 | addr += size; | |
74 | ||
75 | } while (len < n); | |
76 | ||
77 | return len; | |
78 | } | |
79 | ||
1da53e02 | 80 | struct event_constraint { |
c91e0f5d PZ |
81 | union { |
82 | unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
b622d644 | 83 | u64 idxmsk64; |
c91e0f5d | 84 | }; |
b622d644 PZ |
85 | u64 code; |
86 | u64 cmask; | |
272d30be | 87 | int weight; |
1da53e02 SE |
88 | }; |
89 | ||
38331f62 SE |
90 | struct amd_nb { |
91 | int nb_id; /* NorthBridge id */ | |
92 | int refcnt; /* reference count */ | |
93 | struct perf_event *owners[X86_PMC_IDX_MAX]; | |
94 | struct event_constraint event_constraints[X86_PMC_IDX_MAX]; | |
95 | }; | |
96 | ||
a7e3ed1e AK |
97 | struct intel_percore; |
98 | ||
caff2bef PZ |
99 | #define MAX_LBR_ENTRIES 16 |
100 | ||
cdd6c482 | 101 | struct cpu_hw_events { |
ca037701 PZ |
102 | /* |
103 | * Generic x86 PMC bits | |
104 | */ | |
1da53e02 | 105 | struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */ |
43f6201a | 106 | unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
63e6be6d | 107 | unsigned long running[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
b0f3f28e | 108 | int enabled; |
241771ef | 109 | |
1da53e02 SE |
110 | int n_events; |
111 | int n_added; | |
90151c35 | 112 | int n_txn; |
1da53e02 | 113 | int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */ |
447a194b | 114 | u64 tags[X86_PMC_IDX_MAX]; |
1da53e02 | 115 | struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */ |
ca037701 | 116 | |
4d1c52b0 LM |
117 | unsigned int group_flag; |
118 | ||
ca037701 PZ |
119 | /* |
120 | * Intel DebugStore bits | |
121 | */ | |
122 | struct debug_store *ds; | |
123 | u64 pebs_enabled; | |
124 | ||
caff2bef PZ |
125 | /* |
126 | * Intel LBR bits | |
127 | */ | |
128 | int lbr_users; | |
129 | void *lbr_context; | |
130 | struct perf_branch_stack lbr_stack; | |
131 | struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES]; | |
132 | ||
a7e3ed1e AK |
133 | /* |
134 | * Intel percore register state. | |
135 | * Coordinate shared resources between HT threads. | |
136 | */ | |
137 | int percore_used; /* Used by this CPU? */ | |
138 | struct intel_percore *per_core; | |
139 | ||
ca037701 PZ |
140 | /* |
141 | * AMD specific bits | |
142 | */ | |
38331f62 | 143 | struct amd_nb *amd_nb; |
b690081d SE |
144 | }; |
145 | ||
fce877e3 | 146 | #define __EVENT_CONSTRAINT(c, n, m, w) {\ |
b622d644 | 147 | { .idxmsk64 = (n) }, \ |
c91e0f5d PZ |
148 | .code = (c), \ |
149 | .cmask = (m), \ | |
fce877e3 | 150 | .weight = (w), \ |
c91e0f5d | 151 | } |
b690081d | 152 | |
fce877e3 PZ |
153 | #define EVENT_CONSTRAINT(c, n, m) \ |
154 | __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n)) | |
155 | ||
ca037701 PZ |
156 | /* |
157 | * Constraint on the Event code. | |
158 | */ | |
ed8777fc | 159 | #define INTEL_EVENT_CONSTRAINT(c, n) \ |
a098f448 | 160 | EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT) |
8433be11 | 161 | |
ca037701 PZ |
162 | /* |
163 | * Constraint on the Event code + UMask + fixed-mask | |
a098f448 RR |
164 | * |
165 | * filter mask to validate fixed counter events. | |
166 | * the following filters disqualify for fixed counters: | |
167 | * - inv | |
168 | * - edge | |
169 | * - cnt-mask | |
170 | * The other filters are supported by fixed counters. | |
171 | * The any-thread option is supported starting with v3. | |
ca037701 | 172 | */ |
ed8777fc | 173 | #define FIXED_EVENT_CONSTRAINT(c, n) \ |
a098f448 | 174 | EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK) |
8433be11 | 175 | |
ca037701 PZ |
176 | /* |
177 | * Constraint on the Event code + UMask | |
178 | */ | |
b06b3d49 | 179 | #define INTEL_UEVENT_CONSTRAINT(c, n) \ |
ca037701 | 180 | EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK) |
b06b3d49 LM |
181 | #define PEBS_EVENT_CONSTRAINT(c, n) \ |
182 | INTEL_UEVENT_CONSTRAINT(c, n) | |
ca037701 | 183 | |
ed8777fc PZ |
184 | #define EVENT_CONSTRAINT_END \ |
185 | EVENT_CONSTRAINT(0, 0, 0) | |
186 | ||
187 | #define for_each_event_constraint(e, c) \ | |
a1f2b70a | 188 | for ((e) = (c); (e)->weight; (e)++) |
b690081d | 189 | |
a7e3ed1e AK |
190 | /* |
191 | * Extra registers for specific events. | |
192 | * Some events need large masks and require external MSRs. | |
193 | * Define a mapping to these extra registers. | |
194 | */ | |
195 | struct extra_reg { | |
196 | unsigned int event; | |
197 | unsigned int msr; | |
198 | u64 config_mask; | |
199 | u64 valid_mask; | |
200 | }; | |
201 | ||
202 | #define EVENT_EXTRA_REG(e, ms, m, vm) { \ | |
203 | .event = (e), \ | |
204 | .msr = (ms), \ | |
205 | .config_mask = (m), \ | |
206 | .valid_mask = (vm), \ | |
207 | } | |
208 | #define INTEL_EVENT_EXTRA_REG(event, msr, vm) \ | |
209 | EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm) | |
210 | #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0) | |
211 | ||
8db909a7 PZ |
212 | union perf_capabilities { |
213 | struct { | |
214 | u64 lbr_format : 6; | |
215 | u64 pebs_trap : 1; | |
216 | u64 pebs_arch_reg : 1; | |
217 | u64 pebs_format : 4; | |
218 | u64 smm_freeze : 1; | |
219 | }; | |
220 | u64 capabilities; | |
221 | }; | |
222 | ||
241771ef | 223 | /* |
5f4ec28f | 224 | * struct x86_pmu - generic x86 pmu |
241771ef | 225 | */ |
5f4ec28f | 226 | struct x86_pmu { |
ca037701 PZ |
227 | /* |
228 | * Generic x86 PMC bits | |
229 | */ | |
faa28ae0 RR |
230 | const char *name; |
231 | int version; | |
a3288106 | 232 | int (*handle_irq)(struct pt_regs *); |
9e35ad38 | 233 | void (*disable_all)(void); |
11164cd4 | 234 | void (*enable_all)(int added); |
aff3d91a PZ |
235 | void (*enable)(struct perf_event *); |
236 | void (*disable)(struct perf_event *); | |
b4cdc5c2 | 237 | int (*hw_config)(struct perf_event *event); |
a072738e | 238 | int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign); |
169e41eb JSR |
239 | unsigned eventsel; |
240 | unsigned perfctr; | |
b0f3f28e | 241 | u64 (*event_map)(int); |
169e41eb | 242 | int max_events; |
948b1bb8 RR |
243 | int num_counters; |
244 | int num_counters_fixed; | |
245 | int cntval_bits; | |
246 | u64 cntval_mask; | |
04da8a43 | 247 | int apic; |
c619b8ff | 248 | u64 max_period; |
63b14649 PZ |
249 | struct event_constraint * |
250 | (*get_event_constraints)(struct cpu_hw_events *cpuc, | |
251 | struct perf_event *event); | |
252 | ||
c91e0f5d PZ |
253 | void (*put_event_constraints)(struct cpu_hw_events *cpuc, |
254 | struct perf_event *event); | |
63b14649 | 255 | struct event_constraint *event_constraints; |
a7e3ed1e | 256 | struct event_constraint *percore_constraints; |
3c44780b | 257 | void (*quirks)(void); |
68aa00ac | 258 | int perfctr_second_write; |
3f6da390 | 259 | |
b38b24ea | 260 | int (*cpu_prepare)(int cpu); |
3f6da390 PZ |
261 | void (*cpu_starting)(int cpu); |
262 | void (*cpu_dying)(int cpu); | |
263 | void (*cpu_dead)(int cpu); | |
ca037701 PZ |
264 | |
265 | /* | |
266 | * Intel Arch Perfmon v2+ | |
267 | */ | |
8db909a7 PZ |
268 | u64 intel_ctrl; |
269 | union perf_capabilities intel_cap; | |
ca037701 PZ |
270 | |
271 | /* | |
272 | * Intel DebugStore bits | |
273 | */ | |
274 | int bts, pebs; | |
6809b6ea | 275 | int bts_active, pebs_active; |
ca037701 PZ |
276 | int pebs_record_size; |
277 | void (*drain_pebs)(struct pt_regs *regs); | |
278 | struct event_constraint *pebs_constraints; | |
caff2bef PZ |
279 | |
280 | /* | |
281 | * Intel LBR | |
282 | */ | |
283 | unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */ | |
284 | int lbr_nr; /* hardware stack size */ | |
a7e3ed1e AK |
285 | |
286 | /* | |
287 | * Extra registers for events | |
288 | */ | |
289 | struct extra_reg *extra_regs; | |
b56a3802 JSR |
290 | }; |
291 | ||
4a06bd85 | 292 | static struct x86_pmu x86_pmu __read_mostly; |
b56a3802 | 293 | |
cdd6c482 | 294 | static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { |
b0f3f28e PZ |
295 | .enabled = 1, |
296 | }; | |
241771ef | 297 | |
07088edb | 298 | static int x86_perf_event_set_period(struct perf_event *event); |
b690081d | 299 | |
8326f44d | 300 | /* |
dfc65094 | 301 | * Generalized hw caching related hw_event table, filled |
8326f44d | 302 | * in on a per model basis. A value of 0 means |
dfc65094 IM |
303 | * 'not supported', -1 means 'hw_event makes no sense on |
304 | * this CPU', any other value means the raw hw_event | |
8326f44d IM |
305 | * ID. |
306 | */ | |
307 | ||
308 | #define C(x) PERF_COUNT_HW_CACHE_##x | |
309 | ||
310 | static u64 __read_mostly hw_cache_event_ids | |
311 | [PERF_COUNT_HW_CACHE_MAX] | |
312 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
313 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
e994d7d2 AK |
314 | static u64 __read_mostly hw_cache_extra_regs |
315 | [PERF_COUNT_HW_CACHE_MAX] | |
316 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
317 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
8326f44d | 318 | |
ee06094f | 319 | /* |
cdd6c482 IM |
320 | * Propagate event elapsed time into the generic event. |
321 | * Can only be executed on the CPU where the event is active. | |
ee06094f IM |
322 | * Returns the delta events processed. |
323 | */ | |
4b7bfd0d | 324 | static u64 |
cc2ad4ba | 325 | x86_perf_event_update(struct perf_event *event) |
ee06094f | 326 | { |
cc2ad4ba | 327 | struct hw_perf_event *hwc = &event->hw; |
948b1bb8 | 328 | int shift = 64 - x86_pmu.cntval_bits; |
ec3232bd | 329 | u64 prev_raw_count, new_raw_count; |
cc2ad4ba | 330 | int idx = hwc->idx; |
ec3232bd | 331 | s64 delta; |
ee06094f | 332 | |
30dd568c MM |
333 | if (idx == X86_PMC_IDX_FIXED_BTS) |
334 | return 0; | |
335 | ||
ee06094f | 336 | /* |
cdd6c482 | 337 | * Careful: an NMI might modify the previous event value. |
ee06094f IM |
338 | * |
339 | * Our tactic to handle this is to first atomically read and | |
340 | * exchange a new raw count - then add that new-prev delta | |
cdd6c482 | 341 | * count to the generic event atomically: |
ee06094f IM |
342 | */ |
343 | again: | |
e7850595 | 344 | prev_raw_count = local64_read(&hwc->prev_count); |
73d6e522 | 345 | rdmsrl(hwc->event_base, new_raw_count); |
ee06094f | 346 | |
e7850595 | 347 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
ee06094f IM |
348 | new_raw_count) != prev_raw_count) |
349 | goto again; | |
350 | ||
351 | /* | |
352 | * Now we have the new raw value and have updated the prev | |
353 | * timestamp already. We can now calculate the elapsed delta | |
cdd6c482 | 354 | * (event-)time and add that to the generic event. |
ee06094f IM |
355 | * |
356 | * Careful, not all hw sign-extends above the physical width | |
ec3232bd | 357 | * of the count. |
ee06094f | 358 | */ |
ec3232bd PZ |
359 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
360 | delta >>= shift; | |
ee06094f | 361 | |
e7850595 PZ |
362 | local64_add(delta, &event->count); |
363 | local64_sub(delta, &hwc->period_left); | |
4b7bfd0d RR |
364 | |
365 | return new_raw_count; | |
ee06094f IM |
366 | } |
367 | ||
4979d272 RR |
368 | /* using X86_FEATURE_PERFCTR_CORE to later implement ALTERNATIVE() here */ |
369 | static inline int x86_pmu_addr_offset(int index) | |
370 | { | |
371 | if (boot_cpu_has(X86_FEATURE_PERFCTR_CORE)) | |
372 | return index << 1; | |
373 | return index; | |
374 | } | |
375 | ||
41bf4989 RR |
376 | static inline unsigned int x86_pmu_config_addr(int index) |
377 | { | |
4979d272 | 378 | return x86_pmu.eventsel + x86_pmu_addr_offset(index); |
41bf4989 RR |
379 | } |
380 | ||
381 | static inline unsigned int x86_pmu_event_addr(int index) | |
382 | { | |
4979d272 | 383 | return x86_pmu.perfctr + x86_pmu_addr_offset(index); |
41bf4989 RR |
384 | } |
385 | ||
a7e3ed1e AK |
386 | /* |
387 | * Find and validate any extra registers to set up. | |
388 | */ | |
389 | static int x86_pmu_extra_regs(u64 config, struct perf_event *event) | |
390 | { | |
391 | struct extra_reg *er; | |
392 | ||
393 | event->hw.extra_reg = 0; | |
394 | event->hw.extra_config = 0; | |
395 | ||
396 | if (!x86_pmu.extra_regs) | |
397 | return 0; | |
398 | ||
399 | for (er = x86_pmu.extra_regs; er->msr; er++) { | |
400 | if (er->event != (config & er->config_mask)) | |
401 | continue; | |
402 | if (event->attr.config1 & ~er->valid_mask) | |
403 | return -EINVAL; | |
404 | event->hw.extra_reg = er->msr; | |
405 | event->hw.extra_config = event->attr.config1; | |
406 | break; | |
407 | } | |
408 | return 0; | |
409 | } | |
410 | ||
cdd6c482 | 411 | static atomic_t active_events; |
4e935e47 PZ |
412 | static DEFINE_MUTEX(pmc_reserve_mutex); |
413 | ||
b27ea29c RR |
414 | #ifdef CONFIG_X86_LOCAL_APIC |
415 | ||
4e935e47 PZ |
416 | static bool reserve_pmc_hardware(void) |
417 | { | |
418 | int i; | |
419 | ||
948b1bb8 | 420 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 | 421 | if (!reserve_perfctr_nmi(x86_pmu_event_addr(i))) |
4e935e47 PZ |
422 | goto perfctr_fail; |
423 | } | |
424 | ||
948b1bb8 | 425 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 | 426 | if (!reserve_evntsel_nmi(x86_pmu_config_addr(i))) |
4e935e47 PZ |
427 | goto eventsel_fail; |
428 | } | |
429 | ||
430 | return true; | |
431 | ||
432 | eventsel_fail: | |
433 | for (i--; i >= 0; i--) | |
41bf4989 | 434 | release_evntsel_nmi(x86_pmu_config_addr(i)); |
4e935e47 | 435 | |
948b1bb8 | 436 | i = x86_pmu.num_counters; |
4e935e47 PZ |
437 | |
438 | perfctr_fail: | |
439 | for (i--; i >= 0; i--) | |
41bf4989 | 440 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
4e935e47 | 441 | |
4e935e47 PZ |
442 | return false; |
443 | } | |
444 | ||
445 | static void release_pmc_hardware(void) | |
446 | { | |
447 | int i; | |
448 | ||
948b1bb8 | 449 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 RR |
450 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
451 | release_evntsel_nmi(x86_pmu_config_addr(i)); | |
4e935e47 | 452 | } |
4e935e47 PZ |
453 | } |
454 | ||
b27ea29c RR |
455 | #else |
456 | ||
457 | static bool reserve_pmc_hardware(void) { return true; } | |
458 | static void release_pmc_hardware(void) {} | |
459 | ||
460 | #endif | |
461 | ||
33c6d6a7 DZ |
462 | static bool check_hw_exists(void) |
463 | { | |
464 | u64 val, val_new = 0; | |
4407204c | 465 | int i, reg, ret = 0; |
33c6d6a7 | 466 | |
4407204c PZ |
467 | /* |
468 | * Check to see if the BIOS enabled any of the counters, if so | |
469 | * complain and bail. | |
470 | */ | |
471 | for (i = 0; i < x86_pmu.num_counters; i++) { | |
41bf4989 | 472 | reg = x86_pmu_config_addr(i); |
4407204c PZ |
473 | ret = rdmsrl_safe(reg, &val); |
474 | if (ret) | |
475 | goto msr_fail; | |
476 | if (val & ARCH_PERFMON_EVENTSEL_ENABLE) | |
477 | goto bios_fail; | |
478 | } | |
479 | ||
480 | if (x86_pmu.num_counters_fixed) { | |
481 | reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; | |
482 | ret = rdmsrl_safe(reg, &val); | |
483 | if (ret) | |
484 | goto msr_fail; | |
485 | for (i = 0; i < x86_pmu.num_counters_fixed; i++) { | |
486 | if (val & (0x03 << i*4)) | |
487 | goto bios_fail; | |
488 | } | |
489 | } | |
490 | ||
491 | /* | |
492 | * Now write a value and read it back to see if it matches, | |
493 | * this is needed to detect certain hardware emulators (qemu/kvm) | |
494 | * that don't trap on the MSR access and always return 0s. | |
495 | */ | |
33c6d6a7 | 496 | val = 0xabcdUL; |
41bf4989 RR |
497 | ret = checking_wrmsrl(x86_pmu_event_addr(0), val); |
498 | ret |= rdmsrl_safe(x86_pmu_event_addr(0), &val_new); | |
33c6d6a7 | 499 | if (ret || val != val_new) |
4407204c | 500 | goto msr_fail; |
33c6d6a7 DZ |
501 | |
502 | return true; | |
4407204c PZ |
503 | |
504 | bios_fail: | |
505 | printk(KERN_CONT "Broken BIOS detected, using software events only.\n"); | |
506 | printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg, val); | |
507 | return false; | |
508 | ||
509 | msr_fail: | |
510 | printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n"); | |
511 | return false; | |
33c6d6a7 DZ |
512 | } |
513 | ||
f80c9e30 | 514 | static void reserve_ds_buffers(void); |
ca037701 | 515 | static void release_ds_buffers(void); |
30dd568c | 516 | |
cdd6c482 | 517 | static void hw_perf_event_destroy(struct perf_event *event) |
4e935e47 | 518 | { |
cdd6c482 | 519 | if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) { |
4e935e47 | 520 | release_pmc_hardware(); |
ca037701 | 521 | release_ds_buffers(); |
4e935e47 PZ |
522 | mutex_unlock(&pmc_reserve_mutex); |
523 | } | |
524 | } | |
525 | ||
85cf9dba RR |
526 | static inline int x86_pmu_initialized(void) |
527 | { | |
528 | return x86_pmu.handle_irq != NULL; | |
529 | } | |
530 | ||
8326f44d | 531 | static inline int |
e994d7d2 | 532 | set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event) |
8326f44d | 533 | { |
e994d7d2 | 534 | struct perf_event_attr *attr = &event->attr; |
8326f44d IM |
535 | unsigned int cache_type, cache_op, cache_result; |
536 | u64 config, val; | |
537 | ||
538 | config = attr->config; | |
539 | ||
540 | cache_type = (config >> 0) & 0xff; | |
541 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
542 | return -EINVAL; | |
543 | ||
544 | cache_op = (config >> 8) & 0xff; | |
545 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
546 | return -EINVAL; | |
547 | ||
548 | cache_result = (config >> 16) & 0xff; | |
549 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
550 | return -EINVAL; | |
551 | ||
552 | val = hw_cache_event_ids[cache_type][cache_op][cache_result]; | |
553 | ||
554 | if (val == 0) | |
555 | return -ENOENT; | |
556 | ||
557 | if (val == -1) | |
558 | return -EINVAL; | |
559 | ||
560 | hwc->config |= val; | |
e994d7d2 AK |
561 | attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result]; |
562 | return x86_pmu_extra_regs(val, event); | |
8326f44d IM |
563 | } |
564 | ||
c1726f34 RR |
565 | static int x86_setup_perfctr(struct perf_event *event) |
566 | { | |
567 | struct perf_event_attr *attr = &event->attr; | |
568 | struct hw_perf_event *hwc = &event->hw; | |
569 | u64 config; | |
570 | ||
6c7e550f | 571 | if (!is_sampling_event(event)) { |
c1726f34 RR |
572 | hwc->sample_period = x86_pmu.max_period; |
573 | hwc->last_period = hwc->sample_period; | |
e7850595 | 574 | local64_set(&hwc->period_left, hwc->sample_period); |
c1726f34 RR |
575 | } else { |
576 | /* | |
577 | * If we have a PMU initialized but no APIC | |
578 | * interrupts, we cannot sample hardware | |
579 | * events (user-space has to fall back and | |
580 | * sample via a hrtimer based software event): | |
581 | */ | |
582 | if (!x86_pmu.apic) | |
583 | return -EOPNOTSUPP; | |
584 | } | |
585 | ||
586 | if (attr->type == PERF_TYPE_RAW) | |
e994d7d2 | 587 | return x86_pmu_extra_regs(event->attr.config, event); |
c1726f34 RR |
588 | |
589 | if (attr->type == PERF_TYPE_HW_CACHE) | |
e994d7d2 | 590 | return set_ext_hw_attr(hwc, event); |
c1726f34 RR |
591 | |
592 | if (attr->config >= x86_pmu.max_events) | |
593 | return -EINVAL; | |
594 | ||
595 | /* | |
596 | * The generic map: | |
597 | */ | |
598 | config = x86_pmu.event_map(attr->config); | |
599 | ||
600 | if (config == 0) | |
601 | return -ENOENT; | |
602 | ||
603 | if (config == -1LL) | |
604 | return -EINVAL; | |
605 | ||
606 | /* | |
607 | * Branch tracing: | |
608 | */ | |
609 | if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) && | |
610 | (hwc->sample_period == 1)) { | |
611 | /* BTS is not supported by this architecture. */ | |
6809b6ea | 612 | if (!x86_pmu.bts_active) |
c1726f34 RR |
613 | return -EOPNOTSUPP; |
614 | ||
615 | /* BTS is currently only allowed for user-mode. */ | |
616 | if (!attr->exclude_kernel) | |
617 | return -EOPNOTSUPP; | |
618 | } | |
619 | ||
620 | hwc->config |= config; | |
621 | ||
622 | return 0; | |
623 | } | |
4261e0e0 | 624 | |
b4cdc5c2 | 625 | static int x86_pmu_hw_config(struct perf_event *event) |
a072738e | 626 | { |
ab608344 PZ |
627 | if (event->attr.precise_ip) { |
628 | int precise = 0; | |
629 | ||
630 | /* Support for constant skid */ | |
6809b6ea | 631 | if (x86_pmu.pebs_active) { |
ab608344 PZ |
632 | precise++; |
633 | ||
5553be26 PZ |
634 | /* Support for IP fixup */ |
635 | if (x86_pmu.lbr_nr) | |
636 | precise++; | |
637 | } | |
ab608344 PZ |
638 | |
639 | if (event->attr.precise_ip > precise) | |
640 | return -EOPNOTSUPP; | |
641 | } | |
642 | ||
a072738e CG |
643 | /* |
644 | * Generate PMC IRQs: | |
645 | * (keep 'enabled' bit clear for now) | |
646 | */ | |
b4cdc5c2 | 647 | event->hw.config = ARCH_PERFMON_EVENTSEL_INT; |
a072738e CG |
648 | |
649 | /* | |
650 | * Count user and OS events unless requested not to | |
651 | */ | |
b4cdc5c2 PZ |
652 | if (!event->attr.exclude_user) |
653 | event->hw.config |= ARCH_PERFMON_EVENTSEL_USR; | |
654 | if (!event->attr.exclude_kernel) | |
655 | event->hw.config |= ARCH_PERFMON_EVENTSEL_OS; | |
a072738e | 656 | |
b4cdc5c2 PZ |
657 | if (event->attr.type == PERF_TYPE_RAW) |
658 | event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK; | |
a072738e | 659 | |
9d0fcba6 | 660 | return x86_setup_perfctr(event); |
a098f448 RR |
661 | } |
662 | ||
241771ef | 663 | /* |
0d48696f | 664 | * Setup the hardware configuration for a given attr_type |
241771ef | 665 | */ |
b0a873eb | 666 | static int __x86_pmu_event_init(struct perf_event *event) |
241771ef | 667 | { |
4e935e47 | 668 | int err; |
241771ef | 669 | |
85cf9dba RR |
670 | if (!x86_pmu_initialized()) |
671 | return -ENODEV; | |
241771ef | 672 | |
4e935e47 | 673 | err = 0; |
cdd6c482 | 674 | if (!atomic_inc_not_zero(&active_events)) { |
4e935e47 | 675 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 | 676 | if (atomic_read(&active_events) == 0) { |
30dd568c MM |
677 | if (!reserve_pmc_hardware()) |
678 | err = -EBUSY; | |
f80c9e30 PZ |
679 | else |
680 | reserve_ds_buffers(); | |
30dd568c MM |
681 | } |
682 | if (!err) | |
cdd6c482 | 683 | atomic_inc(&active_events); |
4e935e47 PZ |
684 | mutex_unlock(&pmc_reserve_mutex); |
685 | } | |
686 | if (err) | |
687 | return err; | |
688 | ||
cdd6c482 | 689 | event->destroy = hw_perf_event_destroy; |
a1792cda | 690 | |
4261e0e0 RR |
691 | event->hw.idx = -1; |
692 | event->hw.last_cpu = -1; | |
693 | event->hw.last_tag = ~0ULL; | |
b690081d | 694 | |
9d0fcba6 | 695 | return x86_pmu.hw_config(event); |
4261e0e0 RR |
696 | } |
697 | ||
8c48e444 | 698 | static void x86_pmu_disable_all(void) |
f87ad35d | 699 | { |
cdd6c482 | 700 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
9e35ad38 PZ |
701 | int idx; |
702 | ||
948b1bb8 | 703 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
b0f3f28e PZ |
704 | u64 val; |
705 | ||
43f6201a | 706 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 707 | continue; |
41bf4989 | 708 | rdmsrl(x86_pmu_config_addr(idx), val); |
bb1165d6 | 709 | if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE)) |
4295ee62 | 710 | continue; |
bb1165d6 | 711 | val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; |
41bf4989 | 712 | wrmsrl(x86_pmu_config_addr(idx), val); |
f87ad35d | 713 | } |
f87ad35d JSR |
714 | } |
715 | ||
a4eaf7f1 | 716 | static void x86_pmu_disable(struct pmu *pmu) |
b56a3802 | 717 | { |
1da53e02 SE |
718 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
719 | ||
85cf9dba | 720 | if (!x86_pmu_initialized()) |
9e35ad38 | 721 | return; |
1da53e02 | 722 | |
1a6e21f7 PZ |
723 | if (!cpuc->enabled) |
724 | return; | |
725 | ||
726 | cpuc->n_added = 0; | |
727 | cpuc->enabled = 0; | |
728 | barrier(); | |
1da53e02 SE |
729 | |
730 | x86_pmu.disable_all(); | |
b56a3802 | 731 | } |
241771ef | 732 | |
d45dd923 RR |
733 | static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, |
734 | u64 enable_mask) | |
735 | { | |
a7e3ed1e AK |
736 | if (hwc->extra_reg) |
737 | wrmsrl(hwc->extra_reg, hwc->extra_config); | |
73d6e522 | 738 | wrmsrl(hwc->config_base, hwc->config | enable_mask); |
d45dd923 RR |
739 | } |
740 | ||
11164cd4 | 741 | static void x86_pmu_enable_all(int added) |
f87ad35d | 742 | { |
cdd6c482 | 743 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
f87ad35d JSR |
744 | int idx; |
745 | ||
948b1bb8 | 746 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
d45dd923 | 747 | struct hw_perf_event *hwc = &cpuc->events[idx]->hw; |
b0f3f28e | 748 | |
43f6201a | 749 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 750 | continue; |
984b838c | 751 | |
d45dd923 | 752 | __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); |
f87ad35d JSR |
753 | } |
754 | } | |
755 | ||
51b0fe39 | 756 | static struct pmu pmu; |
1da53e02 SE |
757 | |
758 | static inline int is_x86_event(struct perf_event *event) | |
759 | { | |
760 | return event->pmu == &pmu; | |
761 | } | |
762 | ||
763 | static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) | |
764 | { | |
63b14649 | 765 | struct event_constraint *c, *constraints[X86_PMC_IDX_MAX]; |
1da53e02 | 766 | unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
c933c1a6 | 767 | int i, j, w, wmax, num = 0; |
1da53e02 SE |
768 | struct hw_perf_event *hwc; |
769 | ||
770 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); | |
771 | ||
772 | for (i = 0; i < n; i++) { | |
b622d644 PZ |
773 | c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]); |
774 | constraints[i] = c; | |
1da53e02 SE |
775 | } |
776 | ||
8113070d SE |
777 | /* |
778 | * fastpath, try to reuse previous register | |
779 | */ | |
c933c1a6 | 780 | for (i = 0; i < n; i++) { |
8113070d | 781 | hwc = &cpuc->event_list[i]->hw; |
81269a08 | 782 | c = constraints[i]; |
8113070d SE |
783 | |
784 | /* never assigned */ | |
785 | if (hwc->idx == -1) | |
786 | break; | |
787 | ||
788 | /* constraint still honored */ | |
63b14649 | 789 | if (!test_bit(hwc->idx, c->idxmsk)) |
8113070d SE |
790 | break; |
791 | ||
792 | /* not already used */ | |
793 | if (test_bit(hwc->idx, used_mask)) | |
794 | break; | |
795 | ||
34538ee7 | 796 | __set_bit(hwc->idx, used_mask); |
8113070d SE |
797 | if (assign) |
798 | assign[i] = hwc->idx; | |
799 | } | |
c933c1a6 | 800 | if (i == n) |
8113070d SE |
801 | goto done; |
802 | ||
803 | /* | |
804 | * begin slow path | |
805 | */ | |
806 | ||
807 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); | |
808 | ||
1da53e02 SE |
809 | /* |
810 | * weight = number of possible counters | |
811 | * | |
812 | * 1 = most constrained, only works on one counter | |
813 | * wmax = least constrained, works on any counter | |
814 | * | |
815 | * assign events to counters starting with most | |
816 | * constrained events. | |
817 | */ | |
948b1bb8 | 818 | wmax = x86_pmu.num_counters; |
1da53e02 SE |
819 | |
820 | /* | |
821 | * when fixed event counters are present, | |
822 | * wmax is incremented by 1 to account | |
823 | * for one more choice | |
824 | */ | |
948b1bb8 | 825 | if (x86_pmu.num_counters_fixed) |
1da53e02 SE |
826 | wmax++; |
827 | ||
8113070d | 828 | for (w = 1, num = n; num && w <= wmax; w++) { |
1da53e02 | 829 | /* for each event */ |
8113070d | 830 | for (i = 0; num && i < n; i++) { |
81269a08 | 831 | c = constraints[i]; |
1da53e02 SE |
832 | hwc = &cpuc->event_list[i]->hw; |
833 | ||
272d30be | 834 | if (c->weight != w) |
1da53e02 SE |
835 | continue; |
836 | ||
984b3f57 | 837 | for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) { |
1da53e02 SE |
838 | if (!test_bit(j, used_mask)) |
839 | break; | |
840 | } | |
841 | ||
842 | if (j == X86_PMC_IDX_MAX) | |
843 | break; | |
1da53e02 | 844 | |
34538ee7 | 845 | __set_bit(j, used_mask); |
8113070d | 846 | |
1da53e02 SE |
847 | if (assign) |
848 | assign[i] = j; | |
849 | num--; | |
850 | } | |
851 | } | |
8113070d | 852 | done: |
1da53e02 SE |
853 | /* |
854 | * scheduling failed or is just a simulation, | |
855 | * free resources if necessary | |
856 | */ | |
857 | if (!assign || num) { | |
858 | for (i = 0; i < n; i++) { | |
859 | if (x86_pmu.put_event_constraints) | |
860 | x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]); | |
861 | } | |
862 | } | |
863 | return num ? -ENOSPC : 0; | |
864 | } | |
865 | ||
866 | /* | |
867 | * dogrp: true if must collect siblings events (group) | |
868 | * returns total number of events and error code | |
869 | */ | |
870 | static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp) | |
871 | { | |
872 | struct perf_event *event; | |
873 | int n, max_count; | |
874 | ||
948b1bb8 | 875 | max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed; |
1da53e02 SE |
876 | |
877 | /* current number of events already accepted */ | |
878 | n = cpuc->n_events; | |
879 | ||
880 | if (is_x86_event(leader)) { | |
881 | if (n >= max_count) | |
882 | return -ENOSPC; | |
883 | cpuc->event_list[n] = leader; | |
884 | n++; | |
885 | } | |
886 | if (!dogrp) | |
887 | return n; | |
888 | ||
889 | list_for_each_entry(event, &leader->sibling_list, group_entry) { | |
890 | if (!is_x86_event(event) || | |
8113070d | 891 | event->state <= PERF_EVENT_STATE_OFF) |
1da53e02 SE |
892 | continue; |
893 | ||
894 | if (n >= max_count) | |
895 | return -ENOSPC; | |
896 | ||
897 | cpuc->event_list[n] = event; | |
898 | n++; | |
899 | } | |
900 | return n; | |
901 | } | |
902 | ||
1da53e02 | 903 | static inline void x86_assign_hw_event(struct perf_event *event, |
447a194b | 904 | struct cpu_hw_events *cpuc, int i) |
1da53e02 | 905 | { |
447a194b SE |
906 | struct hw_perf_event *hwc = &event->hw; |
907 | ||
908 | hwc->idx = cpuc->assign[i]; | |
909 | hwc->last_cpu = smp_processor_id(); | |
910 | hwc->last_tag = ++cpuc->tags[i]; | |
1da53e02 SE |
911 | |
912 | if (hwc->idx == X86_PMC_IDX_FIXED_BTS) { | |
913 | hwc->config_base = 0; | |
914 | hwc->event_base = 0; | |
915 | } else if (hwc->idx >= X86_PMC_IDX_FIXED) { | |
916 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; | |
73d6e522 | 917 | hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0; |
1da53e02 | 918 | } else { |
73d6e522 RR |
919 | hwc->config_base = x86_pmu_config_addr(hwc->idx); |
920 | hwc->event_base = x86_pmu_event_addr(hwc->idx); | |
1da53e02 SE |
921 | } |
922 | } | |
923 | ||
447a194b SE |
924 | static inline int match_prev_assignment(struct hw_perf_event *hwc, |
925 | struct cpu_hw_events *cpuc, | |
926 | int i) | |
927 | { | |
928 | return hwc->idx == cpuc->assign[i] && | |
929 | hwc->last_cpu == smp_processor_id() && | |
930 | hwc->last_tag == cpuc->tags[i]; | |
931 | } | |
932 | ||
a4eaf7f1 PZ |
933 | static void x86_pmu_start(struct perf_event *event, int flags); |
934 | static void x86_pmu_stop(struct perf_event *event, int flags); | |
2e841873 | 935 | |
a4eaf7f1 | 936 | static void x86_pmu_enable(struct pmu *pmu) |
ee06094f | 937 | { |
1da53e02 SE |
938 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
939 | struct perf_event *event; | |
940 | struct hw_perf_event *hwc; | |
11164cd4 | 941 | int i, added = cpuc->n_added; |
1da53e02 | 942 | |
85cf9dba | 943 | if (!x86_pmu_initialized()) |
2b9ff0db | 944 | return; |
1a6e21f7 PZ |
945 | |
946 | if (cpuc->enabled) | |
947 | return; | |
948 | ||
1da53e02 | 949 | if (cpuc->n_added) { |
19925ce7 | 950 | int n_running = cpuc->n_events - cpuc->n_added; |
1da53e02 SE |
951 | /* |
952 | * apply assignment obtained either from | |
953 | * hw_perf_group_sched_in() or x86_pmu_enable() | |
954 | * | |
955 | * step1: save events moving to new counters | |
956 | * step2: reprogram moved events into new counters | |
957 | */ | |
19925ce7 | 958 | for (i = 0; i < n_running; i++) { |
1da53e02 SE |
959 | event = cpuc->event_list[i]; |
960 | hwc = &event->hw; | |
961 | ||
447a194b SE |
962 | /* |
963 | * we can avoid reprogramming counter if: | |
964 | * - assigned same counter as last time | |
965 | * - running on same CPU as last time | |
966 | * - no other event has used the counter since | |
967 | */ | |
968 | if (hwc->idx == -1 || | |
969 | match_prev_assignment(hwc, cpuc, i)) | |
1da53e02 SE |
970 | continue; |
971 | ||
a4eaf7f1 PZ |
972 | /* |
973 | * Ensure we don't accidentally enable a stopped | |
974 | * counter simply because we rescheduled. | |
975 | */ | |
976 | if (hwc->state & PERF_HES_STOPPED) | |
977 | hwc->state |= PERF_HES_ARCH; | |
978 | ||
979 | x86_pmu_stop(event, PERF_EF_UPDATE); | |
1da53e02 SE |
980 | } |
981 | ||
982 | for (i = 0; i < cpuc->n_events; i++) { | |
1da53e02 SE |
983 | event = cpuc->event_list[i]; |
984 | hwc = &event->hw; | |
985 | ||
45e16a68 | 986 | if (!match_prev_assignment(hwc, cpuc, i)) |
447a194b | 987 | x86_assign_hw_event(event, cpuc, i); |
45e16a68 PZ |
988 | else if (i < n_running) |
989 | continue; | |
1da53e02 | 990 | |
a4eaf7f1 PZ |
991 | if (hwc->state & PERF_HES_ARCH) |
992 | continue; | |
993 | ||
994 | x86_pmu_start(event, PERF_EF_RELOAD); | |
1da53e02 SE |
995 | } |
996 | cpuc->n_added = 0; | |
997 | perf_events_lapic_init(); | |
998 | } | |
1a6e21f7 PZ |
999 | |
1000 | cpuc->enabled = 1; | |
1001 | barrier(); | |
1002 | ||
11164cd4 | 1003 | x86_pmu.enable_all(added); |
ee06094f | 1004 | } |
ee06094f | 1005 | |
aff3d91a | 1006 | static inline void x86_pmu_disable_event(struct perf_event *event) |
b0f3f28e | 1007 | { |
aff3d91a | 1008 | struct hw_perf_event *hwc = &event->hw; |
7645a24c | 1009 | |
73d6e522 | 1010 | wrmsrl(hwc->config_base, hwc->config); |
b0f3f28e PZ |
1011 | } |
1012 | ||
245b2e70 | 1013 | static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); |
241771ef | 1014 | |
ee06094f IM |
1015 | /* |
1016 | * Set the next IRQ period, based on the hwc->period_left value. | |
cdd6c482 | 1017 | * To be called with the event disabled in hw: |
ee06094f | 1018 | */ |
e4abb5d4 | 1019 | static int |
07088edb | 1020 | x86_perf_event_set_period(struct perf_event *event) |
241771ef | 1021 | { |
07088edb | 1022 | struct hw_perf_event *hwc = &event->hw; |
e7850595 | 1023 | s64 left = local64_read(&hwc->period_left); |
e4abb5d4 | 1024 | s64 period = hwc->sample_period; |
7645a24c | 1025 | int ret = 0, idx = hwc->idx; |
ee06094f | 1026 | |
30dd568c MM |
1027 | if (idx == X86_PMC_IDX_FIXED_BTS) |
1028 | return 0; | |
1029 | ||
ee06094f | 1030 | /* |
af901ca1 | 1031 | * If we are way outside a reasonable range then just skip forward: |
ee06094f IM |
1032 | */ |
1033 | if (unlikely(left <= -period)) { | |
1034 | left = period; | |
e7850595 | 1035 | local64_set(&hwc->period_left, left); |
9e350de3 | 1036 | hwc->last_period = period; |
e4abb5d4 | 1037 | ret = 1; |
ee06094f IM |
1038 | } |
1039 | ||
1040 | if (unlikely(left <= 0)) { | |
1041 | left += period; | |
e7850595 | 1042 | local64_set(&hwc->period_left, left); |
9e350de3 | 1043 | hwc->last_period = period; |
e4abb5d4 | 1044 | ret = 1; |
ee06094f | 1045 | } |
1c80f4b5 | 1046 | /* |
dfc65094 | 1047 | * Quirk: certain CPUs dont like it if just 1 hw_event is left: |
1c80f4b5 IM |
1048 | */ |
1049 | if (unlikely(left < 2)) | |
1050 | left = 2; | |
241771ef | 1051 | |
e4abb5d4 PZ |
1052 | if (left > x86_pmu.max_period) |
1053 | left = x86_pmu.max_period; | |
1054 | ||
245b2e70 | 1055 | per_cpu(pmc_prev_left[idx], smp_processor_id()) = left; |
ee06094f IM |
1056 | |
1057 | /* | |
cdd6c482 | 1058 | * The hw event starts counting from this event offset, |
ee06094f IM |
1059 | * mark it to be able to extra future deltas: |
1060 | */ | |
e7850595 | 1061 | local64_set(&hwc->prev_count, (u64)-left); |
ee06094f | 1062 | |
73d6e522 | 1063 | wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac CG |
1064 | |
1065 | /* | |
1066 | * Due to erratum on certan cpu we need | |
1067 | * a second write to be sure the register | |
1068 | * is updated properly | |
1069 | */ | |
1070 | if (x86_pmu.perfctr_second_write) { | |
73d6e522 | 1071 | wrmsrl(hwc->event_base, |
948b1bb8 | 1072 | (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac | 1073 | } |
e4abb5d4 | 1074 | |
cdd6c482 | 1075 | perf_event_update_userpage(event); |
194002b2 | 1076 | |
e4abb5d4 | 1077 | return ret; |
2f18d1e8 IM |
1078 | } |
1079 | ||
aff3d91a | 1080 | static void x86_pmu_enable_event(struct perf_event *event) |
7c90cc45 | 1081 | { |
0a3aee0d | 1082 | if (__this_cpu_read(cpu_hw_events.enabled)) |
31fa58af RR |
1083 | __x86_pmu_enable_event(&event->hw, |
1084 | ARCH_PERFMON_EVENTSEL_ENABLE); | |
241771ef IM |
1085 | } |
1086 | ||
b690081d | 1087 | /* |
a4eaf7f1 | 1088 | * Add a single event to the PMU. |
1da53e02 SE |
1089 | * |
1090 | * The event is added to the group of enabled events | |
1091 | * but only if it can be scehduled with existing events. | |
fe9081cc | 1092 | */ |
a4eaf7f1 | 1093 | static int x86_pmu_add(struct perf_event *event, int flags) |
fe9081cc PZ |
1094 | { |
1095 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1da53e02 SE |
1096 | struct hw_perf_event *hwc; |
1097 | int assign[X86_PMC_IDX_MAX]; | |
1098 | int n, n0, ret; | |
fe9081cc | 1099 | |
1da53e02 | 1100 | hwc = &event->hw; |
fe9081cc | 1101 | |
33696fc0 | 1102 | perf_pmu_disable(event->pmu); |
1da53e02 | 1103 | n0 = cpuc->n_events; |
24cd7f54 PZ |
1104 | ret = n = collect_events(cpuc, event, false); |
1105 | if (ret < 0) | |
1106 | goto out; | |
53b441a5 | 1107 | |
a4eaf7f1 PZ |
1108 | hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; |
1109 | if (!(flags & PERF_EF_START)) | |
1110 | hwc->state |= PERF_HES_ARCH; | |
1111 | ||
4d1c52b0 LM |
1112 | /* |
1113 | * If group events scheduling transaction was started, | |
1114 | * skip the schedulability test here, it will be peformed | |
a4eaf7f1 | 1115 | * at commit time (->commit_txn) as a whole |
4d1c52b0 | 1116 | */ |
8d2cacbb | 1117 | if (cpuc->group_flag & PERF_EVENT_TXN) |
24cd7f54 | 1118 | goto done_collect; |
4d1c52b0 | 1119 | |
a072738e | 1120 | ret = x86_pmu.schedule_events(cpuc, n, assign); |
1da53e02 | 1121 | if (ret) |
24cd7f54 | 1122 | goto out; |
1da53e02 SE |
1123 | /* |
1124 | * copy new assignment, now we know it is possible | |
1125 | * will be used by hw_perf_enable() | |
1126 | */ | |
1127 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
7e2ae347 | 1128 | |
24cd7f54 | 1129 | done_collect: |
1da53e02 | 1130 | cpuc->n_events = n; |
356e1f2e | 1131 | cpuc->n_added += n - n0; |
90151c35 | 1132 | cpuc->n_txn += n - n0; |
95cdd2e7 | 1133 | |
24cd7f54 PZ |
1134 | ret = 0; |
1135 | out: | |
33696fc0 | 1136 | perf_pmu_enable(event->pmu); |
24cd7f54 | 1137 | return ret; |
241771ef IM |
1138 | } |
1139 | ||
a4eaf7f1 | 1140 | static void x86_pmu_start(struct perf_event *event, int flags) |
d76a0812 | 1141 | { |
c08053e6 PZ |
1142 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
1143 | int idx = event->hw.idx; | |
1144 | ||
a4eaf7f1 PZ |
1145 | if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) |
1146 | return; | |
1147 | ||
1148 | if (WARN_ON_ONCE(idx == -1)) | |
1149 | return; | |
1150 | ||
1151 | if (flags & PERF_EF_RELOAD) { | |
1152 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); | |
1153 | x86_perf_event_set_period(event); | |
1154 | } | |
1155 | ||
1156 | event->hw.state = 0; | |
d76a0812 | 1157 | |
c08053e6 PZ |
1158 | cpuc->events[idx] = event; |
1159 | __set_bit(idx, cpuc->active_mask); | |
63e6be6d | 1160 | __set_bit(idx, cpuc->running); |
aff3d91a | 1161 | x86_pmu.enable(event); |
c08053e6 | 1162 | perf_event_update_userpage(event); |
a78ac325 PZ |
1163 | } |
1164 | ||
cdd6c482 | 1165 | void perf_event_print_debug(void) |
241771ef | 1166 | { |
2f18d1e8 | 1167 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
ca037701 | 1168 | u64 pebs; |
cdd6c482 | 1169 | struct cpu_hw_events *cpuc; |
5bb9efe3 | 1170 | unsigned long flags; |
1e125676 IM |
1171 | int cpu, idx; |
1172 | ||
948b1bb8 | 1173 | if (!x86_pmu.num_counters) |
1e125676 | 1174 | return; |
241771ef | 1175 | |
5bb9efe3 | 1176 | local_irq_save(flags); |
241771ef IM |
1177 | |
1178 | cpu = smp_processor_id(); | |
cdd6c482 | 1179 | cpuc = &per_cpu(cpu_hw_events, cpu); |
241771ef | 1180 | |
faa28ae0 | 1181 | if (x86_pmu.version >= 2) { |
a1ef58f4 JSR |
1182 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
1183 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
1184 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
1185 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); | |
ca037701 | 1186 | rdmsrl(MSR_IA32_PEBS_ENABLE, pebs); |
a1ef58f4 JSR |
1187 | |
1188 | pr_info("\n"); | |
1189 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
1190 | pr_info("CPU#%d: status: %016llx\n", cpu, status); | |
1191 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); | |
1192 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); | |
ca037701 | 1193 | pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs); |
f87ad35d | 1194 | } |
7645a24c | 1195 | pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); |
241771ef | 1196 | |
948b1bb8 | 1197 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
41bf4989 RR |
1198 | rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl); |
1199 | rdmsrl(x86_pmu_event_addr(idx), pmc_count); | |
241771ef | 1200 | |
245b2e70 | 1201 | prev_left = per_cpu(pmc_prev_left[idx], cpu); |
241771ef | 1202 | |
a1ef58f4 | 1203 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 1204 | cpu, idx, pmc_ctrl); |
a1ef58f4 | 1205 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 1206 | cpu, idx, pmc_count); |
a1ef58f4 | 1207 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 1208 | cpu, idx, prev_left); |
241771ef | 1209 | } |
948b1bb8 | 1210 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { |
2f18d1e8 IM |
1211 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
1212 | ||
a1ef58f4 | 1213 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
2f18d1e8 IM |
1214 | cpu, idx, pmc_count); |
1215 | } | |
5bb9efe3 | 1216 | local_irq_restore(flags); |
241771ef IM |
1217 | } |
1218 | ||
a4eaf7f1 | 1219 | static void x86_pmu_stop(struct perf_event *event, int flags) |
241771ef | 1220 | { |
d76a0812 | 1221 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
cdd6c482 | 1222 | struct hw_perf_event *hwc = &event->hw; |
241771ef | 1223 | |
a4eaf7f1 PZ |
1224 | if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) { |
1225 | x86_pmu.disable(event); | |
1226 | cpuc->events[hwc->idx] = NULL; | |
1227 | WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); | |
1228 | hwc->state |= PERF_HES_STOPPED; | |
1229 | } | |
30dd568c | 1230 | |
a4eaf7f1 PZ |
1231 | if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { |
1232 | /* | |
1233 | * Drain the remaining delta count out of a event | |
1234 | * that we are disabling: | |
1235 | */ | |
1236 | x86_perf_event_update(event); | |
1237 | hwc->state |= PERF_HES_UPTODATE; | |
1238 | } | |
2e841873 PZ |
1239 | } |
1240 | ||
a4eaf7f1 | 1241 | static void x86_pmu_del(struct perf_event *event, int flags) |
2e841873 PZ |
1242 | { |
1243 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1244 | int i; | |
1245 | ||
90151c35 SE |
1246 | /* |
1247 | * If we're called during a txn, we don't need to do anything. | |
1248 | * The events never got scheduled and ->cancel_txn will truncate | |
1249 | * the event_list. | |
1250 | */ | |
8d2cacbb | 1251 | if (cpuc->group_flag & PERF_EVENT_TXN) |
90151c35 SE |
1252 | return; |
1253 | ||
a4eaf7f1 | 1254 | x86_pmu_stop(event, PERF_EF_UPDATE); |
194002b2 | 1255 | |
1da53e02 SE |
1256 | for (i = 0; i < cpuc->n_events; i++) { |
1257 | if (event == cpuc->event_list[i]) { | |
1258 | ||
1259 | if (x86_pmu.put_event_constraints) | |
1260 | x86_pmu.put_event_constraints(cpuc, event); | |
1261 | ||
1262 | while (++i < cpuc->n_events) | |
1263 | cpuc->event_list[i-1] = cpuc->event_list[i]; | |
1264 | ||
1265 | --cpuc->n_events; | |
6c9687ab | 1266 | break; |
1da53e02 SE |
1267 | } |
1268 | } | |
cdd6c482 | 1269 | perf_event_update_userpage(event); |
241771ef IM |
1270 | } |
1271 | ||
8c48e444 | 1272 | static int x86_pmu_handle_irq(struct pt_regs *regs) |
a29aa8a7 | 1273 | { |
df1a132b | 1274 | struct perf_sample_data data; |
cdd6c482 IM |
1275 | struct cpu_hw_events *cpuc; |
1276 | struct perf_event *event; | |
11d1578f | 1277 | int idx, handled = 0; |
9029a5e3 IM |
1278 | u64 val; |
1279 | ||
dc1d628a | 1280 | perf_sample_data_init(&data, 0); |
df1a132b | 1281 | |
cdd6c482 | 1282 | cpuc = &__get_cpu_var(cpu_hw_events); |
962bf7a6 | 1283 | |
948b1bb8 | 1284 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
63e6be6d RR |
1285 | if (!test_bit(idx, cpuc->active_mask)) { |
1286 | /* | |
1287 | * Though we deactivated the counter some cpus | |
1288 | * might still deliver spurious interrupts still | |
1289 | * in flight. Catch them: | |
1290 | */ | |
1291 | if (__test_and_clear_bit(idx, cpuc->running)) | |
1292 | handled++; | |
a29aa8a7 | 1293 | continue; |
63e6be6d | 1294 | } |
962bf7a6 | 1295 | |
cdd6c482 | 1296 | event = cpuc->events[idx]; |
a4016a79 | 1297 | |
cc2ad4ba | 1298 | val = x86_perf_event_update(event); |
948b1bb8 | 1299 | if (val & (1ULL << (x86_pmu.cntval_bits - 1))) |
48e22d56 | 1300 | continue; |
962bf7a6 | 1301 | |
9e350de3 | 1302 | /* |
cdd6c482 | 1303 | * event overflow |
9e350de3 | 1304 | */ |
4177c42a | 1305 | handled++; |
cdd6c482 | 1306 | data.period = event->hw.last_period; |
9e350de3 | 1307 | |
07088edb | 1308 | if (!x86_perf_event_set_period(event)) |
e4abb5d4 PZ |
1309 | continue; |
1310 | ||
cdd6c482 | 1311 | if (perf_event_overflow(event, 1, &data, regs)) |
a4eaf7f1 | 1312 | x86_pmu_stop(event, 0); |
a29aa8a7 | 1313 | } |
962bf7a6 | 1314 | |
9e350de3 PZ |
1315 | if (handled) |
1316 | inc_irq_stat(apic_perf_irqs); | |
1317 | ||
a29aa8a7 RR |
1318 | return handled; |
1319 | } | |
39d81eab | 1320 | |
cdd6c482 | 1321 | void perf_events_lapic_init(void) |
241771ef | 1322 | { |
04da8a43 | 1323 | if (!x86_pmu.apic || !x86_pmu_initialized()) |
241771ef | 1324 | return; |
85cf9dba | 1325 | |
241771ef | 1326 | /* |
c323d95f | 1327 | * Always use NMI for PMU |
241771ef | 1328 | */ |
c323d95f | 1329 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
241771ef IM |
1330 | } |
1331 | ||
4177c42a RR |
1332 | struct pmu_nmi_state { |
1333 | unsigned int marked; | |
1334 | int handled; | |
1335 | }; | |
1336 | ||
1337 | static DEFINE_PER_CPU(struct pmu_nmi_state, pmu_nmi); | |
1338 | ||
241771ef | 1339 | static int __kprobes |
cdd6c482 | 1340 | perf_event_nmi_handler(struct notifier_block *self, |
241771ef IM |
1341 | unsigned long cmd, void *__args) |
1342 | { | |
1343 | struct die_args *args = __args; | |
4177c42a RR |
1344 | unsigned int this_nmi; |
1345 | int handled; | |
b0f3f28e | 1346 | |
cdd6c482 | 1347 | if (!atomic_read(&active_events)) |
63a809a2 PZ |
1348 | return NOTIFY_DONE; |
1349 | ||
b0f3f28e PZ |
1350 | switch (cmd) { |
1351 | case DIE_NMI: | |
b0f3f28e | 1352 | break; |
4177c42a RR |
1353 | case DIE_NMIUNKNOWN: |
1354 | this_nmi = percpu_read(irq_stat.__nmi_count); | |
0a3aee0d | 1355 | if (this_nmi != __this_cpu_read(pmu_nmi.marked)) |
4177c42a RR |
1356 | /* let the kernel handle the unknown nmi */ |
1357 | return NOTIFY_DONE; | |
1358 | /* | |
1359 | * This one is a PMU back-to-back nmi. Two events | |
1360 | * trigger 'simultaneously' raising two back-to-back | |
1361 | * NMIs. If the first NMI handles both, the latter | |
1362 | * will be empty and daze the CPU. So, we drop it to | |
1363 | * avoid false-positive 'unknown nmi' messages. | |
1364 | */ | |
1365 | return NOTIFY_STOP; | |
b0f3f28e | 1366 | default: |
241771ef | 1367 | return NOTIFY_DONE; |
b0f3f28e | 1368 | } |
241771ef | 1369 | |
241771ef | 1370 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
4177c42a RR |
1371 | |
1372 | handled = x86_pmu.handle_irq(args->regs); | |
1373 | if (!handled) | |
1374 | return NOTIFY_DONE; | |
1375 | ||
1376 | this_nmi = percpu_read(irq_stat.__nmi_count); | |
1377 | if ((handled > 1) || | |
1378 | /* the next nmi could be a back-to-back nmi */ | |
0a3aee0d TH |
1379 | ((__this_cpu_read(pmu_nmi.marked) == this_nmi) && |
1380 | (__this_cpu_read(pmu_nmi.handled) > 1))) { | |
4177c42a RR |
1381 | /* |
1382 | * We could have two subsequent back-to-back nmis: The | |
1383 | * first handles more than one counter, the 2nd | |
1384 | * handles only one counter and the 3rd handles no | |
1385 | * counter. | |
1386 | * | |
1387 | * This is the 2nd nmi because the previous was | |
1388 | * handling more than one counter. We will mark the | |
1389 | * next (3rd) and then drop it if unhandled. | |
1390 | */ | |
0a3aee0d TH |
1391 | __this_cpu_write(pmu_nmi.marked, this_nmi + 1); |
1392 | __this_cpu_write(pmu_nmi.handled, handled); | |
4177c42a | 1393 | } |
241771ef | 1394 | |
a4016a79 | 1395 | return NOTIFY_STOP; |
241771ef IM |
1396 | } |
1397 | ||
f22f54f4 PZ |
1398 | static __read_mostly struct notifier_block perf_event_nmi_notifier = { |
1399 | .notifier_call = perf_event_nmi_handler, | |
1400 | .next = NULL, | |
166d7514 | 1401 | .priority = NMI_LOCAL_LOW_PRIOR, |
f22f54f4 PZ |
1402 | }; |
1403 | ||
63b14649 | 1404 | static struct event_constraint unconstrained; |
38331f62 | 1405 | static struct event_constraint emptyconstraint; |
63b14649 | 1406 | |
63b14649 | 1407 | static struct event_constraint * |
f22f54f4 | 1408 | x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event) |
1da53e02 | 1409 | { |
63b14649 | 1410 | struct event_constraint *c; |
1da53e02 | 1411 | |
1da53e02 SE |
1412 | if (x86_pmu.event_constraints) { |
1413 | for_each_event_constraint(c, x86_pmu.event_constraints) { | |
63b14649 PZ |
1414 | if ((event->hw.config & c->cmask) == c->code) |
1415 | return c; | |
1da53e02 SE |
1416 | } |
1417 | } | |
63b14649 PZ |
1418 | |
1419 | return &unconstrained; | |
1da53e02 SE |
1420 | } |
1421 | ||
f22f54f4 PZ |
1422 | #include "perf_event_amd.c" |
1423 | #include "perf_event_p6.c" | |
a072738e | 1424 | #include "perf_event_p4.c" |
caff2bef | 1425 | #include "perf_event_intel_lbr.c" |
ca037701 | 1426 | #include "perf_event_intel_ds.c" |
f22f54f4 | 1427 | #include "perf_event_intel.c" |
f87ad35d | 1428 | |
3f6da390 PZ |
1429 | static int __cpuinit |
1430 | x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) | |
1431 | { | |
1432 | unsigned int cpu = (long)hcpu; | |
b38b24ea | 1433 | int ret = NOTIFY_OK; |
3f6da390 PZ |
1434 | |
1435 | switch (action & ~CPU_TASKS_FROZEN) { | |
1436 | case CPU_UP_PREPARE: | |
1437 | if (x86_pmu.cpu_prepare) | |
b38b24ea | 1438 | ret = x86_pmu.cpu_prepare(cpu); |
3f6da390 PZ |
1439 | break; |
1440 | ||
1441 | case CPU_STARTING: | |
1442 | if (x86_pmu.cpu_starting) | |
1443 | x86_pmu.cpu_starting(cpu); | |
1444 | break; | |
1445 | ||
1446 | case CPU_DYING: | |
1447 | if (x86_pmu.cpu_dying) | |
1448 | x86_pmu.cpu_dying(cpu); | |
1449 | break; | |
1450 | ||
b38b24ea | 1451 | case CPU_UP_CANCELED: |
3f6da390 PZ |
1452 | case CPU_DEAD: |
1453 | if (x86_pmu.cpu_dead) | |
1454 | x86_pmu.cpu_dead(cpu); | |
1455 | break; | |
1456 | ||
1457 | default: | |
1458 | break; | |
1459 | } | |
1460 | ||
b38b24ea | 1461 | return ret; |
3f6da390 PZ |
1462 | } |
1463 | ||
12558038 CG |
1464 | static void __init pmu_check_apic(void) |
1465 | { | |
1466 | if (cpu_has_apic) | |
1467 | return; | |
1468 | ||
1469 | x86_pmu.apic = 0; | |
1470 | pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n"); | |
1471 | pr_info("no hardware sampling interrupt available.\n"); | |
1472 | } | |
1473 | ||
dda99116 | 1474 | static int __init init_hw_perf_events(void) |
b56a3802 | 1475 | { |
b622d644 | 1476 | struct event_constraint *c; |
72eae04d RR |
1477 | int err; |
1478 | ||
cdd6c482 | 1479 | pr_info("Performance Events: "); |
1123e3ad | 1480 | |
b56a3802 JSR |
1481 | switch (boot_cpu_data.x86_vendor) { |
1482 | case X86_VENDOR_INTEL: | |
72eae04d | 1483 | err = intel_pmu_init(); |
b56a3802 | 1484 | break; |
f87ad35d | 1485 | case X86_VENDOR_AMD: |
72eae04d | 1486 | err = amd_pmu_init(); |
f87ad35d | 1487 | break; |
4138960a | 1488 | default: |
004417a6 | 1489 | return 0; |
b56a3802 | 1490 | } |
1123e3ad | 1491 | if (err != 0) { |
cdd6c482 | 1492 | pr_cont("no PMU driver, software events only.\n"); |
004417a6 | 1493 | return 0; |
1123e3ad | 1494 | } |
b56a3802 | 1495 | |
12558038 CG |
1496 | pmu_check_apic(); |
1497 | ||
33c6d6a7 | 1498 | /* sanity check that the hardware exists or is emulated */ |
4407204c | 1499 | if (!check_hw_exists()) |
004417a6 | 1500 | return 0; |
33c6d6a7 | 1501 | |
1123e3ad | 1502 | pr_cont("%s PMU driver.\n", x86_pmu.name); |
faa28ae0 | 1503 | |
3c44780b PZ |
1504 | if (x86_pmu.quirks) |
1505 | x86_pmu.quirks(); | |
1506 | ||
948b1bb8 | 1507 | if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) { |
cdd6c482 | 1508 | WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", |
948b1bb8 RR |
1509 | x86_pmu.num_counters, X86_PMC_MAX_GENERIC); |
1510 | x86_pmu.num_counters = X86_PMC_MAX_GENERIC; | |
241771ef | 1511 | } |
948b1bb8 | 1512 | x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1; |
241771ef | 1513 | |
948b1bb8 | 1514 | if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) { |
cdd6c482 | 1515 | WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", |
948b1bb8 RR |
1516 | x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED); |
1517 | x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED; | |
703e937c | 1518 | } |
862a1a5f | 1519 | |
d6dc0b4e | 1520 | x86_pmu.intel_ctrl |= |
948b1bb8 | 1521 | ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED; |
241771ef | 1522 | |
cdd6c482 IM |
1523 | perf_events_lapic_init(); |
1524 | register_die_notifier(&perf_event_nmi_notifier); | |
1123e3ad | 1525 | |
63b14649 | 1526 | unconstrained = (struct event_constraint) |
948b1bb8 RR |
1527 | __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1, |
1528 | 0, x86_pmu.num_counters); | |
63b14649 | 1529 | |
b622d644 PZ |
1530 | if (x86_pmu.event_constraints) { |
1531 | for_each_event_constraint(c, x86_pmu.event_constraints) { | |
a098f448 | 1532 | if (c->cmask != X86_RAW_EVENT_MASK) |
b622d644 PZ |
1533 | continue; |
1534 | ||
948b1bb8 RR |
1535 | c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1; |
1536 | c->weight += x86_pmu.num_counters; | |
b622d644 PZ |
1537 | } |
1538 | } | |
1539 | ||
57c0c15b | 1540 | pr_info("... version: %d\n", x86_pmu.version); |
948b1bb8 RR |
1541 | pr_info("... bit width: %d\n", x86_pmu.cntval_bits); |
1542 | pr_info("... generic registers: %d\n", x86_pmu.num_counters); | |
1543 | pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask); | |
57c0c15b | 1544 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); |
948b1bb8 | 1545 | pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed); |
d6dc0b4e | 1546 | pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl); |
3f6da390 | 1547 | |
2e80a82a | 1548 | perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); |
3f6da390 | 1549 | perf_cpu_notifier(x86_pmu_notifier); |
004417a6 PZ |
1550 | |
1551 | return 0; | |
241771ef | 1552 | } |
004417a6 | 1553 | early_initcall(init_hw_perf_events); |
621a01ea | 1554 | |
cdd6c482 | 1555 | static inline void x86_pmu_read(struct perf_event *event) |
ee06094f | 1556 | { |
cc2ad4ba | 1557 | x86_perf_event_update(event); |
ee06094f IM |
1558 | } |
1559 | ||
4d1c52b0 LM |
1560 | /* |
1561 | * Start group events scheduling transaction | |
1562 | * Set the flag to make pmu::enable() not perform the | |
1563 | * schedulability test, it will be performed at commit time | |
1564 | */ | |
51b0fe39 | 1565 | static void x86_pmu_start_txn(struct pmu *pmu) |
4d1c52b0 | 1566 | { |
33696fc0 | 1567 | perf_pmu_disable(pmu); |
0a3aee0d TH |
1568 | __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN); |
1569 | __this_cpu_write(cpu_hw_events.n_txn, 0); | |
4d1c52b0 LM |
1570 | } |
1571 | ||
1572 | /* | |
1573 | * Stop group events scheduling transaction | |
1574 | * Clear the flag and pmu::enable() will perform the | |
1575 | * schedulability test. | |
1576 | */ | |
51b0fe39 | 1577 | static void x86_pmu_cancel_txn(struct pmu *pmu) |
4d1c52b0 | 1578 | { |
0a3aee0d | 1579 | __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN); |
90151c35 SE |
1580 | /* |
1581 | * Truncate the collected events. | |
1582 | */ | |
0a3aee0d TH |
1583 | __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn)); |
1584 | __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn)); | |
33696fc0 | 1585 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1586 | } |
1587 | ||
1588 | /* | |
1589 | * Commit group events scheduling transaction | |
1590 | * Perform the group schedulability test as a whole | |
1591 | * Return 0 if success | |
1592 | */ | |
51b0fe39 | 1593 | static int x86_pmu_commit_txn(struct pmu *pmu) |
4d1c52b0 LM |
1594 | { |
1595 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1596 | int assign[X86_PMC_IDX_MAX]; | |
1597 | int n, ret; | |
1598 | ||
1599 | n = cpuc->n_events; | |
1600 | ||
1601 | if (!x86_pmu_initialized()) | |
1602 | return -EAGAIN; | |
1603 | ||
1604 | ret = x86_pmu.schedule_events(cpuc, n, assign); | |
1605 | if (ret) | |
1606 | return ret; | |
1607 | ||
1608 | /* | |
1609 | * copy new assignment, now we know it is possible | |
1610 | * will be used by hw_perf_enable() | |
1611 | */ | |
1612 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
1613 | ||
8d2cacbb | 1614 | cpuc->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 1615 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1616 | return 0; |
1617 | } | |
1618 | ||
ca037701 PZ |
1619 | /* |
1620 | * validate that we can schedule this event | |
1621 | */ | |
1622 | static int validate_event(struct perf_event *event) | |
1623 | { | |
1624 | struct cpu_hw_events *fake_cpuc; | |
1625 | struct event_constraint *c; | |
1626 | int ret = 0; | |
1627 | ||
1628 | fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO); | |
1629 | if (!fake_cpuc) | |
1630 | return -ENOMEM; | |
1631 | ||
1632 | c = x86_pmu.get_event_constraints(fake_cpuc, event); | |
1633 | ||
1634 | if (!c || !c->weight) | |
1635 | ret = -ENOSPC; | |
1636 | ||
1637 | if (x86_pmu.put_event_constraints) | |
1638 | x86_pmu.put_event_constraints(fake_cpuc, event); | |
1639 | ||
1640 | kfree(fake_cpuc); | |
1641 | ||
1642 | return ret; | |
1643 | } | |
1644 | ||
1da53e02 SE |
1645 | /* |
1646 | * validate a single event group | |
1647 | * | |
1648 | * validation include: | |
184f412c IM |
1649 | * - check events are compatible which each other |
1650 | * - events do not compete for the same counter | |
1651 | * - number of events <= number of counters | |
1da53e02 SE |
1652 | * |
1653 | * validation ensures the group can be loaded onto the | |
1654 | * PMU if it was the only group available. | |
1655 | */ | |
fe9081cc PZ |
1656 | static int validate_group(struct perf_event *event) |
1657 | { | |
1da53e02 | 1658 | struct perf_event *leader = event->group_leader; |
502568d5 PZ |
1659 | struct cpu_hw_events *fake_cpuc; |
1660 | int ret, n; | |
fe9081cc | 1661 | |
502568d5 PZ |
1662 | ret = -ENOMEM; |
1663 | fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO); | |
1664 | if (!fake_cpuc) | |
1665 | goto out; | |
fe9081cc | 1666 | |
1da53e02 SE |
1667 | /* |
1668 | * the event is not yet connected with its | |
1669 | * siblings therefore we must first collect | |
1670 | * existing siblings, then add the new event | |
1671 | * before we can simulate the scheduling | |
1672 | */ | |
502568d5 PZ |
1673 | ret = -ENOSPC; |
1674 | n = collect_events(fake_cpuc, leader, true); | |
1da53e02 | 1675 | if (n < 0) |
502568d5 | 1676 | goto out_free; |
fe9081cc | 1677 | |
502568d5 PZ |
1678 | fake_cpuc->n_events = n; |
1679 | n = collect_events(fake_cpuc, event, false); | |
1da53e02 | 1680 | if (n < 0) |
502568d5 | 1681 | goto out_free; |
fe9081cc | 1682 | |
502568d5 | 1683 | fake_cpuc->n_events = n; |
1da53e02 | 1684 | |
a072738e | 1685 | ret = x86_pmu.schedule_events(fake_cpuc, n, NULL); |
502568d5 PZ |
1686 | |
1687 | out_free: | |
1688 | kfree(fake_cpuc); | |
1689 | out: | |
1690 | return ret; | |
fe9081cc PZ |
1691 | } |
1692 | ||
dda99116 | 1693 | static int x86_pmu_event_init(struct perf_event *event) |
621a01ea | 1694 | { |
51b0fe39 | 1695 | struct pmu *tmp; |
621a01ea IM |
1696 | int err; |
1697 | ||
b0a873eb PZ |
1698 | switch (event->attr.type) { |
1699 | case PERF_TYPE_RAW: | |
1700 | case PERF_TYPE_HARDWARE: | |
1701 | case PERF_TYPE_HW_CACHE: | |
1702 | break; | |
1703 | ||
1704 | default: | |
1705 | return -ENOENT; | |
1706 | } | |
1707 | ||
1708 | err = __x86_pmu_event_init(event); | |
fe9081cc | 1709 | if (!err) { |
8113070d SE |
1710 | /* |
1711 | * we temporarily connect event to its pmu | |
1712 | * such that validate_group() can classify | |
1713 | * it as an x86 event using is_x86_event() | |
1714 | */ | |
1715 | tmp = event->pmu; | |
1716 | event->pmu = &pmu; | |
1717 | ||
fe9081cc PZ |
1718 | if (event->group_leader != event) |
1719 | err = validate_group(event); | |
ca037701 PZ |
1720 | else |
1721 | err = validate_event(event); | |
8113070d SE |
1722 | |
1723 | event->pmu = tmp; | |
fe9081cc | 1724 | } |
a1792cda | 1725 | if (err) { |
cdd6c482 IM |
1726 | if (event->destroy) |
1727 | event->destroy(event); | |
a1792cda | 1728 | } |
621a01ea | 1729 | |
b0a873eb | 1730 | return err; |
621a01ea | 1731 | } |
d7d59fb3 | 1732 | |
b0a873eb | 1733 | static struct pmu pmu = { |
a4eaf7f1 PZ |
1734 | .pmu_enable = x86_pmu_enable, |
1735 | .pmu_disable = x86_pmu_disable, | |
1736 | ||
b0a873eb | 1737 | .event_init = x86_pmu_event_init, |
a4eaf7f1 PZ |
1738 | |
1739 | .add = x86_pmu_add, | |
1740 | .del = x86_pmu_del, | |
b0a873eb PZ |
1741 | .start = x86_pmu_start, |
1742 | .stop = x86_pmu_stop, | |
1743 | .read = x86_pmu_read, | |
a4eaf7f1 | 1744 | |
b0a873eb PZ |
1745 | .start_txn = x86_pmu_start_txn, |
1746 | .cancel_txn = x86_pmu_cancel_txn, | |
1747 | .commit_txn = x86_pmu_commit_txn, | |
1748 | }; | |
1749 | ||
d7d59fb3 PZ |
1750 | /* |
1751 | * callchain support | |
1752 | */ | |
1753 | ||
d7d59fb3 PZ |
1754 | static void |
1755 | backtrace_warning_symbol(void *data, char *msg, unsigned long symbol) | |
1756 | { | |
1757 | /* Ignore warnings */ | |
1758 | } | |
1759 | ||
1760 | static void backtrace_warning(void *data, char *msg) | |
1761 | { | |
1762 | /* Ignore warnings */ | |
1763 | } | |
1764 | ||
1765 | static int backtrace_stack(void *data, char *name) | |
1766 | { | |
038e836e | 1767 | return 0; |
d7d59fb3 PZ |
1768 | } |
1769 | ||
1770 | static void backtrace_address(void *data, unsigned long addr, int reliable) | |
1771 | { | |
1772 | struct perf_callchain_entry *entry = data; | |
1773 | ||
70791ce9 | 1774 | perf_callchain_store(entry, addr); |
d7d59fb3 PZ |
1775 | } |
1776 | ||
1777 | static const struct stacktrace_ops backtrace_ops = { | |
1778 | .warning = backtrace_warning, | |
1779 | .warning_symbol = backtrace_warning_symbol, | |
1780 | .stack = backtrace_stack, | |
1781 | .address = backtrace_address, | |
06d65bda | 1782 | .walk_stack = print_context_stack_bp, |
d7d59fb3 PZ |
1783 | }; |
1784 | ||
56962b44 FW |
1785 | void |
1786 | perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 | 1787 | { |
927c7a9e FW |
1788 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
1789 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 1790 | return; |
927c7a9e FW |
1791 | } |
1792 | ||
70791ce9 | 1793 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 1794 | |
9c0729dc | 1795 | dump_trace(NULL, regs, NULL, &backtrace_ops, entry); |
d7d59fb3 PZ |
1796 | } |
1797 | ||
257ef9d2 TE |
1798 | #ifdef CONFIG_COMPAT |
1799 | static inline int | |
1800 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
74193ef0 | 1801 | { |
257ef9d2 TE |
1802 | /* 32-bit process in 64-bit kernel. */ |
1803 | struct stack_frame_ia32 frame; | |
1804 | const void __user *fp; | |
74193ef0 | 1805 | |
257ef9d2 TE |
1806 | if (!test_thread_flag(TIF_IA32)) |
1807 | return 0; | |
1808 | ||
1809 | fp = compat_ptr(regs->bp); | |
1810 | while (entry->nr < PERF_MAX_STACK_DEPTH) { | |
1811 | unsigned long bytes; | |
1812 | frame.next_frame = 0; | |
1813 | frame.return_address = 0; | |
1814 | ||
1815 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); | |
1816 | if (bytes != sizeof(frame)) | |
1817 | break; | |
74193ef0 | 1818 | |
257ef9d2 TE |
1819 | if (fp < compat_ptr(regs->sp)) |
1820 | break; | |
74193ef0 | 1821 | |
70791ce9 | 1822 | perf_callchain_store(entry, frame.return_address); |
257ef9d2 TE |
1823 | fp = compat_ptr(frame.next_frame); |
1824 | } | |
1825 | return 1; | |
d7d59fb3 | 1826 | } |
257ef9d2 TE |
1827 | #else |
1828 | static inline int | |
1829 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1830 | { | |
1831 | return 0; | |
1832 | } | |
1833 | #endif | |
d7d59fb3 | 1834 | |
56962b44 FW |
1835 | void |
1836 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 PZ |
1837 | { |
1838 | struct stack_frame frame; | |
1839 | const void __user *fp; | |
1840 | ||
927c7a9e FW |
1841 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
1842 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 1843 | return; |
927c7a9e | 1844 | } |
5a6cec3a | 1845 | |
74193ef0 | 1846 | fp = (void __user *)regs->bp; |
d7d59fb3 | 1847 | |
70791ce9 | 1848 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 1849 | |
257ef9d2 TE |
1850 | if (perf_callchain_user32(regs, entry)) |
1851 | return; | |
1852 | ||
f9188e02 | 1853 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
257ef9d2 | 1854 | unsigned long bytes; |
038e836e | 1855 | frame.next_frame = NULL; |
d7d59fb3 PZ |
1856 | frame.return_address = 0; |
1857 | ||
257ef9d2 TE |
1858 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); |
1859 | if (bytes != sizeof(frame)) | |
d7d59fb3 PZ |
1860 | break; |
1861 | ||
5a6cec3a | 1862 | if ((unsigned long)fp < regs->sp) |
d7d59fb3 PZ |
1863 | break; |
1864 | ||
70791ce9 | 1865 | perf_callchain_store(entry, frame.return_address); |
038e836e | 1866 | fp = frame.next_frame; |
d7d59fb3 PZ |
1867 | } |
1868 | } | |
1869 | ||
39447b38 ZY |
1870 | unsigned long perf_instruction_pointer(struct pt_regs *regs) |
1871 | { | |
1872 | unsigned long ip; | |
dcf46b94 | 1873 | |
39447b38 ZY |
1874 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) |
1875 | ip = perf_guest_cbs->get_guest_ip(); | |
1876 | else | |
1877 | ip = instruction_pointer(regs); | |
dcf46b94 | 1878 | |
39447b38 ZY |
1879 | return ip; |
1880 | } | |
1881 | ||
1882 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
1883 | { | |
1884 | int misc = 0; | |
dcf46b94 | 1885 | |
39447b38 | 1886 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
dcf46b94 ZY |
1887 | if (perf_guest_cbs->is_user_mode()) |
1888 | misc |= PERF_RECORD_MISC_GUEST_USER; | |
1889 | else | |
1890 | misc |= PERF_RECORD_MISC_GUEST_KERNEL; | |
1891 | } else { | |
1892 | if (user_mode(regs)) | |
1893 | misc |= PERF_RECORD_MISC_USER; | |
1894 | else | |
1895 | misc |= PERF_RECORD_MISC_KERNEL; | |
1896 | } | |
1897 | ||
39447b38 | 1898 | if (regs->flags & PERF_EFLAGS_EXACT) |
ab608344 | 1899 | misc |= PERF_RECORD_MISC_EXACT_IP; |
39447b38 ZY |
1900 | |
1901 | return misc; | |
1902 | } |