Commit | Line | Data |
---|---|---|
241771ef | 1 | /* |
cdd6c482 | 2 | * Performance events x86 architecture code |
241771ef | 3 | * |
98144511 IM |
4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> | |
30dd568c | 9 | * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> |
1da53e02 | 10 | * Copyright (C) 2009 Google, Inc., Stephane Eranian |
241771ef IM |
11 | * |
12 | * For licencing details see kernel-base/COPYING | |
13 | */ | |
14 | ||
cdd6c482 | 15 | #include <linux/perf_event.h> |
241771ef IM |
16 | #include <linux/capability.h> |
17 | #include <linux/notifier.h> | |
18 | #include <linux/hardirq.h> | |
19 | #include <linux/kprobes.h> | |
4ac13294 | 20 | #include <linux/module.h> |
241771ef IM |
21 | #include <linux/kdebug.h> |
22 | #include <linux/sched.h> | |
d7d59fb3 | 23 | #include <linux/uaccess.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
74193ef0 | 25 | #include <linux/highmem.h> |
30dd568c | 26 | #include <linux/cpu.h> |
272d30be | 27 | #include <linux/bitops.h> |
241771ef | 28 | |
241771ef | 29 | #include <asm/apic.h> |
d7d59fb3 | 30 | #include <asm/stacktrace.h> |
4e935e47 | 31 | #include <asm/nmi.h> |
257ef9d2 | 32 | #include <asm/compat.h> |
241771ef | 33 | |
7645a24c PZ |
34 | #if 0 |
35 | #undef wrmsrl | |
36 | #define wrmsrl(msr, val) \ | |
37 | do { \ | |
38 | trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\ | |
39 | (unsigned long)(val)); \ | |
40 | native_write_msr((msr), (u32)((u64)(val)), \ | |
41 | (u32)((u64)(val) >> 32)); \ | |
42 | } while (0) | |
43 | #endif | |
44 | ||
ef21f683 PZ |
45 | /* |
46 | * best effort, GUP based copy_from_user() that assumes IRQ or NMI context | |
47 | */ | |
48 | static unsigned long | |
49 | copy_from_user_nmi(void *to, const void __user *from, unsigned long n) | |
50 | { | |
51 | unsigned long offset, addr = (unsigned long)from; | |
ef21f683 PZ |
52 | unsigned long size, len = 0; |
53 | struct page *page; | |
54 | void *map; | |
55 | int ret; | |
56 | ||
57 | do { | |
58 | ret = __get_user_pages_fast(addr, 1, 0, &page); | |
59 | if (!ret) | |
60 | break; | |
61 | ||
62 | offset = addr & (PAGE_SIZE - 1); | |
63 | size = min(PAGE_SIZE - offset, n - len); | |
64 | ||
7a837d1b | 65 | map = kmap_atomic(page); |
ef21f683 | 66 | memcpy(to, map+offset, size); |
7a837d1b | 67 | kunmap_atomic(map); |
ef21f683 PZ |
68 | put_page(page); |
69 | ||
70 | len += size; | |
71 | to += size; | |
72 | addr += size; | |
73 | ||
74 | } while (len < n); | |
75 | ||
76 | return len; | |
77 | } | |
78 | ||
1da53e02 | 79 | struct event_constraint { |
c91e0f5d PZ |
80 | union { |
81 | unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
b622d644 | 82 | u64 idxmsk64; |
c91e0f5d | 83 | }; |
b622d644 PZ |
84 | u64 code; |
85 | u64 cmask; | |
272d30be | 86 | int weight; |
1da53e02 SE |
87 | }; |
88 | ||
38331f62 SE |
89 | struct amd_nb { |
90 | int nb_id; /* NorthBridge id */ | |
91 | int refcnt; /* reference count */ | |
92 | struct perf_event *owners[X86_PMC_IDX_MAX]; | |
93 | struct event_constraint event_constraints[X86_PMC_IDX_MAX]; | |
94 | }; | |
95 | ||
a7e3ed1e AK |
96 | struct intel_percore; |
97 | ||
caff2bef PZ |
98 | #define MAX_LBR_ENTRIES 16 |
99 | ||
cdd6c482 | 100 | struct cpu_hw_events { |
ca037701 PZ |
101 | /* |
102 | * Generic x86 PMC bits | |
103 | */ | |
1da53e02 | 104 | struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */ |
43f6201a | 105 | unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
63e6be6d | 106 | unsigned long running[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
b0f3f28e | 107 | int enabled; |
241771ef | 108 | |
1da53e02 SE |
109 | int n_events; |
110 | int n_added; | |
90151c35 | 111 | int n_txn; |
1da53e02 | 112 | int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */ |
447a194b | 113 | u64 tags[X86_PMC_IDX_MAX]; |
1da53e02 | 114 | struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */ |
ca037701 | 115 | |
4d1c52b0 LM |
116 | unsigned int group_flag; |
117 | ||
ca037701 PZ |
118 | /* |
119 | * Intel DebugStore bits | |
120 | */ | |
121 | struct debug_store *ds; | |
122 | u64 pebs_enabled; | |
123 | ||
caff2bef PZ |
124 | /* |
125 | * Intel LBR bits | |
126 | */ | |
127 | int lbr_users; | |
128 | void *lbr_context; | |
129 | struct perf_branch_stack lbr_stack; | |
130 | struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES]; | |
131 | ||
a7e3ed1e AK |
132 | /* |
133 | * Intel percore register state. | |
134 | * Coordinate shared resources between HT threads. | |
135 | */ | |
136 | int percore_used; /* Used by this CPU? */ | |
137 | struct intel_percore *per_core; | |
138 | ||
ca037701 PZ |
139 | /* |
140 | * AMD specific bits | |
141 | */ | |
38331f62 | 142 | struct amd_nb *amd_nb; |
b690081d SE |
143 | }; |
144 | ||
fce877e3 | 145 | #define __EVENT_CONSTRAINT(c, n, m, w) {\ |
b622d644 | 146 | { .idxmsk64 = (n) }, \ |
c91e0f5d PZ |
147 | .code = (c), \ |
148 | .cmask = (m), \ | |
fce877e3 | 149 | .weight = (w), \ |
c91e0f5d | 150 | } |
b690081d | 151 | |
fce877e3 PZ |
152 | #define EVENT_CONSTRAINT(c, n, m) \ |
153 | __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n)) | |
154 | ||
ca037701 PZ |
155 | /* |
156 | * Constraint on the Event code. | |
157 | */ | |
ed8777fc | 158 | #define INTEL_EVENT_CONSTRAINT(c, n) \ |
a098f448 | 159 | EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT) |
8433be11 | 160 | |
ca037701 PZ |
161 | /* |
162 | * Constraint on the Event code + UMask + fixed-mask | |
a098f448 RR |
163 | * |
164 | * filter mask to validate fixed counter events. | |
165 | * the following filters disqualify for fixed counters: | |
166 | * - inv | |
167 | * - edge | |
168 | * - cnt-mask | |
169 | * The other filters are supported by fixed counters. | |
170 | * The any-thread option is supported starting with v3. | |
ca037701 | 171 | */ |
ed8777fc | 172 | #define FIXED_EVENT_CONSTRAINT(c, n) \ |
a098f448 | 173 | EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK) |
8433be11 | 174 | |
ca037701 PZ |
175 | /* |
176 | * Constraint on the Event code + UMask | |
177 | */ | |
b06b3d49 | 178 | #define INTEL_UEVENT_CONSTRAINT(c, n) \ |
ca037701 | 179 | EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK) |
b06b3d49 LM |
180 | #define PEBS_EVENT_CONSTRAINT(c, n) \ |
181 | INTEL_UEVENT_CONSTRAINT(c, n) | |
ca037701 | 182 | |
ed8777fc PZ |
183 | #define EVENT_CONSTRAINT_END \ |
184 | EVENT_CONSTRAINT(0, 0, 0) | |
185 | ||
186 | #define for_each_event_constraint(e, c) \ | |
a1f2b70a | 187 | for ((e) = (c); (e)->weight; (e)++) |
b690081d | 188 | |
a7e3ed1e AK |
189 | /* |
190 | * Extra registers for specific events. | |
191 | * Some events need large masks and require external MSRs. | |
192 | * Define a mapping to these extra registers. | |
193 | */ | |
194 | struct extra_reg { | |
195 | unsigned int event; | |
196 | unsigned int msr; | |
197 | u64 config_mask; | |
198 | u64 valid_mask; | |
199 | }; | |
200 | ||
201 | #define EVENT_EXTRA_REG(e, ms, m, vm) { \ | |
202 | .event = (e), \ | |
203 | .msr = (ms), \ | |
204 | .config_mask = (m), \ | |
205 | .valid_mask = (vm), \ | |
206 | } | |
207 | #define INTEL_EVENT_EXTRA_REG(event, msr, vm) \ | |
208 | EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm) | |
209 | #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0) | |
210 | ||
8db909a7 PZ |
211 | union perf_capabilities { |
212 | struct { | |
213 | u64 lbr_format : 6; | |
214 | u64 pebs_trap : 1; | |
215 | u64 pebs_arch_reg : 1; | |
216 | u64 pebs_format : 4; | |
217 | u64 smm_freeze : 1; | |
218 | }; | |
219 | u64 capabilities; | |
220 | }; | |
221 | ||
241771ef | 222 | /* |
5f4ec28f | 223 | * struct x86_pmu - generic x86 pmu |
241771ef | 224 | */ |
5f4ec28f | 225 | struct x86_pmu { |
ca037701 PZ |
226 | /* |
227 | * Generic x86 PMC bits | |
228 | */ | |
faa28ae0 RR |
229 | const char *name; |
230 | int version; | |
a3288106 | 231 | int (*handle_irq)(struct pt_regs *); |
9e35ad38 | 232 | void (*disable_all)(void); |
11164cd4 | 233 | void (*enable_all)(int added); |
aff3d91a PZ |
234 | void (*enable)(struct perf_event *); |
235 | void (*disable)(struct perf_event *); | |
b4cdc5c2 | 236 | int (*hw_config)(struct perf_event *event); |
a072738e | 237 | int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign); |
169e41eb JSR |
238 | unsigned eventsel; |
239 | unsigned perfctr; | |
b0f3f28e | 240 | u64 (*event_map)(int); |
169e41eb | 241 | int max_events; |
948b1bb8 RR |
242 | int num_counters; |
243 | int num_counters_fixed; | |
244 | int cntval_bits; | |
245 | u64 cntval_mask; | |
04da8a43 | 246 | int apic; |
c619b8ff | 247 | u64 max_period; |
63b14649 PZ |
248 | struct event_constraint * |
249 | (*get_event_constraints)(struct cpu_hw_events *cpuc, | |
250 | struct perf_event *event); | |
251 | ||
c91e0f5d PZ |
252 | void (*put_event_constraints)(struct cpu_hw_events *cpuc, |
253 | struct perf_event *event); | |
63b14649 | 254 | struct event_constraint *event_constraints; |
a7e3ed1e | 255 | struct event_constraint *percore_constraints; |
3c44780b | 256 | void (*quirks)(void); |
68aa00ac | 257 | int perfctr_second_write; |
3f6da390 | 258 | |
b38b24ea | 259 | int (*cpu_prepare)(int cpu); |
3f6da390 PZ |
260 | void (*cpu_starting)(int cpu); |
261 | void (*cpu_dying)(int cpu); | |
262 | void (*cpu_dead)(int cpu); | |
ca037701 PZ |
263 | |
264 | /* | |
265 | * Intel Arch Perfmon v2+ | |
266 | */ | |
8db909a7 PZ |
267 | u64 intel_ctrl; |
268 | union perf_capabilities intel_cap; | |
ca037701 PZ |
269 | |
270 | /* | |
271 | * Intel DebugStore bits | |
272 | */ | |
273 | int bts, pebs; | |
6809b6ea | 274 | int bts_active, pebs_active; |
ca037701 PZ |
275 | int pebs_record_size; |
276 | void (*drain_pebs)(struct pt_regs *regs); | |
277 | struct event_constraint *pebs_constraints; | |
caff2bef PZ |
278 | |
279 | /* | |
280 | * Intel LBR | |
281 | */ | |
282 | unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */ | |
283 | int lbr_nr; /* hardware stack size */ | |
a7e3ed1e AK |
284 | |
285 | /* | |
286 | * Extra registers for events | |
287 | */ | |
288 | struct extra_reg *extra_regs; | |
b56a3802 JSR |
289 | }; |
290 | ||
4a06bd85 | 291 | static struct x86_pmu x86_pmu __read_mostly; |
b56a3802 | 292 | |
cdd6c482 | 293 | static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { |
b0f3f28e PZ |
294 | .enabled = 1, |
295 | }; | |
241771ef | 296 | |
07088edb | 297 | static int x86_perf_event_set_period(struct perf_event *event); |
b690081d | 298 | |
8326f44d | 299 | /* |
dfc65094 | 300 | * Generalized hw caching related hw_event table, filled |
8326f44d | 301 | * in on a per model basis. A value of 0 means |
dfc65094 IM |
302 | * 'not supported', -1 means 'hw_event makes no sense on |
303 | * this CPU', any other value means the raw hw_event | |
8326f44d IM |
304 | * ID. |
305 | */ | |
306 | ||
307 | #define C(x) PERF_COUNT_HW_CACHE_##x | |
308 | ||
309 | static u64 __read_mostly hw_cache_event_ids | |
310 | [PERF_COUNT_HW_CACHE_MAX] | |
311 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
312 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
313 | ||
ee06094f | 314 | /* |
cdd6c482 IM |
315 | * Propagate event elapsed time into the generic event. |
316 | * Can only be executed on the CPU where the event is active. | |
ee06094f IM |
317 | * Returns the delta events processed. |
318 | */ | |
4b7bfd0d | 319 | static u64 |
cc2ad4ba | 320 | x86_perf_event_update(struct perf_event *event) |
ee06094f | 321 | { |
cc2ad4ba | 322 | struct hw_perf_event *hwc = &event->hw; |
948b1bb8 | 323 | int shift = 64 - x86_pmu.cntval_bits; |
ec3232bd | 324 | u64 prev_raw_count, new_raw_count; |
cc2ad4ba | 325 | int idx = hwc->idx; |
ec3232bd | 326 | s64 delta; |
ee06094f | 327 | |
30dd568c MM |
328 | if (idx == X86_PMC_IDX_FIXED_BTS) |
329 | return 0; | |
330 | ||
ee06094f | 331 | /* |
cdd6c482 | 332 | * Careful: an NMI might modify the previous event value. |
ee06094f IM |
333 | * |
334 | * Our tactic to handle this is to first atomically read and | |
335 | * exchange a new raw count - then add that new-prev delta | |
cdd6c482 | 336 | * count to the generic event atomically: |
ee06094f IM |
337 | */ |
338 | again: | |
e7850595 | 339 | prev_raw_count = local64_read(&hwc->prev_count); |
73d6e522 | 340 | rdmsrl(hwc->event_base, new_raw_count); |
ee06094f | 341 | |
e7850595 | 342 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
ee06094f IM |
343 | new_raw_count) != prev_raw_count) |
344 | goto again; | |
345 | ||
346 | /* | |
347 | * Now we have the new raw value and have updated the prev | |
348 | * timestamp already. We can now calculate the elapsed delta | |
cdd6c482 | 349 | * (event-)time and add that to the generic event. |
ee06094f IM |
350 | * |
351 | * Careful, not all hw sign-extends above the physical width | |
ec3232bd | 352 | * of the count. |
ee06094f | 353 | */ |
ec3232bd PZ |
354 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
355 | delta >>= shift; | |
ee06094f | 356 | |
e7850595 PZ |
357 | local64_add(delta, &event->count); |
358 | local64_sub(delta, &hwc->period_left); | |
4b7bfd0d RR |
359 | |
360 | return new_raw_count; | |
ee06094f IM |
361 | } |
362 | ||
4979d272 RR |
363 | /* using X86_FEATURE_PERFCTR_CORE to later implement ALTERNATIVE() here */ |
364 | static inline int x86_pmu_addr_offset(int index) | |
365 | { | |
366 | if (boot_cpu_has(X86_FEATURE_PERFCTR_CORE)) | |
367 | return index << 1; | |
368 | return index; | |
369 | } | |
370 | ||
41bf4989 RR |
371 | static inline unsigned int x86_pmu_config_addr(int index) |
372 | { | |
4979d272 | 373 | return x86_pmu.eventsel + x86_pmu_addr_offset(index); |
41bf4989 RR |
374 | } |
375 | ||
376 | static inline unsigned int x86_pmu_event_addr(int index) | |
377 | { | |
4979d272 | 378 | return x86_pmu.perfctr + x86_pmu_addr_offset(index); |
41bf4989 RR |
379 | } |
380 | ||
a7e3ed1e AK |
381 | /* |
382 | * Find and validate any extra registers to set up. | |
383 | */ | |
384 | static int x86_pmu_extra_regs(u64 config, struct perf_event *event) | |
385 | { | |
386 | struct extra_reg *er; | |
387 | ||
388 | event->hw.extra_reg = 0; | |
389 | event->hw.extra_config = 0; | |
390 | ||
391 | if (!x86_pmu.extra_regs) | |
392 | return 0; | |
393 | ||
394 | for (er = x86_pmu.extra_regs; er->msr; er++) { | |
395 | if (er->event != (config & er->config_mask)) | |
396 | continue; | |
397 | if (event->attr.config1 & ~er->valid_mask) | |
398 | return -EINVAL; | |
399 | event->hw.extra_reg = er->msr; | |
400 | event->hw.extra_config = event->attr.config1; | |
401 | break; | |
402 | } | |
403 | return 0; | |
404 | } | |
405 | ||
cdd6c482 | 406 | static atomic_t active_events; |
4e935e47 PZ |
407 | static DEFINE_MUTEX(pmc_reserve_mutex); |
408 | ||
b27ea29c RR |
409 | #ifdef CONFIG_X86_LOCAL_APIC |
410 | ||
4e935e47 PZ |
411 | static bool reserve_pmc_hardware(void) |
412 | { | |
413 | int i; | |
414 | ||
948b1bb8 | 415 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 | 416 | if (!reserve_perfctr_nmi(x86_pmu_event_addr(i))) |
4e935e47 PZ |
417 | goto perfctr_fail; |
418 | } | |
419 | ||
948b1bb8 | 420 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 | 421 | if (!reserve_evntsel_nmi(x86_pmu_config_addr(i))) |
4e935e47 PZ |
422 | goto eventsel_fail; |
423 | } | |
424 | ||
425 | return true; | |
426 | ||
427 | eventsel_fail: | |
428 | for (i--; i >= 0; i--) | |
41bf4989 | 429 | release_evntsel_nmi(x86_pmu_config_addr(i)); |
4e935e47 | 430 | |
948b1bb8 | 431 | i = x86_pmu.num_counters; |
4e935e47 PZ |
432 | |
433 | perfctr_fail: | |
434 | for (i--; i >= 0; i--) | |
41bf4989 | 435 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
4e935e47 | 436 | |
4e935e47 PZ |
437 | return false; |
438 | } | |
439 | ||
440 | static void release_pmc_hardware(void) | |
441 | { | |
442 | int i; | |
443 | ||
948b1bb8 | 444 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 RR |
445 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
446 | release_evntsel_nmi(x86_pmu_config_addr(i)); | |
4e935e47 | 447 | } |
4e935e47 PZ |
448 | } |
449 | ||
b27ea29c RR |
450 | #else |
451 | ||
452 | static bool reserve_pmc_hardware(void) { return true; } | |
453 | static void release_pmc_hardware(void) {} | |
454 | ||
455 | #endif | |
456 | ||
33c6d6a7 DZ |
457 | static bool check_hw_exists(void) |
458 | { | |
459 | u64 val, val_new = 0; | |
4407204c | 460 | int i, reg, ret = 0; |
33c6d6a7 | 461 | |
4407204c PZ |
462 | /* |
463 | * Check to see if the BIOS enabled any of the counters, if so | |
464 | * complain and bail. | |
465 | */ | |
466 | for (i = 0; i < x86_pmu.num_counters; i++) { | |
41bf4989 | 467 | reg = x86_pmu_config_addr(i); |
4407204c PZ |
468 | ret = rdmsrl_safe(reg, &val); |
469 | if (ret) | |
470 | goto msr_fail; | |
471 | if (val & ARCH_PERFMON_EVENTSEL_ENABLE) | |
472 | goto bios_fail; | |
473 | } | |
474 | ||
475 | if (x86_pmu.num_counters_fixed) { | |
476 | reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; | |
477 | ret = rdmsrl_safe(reg, &val); | |
478 | if (ret) | |
479 | goto msr_fail; | |
480 | for (i = 0; i < x86_pmu.num_counters_fixed; i++) { | |
481 | if (val & (0x03 << i*4)) | |
482 | goto bios_fail; | |
483 | } | |
484 | } | |
485 | ||
486 | /* | |
487 | * Now write a value and read it back to see if it matches, | |
488 | * this is needed to detect certain hardware emulators (qemu/kvm) | |
489 | * that don't trap on the MSR access and always return 0s. | |
490 | */ | |
33c6d6a7 | 491 | val = 0xabcdUL; |
41bf4989 RR |
492 | ret = checking_wrmsrl(x86_pmu_event_addr(0), val); |
493 | ret |= rdmsrl_safe(x86_pmu_event_addr(0), &val_new); | |
33c6d6a7 | 494 | if (ret || val != val_new) |
4407204c | 495 | goto msr_fail; |
33c6d6a7 DZ |
496 | |
497 | return true; | |
4407204c PZ |
498 | |
499 | bios_fail: | |
500 | printk(KERN_CONT "Broken BIOS detected, using software events only.\n"); | |
501 | printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg, val); | |
502 | return false; | |
503 | ||
504 | msr_fail: | |
505 | printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n"); | |
506 | return false; | |
33c6d6a7 DZ |
507 | } |
508 | ||
f80c9e30 | 509 | static void reserve_ds_buffers(void); |
ca037701 | 510 | static void release_ds_buffers(void); |
30dd568c | 511 | |
cdd6c482 | 512 | static void hw_perf_event_destroy(struct perf_event *event) |
4e935e47 | 513 | { |
cdd6c482 | 514 | if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) { |
4e935e47 | 515 | release_pmc_hardware(); |
ca037701 | 516 | release_ds_buffers(); |
4e935e47 PZ |
517 | mutex_unlock(&pmc_reserve_mutex); |
518 | } | |
519 | } | |
520 | ||
85cf9dba RR |
521 | static inline int x86_pmu_initialized(void) |
522 | { | |
523 | return x86_pmu.handle_irq != NULL; | |
524 | } | |
525 | ||
8326f44d | 526 | static inline int |
cdd6c482 | 527 | set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr) |
8326f44d IM |
528 | { |
529 | unsigned int cache_type, cache_op, cache_result; | |
530 | u64 config, val; | |
531 | ||
532 | config = attr->config; | |
533 | ||
534 | cache_type = (config >> 0) & 0xff; | |
535 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
536 | return -EINVAL; | |
537 | ||
538 | cache_op = (config >> 8) & 0xff; | |
539 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
540 | return -EINVAL; | |
541 | ||
542 | cache_result = (config >> 16) & 0xff; | |
543 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
544 | return -EINVAL; | |
545 | ||
546 | val = hw_cache_event_ids[cache_type][cache_op][cache_result]; | |
547 | ||
548 | if (val == 0) | |
549 | return -ENOENT; | |
550 | ||
551 | if (val == -1) | |
552 | return -EINVAL; | |
553 | ||
554 | hwc->config |= val; | |
555 | ||
556 | return 0; | |
557 | } | |
558 | ||
c1726f34 RR |
559 | static int x86_setup_perfctr(struct perf_event *event) |
560 | { | |
561 | struct perf_event_attr *attr = &event->attr; | |
562 | struct hw_perf_event *hwc = &event->hw; | |
563 | u64 config; | |
564 | ||
6c7e550f | 565 | if (!is_sampling_event(event)) { |
c1726f34 RR |
566 | hwc->sample_period = x86_pmu.max_period; |
567 | hwc->last_period = hwc->sample_period; | |
e7850595 | 568 | local64_set(&hwc->period_left, hwc->sample_period); |
c1726f34 RR |
569 | } else { |
570 | /* | |
571 | * If we have a PMU initialized but no APIC | |
572 | * interrupts, we cannot sample hardware | |
573 | * events (user-space has to fall back and | |
574 | * sample via a hrtimer based software event): | |
575 | */ | |
576 | if (!x86_pmu.apic) | |
577 | return -EOPNOTSUPP; | |
578 | } | |
579 | ||
580 | if (attr->type == PERF_TYPE_RAW) | |
581 | return 0; | |
582 | ||
583 | if (attr->type == PERF_TYPE_HW_CACHE) | |
584 | return set_ext_hw_attr(hwc, attr); | |
585 | ||
586 | if (attr->config >= x86_pmu.max_events) | |
587 | return -EINVAL; | |
588 | ||
589 | /* | |
590 | * The generic map: | |
591 | */ | |
592 | config = x86_pmu.event_map(attr->config); | |
593 | ||
594 | if (config == 0) | |
595 | return -ENOENT; | |
596 | ||
597 | if (config == -1LL) | |
598 | return -EINVAL; | |
599 | ||
600 | /* | |
601 | * Branch tracing: | |
602 | */ | |
603 | if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) && | |
604 | (hwc->sample_period == 1)) { | |
605 | /* BTS is not supported by this architecture. */ | |
6809b6ea | 606 | if (!x86_pmu.bts_active) |
c1726f34 RR |
607 | return -EOPNOTSUPP; |
608 | ||
609 | /* BTS is currently only allowed for user-mode. */ | |
610 | if (!attr->exclude_kernel) | |
611 | return -EOPNOTSUPP; | |
612 | } | |
613 | ||
614 | hwc->config |= config; | |
615 | ||
616 | return 0; | |
617 | } | |
4261e0e0 | 618 | |
b4cdc5c2 | 619 | static int x86_pmu_hw_config(struct perf_event *event) |
a072738e | 620 | { |
ab608344 PZ |
621 | if (event->attr.precise_ip) { |
622 | int precise = 0; | |
623 | ||
624 | /* Support for constant skid */ | |
6809b6ea | 625 | if (x86_pmu.pebs_active) { |
ab608344 PZ |
626 | precise++; |
627 | ||
5553be26 PZ |
628 | /* Support for IP fixup */ |
629 | if (x86_pmu.lbr_nr) | |
630 | precise++; | |
631 | } | |
ab608344 PZ |
632 | |
633 | if (event->attr.precise_ip > precise) | |
634 | return -EOPNOTSUPP; | |
635 | } | |
636 | ||
a072738e CG |
637 | /* |
638 | * Generate PMC IRQs: | |
639 | * (keep 'enabled' bit clear for now) | |
640 | */ | |
b4cdc5c2 | 641 | event->hw.config = ARCH_PERFMON_EVENTSEL_INT; |
a072738e CG |
642 | |
643 | /* | |
644 | * Count user and OS events unless requested not to | |
645 | */ | |
b4cdc5c2 PZ |
646 | if (!event->attr.exclude_user) |
647 | event->hw.config |= ARCH_PERFMON_EVENTSEL_USR; | |
648 | if (!event->attr.exclude_kernel) | |
649 | event->hw.config |= ARCH_PERFMON_EVENTSEL_OS; | |
a072738e | 650 | |
b4cdc5c2 PZ |
651 | if (event->attr.type == PERF_TYPE_RAW) |
652 | event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK; | |
a072738e | 653 | |
9d0fcba6 | 654 | return x86_setup_perfctr(event); |
a098f448 RR |
655 | } |
656 | ||
241771ef | 657 | /* |
0d48696f | 658 | * Setup the hardware configuration for a given attr_type |
241771ef | 659 | */ |
b0a873eb | 660 | static int __x86_pmu_event_init(struct perf_event *event) |
241771ef | 661 | { |
4e935e47 | 662 | int err; |
241771ef | 663 | |
85cf9dba RR |
664 | if (!x86_pmu_initialized()) |
665 | return -ENODEV; | |
241771ef | 666 | |
4e935e47 | 667 | err = 0; |
cdd6c482 | 668 | if (!atomic_inc_not_zero(&active_events)) { |
4e935e47 | 669 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 | 670 | if (atomic_read(&active_events) == 0) { |
30dd568c MM |
671 | if (!reserve_pmc_hardware()) |
672 | err = -EBUSY; | |
f80c9e30 PZ |
673 | else |
674 | reserve_ds_buffers(); | |
30dd568c MM |
675 | } |
676 | if (!err) | |
cdd6c482 | 677 | atomic_inc(&active_events); |
4e935e47 PZ |
678 | mutex_unlock(&pmc_reserve_mutex); |
679 | } | |
680 | if (err) | |
681 | return err; | |
682 | ||
cdd6c482 | 683 | event->destroy = hw_perf_event_destroy; |
a1792cda | 684 | |
4261e0e0 RR |
685 | event->hw.idx = -1; |
686 | event->hw.last_cpu = -1; | |
687 | event->hw.last_tag = ~0ULL; | |
b690081d | 688 | |
9d0fcba6 | 689 | return x86_pmu.hw_config(event); |
4261e0e0 RR |
690 | } |
691 | ||
8c48e444 | 692 | static void x86_pmu_disable_all(void) |
f87ad35d | 693 | { |
cdd6c482 | 694 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
9e35ad38 PZ |
695 | int idx; |
696 | ||
948b1bb8 | 697 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
b0f3f28e PZ |
698 | u64 val; |
699 | ||
43f6201a | 700 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 701 | continue; |
41bf4989 | 702 | rdmsrl(x86_pmu_config_addr(idx), val); |
bb1165d6 | 703 | if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE)) |
4295ee62 | 704 | continue; |
bb1165d6 | 705 | val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; |
41bf4989 | 706 | wrmsrl(x86_pmu_config_addr(idx), val); |
f87ad35d | 707 | } |
f87ad35d JSR |
708 | } |
709 | ||
a4eaf7f1 | 710 | static void x86_pmu_disable(struct pmu *pmu) |
b56a3802 | 711 | { |
1da53e02 SE |
712 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
713 | ||
85cf9dba | 714 | if (!x86_pmu_initialized()) |
9e35ad38 | 715 | return; |
1da53e02 | 716 | |
1a6e21f7 PZ |
717 | if (!cpuc->enabled) |
718 | return; | |
719 | ||
720 | cpuc->n_added = 0; | |
721 | cpuc->enabled = 0; | |
722 | barrier(); | |
1da53e02 SE |
723 | |
724 | x86_pmu.disable_all(); | |
b56a3802 | 725 | } |
241771ef | 726 | |
d45dd923 RR |
727 | static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, |
728 | u64 enable_mask) | |
729 | { | |
a7e3ed1e AK |
730 | if (hwc->extra_reg) |
731 | wrmsrl(hwc->extra_reg, hwc->extra_config); | |
73d6e522 | 732 | wrmsrl(hwc->config_base, hwc->config | enable_mask); |
d45dd923 RR |
733 | } |
734 | ||
11164cd4 | 735 | static void x86_pmu_enable_all(int added) |
f87ad35d | 736 | { |
cdd6c482 | 737 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
f87ad35d JSR |
738 | int idx; |
739 | ||
948b1bb8 | 740 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
d45dd923 | 741 | struct hw_perf_event *hwc = &cpuc->events[idx]->hw; |
b0f3f28e | 742 | |
43f6201a | 743 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 744 | continue; |
984b838c | 745 | |
d45dd923 | 746 | __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); |
f87ad35d JSR |
747 | } |
748 | } | |
749 | ||
51b0fe39 | 750 | static struct pmu pmu; |
1da53e02 SE |
751 | |
752 | static inline int is_x86_event(struct perf_event *event) | |
753 | { | |
754 | return event->pmu == &pmu; | |
755 | } | |
756 | ||
757 | static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) | |
758 | { | |
63b14649 | 759 | struct event_constraint *c, *constraints[X86_PMC_IDX_MAX]; |
1da53e02 | 760 | unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
c933c1a6 | 761 | int i, j, w, wmax, num = 0; |
1da53e02 SE |
762 | struct hw_perf_event *hwc; |
763 | ||
764 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); | |
765 | ||
766 | for (i = 0; i < n; i++) { | |
b622d644 PZ |
767 | c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]); |
768 | constraints[i] = c; | |
1da53e02 SE |
769 | } |
770 | ||
8113070d SE |
771 | /* |
772 | * fastpath, try to reuse previous register | |
773 | */ | |
c933c1a6 | 774 | for (i = 0; i < n; i++) { |
8113070d | 775 | hwc = &cpuc->event_list[i]->hw; |
81269a08 | 776 | c = constraints[i]; |
8113070d SE |
777 | |
778 | /* never assigned */ | |
779 | if (hwc->idx == -1) | |
780 | break; | |
781 | ||
782 | /* constraint still honored */ | |
63b14649 | 783 | if (!test_bit(hwc->idx, c->idxmsk)) |
8113070d SE |
784 | break; |
785 | ||
786 | /* not already used */ | |
787 | if (test_bit(hwc->idx, used_mask)) | |
788 | break; | |
789 | ||
34538ee7 | 790 | __set_bit(hwc->idx, used_mask); |
8113070d SE |
791 | if (assign) |
792 | assign[i] = hwc->idx; | |
793 | } | |
c933c1a6 | 794 | if (i == n) |
8113070d SE |
795 | goto done; |
796 | ||
797 | /* | |
798 | * begin slow path | |
799 | */ | |
800 | ||
801 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); | |
802 | ||
1da53e02 SE |
803 | /* |
804 | * weight = number of possible counters | |
805 | * | |
806 | * 1 = most constrained, only works on one counter | |
807 | * wmax = least constrained, works on any counter | |
808 | * | |
809 | * assign events to counters starting with most | |
810 | * constrained events. | |
811 | */ | |
948b1bb8 | 812 | wmax = x86_pmu.num_counters; |
1da53e02 SE |
813 | |
814 | /* | |
815 | * when fixed event counters are present, | |
816 | * wmax is incremented by 1 to account | |
817 | * for one more choice | |
818 | */ | |
948b1bb8 | 819 | if (x86_pmu.num_counters_fixed) |
1da53e02 SE |
820 | wmax++; |
821 | ||
8113070d | 822 | for (w = 1, num = n; num && w <= wmax; w++) { |
1da53e02 | 823 | /* for each event */ |
8113070d | 824 | for (i = 0; num && i < n; i++) { |
81269a08 | 825 | c = constraints[i]; |
1da53e02 SE |
826 | hwc = &cpuc->event_list[i]->hw; |
827 | ||
272d30be | 828 | if (c->weight != w) |
1da53e02 SE |
829 | continue; |
830 | ||
984b3f57 | 831 | for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) { |
1da53e02 SE |
832 | if (!test_bit(j, used_mask)) |
833 | break; | |
834 | } | |
835 | ||
836 | if (j == X86_PMC_IDX_MAX) | |
837 | break; | |
1da53e02 | 838 | |
34538ee7 | 839 | __set_bit(j, used_mask); |
8113070d | 840 | |
1da53e02 SE |
841 | if (assign) |
842 | assign[i] = j; | |
843 | num--; | |
844 | } | |
845 | } | |
8113070d | 846 | done: |
1da53e02 SE |
847 | /* |
848 | * scheduling failed or is just a simulation, | |
849 | * free resources if necessary | |
850 | */ | |
851 | if (!assign || num) { | |
852 | for (i = 0; i < n; i++) { | |
853 | if (x86_pmu.put_event_constraints) | |
854 | x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]); | |
855 | } | |
856 | } | |
857 | return num ? -ENOSPC : 0; | |
858 | } | |
859 | ||
860 | /* | |
861 | * dogrp: true if must collect siblings events (group) | |
862 | * returns total number of events and error code | |
863 | */ | |
864 | static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp) | |
865 | { | |
866 | struct perf_event *event; | |
867 | int n, max_count; | |
868 | ||
948b1bb8 | 869 | max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed; |
1da53e02 SE |
870 | |
871 | /* current number of events already accepted */ | |
872 | n = cpuc->n_events; | |
873 | ||
874 | if (is_x86_event(leader)) { | |
875 | if (n >= max_count) | |
876 | return -ENOSPC; | |
877 | cpuc->event_list[n] = leader; | |
878 | n++; | |
879 | } | |
880 | if (!dogrp) | |
881 | return n; | |
882 | ||
883 | list_for_each_entry(event, &leader->sibling_list, group_entry) { | |
884 | if (!is_x86_event(event) || | |
8113070d | 885 | event->state <= PERF_EVENT_STATE_OFF) |
1da53e02 SE |
886 | continue; |
887 | ||
888 | if (n >= max_count) | |
889 | return -ENOSPC; | |
890 | ||
891 | cpuc->event_list[n] = event; | |
892 | n++; | |
893 | } | |
894 | return n; | |
895 | } | |
896 | ||
1da53e02 | 897 | static inline void x86_assign_hw_event(struct perf_event *event, |
447a194b | 898 | struct cpu_hw_events *cpuc, int i) |
1da53e02 | 899 | { |
447a194b SE |
900 | struct hw_perf_event *hwc = &event->hw; |
901 | ||
902 | hwc->idx = cpuc->assign[i]; | |
903 | hwc->last_cpu = smp_processor_id(); | |
904 | hwc->last_tag = ++cpuc->tags[i]; | |
1da53e02 SE |
905 | |
906 | if (hwc->idx == X86_PMC_IDX_FIXED_BTS) { | |
907 | hwc->config_base = 0; | |
908 | hwc->event_base = 0; | |
909 | } else if (hwc->idx >= X86_PMC_IDX_FIXED) { | |
910 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; | |
73d6e522 | 911 | hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0; |
1da53e02 | 912 | } else { |
73d6e522 RR |
913 | hwc->config_base = x86_pmu_config_addr(hwc->idx); |
914 | hwc->event_base = x86_pmu_event_addr(hwc->idx); | |
1da53e02 SE |
915 | } |
916 | } | |
917 | ||
447a194b SE |
918 | static inline int match_prev_assignment(struct hw_perf_event *hwc, |
919 | struct cpu_hw_events *cpuc, | |
920 | int i) | |
921 | { | |
922 | return hwc->idx == cpuc->assign[i] && | |
923 | hwc->last_cpu == smp_processor_id() && | |
924 | hwc->last_tag == cpuc->tags[i]; | |
925 | } | |
926 | ||
a4eaf7f1 PZ |
927 | static void x86_pmu_start(struct perf_event *event, int flags); |
928 | static void x86_pmu_stop(struct perf_event *event, int flags); | |
2e841873 | 929 | |
a4eaf7f1 | 930 | static void x86_pmu_enable(struct pmu *pmu) |
ee06094f | 931 | { |
1da53e02 SE |
932 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
933 | struct perf_event *event; | |
934 | struct hw_perf_event *hwc; | |
11164cd4 | 935 | int i, added = cpuc->n_added; |
1da53e02 | 936 | |
85cf9dba | 937 | if (!x86_pmu_initialized()) |
2b9ff0db | 938 | return; |
1a6e21f7 PZ |
939 | |
940 | if (cpuc->enabled) | |
941 | return; | |
942 | ||
1da53e02 | 943 | if (cpuc->n_added) { |
19925ce7 | 944 | int n_running = cpuc->n_events - cpuc->n_added; |
1da53e02 SE |
945 | /* |
946 | * apply assignment obtained either from | |
947 | * hw_perf_group_sched_in() or x86_pmu_enable() | |
948 | * | |
949 | * step1: save events moving to new counters | |
950 | * step2: reprogram moved events into new counters | |
951 | */ | |
19925ce7 | 952 | for (i = 0; i < n_running; i++) { |
1da53e02 SE |
953 | event = cpuc->event_list[i]; |
954 | hwc = &event->hw; | |
955 | ||
447a194b SE |
956 | /* |
957 | * we can avoid reprogramming counter if: | |
958 | * - assigned same counter as last time | |
959 | * - running on same CPU as last time | |
960 | * - no other event has used the counter since | |
961 | */ | |
962 | if (hwc->idx == -1 || | |
963 | match_prev_assignment(hwc, cpuc, i)) | |
1da53e02 SE |
964 | continue; |
965 | ||
a4eaf7f1 PZ |
966 | /* |
967 | * Ensure we don't accidentally enable a stopped | |
968 | * counter simply because we rescheduled. | |
969 | */ | |
970 | if (hwc->state & PERF_HES_STOPPED) | |
971 | hwc->state |= PERF_HES_ARCH; | |
972 | ||
973 | x86_pmu_stop(event, PERF_EF_UPDATE); | |
1da53e02 SE |
974 | } |
975 | ||
976 | for (i = 0; i < cpuc->n_events; i++) { | |
1da53e02 SE |
977 | event = cpuc->event_list[i]; |
978 | hwc = &event->hw; | |
979 | ||
45e16a68 | 980 | if (!match_prev_assignment(hwc, cpuc, i)) |
447a194b | 981 | x86_assign_hw_event(event, cpuc, i); |
45e16a68 PZ |
982 | else if (i < n_running) |
983 | continue; | |
1da53e02 | 984 | |
a4eaf7f1 PZ |
985 | if (hwc->state & PERF_HES_ARCH) |
986 | continue; | |
987 | ||
988 | x86_pmu_start(event, PERF_EF_RELOAD); | |
1da53e02 SE |
989 | } |
990 | cpuc->n_added = 0; | |
991 | perf_events_lapic_init(); | |
992 | } | |
1a6e21f7 PZ |
993 | |
994 | cpuc->enabled = 1; | |
995 | barrier(); | |
996 | ||
11164cd4 | 997 | x86_pmu.enable_all(added); |
ee06094f | 998 | } |
ee06094f | 999 | |
aff3d91a | 1000 | static inline void x86_pmu_disable_event(struct perf_event *event) |
b0f3f28e | 1001 | { |
aff3d91a | 1002 | struct hw_perf_event *hwc = &event->hw; |
7645a24c | 1003 | |
73d6e522 | 1004 | wrmsrl(hwc->config_base, hwc->config); |
b0f3f28e PZ |
1005 | } |
1006 | ||
245b2e70 | 1007 | static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); |
241771ef | 1008 | |
ee06094f IM |
1009 | /* |
1010 | * Set the next IRQ period, based on the hwc->period_left value. | |
cdd6c482 | 1011 | * To be called with the event disabled in hw: |
ee06094f | 1012 | */ |
e4abb5d4 | 1013 | static int |
07088edb | 1014 | x86_perf_event_set_period(struct perf_event *event) |
241771ef | 1015 | { |
07088edb | 1016 | struct hw_perf_event *hwc = &event->hw; |
e7850595 | 1017 | s64 left = local64_read(&hwc->period_left); |
e4abb5d4 | 1018 | s64 period = hwc->sample_period; |
7645a24c | 1019 | int ret = 0, idx = hwc->idx; |
ee06094f | 1020 | |
30dd568c MM |
1021 | if (idx == X86_PMC_IDX_FIXED_BTS) |
1022 | return 0; | |
1023 | ||
ee06094f | 1024 | /* |
af901ca1 | 1025 | * If we are way outside a reasonable range then just skip forward: |
ee06094f IM |
1026 | */ |
1027 | if (unlikely(left <= -period)) { | |
1028 | left = period; | |
e7850595 | 1029 | local64_set(&hwc->period_left, left); |
9e350de3 | 1030 | hwc->last_period = period; |
e4abb5d4 | 1031 | ret = 1; |
ee06094f IM |
1032 | } |
1033 | ||
1034 | if (unlikely(left <= 0)) { | |
1035 | left += period; | |
e7850595 | 1036 | local64_set(&hwc->period_left, left); |
9e350de3 | 1037 | hwc->last_period = period; |
e4abb5d4 | 1038 | ret = 1; |
ee06094f | 1039 | } |
1c80f4b5 | 1040 | /* |
dfc65094 | 1041 | * Quirk: certain CPUs dont like it if just 1 hw_event is left: |
1c80f4b5 IM |
1042 | */ |
1043 | if (unlikely(left < 2)) | |
1044 | left = 2; | |
241771ef | 1045 | |
e4abb5d4 PZ |
1046 | if (left > x86_pmu.max_period) |
1047 | left = x86_pmu.max_period; | |
1048 | ||
245b2e70 | 1049 | per_cpu(pmc_prev_left[idx], smp_processor_id()) = left; |
ee06094f IM |
1050 | |
1051 | /* | |
cdd6c482 | 1052 | * The hw event starts counting from this event offset, |
ee06094f IM |
1053 | * mark it to be able to extra future deltas: |
1054 | */ | |
e7850595 | 1055 | local64_set(&hwc->prev_count, (u64)-left); |
ee06094f | 1056 | |
73d6e522 | 1057 | wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac CG |
1058 | |
1059 | /* | |
1060 | * Due to erratum on certan cpu we need | |
1061 | * a second write to be sure the register | |
1062 | * is updated properly | |
1063 | */ | |
1064 | if (x86_pmu.perfctr_second_write) { | |
73d6e522 | 1065 | wrmsrl(hwc->event_base, |
948b1bb8 | 1066 | (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac | 1067 | } |
e4abb5d4 | 1068 | |
cdd6c482 | 1069 | perf_event_update_userpage(event); |
194002b2 | 1070 | |
e4abb5d4 | 1071 | return ret; |
2f18d1e8 IM |
1072 | } |
1073 | ||
aff3d91a | 1074 | static void x86_pmu_enable_event(struct perf_event *event) |
7c90cc45 | 1075 | { |
0a3aee0d | 1076 | if (__this_cpu_read(cpu_hw_events.enabled)) |
31fa58af RR |
1077 | __x86_pmu_enable_event(&event->hw, |
1078 | ARCH_PERFMON_EVENTSEL_ENABLE); | |
241771ef IM |
1079 | } |
1080 | ||
b690081d | 1081 | /* |
a4eaf7f1 | 1082 | * Add a single event to the PMU. |
1da53e02 SE |
1083 | * |
1084 | * The event is added to the group of enabled events | |
1085 | * but only if it can be scehduled with existing events. | |
fe9081cc | 1086 | */ |
a4eaf7f1 | 1087 | static int x86_pmu_add(struct perf_event *event, int flags) |
fe9081cc PZ |
1088 | { |
1089 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1da53e02 SE |
1090 | struct hw_perf_event *hwc; |
1091 | int assign[X86_PMC_IDX_MAX]; | |
1092 | int n, n0, ret; | |
fe9081cc | 1093 | |
1da53e02 | 1094 | hwc = &event->hw; |
fe9081cc | 1095 | |
33696fc0 | 1096 | perf_pmu_disable(event->pmu); |
1da53e02 | 1097 | n0 = cpuc->n_events; |
24cd7f54 PZ |
1098 | ret = n = collect_events(cpuc, event, false); |
1099 | if (ret < 0) | |
1100 | goto out; | |
53b441a5 | 1101 | |
a4eaf7f1 PZ |
1102 | hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; |
1103 | if (!(flags & PERF_EF_START)) | |
1104 | hwc->state |= PERF_HES_ARCH; | |
1105 | ||
4d1c52b0 LM |
1106 | /* |
1107 | * If group events scheduling transaction was started, | |
1108 | * skip the schedulability test here, it will be peformed | |
a4eaf7f1 | 1109 | * at commit time (->commit_txn) as a whole |
4d1c52b0 | 1110 | */ |
8d2cacbb | 1111 | if (cpuc->group_flag & PERF_EVENT_TXN) |
24cd7f54 | 1112 | goto done_collect; |
4d1c52b0 | 1113 | |
a072738e | 1114 | ret = x86_pmu.schedule_events(cpuc, n, assign); |
1da53e02 | 1115 | if (ret) |
24cd7f54 | 1116 | goto out; |
1da53e02 SE |
1117 | /* |
1118 | * copy new assignment, now we know it is possible | |
1119 | * will be used by hw_perf_enable() | |
1120 | */ | |
1121 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
7e2ae347 | 1122 | |
24cd7f54 | 1123 | done_collect: |
1da53e02 | 1124 | cpuc->n_events = n; |
356e1f2e | 1125 | cpuc->n_added += n - n0; |
90151c35 | 1126 | cpuc->n_txn += n - n0; |
95cdd2e7 | 1127 | |
24cd7f54 PZ |
1128 | ret = 0; |
1129 | out: | |
33696fc0 | 1130 | perf_pmu_enable(event->pmu); |
24cd7f54 | 1131 | return ret; |
241771ef IM |
1132 | } |
1133 | ||
a4eaf7f1 | 1134 | static void x86_pmu_start(struct perf_event *event, int flags) |
d76a0812 | 1135 | { |
c08053e6 PZ |
1136 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
1137 | int idx = event->hw.idx; | |
1138 | ||
a4eaf7f1 PZ |
1139 | if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) |
1140 | return; | |
1141 | ||
1142 | if (WARN_ON_ONCE(idx == -1)) | |
1143 | return; | |
1144 | ||
1145 | if (flags & PERF_EF_RELOAD) { | |
1146 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); | |
1147 | x86_perf_event_set_period(event); | |
1148 | } | |
1149 | ||
1150 | event->hw.state = 0; | |
d76a0812 | 1151 | |
c08053e6 PZ |
1152 | cpuc->events[idx] = event; |
1153 | __set_bit(idx, cpuc->active_mask); | |
63e6be6d | 1154 | __set_bit(idx, cpuc->running); |
aff3d91a | 1155 | x86_pmu.enable(event); |
c08053e6 | 1156 | perf_event_update_userpage(event); |
a78ac325 PZ |
1157 | } |
1158 | ||
cdd6c482 | 1159 | void perf_event_print_debug(void) |
241771ef | 1160 | { |
2f18d1e8 | 1161 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
ca037701 | 1162 | u64 pebs; |
cdd6c482 | 1163 | struct cpu_hw_events *cpuc; |
5bb9efe3 | 1164 | unsigned long flags; |
1e125676 IM |
1165 | int cpu, idx; |
1166 | ||
948b1bb8 | 1167 | if (!x86_pmu.num_counters) |
1e125676 | 1168 | return; |
241771ef | 1169 | |
5bb9efe3 | 1170 | local_irq_save(flags); |
241771ef IM |
1171 | |
1172 | cpu = smp_processor_id(); | |
cdd6c482 | 1173 | cpuc = &per_cpu(cpu_hw_events, cpu); |
241771ef | 1174 | |
faa28ae0 | 1175 | if (x86_pmu.version >= 2) { |
a1ef58f4 JSR |
1176 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
1177 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
1178 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
1179 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); | |
ca037701 | 1180 | rdmsrl(MSR_IA32_PEBS_ENABLE, pebs); |
a1ef58f4 JSR |
1181 | |
1182 | pr_info("\n"); | |
1183 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
1184 | pr_info("CPU#%d: status: %016llx\n", cpu, status); | |
1185 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); | |
1186 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); | |
ca037701 | 1187 | pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs); |
f87ad35d | 1188 | } |
7645a24c | 1189 | pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); |
241771ef | 1190 | |
948b1bb8 | 1191 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
41bf4989 RR |
1192 | rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl); |
1193 | rdmsrl(x86_pmu_event_addr(idx), pmc_count); | |
241771ef | 1194 | |
245b2e70 | 1195 | prev_left = per_cpu(pmc_prev_left[idx], cpu); |
241771ef | 1196 | |
a1ef58f4 | 1197 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 1198 | cpu, idx, pmc_ctrl); |
a1ef58f4 | 1199 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 1200 | cpu, idx, pmc_count); |
a1ef58f4 | 1201 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 1202 | cpu, idx, prev_left); |
241771ef | 1203 | } |
948b1bb8 | 1204 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { |
2f18d1e8 IM |
1205 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
1206 | ||
a1ef58f4 | 1207 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
2f18d1e8 IM |
1208 | cpu, idx, pmc_count); |
1209 | } | |
5bb9efe3 | 1210 | local_irq_restore(flags); |
241771ef IM |
1211 | } |
1212 | ||
a4eaf7f1 | 1213 | static void x86_pmu_stop(struct perf_event *event, int flags) |
241771ef | 1214 | { |
d76a0812 | 1215 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
cdd6c482 | 1216 | struct hw_perf_event *hwc = &event->hw; |
241771ef | 1217 | |
a4eaf7f1 PZ |
1218 | if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) { |
1219 | x86_pmu.disable(event); | |
1220 | cpuc->events[hwc->idx] = NULL; | |
1221 | WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); | |
1222 | hwc->state |= PERF_HES_STOPPED; | |
1223 | } | |
30dd568c | 1224 | |
a4eaf7f1 PZ |
1225 | if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { |
1226 | /* | |
1227 | * Drain the remaining delta count out of a event | |
1228 | * that we are disabling: | |
1229 | */ | |
1230 | x86_perf_event_update(event); | |
1231 | hwc->state |= PERF_HES_UPTODATE; | |
1232 | } | |
2e841873 PZ |
1233 | } |
1234 | ||
a4eaf7f1 | 1235 | static void x86_pmu_del(struct perf_event *event, int flags) |
2e841873 PZ |
1236 | { |
1237 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1238 | int i; | |
1239 | ||
90151c35 SE |
1240 | /* |
1241 | * If we're called during a txn, we don't need to do anything. | |
1242 | * The events never got scheduled and ->cancel_txn will truncate | |
1243 | * the event_list. | |
1244 | */ | |
8d2cacbb | 1245 | if (cpuc->group_flag & PERF_EVENT_TXN) |
90151c35 SE |
1246 | return; |
1247 | ||
a4eaf7f1 | 1248 | x86_pmu_stop(event, PERF_EF_UPDATE); |
194002b2 | 1249 | |
1da53e02 SE |
1250 | for (i = 0; i < cpuc->n_events; i++) { |
1251 | if (event == cpuc->event_list[i]) { | |
1252 | ||
1253 | if (x86_pmu.put_event_constraints) | |
1254 | x86_pmu.put_event_constraints(cpuc, event); | |
1255 | ||
1256 | while (++i < cpuc->n_events) | |
1257 | cpuc->event_list[i-1] = cpuc->event_list[i]; | |
1258 | ||
1259 | --cpuc->n_events; | |
6c9687ab | 1260 | break; |
1da53e02 SE |
1261 | } |
1262 | } | |
cdd6c482 | 1263 | perf_event_update_userpage(event); |
241771ef IM |
1264 | } |
1265 | ||
8c48e444 | 1266 | static int x86_pmu_handle_irq(struct pt_regs *regs) |
a29aa8a7 | 1267 | { |
df1a132b | 1268 | struct perf_sample_data data; |
cdd6c482 IM |
1269 | struct cpu_hw_events *cpuc; |
1270 | struct perf_event *event; | |
11d1578f | 1271 | int idx, handled = 0; |
9029a5e3 IM |
1272 | u64 val; |
1273 | ||
dc1d628a | 1274 | perf_sample_data_init(&data, 0); |
df1a132b | 1275 | |
cdd6c482 | 1276 | cpuc = &__get_cpu_var(cpu_hw_events); |
962bf7a6 | 1277 | |
948b1bb8 | 1278 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
63e6be6d RR |
1279 | if (!test_bit(idx, cpuc->active_mask)) { |
1280 | /* | |
1281 | * Though we deactivated the counter some cpus | |
1282 | * might still deliver spurious interrupts still | |
1283 | * in flight. Catch them: | |
1284 | */ | |
1285 | if (__test_and_clear_bit(idx, cpuc->running)) | |
1286 | handled++; | |
a29aa8a7 | 1287 | continue; |
63e6be6d | 1288 | } |
962bf7a6 | 1289 | |
cdd6c482 | 1290 | event = cpuc->events[idx]; |
a4016a79 | 1291 | |
cc2ad4ba | 1292 | val = x86_perf_event_update(event); |
948b1bb8 | 1293 | if (val & (1ULL << (x86_pmu.cntval_bits - 1))) |
48e22d56 | 1294 | continue; |
962bf7a6 | 1295 | |
9e350de3 | 1296 | /* |
cdd6c482 | 1297 | * event overflow |
9e350de3 | 1298 | */ |
4177c42a | 1299 | handled++; |
cdd6c482 | 1300 | data.period = event->hw.last_period; |
9e350de3 | 1301 | |
07088edb | 1302 | if (!x86_perf_event_set_period(event)) |
e4abb5d4 PZ |
1303 | continue; |
1304 | ||
cdd6c482 | 1305 | if (perf_event_overflow(event, 1, &data, regs)) |
a4eaf7f1 | 1306 | x86_pmu_stop(event, 0); |
a29aa8a7 | 1307 | } |
962bf7a6 | 1308 | |
9e350de3 PZ |
1309 | if (handled) |
1310 | inc_irq_stat(apic_perf_irqs); | |
1311 | ||
a29aa8a7 RR |
1312 | return handled; |
1313 | } | |
39d81eab | 1314 | |
cdd6c482 | 1315 | void perf_events_lapic_init(void) |
241771ef | 1316 | { |
04da8a43 | 1317 | if (!x86_pmu.apic || !x86_pmu_initialized()) |
241771ef | 1318 | return; |
85cf9dba | 1319 | |
241771ef | 1320 | /* |
c323d95f | 1321 | * Always use NMI for PMU |
241771ef | 1322 | */ |
c323d95f | 1323 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
241771ef IM |
1324 | } |
1325 | ||
4177c42a RR |
1326 | struct pmu_nmi_state { |
1327 | unsigned int marked; | |
1328 | int handled; | |
1329 | }; | |
1330 | ||
1331 | static DEFINE_PER_CPU(struct pmu_nmi_state, pmu_nmi); | |
1332 | ||
241771ef | 1333 | static int __kprobes |
cdd6c482 | 1334 | perf_event_nmi_handler(struct notifier_block *self, |
241771ef IM |
1335 | unsigned long cmd, void *__args) |
1336 | { | |
1337 | struct die_args *args = __args; | |
4177c42a RR |
1338 | unsigned int this_nmi; |
1339 | int handled; | |
b0f3f28e | 1340 | |
cdd6c482 | 1341 | if (!atomic_read(&active_events)) |
63a809a2 PZ |
1342 | return NOTIFY_DONE; |
1343 | ||
b0f3f28e PZ |
1344 | switch (cmd) { |
1345 | case DIE_NMI: | |
b0f3f28e | 1346 | break; |
4177c42a RR |
1347 | case DIE_NMIUNKNOWN: |
1348 | this_nmi = percpu_read(irq_stat.__nmi_count); | |
0a3aee0d | 1349 | if (this_nmi != __this_cpu_read(pmu_nmi.marked)) |
4177c42a RR |
1350 | /* let the kernel handle the unknown nmi */ |
1351 | return NOTIFY_DONE; | |
1352 | /* | |
1353 | * This one is a PMU back-to-back nmi. Two events | |
1354 | * trigger 'simultaneously' raising two back-to-back | |
1355 | * NMIs. If the first NMI handles both, the latter | |
1356 | * will be empty and daze the CPU. So, we drop it to | |
1357 | * avoid false-positive 'unknown nmi' messages. | |
1358 | */ | |
1359 | return NOTIFY_STOP; | |
b0f3f28e | 1360 | default: |
241771ef | 1361 | return NOTIFY_DONE; |
b0f3f28e | 1362 | } |
241771ef | 1363 | |
241771ef | 1364 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
4177c42a RR |
1365 | |
1366 | handled = x86_pmu.handle_irq(args->regs); | |
1367 | if (!handled) | |
1368 | return NOTIFY_DONE; | |
1369 | ||
1370 | this_nmi = percpu_read(irq_stat.__nmi_count); | |
1371 | if ((handled > 1) || | |
1372 | /* the next nmi could be a back-to-back nmi */ | |
0a3aee0d TH |
1373 | ((__this_cpu_read(pmu_nmi.marked) == this_nmi) && |
1374 | (__this_cpu_read(pmu_nmi.handled) > 1))) { | |
4177c42a RR |
1375 | /* |
1376 | * We could have two subsequent back-to-back nmis: The | |
1377 | * first handles more than one counter, the 2nd | |
1378 | * handles only one counter and the 3rd handles no | |
1379 | * counter. | |
1380 | * | |
1381 | * This is the 2nd nmi because the previous was | |
1382 | * handling more than one counter. We will mark the | |
1383 | * next (3rd) and then drop it if unhandled. | |
1384 | */ | |
0a3aee0d TH |
1385 | __this_cpu_write(pmu_nmi.marked, this_nmi + 1); |
1386 | __this_cpu_write(pmu_nmi.handled, handled); | |
4177c42a | 1387 | } |
241771ef | 1388 | |
a4016a79 | 1389 | return NOTIFY_STOP; |
241771ef IM |
1390 | } |
1391 | ||
f22f54f4 PZ |
1392 | static __read_mostly struct notifier_block perf_event_nmi_notifier = { |
1393 | .notifier_call = perf_event_nmi_handler, | |
1394 | .next = NULL, | |
166d7514 | 1395 | .priority = NMI_LOCAL_LOW_PRIOR, |
f22f54f4 PZ |
1396 | }; |
1397 | ||
63b14649 | 1398 | static struct event_constraint unconstrained; |
38331f62 | 1399 | static struct event_constraint emptyconstraint; |
63b14649 | 1400 | |
63b14649 | 1401 | static struct event_constraint * |
f22f54f4 | 1402 | x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event) |
1da53e02 | 1403 | { |
63b14649 | 1404 | struct event_constraint *c; |
1da53e02 | 1405 | |
1da53e02 SE |
1406 | if (x86_pmu.event_constraints) { |
1407 | for_each_event_constraint(c, x86_pmu.event_constraints) { | |
63b14649 PZ |
1408 | if ((event->hw.config & c->cmask) == c->code) |
1409 | return c; | |
1da53e02 SE |
1410 | } |
1411 | } | |
63b14649 PZ |
1412 | |
1413 | return &unconstrained; | |
1da53e02 SE |
1414 | } |
1415 | ||
f22f54f4 PZ |
1416 | #include "perf_event_amd.c" |
1417 | #include "perf_event_p6.c" | |
a072738e | 1418 | #include "perf_event_p4.c" |
caff2bef | 1419 | #include "perf_event_intel_lbr.c" |
ca037701 | 1420 | #include "perf_event_intel_ds.c" |
f22f54f4 | 1421 | #include "perf_event_intel.c" |
f87ad35d | 1422 | |
3f6da390 PZ |
1423 | static int __cpuinit |
1424 | x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) | |
1425 | { | |
1426 | unsigned int cpu = (long)hcpu; | |
b38b24ea | 1427 | int ret = NOTIFY_OK; |
3f6da390 PZ |
1428 | |
1429 | switch (action & ~CPU_TASKS_FROZEN) { | |
1430 | case CPU_UP_PREPARE: | |
1431 | if (x86_pmu.cpu_prepare) | |
b38b24ea | 1432 | ret = x86_pmu.cpu_prepare(cpu); |
3f6da390 PZ |
1433 | break; |
1434 | ||
1435 | case CPU_STARTING: | |
1436 | if (x86_pmu.cpu_starting) | |
1437 | x86_pmu.cpu_starting(cpu); | |
1438 | break; | |
1439 | ||
1440 | case CPU_DYING: | |
1441 | if (x86_pmu.cpu_dying) | |
1442 | x86_pmu.cpu_dying(cpu); | |
1443 | break; | |
1444 | ||
b38b24ea | 1445 | case CPU_UP_CANCELED: |
3f6da390 PZ |
1446 | case CPU_DEAD: |
1447 | if (x86_pmu.cpu_dead) | |
1448 | x86_pmu.cpu_dead(cpu); | |
1449 | break; | |
1450 | ||
1451 | default: | |
1452 | break; | |
1453 | } | |
1454 | ||
b38b24ea | 1455 | return ret; |
3f6da390 PZ |
1456 | } |
1457 | ||
12558038 CG |
1458 | static void __init pmu_check_apic(void) |
1459 | { | |
1460 | if (cpu_has_apic) | |
1461 | return; | |
1462 | ||
1463 | x86_pmu.apic = 0; | |
1464 | pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n"); | |
1465 | pr_info("no hardware sampling interrupt available.\n"); | |
1466 | } | |
1467 | ||
dda99116 | 1468 | static int __init init_hw_perf_events(void) |
b56a3802 | 1469 | { |
b622d644 | 1470 | struct event_constraint *c; |
72eae04d RR |
1471 | int err; |
1472 | ||
cdd6c482 | 1473 | pr_info("Performance Events: "); |
1123e3ad | 1474 | |
b56a3802 JSR |
1475 | switch (boot_cpu_data.x86_vendor) { |
1476 | case X86_VENDOR_INTEL: | |
72eae04d | 1477 | err = intel_pmu_init(); |
b56a3802 | 1478 | break; |
f87ad35d | 1479 | case X86_VENDOR_AMD: |
72eae04d | 1480 | err = amd_pmu_init(); |
f87ad35d | 1481 | break; |
4138960a | 1482 | default: |
004417a6 | 1483 | return 0; |
b56a3802 | 1484 | } |
1123e3ad | 1485 | if (err != 0) { |
cdd6c482 | 1486 | pr_cont("no PMU driver, software events only.\n"); |
004417a6 | 1487 | return 0; |
1123e3ad | 1488 | } |
b56a3802 | 1489 | |
12558038 CG |
1490 | pmu_check_apic(); |
1491 | ||
33c6d6a7 | 1492 | /* sanity check that the hardware exists or is emulated */ |
4407204c | 1493 | if (!check_hw_exists()) |
004417a6 | 1494 | return 0; |
33c6d6a7 | 1495 | |
1123e3ad | 1496 | pr_cont("%s PMU driver.\n", x86_pmu.name); |
faa28ae0 | 1497 | |
3c44780b PZ |
1498 | if (x86_pmu.quirks) |
1499 | x86_pmu.quirks(); | |
1500 | ||
948b1bb8 | 1501 | if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) { |
cdd6c482 | 1502 | WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", |
948b1bb8 RR |
1503 | x86_pmu.num_counters, X86_PMC_MAX_GENERIC); |
1504 | x86_pmu.num_counters = X86_PMC_MAX_GENERIC; | |
241771ef | 1505 | } |
948b1bb8 | 1506 | x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1; |
241771ef | 1507 | |
948b1bb8 | 1508 | if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) { |
cdd6c482 | 1509 | WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", |
948b1bb8 RR |
1510 | x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED); |
1511 | x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED; | |
703e937c | 1512 | } |
862a1a5f | 1513 | |
d6dc0b4e | 1514 | x86_pmu.intel_ctrl |= |
948b1bb8 | 1515 | ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED; |
241771ef | 1516 | |
cdd6c482 IM |
1517 | perf_events_lapic_init(); |
1518 | register_die_notifier(&perf_event_nmi_notifier); | |
1123e3ad | 1519 | |
63b14649 | 1520 | unconstrained = (struct event_constraint) |
948b1bb8 RR |
1521 | __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1, |
1522 | 0, x86_pmu.num_counters); | |
63b14649 | 1523 | |
b622d644 PZ |
1524 | if (x86_pmu.event_constraints) { |
1525 | for_each_event_constraint(c, x86_pmu.event_constraints) { | |
a098f448 | 1526 | if (c->cmask != X86_RAW_EVENT_MASK) |
b622d644 PZ |
1527 | continue; |
1528 | ||
948b1bb8 RR |
1529 | c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1; |
1530 | c->weight += x86_pmu.num_counters; | |
b622d644 PZ |
1531 | } |
1532 | } | |
1533 | ||
57c0c15b | 1534 | pr_info("... version: %d\n", x86_pmu.version); |
948b1bb8 RR |
1535 | pr_info("... bit width: %d\n", x86_pmu.cntval_bits); |
1536 | pr_info("... generic registers: %d\n", x86_pmu.num_counters); | |
1537 | pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask); | |
57c0c15b | 1538 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); |
948b1bb8 | 1539 | pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed); |
d6dc0b4e | 1540 | pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl); |
3f6da390 | 1541 | |
2e80a82a | 1542 | perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); |
3f6da390 | 1543 | perf_cpu_notifier(x86_pmu_notifier); |
004417a6 PZ |
1544 | |
1545 | return 0; | |
241771ef | 1546 | } |
004417a6 | 1547 | early_initcall(init_hw_perf_events); |
621a01ea | 1548 | |
cdd6c482 | 1549 | static inline void x86_pmu_read(struct perf_event *event) |
ee06094f | 1550 | { |
cc2ad4ba | 1551 | x86_perf_event_update(event); |
ee06094f IM |
1552 | } |
1553 | ||
4d1c52b0 LM |
1554 | /* |
1555 | * Start group events scheduling transaction | |
1556 | * Set the flag to make pmu::enable() not perform the | |
1557 | * schedulability test, it will be performed at commit time | |
1558 | */ | |
51b0fe39 | 1559 | static void x86_pmu_start_txn(struct pmu *pmu) |
4d1c52b0 | 1560 | { |
33696fc0 | 1561 | perf_pmu_disable(pmu); |
0a3aee0d TH |
1562 | __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN); |
1563 | __this_cpu_write(cpu_hw_events.n_txn, 0); | |
4d1c52b0 LM |
1564 | } |
1565 | ||
1566 | /* | |
1567 | * Stop group events scheduling transaction | |
1568 | * Clear the flag and pmu::enable() will perform the | |
1569 | * schedulability test. | |
1570 | */ | |
51b0fe39 | 1571 | static void x86_pmu_cancel_txn(struct pmu *pmu) |
4d1c52b0 | 1572 | { |
0a3aee0d | 1573 | __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN); |
90151c35 SE |
1574 | /* |
1575 | * Truncate the collected events. | |
1576 | */ | |
0a3aee0d TH |
1577 | __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn)); |
1578 | __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn)); | |
33696fc0 | 1579 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1580 | } |
1581 | ||
1582 | /* | |
1583 | * Commit group events scheduling transaction | |
1584 | * Perform the group schedulability test as a whole | |
1585 | * Return 0 if success | |
1586 | */ | |
51b0fe39 | 1587 | static int x86_pmu_commit_txn(struct pmu *pmu) |
4d1c52b0 LM |
1588 | { |
1589 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1590 | int assign[X86_PMC_IDX_MAX]; | |
1591 | int n, ret; | |
1592 | ||
1593 | n = cpuc->n_events; | |
1594 | ||
1595 | if (!x86_pmu_initialized()) | |
1596 | return -EAGAIN; | |
1597 | ||
1598 | ret = x86_pmu.schedule_events(cpuc, n, assign); | |
1599 | if (ret) | |
1600 | return ret; | |
1601 | ||
1602 | /* | |
1603 | * copy new assignment, now we know it is possible | |
1604 | * will be used by hw_perf_enable() | |
1605 | */ | |
1606 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
1607 | ||
8d2cacbb | 1608 | cpuc->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 1609 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1610 | return 0; |
1611 | } | |
1612 | ||
ca037701 PZ |
1613 | /* |
1614 | * validate that we can schedule this event | |
1615 | */ | |
1616 | static int validate_event(struct perf_event *event) | |
1617 | { | |
1618 | struct cpu_hw_events *fake_cpuc; | |
1619 | struct event_constraint *c; | |
1620 | int ret = 0; | |
1621 | ||
1622 | fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO); | |
1623 | if (!fake_cpuc) | |
1624 | return -ENOMEM; | |
1625 | ||
1626 | c = x86_pmu.get_event_constraints(fake_cpuc, event); | |
1627 | ||
1628 | if (!c || !c->weight) | |
1629 | ret = -ENOSPC; | |
1630 | ||
1631 | if (x86_pmu.put_event_constraints) | |
1632 | x86_pmu.put_event_constraints(fake_cpuc, event); | |
1633 | ||
1634 | kfree(fake_cpuc); | |
1635 | ||
1636 | return ret; | |
1637 | } | |
1638 | ||
1da53e02 SE |
1639 | /* |
1640 | * validate a single event group | |
1641 | * | |
1642 | * validation include: | |
184f412c IM |
1643 | * - check events are compatible which each other |
1644 | * - events do not compete for the same counter | |
1645 | * - number of events <= number of counters | |
1da53e02 SE |
1646 | * |
1647 | * validation ensures the group can be loaded onto the | |
1648 | * PMU if it was the only group available. | |
1649 | */ | |
fe9081cc PZ |
1650 | static int validate_group(struct perf_event *event) |
1651 | { | |
1da53e02 | 1652 | struct perf_event *leader = event->group_leader; |
502568d5 PZ |
1653 | struct cpu_hw_events *fake_cpuc; |
1654 | int ret, n; | |
fe9081cc | 1655 | |
502568d5 PZ |
1656 | ret = -ENOMEM; |
1657 | fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO); | |
1658 | if (!fake_cpuc) | |
1659 | goto out; | |
fe9081cc | 1660 | |
1da53e02 SE |
1661 | /* |
1662 | * the event is not yet connected with its | |
1663 | * siblings therefore we must first collect | |
1664 | * existing siblings, then add the new event | |
1665 | * before we can simulate the scheduling | |
1666 | */ | |
502568d5 PZ |
1667 | ret = -ENOSPC; |
1668 | n = collect_events(fake_cpuc, leader, true); | |
1da53e02 | 1669 | if (n < 0) |
502568d5 | 1670 | goto out_free; |
fe9081cc | 1671 | |
502568d5 PZ |
1672 | fake_cpuc->n_events = n; |
1673 | n = collect_events(fake_cpuc, event, false); | |
1da53e02 | 1674 | if (n < 0) |
502568d5 | 1675 | goto out_free; |
fe9081cc | 1676 | |
502568d5 | 1677 | fake_cpuc->n_events = n; |
1da53e02 | 1678 | |
a072738e | 1679 | ret = x86_pmu.schedule_events(fake_cpuc, n, NULL); |
502568d5 PZ |
1680 | |
1681 | out_free: | |
1682 | kfree(fake_cpuc); | |
1683 | out: | |
1684 | return ret; | |
fe9081cc PZ |
1685 | } |
1686 | ||
dda99116 | 1687 | static int x86_pmu_event_init(struct perf_event *event) |
621a01ea | 1688 | { |
51b0fe39 | 1689 | struct pmu *tmp; |
621a01ea IM |
1690 | int err; |
1691 | ||
b0a873eb PZ |
1692 | switch (event->attr.type) { |
1693 | case PERF_TYPE_RAW: | |
1694 | case PERF_TYPE_HARDWARE: | |
1695 | case PERF_TYPE_HW_CACHE: | |
1696 | break; | |
1697 | ||
1698 | default: | |
1699 | return -ENOENT; | |
1700 | } | |
1701 | ||
1702 | err = __x86_pmu_event_init(event); | |
fe9081cc | 1703 | if (!err) { |
8113070d SE |
1704 | /* |
1705 | * we temporarily connect event to its pmu | |
1706 | * such that validate_group() can classify | |
1707 | * it as an x86 event using is_x86_event() | |
1708 | */ | |
1709 | tmp = event->pmu; | |
1710 | event->pmu = &pmu; | |
1711 | ||
fe9081cc PZ |
1712 | if (event->group_leader != event) |
1713 | err = validate_group(event); | |
ca037701 PZ |
1714 | else |
1715 | err = validate_event(event); | |
8113070d SE |
1716 | |
1717 | event->pmu = tmp; | |
fe9081cc | 1718 | } |
a1792cda | 1719 | if (err) { |
cdd6c482 IM |
1720 | if (event->destroy) |
1721 | event->destroy(event); | |
a1792cda | 1722 | } |
621a01ea | 1723 | |
b0a873eb | 1724 | return err; |
621a01ea | 1725 | } |
d7d59fb3 | 1726 | |
b0a873eb | 1727 | static struct pmu pmu = { |
a4eaf7f1 PZ |
1728 | .pmu_enable = x86_pmu_enable, |
1729 | .pmu_disable = x86_pmu_disable, | |
1730 | ||
b0a873eb | 1731 | .event_init = x86_pmu_event_init, |
a4eaf7f1 PZ |
1732 | |
1733 | .add = x86_pmu_add, | |
1734 | .del = x86_pmu_del, | |
b0a873eb PZ |
1735 | .start = x86_pmu_start, |
1736 | .stop = x86_pmu_stop, | |
1737 | .read = x86_pmu_read, | |
a4eaf7f1 | 1738 | |
b0a873eb PZ |
1739 | .start_txn = x86_pmu_start_txn, |
1740 | .cancel_txn = x86_pmu_cancel_txn, | |
1741 | .commit_txn = x86_pmu_commit_txn, | |
1742 | }; | |
1743 | ||
d7d59fb3 PZ |
1744 | /* |
1745 | * callchain support | |
1746 | */ | |
1747 | ||
d7d59fb3 PZ |
1748 | static void |
1749 | backtrace_warning_symbol(void *data, char *msg, unsigned long symbol) | |
1750 | { | |
1751 | /* Ignore warnings */ | |
1752 | } | |
1753 | ||
1754 | static void backtrace_warning(void *data, char *msg) | |
1755 | { | |
1756 | /* Ignore warnings */ | |
1757 | } | |
1758 | ||
1759 | static int backtrace_stack(void *data, char *name) | |
1760 | { | |
038e836e | 1761 | return 0; |
d7d59fb3 PZ |
1762 | } |
1763 | ||
1764 | static void backtrace_address(void *data, unsigned long addr, int reliable) | |
1765 | { | |
1766 | struct perf_callchain_entry *entry = data; | |
1767 | ||
70791ce9 | 1768 | perf_callchain_store(entry, addr); |
d7d59fb3 PZ |
1769 | } |
1770 | ||
1771 | static const struct stacktrace_ops backtrace_ops = { | |
1772 | .warning = backtrace_warning, | |
1773 | .warning_symbol = backtrace_warning_symbol, | |
1774 | .stack = backtrace_stack, | |
1775 | .address = backtrace_address, | |
06d65bda | 1776 | .walk_stack = print_context_stack_bp, |
d7d59fb3 PZ |
1777 | }; |
1778 | ||
56962b44 FW |
1779 | void |
1780 | perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 | 1781 | { |
927c7a9e FW |
1782 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
1783 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 1784 | return; |
927c7a9e FW |
1785 | } |
1786 | ||
70791ce9 | 1787 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 1788 | |
9c0729dc | 1789 | dump_trace(NULL, regs, NULL, &backtrace_ops, entry); |
d7d59fb3 PZ |
1790 | } |
1791 | ||
257ef9d2 TE |
1792 | #ifdef CONFIG_COMPAT |
1793 | static inline int | |
1794 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
74193ef0 | 1795 | { |
257ef9d2 TE |
1796 | /* 32-bit process in 64-bit kernel. */ |
1797 | struct stack_frame_ia32 frame; | |
1798 | const void __user *fp; | |
74193ef0 | 1799 | |
257ef9d2 TE |
1800 | if (!test_thread_flag(TIF_IA32)) |
1801 | return 0; | |
1802 | ||
1803 | fp = compat_ptr(regs->bp); | |
1804 | while (entry->nr < PERF_MAX_STACK_DEPTH) { | |
1805 | unsigned long bytes; | |
1806 | frame.next_frame = 0; | |
1807 | frame.return_address = 0; | |
1808 | ||
1809 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); | |
1810 | if (bytes != sizeof(frame)) | |
1811 | break; | |
74193ef0 | 1812 | |
257ef9d2 TE |
1813 | if (fp < compat_ptr(regs->sp)) |
1814 | break; | |
74193ef0 | 1815 | |
70791ce9 | 1816 | perf_callchain_store(entry, frame.return_address); |
257ef9d2 TE |
1817 | fp = compat_ptr(frame.next_frame); |
1818 | } | |
1819 | return 1; | |
d7d59fb3 | 1820 | } |
257ef9d2 TE |
1821 | #else |
1822 | static inline int | |
1823 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1824 | { | |
1825 | return 0; | |
1826 | } | |
1827 | #endif | |
d7d59fb3 | 1828 | |
56962b44 FW |
1829 | void |
1830 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 PZ |
1831 | { |
1832 | struct stack_frame frame; | |
1833 | const void __user *fp; | |
1834 | ||
927c7a9e FW |
1835 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
1836 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 1837 | return; |
927c7a9e | 1838 | } |
5a6cec3a | 1839 | |
74193ef0 | 1840 | fp = (void __user *)regs->bp; |
d7d59fb3 | 1841 | |
70791ce9 | 1842 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 1843 | |
257ef9d2 TE |
1844 | if (perf_callchain_user32(regs, entry)) |
1845 | return; | |
1846 | ||
f9188e02 | 1847 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
257ef9d2 | 1848 | unsigned long bytes; |
038e836e | 1849 | frame.next_frame = NULL; |
d7d59fb3 PZ |
1850 | frame.return_address = 0; |
1851 | ||
257ef9d2 TE |
1852 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); |
1853 | if (bytes != sizeof(frame)) | |
d7d59fb3 PZ |
1854 | break; |
1855 | ||
5a6cec3a | 1856 | if ((unsigned long)fp < regs->sp) |
d7d59fb3 PZ |
1857 | break; |
1858 | ||
70791ce9 | 1859 | perf_callchain_store(entry, frame.return_address); |
038e836e | 1860 | fp = frame.next_frame; |
d7d59fb3 PZ |
1861 | } |
1862 | } | |
1863 | ||
39447b38 ZY |
1864 | unsigned long perf_instruction_pointer(struct pt_regs *regs) |
1865 | { | |
1866 | unsigned long ip; | |
dcf46b94 | 1867 | |
39447b38 ZY |
1868 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) |
1869 | ip = perf_guest_cbs->get_guest_ip(); | |
1870 | else | |
1871 | ip = instruction_pointer(regs); | |
dcf46b94 | 1872 | |
39447b38 ZY |
1873 | return ip; |
1874 | } | |
1875 | ||
1876 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
1877 | { | |
1878 | int misc = 0; | |
dcf46b94 | 1879 | |
39447b38 | 1880 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
dcf46b94 ZY |
1881 | if (perf_guest_cbs->is_user_mode()) |
1882 | misc |= PERF_RECORD_MISC_GUEST_USER; | |
1883 | else | |
1884 | misc |= PERF_RECORD_MISC_GUEST_KERNEL; | |
1885 | } else { | |
1886 | if (user_mode(regs)) | |
1887 | misc |= PERF_RECORD_MISC_USER; | |
1888 | else | |
1889 | misc |= PERF_RECORD_MISC_KERNEL; | |
1890 | } | |
1891 | ||
39447b38 | 1892 | if (regs->flags & PERF_EFLAGS_EXACT) |
ab608344 | 1893 | misc |= PERF_RECORD_MISC_EXACT_IP; |
39447b38 ZY |
1894 | |
1895 | return misc; | |
1896 | } |