Commit | Line | Data |
---|---|---|
241771ef | 1 | /* |
cdd6c482 | 2 | * Performance events x86 architecture code |
241771ef | 3 | * |
98144511 IM |
4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> | |
30dd568c | 9 | * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> |
1da53e02 | 10 | * Copyright (C) 2009 Google, Inc., Stephane Eranian |
241771ef IM |
11 | * |
12 | * For licencing details see kernel-base/COPYING | |
13 | */ | |
14 | ||
cdd6c482 | 15 | #include <linux/perf_event.h> |
241771ef IM |
16 | #include <linux/capability.h> |
17 | #include <linux/notifier.h> | |
18 | #include <linux/hardirq.h> | |
19 | #include <linux/kprobes.h> | |
4ac13294 | 20 | #include <linux/module.h> |
241771ef IM |
21 | #include <linux/kdebug.h> |
22 | #include <linux/sched.h> | |
d7d59fb3 | 23 | #include <linux/uaccess.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
30dd568c | 25 | #include <linux/cpu.h> |
272d30be | 26 | #include <linux/bitops.h> |
0c9d42ed | 27 | #include <linux/device.h> |
241771ef | 28 | |
241771ef | 29 | #include <asm/apic.h> |
d7d59fb3 | 30 | #include <asm/stacktrace.h> |
4e935e47 | 31 | #include <asm/nmi.h> |
69092624 | 32 | #include <asm/smp.h> |
c8e5910e | 33 | #include <asm/alternative.h> |
e3f3541c | 34 | #include <asm/timer.h> |
d07bdfd3 PZ |
35 | #include <asm/desc.h> |
36 | #include <asm/ldt.h> | |
241771ef | 37 | |
de0428a7 KW |
38 | #include "perf_event.h" |
39 | ||
de0428a7 | 40 | struct x86_pmu x86_pmu __read_mostly; |
efc9f05d | 41 | |
de0428a7 | 42 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { |
b0f3f28e PZ |
43 | .enabled = 1, |
44 | }; | |
241771ef | 45 | |
de0428a7 | 46 | u64 __read_mostly hw_cache_event_ids |
8326f44d IM |
47 | [PERF_COUNT_HW_CACHE_MAX] |
48 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
49 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
de0428a7 | 50 | u64 __read_mostly hw_cache_extra_regs |
e994d7d2 AK |
51 | [PERF_COUNT_HW_CACHE_MAX] |
52 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
53 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
8326f44d | 54 | |
ee06094f | 55 | /* |
cdd6c482 IM |
56 | * Propagate event elapsed time into the generic event. |
57 | * Can only be executed on the CPU where the event is active. | |
ee06094f IM |
58 | * Returns the delta events processed. |
59 | */ | |
de0428a7 | 60 | u64 x86_perf_event_update(struct perf_event *event) |
ee06094f | 61 | { |
cc2ad4ba | 62 | struct hw_perf_event *hwc = &event->hw; |
948b1bb8 | 63 | int shift = 64 - x86_pmu.cntval_bits; |
ec3232bd | 64 | u64 prev_raw_count, new_raw_count; |
cc2ad4ba | 65 | int idx = hwc->idx; |
ec3232bd | 66 | s64 delta; |
ee06094f | 67 | |
15c7ad51 | 68 | if (idx == INTEL_PMC_IDX_FIXED_BTS) |
30dd568c MM |
69 | return 0; |
70 | ||
ee06094f | 71 | /* |
cdd6c482 | 72 | * Careful: an NMI might modify the previous event value. |
ee06094f IM |
73 | * |
74 | * Our tactic to handle this is to first atomically read and | |
75 | * exchange a new raw count - then add that new-prev delta | |
cdd6c482 | 76 | * count to the generic event atomically: |
ee06094f IM |
77 | */ |
78 | again: | |
e7850595 | 79 | prev_raw_count = local64_read(&hwc->prev_count); |
c48b6053 | 80 | rdpmcl(hwc->event_base_rdpmc, new_raw_count); |
ee06094f | 81 | |
e7850595 | 82 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
ee06094f IM |
83 | new_raw_count) != prev_raw_count) |
84 | goto again; | |
85 | ||
86 | /* | |
87 | * Now we have the new raw value and have updated the prev | |
88 | * timestamp already. We can now calculate the elapsed delta | |
cdd6c482 | 89 | * (event-)time and add that to the generic event. |
ee06094f IM |
90 | * |
91 | * Careful, not all hw sign-extends above the physical width | |
ec3232bd | 92 | * of the count. |
ee06094f | 93 | */ |
ec3232bd PZ |
94 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
95 | delta >>= shift; | |
ee06094f | 96 | |
e7850595 PZ |
97 | local64_add(delta, &event->count); |
98 | local64_sub(delta, &hwc->period_left); | |
4b7bfd0d RR |
99 | |
100 | return new_raw_count; | |
ee06094f IM |
101 | } |
102 | ||
a7e3ed1e AK |
103 | /* |
104 | * Find and validate any extra registers to set up. | |
105 | */ | |
106 | static int x86_pmu_extra_regs(u64 config, struct perf_event *event) | |
107 | { | |
efc9f05d | 108 | struct hw_perf_event_extra *reg; |
a7e3ed1e AK |
109 | struct extra_reg *er; |
110 | ||
efc9f05d | 111 | reg = &event->hw.extra_reg; |
a7e3ed1e AK |
112 | |
113 | if (!x86_pmu.extra_regs) | |
114 | return 0; | |
115 | ||
116 | for (er = x86_pmu.extra_regs; er->msr; er++) { | |
117 | if (er->event != (config & er->config_mask)) | |
118 | continue; | |
119 | if (event->attr.config1 & ~er->valid_mask) | |
120 | return -EINVAL; | |
338b522c KL |
121 | /* Check if the extra msrs can be safely accessed*/ |
122 | if (!er->extra_msr_access) | |
123 | return -ENXIO; | |
efc9f05d SE |
124 | |
125 | reg->idx = er->idx; | |
126 | reg->config = event->attr.config1; | |
127 | reg->reg = er->msr; | |
a7e3ed1e AK |
128 | break; |
129 | } | |
130 | return 0; | |
131 | } | |
132 | ||
cdd6c482 | 133 | static atomic_t active_events; |
4e935e47 PZ |
134 | static DEFINE_MUTEX(pmc_reserve_mutex); |
135 | ||
b27ea29c RR |
136 | #ifdef CONFIG_X86_LOCAL_APIC |
137 | ||
4e935e47 PZ |
138 | static bool reserve_pmc_hardware(void) |
139 | { | |
140 | int i; | |
141 | ||
948b1bb8 | 142 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 | 143 | if (!reserve_perfctr_nmi(x86_pmu_event_addr(i))) |
4e935e47 PZ |
144 | goto perfctr_fail; |
145 | } | |
146 | ||
948b1bb8 | 147 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 | 148 | if (!reserve_evntsel_nmi(x86_pmu_config_addr(i))) |
4e935e47 PZ |
149 | goto eventsel_fail; |
150 | } | |
151 | ||
152 | return true; | |
153 | ||
154 | eventsel_fail: | |
155 | for (i--; i >= 0; i--) | |
41bf4989 | 156 | release_evntsel_nmi(x86_pmu_config_addr(i)); |
4e935e47 | 157 | |
948b1bb8 | 158 | i = x86_pmu.num_counters; |
4e935e47 PZ |
159 | |
160 | perfctr_fail: | |
161 | for (i--; i >= 0; i--) | |
41bf4989 | 162 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
4e935e47 | 163 | |
4e935e47 PZ |
164 | return false; |
165 | } | |
166 | ||
167 | static void release_pmc_hardware(void) | |
168 | { | |
169 | int i; | |
170 | ||
948b1bb8 | 171 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 RR |
172 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
173 | release_evntsel_nmi(x86_pmu_config_addr(i)); | |
4e935e47 | 174 | } |
4e935e47 PZ |
175 | } |
176 | ||
b27ea29c RR |
177 | #else |
178 | ||
179 | static bool reserve_pmc_hardware(void) { return true; } | |
180 | static void release_pmc_hardware(void) {} | |
181 | ||
182 | #endif | |
183 | ||
33c6d6a7 DZ |
184 | static bool check_hw_exists(void) |
185 | { | |
a5ebe0ba GD |
186 | u64 val, val_fail, val_new= ~0; |
187 | int i, reg, reg_fail, ret = 0; | |
188 | int bios_fail = 0; | |
33c6d6a7 | 189 | |
4407204c PZ |
190 | /* |
191 | * Check to see if the BIOS enabled any of the counters, if so | |
192 | * complain and bail. | |
193 | */ | |
194 | for (i = 0; i < x86_pmu.num_counters; i++) { | |
41bf4989 | 195 | reg = x86_pmu_config_addr(i); |
4407204c PZ |
196 | ret = rdmsrl_safe(reg, &val); |
197 | if (ret) | |
198 | goto msr_fail; | |
a5ebe0ba GD |
199 | if (val & ARCH_PERFMON_EVENTSEL_ENABLE) { |
200 | bios_fail = 1; | |
201 | val_fail = val; | |
202 | reg_fail = reg; | |
203 | } | |
4407204c PZ |
204 | } |
205 | ||
206 | if (x86_pmu.num_counters_fixed) { | |
207 | reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; | |
208 | ret = rdmsrl_safe(reg, &val); | |
209 | if (ret) | |
210 | goto msr_fail; | |
211 | for (i = 0; i < x86_pmu.num_counters_fixed; i++) { | |
a5ebe0ba GD |
212 | if (val & (0x03 << i*4)) { |
213 | bios_fail = 1; | |
214 | val_fail = val; | |
215 | reg_fail = reg; | |
216 | } | |
4407204c PZ |
217 | } |
218 | } | |
219 | ||
220 | /* | |
bffd5fc2 AP |
221 | * Read the current value, change it and read it back to see if it |
222 | * matches, this is needed to detect certain hardware emulators | |
223 | * (qemu/kvm) that don't trap on the MSR access and always return 0s. | |
4407204c | 224 | */ |
f285f92f | 225 | reg = x86_pmu_event_addr(0); |
bffd5fc2 AP |
226 | if (rdmsrl_safe(reg, &val)) |
227 | goto msr_fail; | |
228 | val ^= 0xffffUL; | |
f285f92f RR |
229 | ret = wrmsrl_safe(reg, val); |
230 | ret |= rdmsrl_safe(reg, &val_new); | |
33c6d6a7 | 231 | if (ret || val != val_new) |
4407204c | 232 | goto msr_fail; |
33c6d6a7 | 233 | |
45daae57 IM |
234 | /* |
235 | * We still allow the PMU driver to operate: | |
236 | */ | |
a5ebe0ba GD |
237 | if (bios_fail) { |
238 | printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n"); | |
239 | printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg_fail, val_fail); | |
240 | } | |
45daae57 IM |
241 | |
242 | return true; | |
4407204c PZ |
243 | |
244 | msr_fail: | |
245 | printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n"); | |
f285f92f | 246 | printk(KERN_ERR "Failed to access perfctr msr (MSR %x is %Lx)\n", reg, val_new); |
45daae57 | 247 | |
4407204c | 248 | return false; |
33c6d6a7 DZ |
249 | } |
250 | ||
cdd6c482 | 251 | static void hw_perf_event_destroy(struct perf_event *event) |
4e935e47 | 252 | { |
cdd6c482 | 253 | if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) { |
4e935e47 | 254 | release_pmc_hardware(); |
ca037701 | 255 | release_ds_buffers(); |
4e935e47 PZ |
256 | mutex_unlock(&pmc_reserve_mutex); |
257 | } | |
258 | } | |
259 | ||
85cf9dba RR |
260 | static inline int x86_pmu_initialized(void) |
261 | { | |
262 | return x86_pmu.handle_irq != NULL; | |
263 | } | |
264 | ||
8326f44d | 265 | static inline int |
e994d7d2 | 266 | set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event) |
8326f44d | 267 | { |
e994d7d2 | 268 | struct perf_event_attr *attr = &event->attr; |
8326f44d IM |
269 | unsigned int cache_type, cache_op, cache_result; |
270 | u64 config, val; | |
271 | ||
272 | config = attr->config; | |
273 | ||
274 | cache_type = (config >> 0) & 0xff; | |
275 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
276 | return -EINVAL; | |
277 | ||
278 | cache_op = (config >> 8) & 0xff; | |
279 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
280 | return -EINVAL; | |
281 | ||
282 | cache_result = (config >> 16) & 0xff; | |
283 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
284 | return -EINVAL; | |
285 | ||
286 | val = hw_cache_event_ids[cache_type][cache_op][cache_result]; | |
287 | ||
288 | if (val == 0) | |
289 | return -ENOENT; | |
290 | ||
291 | if (val == -1) | |
292 | return -EINVAL; | |
293 | ||
294 | hwc->config |= val; | |
e994d7d2 AK |
295 | attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result]; |
296 | return x86_pmu_extra_regs(val, event); | |
8326f44d IM |
297 | } |
298 | ||
de0428a7 | 299 | int x86_setup_perfctr(struct perf_event *event) |
c1726f34 RR |
300 | { |
301 | struct perf_event_attr *attr = &event->attr; | |
302 | struct hw_perf_event *hwc = &event->hw; | |
303 | u64 config; | |
304 | ||
6c7e550f | 305 | if (!is_sampling_event(event)) { |
c1726f34 RR |
306 | hwc->sample_period = x86_pmu.max_period; |
307 | hwc->last_period = hwc->sample_period; | |
e7850595 | 308 | local64_set(&hwc->period_left, hwc->sample_period); |
c1726f34 RR |
309 | } |
310 | ||
311 | if (attr->type == PERF_TYPE_RAW) | |
ed13ec58 | 312 | return x86_pmu_extra_regs(event->attr.config, event); |
c1726f34 RR |
313 | |
314 | if (attr->type == PERF_TYPE_HW_CACHE) | |
e994d7d2 | 315 | return set_ext_hw_attr(hwc, event); |
c1726f34 RR |
316 | |
317 | if (attr->config >= x86_pmu.max_events) | |
318 | return -EINVAL; | |
319 | ||
320 | /* | |
321 | * The generic map: | |
322 | */ | |
323 | config = x86_pmu.event_map(attr->config); | |
324 | ||
325 | if (config == 0) | |
326 | return -ENOENT; | |
327 | ||
328 | if (config == -1LL) | |
329 | return -EINVAL; | |
330 | ||
331 | /* | |
332 | * Branch tracing: | |
333 | */ | |
18a073a3 PZ |
334 | if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS && |
335 | !attr->freq && hwc->sample_period == 1) { | |
c1726f34 | 336 | /* BTS is not supported by this architecture. */ |
6809b6ea | 337 | if (!x86_pmu.bts_active) |
c1726f34 RR |
338 | return -EOPNOTSUPP; |
339 | ||
340 | /* BTS is currently only allowed for user-mode. */ | |
341 | if (!attr->exclude_kernel) | |
342 | return -EOPNOTSUPP; | |
343 | } | |
344 | ||
345 | hwc->config |= config; | |
346 | ||
347 | return 0; | |
348 | } | |
4261e0e0 | 349 | |
ff3fb511 SE |
350 | /* |
351 | * check that branch_sample_type is compatible with | |
352 | * settings needed for precise_ip > 1 which implies | |
353 | * using the LBR to capture ALL taken branches at the | |
354 | * priv levels of the measurement | |
355 | */ | |
356 | static inline int precise_br_compat(struct perf_event *event) | |
357 | { | |
358 | u64 m = event->attr.branch_sample_type; | |
359 | u64 b = 0; | |
360 | ||
361 | /* must capture all branches */ | |
362 | if (!(m & PERF_SAMPLE_BRANCH_ANY)) | |
363 | return 0; | |
364 | ||
365 | m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER; | |
366 | ||
367 | if (!event->attr.exclude_user) | |
368 | b |= PERF_SAMPLE_BRANCH_USER; | |
369 | ||
370 | if (!event->attr.exclude_kernel) | |
371 | b |= PERF_SAMPLE_BRANCH_KERNEL; | |
372 | ||
373 | /* | |
374 | * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86 | |
375 | */ | |
376 | ||
377 | return m == b; | |
378 | } | |
379 | ||
de0428a7 | 380 | int x86_pmu_hw_config(struct perf_event *event) |
a072738e | 381 | { |
ab608344 PZ |
382 | if (event->attr.precise_ip) { |
383 | int precise = 0; | |
384 | ||
385 | /* Support for constant skid */ | |
c93dc84c | 386 | if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) { |
ab608344 PZ |
387 | precise++; |
388 | ||
5553be26 | 389 | /* Support for IP fixup */ |
03de874a | 390 | if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2) |
5553be26 PZ |
391 | precise++; |
392 | } | |
ab608344 PZ |
393 | |
394 | if (event->attr.precise_ip > precise) | |
395 | return -EOPNOTSUPP; | |
ff3fb511 SE |
396 | /* |
397 | * check that PEBS LBR correction does not conflict with | |
398 | * whatever the user is asking with attr->branch_sample_type | |
399 | */ | |
130768b8 AK |
400 | if (event->attr.precise_ip > 1 && |
401 | x86_pmu.intel_cap.pebs_format < 2) { | |
ff3fb511 SE |
402 | u64 *br_type = &event->attr.branch_sample_type; |
403 | ||
404 | if (has_branch_stack(event)) { | |
405 | if (!precise_br_compat(event)) | |
406 | return -EOPNOTSUPP; | |
407 | ||
408 | /* branch_sample_type is compatible */ | |
409 | ||
410 | } else { | |
411 | /* | |
412 | * user did not specify branch_sample_type | |
413 | * | |
414 | * For PEBS fixups, we capture all | |
415 | * the branches at the priv level of the | |
416 | * event. | |
417 | */ | |
418 | *br_type = PERF_SAMPLE_BRANCH_ANY; | |
419 | ||
420 | if (!event->attr.exclude_user) | |
421 | *br_type |= PERF_SAMPLE_BRANCH_USER; | |
422 | ||
423 | if (!event->attr.exclude_kernel) | |
424 | *br_type |= PERF_SAMPLE_BRANCH_KERNEL; | |
425 | } | |
426 | } | |
ab608344 PZ |
427 | } |
428 | ||
a072738e CG |
429 | /* |
430 | * Generate PMC IRQs: | |
431 | * (keep 'enabled' bit clear for now) | |
432 | */ | |
b4cdc5c2 | 433 | event->hw.config = ARCH_PERFMON_EVENTSEL_INT; |
a072738e CG |
434 | |
435 | /* | |
436 | * Count user and OS events unless requested not to | |
437 | */ | |
b4cdc5c2 PZ |
438 | if (!event->attr.exclude_user) |
439 | event->hw.config |= ARCH_PERFMON_EVENTSEL_USR; | |
440 | if (!event->attr.exclude_kernel) | |
441 | event->hw.config |= ARCH_PERFMON_EVENTSEL_OS; | |
a072738e | 442 | |
b4cdc5c2 PZ |
443 | if (event->attr.type == PERF_TYPE_RAW) |
444 | event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK; | |
a072738e | 445 | |
c46e665f AK |
446 | if (event->attr.sample_period && x86_pmu.limit_period) { |
447 | if (x86_pmu.limit_period(event, event->attr.sample_period) > | |
448 | event->attr.sample_period) | |
449 | return -EINVAL; | |
450 | } | |
451 | ||
9d0fcba6 | 452 | return x86_setup_perfctr(event); |
a098f448 RR |
453 | } |
454 | ||
241771ef | 455 | /* |
0d48696f | 456 | * Setup the hardware configuration for a given attr_type |
241771ef | 457 | */ |
b0a873eb | 458 | static int __x86_pmu_event_init(struct perf_event *event) |
241771ef | 459 | { |
4e935e47 | 460 | int err; |
241771ef | 461 | |
85cf9dba RR |
462 | if (!x86_pmu_initialized()) |
463 | return -ENODEV; | |
241771ef | 464 | |
4e935e47 | 465 | err = 0; |
cdd6c482 | 466 | if (!atomic_inc_not_zero(&active_events)) { |
4e935e47 | 467 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 | 468 | if (atomic_read(&active_events) == 0) { |
30dd568c MM |
469 | if (!reserve_pmc_hardware()) |
470 | err = -EBUSY; | |
f80c9e30 PZ |
471 | else |
472 | reserve_ds_buffers(); | |
30dd568c MM |
473 | } |
474 | if (!err) | |
cdd6c482 | 475 | atomic_inc(&active_events); |
4e935e47 PZ |
476 | mutex_unlock(&pmc_reserve_mutex); |
477 | } | |
478 | if (err) | |
479 | return err; | |
480 | ||
cdd6c482 | 481 | event->destroy = hw_perf_event_destroy; |
a1792cda | 482 | |
4261e0e0 RR |
483 | event->hw.idx = -1; |
484 | event->hw.last_cpu = -1; | |
485 | event->hw.last_tag = ~0ULL; | |
b690081d | 486 | |
efc9f05d SE |
487 | /* mark unused */ |
488 | event->hw.extra_reg.idx = EXTRA_REG_NONE; | |
b36817e8 SE |
489 | event->hw.branch_reg.idx = EXTRA_REG_NONE; |
490 | ||
9d0fcba6 | 491 | return x86_pmu.hw_config(event); |
4261e0e0 RR |
492 | } |
493 | ||
de0428a7 | 494 | void x86_pmu_disable_all(void) |
f87ad35d | 495 | { |
cdd6c482 | 496 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
9e35ad38 PZ |
497 | int idx; |
498 | ||
948b1bb8 | 499 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
b0f3f28e PZ |
500 | u64 val; |
501 | ||
43f6201a | 502 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 503 | continue; |
41bf4989 | 504 | rdmsrl(x86_pmu_config_addr(idx), val); |
bb1165d6 | 505 | if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE)) |
4295ee62 | 506 | continue; |
bb1165d6 | 507 | val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; |
41bf4989 | 508 | wrmsrl(x86_pmu_config_addr(idx), val); |
f87ad35d | 509 | } |
f87ad35d JSR |
510 | } |
511 | ||
a4eaf7f1 | 512 | static void x86_pmu_disable(struct pmu *pmu) |
b56a3802 | 513 | { |
1da53e02 SE |
514 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
515 | ||
85cf9dba | 516 | if (!x86_pmu_initialized()) |
9e35ad38 | 517 | return; |
1da53e02 | 518 | |
1a6e21f7 PZ |
519 | if (!cpuc->enabled) |
520 | return; | |
521 | ||
522 | cpuc->n_added = 0; | |
523 | cpuc->enabled = 0; | |
524 | barrier(); | |
1da53e02 SE |
525 | |
526 | x86_pmu.disable_all(); | |
b56a3802 | 527 | } |
241771ef | 528 | |
de0428a7 | 529 | void x86_pmu_enable_all(int added) |
f87ad35d | 530 | { |
cdd6c482 | 531 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
f87ad35d JSR |
532 | int idx; |
533 | ||
948b1bb8 | 534 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
d45dd923 | 535 | struct hw_perf_event *hwc = &cpuc->events[idx]->hw; |
b0f3f28e | 536 | |
43f6201a | 537 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 538 | continue; |
984b838c | 539 | |
d45dd923 | 540 | __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); |
f87ad35d JSR |
541 | } |
542 | } | |
543 | ||
51b0fe39 | 544 | static struct pmu pmu; |
1da53e02 SE |
545 | |
546 | static inline int is_x86_event(struct perf_event *event) | |
547 | { | |
548 | return event->pmu == &pmu; | |
549 | } | |
550 | ||
1e2ad28f RR |
551 | /* |
552 | * Event scheduler state: | |
553 | * | |
554 | * Assign events iterating over all events and counters, beginning | |
555 | * with events with least weights first. Keep the current iterator | |
556 | * state in struct sched_state. | |
557 | */ | |
558 | struct sched_state { | |
559 | int weight; | |
560 | int event; /* event index */ | |
561 | int counter; /* counter index */ | |
562 | int unassigned; /* number of events to be assigned left */ | |
563 | unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
564 | }; | |
565 | ||
bc1738f6 RR |
566 | /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */ |
567 | #define SCHED_STATES_MAX 2 | |
568 | ||
1e2ad28f RR |
569 | struct perf_sched { |
570 | int max_weight; | |
571 | int max_events; | |
43b45780 | 572 | struct perf_event **events; |
1e2ad28f | 573 | struct sched_state state; |
bc1738f6 RR |
574 | int saved_states; |
575 | struct sched_state saved[SCHED_STATES_MAX]; | |
1e2ad28f RR |
576 | }; |
577 | ||
578 | /* | |
579 | * Initialize interator that runs through all events and counters. | |
580 | */ | |
43b45780 | 581 | static void perf_sched_init(struct perf_sched *sched, struct perf_event **events, |
1e2ad28f RR |
582 | int num, int wmin, int wmax) |
583 | { | |
584 | int idx; | |
585 | ||
586 | memset(sched, 0, sizeof(*sched)); | |
587 | sched->max_events = num; | |
588 | sched->max_weight = wmax; | |
43b45780 | 589 | sched->events = events; |
1e2ad28f RR |
590 | |
591 | for (idx = 0; idx < num; idx++) { | |
43b45780 | 592 | if (events[idx]->hw.constraint->weight == wmin) |
1e2ad28f RR |
593 | break; |
594 | } | |
595 | ||
596 | sched->state.event = idx; /* start with min weight */ | |
597 | sched->state.weight = wmin; | |
598 | sched->state.unassigned = num; | |
599 | } | |
600 | ||
bc1738f6 RR |
601 | static void perf_sched_save_state(struct perf_sched *sched) |
602 | { | |
603 | if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX)) | |
604 | return; | |
605 | ||
606 | sched->saved[sched->saved_states] = sched->state; | |
607 | sched->saved_states++; | |
608 | } | |
609 | ||
610 | static bool perf_sched_restore_state(struct perf_sched *sched) | |
611 | { | |
612 | if (!sched->saved_states) | |
613 | return false; | |
614 | ||
615 | sched->saved_states--; | |
616 | sched->state = sched->saved[sched->saved_states]; | |
617 | ||
618 | /* continue with next counter: */ | |
619 | clear_bit(sched->state.counter++, sched->state.used); | |
620 | ||
621 | return true; | |
622 | } | |
623 | ||
1e2ad28f RR |
624 | /* |
625 | * Select a counter for the current event to schedule. Return true on | |
626 | * success. | |
627 | */ | |
bc1738f6 | 628 | static bool __perf_sched_find_counter(struct perf_sched *sched) |
1e2ad28f RR |
629 | { |
630 | struct event_constraint *c; | |
631 | int idx; | |
632 | ||
633 | if (!sched->state.unassigned) | |
634 | return false; | |
635 | ||
636 | if (sched->state.event >= sched->max_events) | |
637 | return false; | |
638 | ||
43b45780 | 639 | c = sched->events[sched->state.event]->hw.constraint; |
4defea85 | 640 | /* Prefer fixed purpose counters */ |
15c7ad51 RR |
641 | if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) { |
642 | idx = INTEL_PMC_IDX_FIXED; | |
307b1cd7 | 643 | for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) { |
4defea85 PZ |
644 | if (!__test_and_set_bit(idx, sched->state.used)) |
645 | goto done; | |
646 | } | |
647 | } | |
1e2ad28f RR |
648 | /* Grab the first unused counter starting with idx */ |
649 | idx = sched->state.counter; | |
15c7ad51 | 650 | for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) { |
1e2ad28f | 651 | if (!__test_and_set_bit(idx, sched->state.used)) |
4defea85 | 652 | goto done; |
1e2ad28f | 653 | } |
1e2ad28f | 654 | |
4defea85 PZ |
655 | return false; |
656 | ||
657 | done: | |
658 | sched->state.counter = idx; | |
1e2ad28f | 659 | |
bc1738f6 RR |
660 | if (c->overlap) |
661 | perf_sched_save_state(sched); | |
662 | ||
663 | return true; | |
664 | } | |
665 | ||
666 | static bool perf_sched_find_counter(struct perf_sched *sched) | |
667 | { | |
668 | while (!__perf_sched_find_counter(sched)) { | |
669 | if (!perf_sched_restore_state(sched)) | |
670 | return false; | |
671 | } | |
672 | ||
1e2ad28f RR |
673 | return true; |
674 | } | |
675 | ||
676 | /* | |
677 | * Go through all unassigned events and find the next one to schedule. | |
678 | * Take events with the least weight first. Return true on success. | |
679 | */ | |
680 | static bool perf_sched_next_event(struct perf_sched *sched) | |
681 | { | |
682 | struct event_constraint *c; | |
683 | ||
684 | if (!sched->state.unassigned || !--sched->state.unassigned) | |
685 | return false; | |
686 | ||
687 | do { | |
688 | /* next event */ | |
689 | sched->state.event++; | |
690 | if (sched->state.event >= sched->max_events) { | |
691 | /* next weight */ | |
692 | sched->state.event = 0; | |
693 | sched->state.weight++; | |
694 | if (sched->state.weight > sched->max_weight) | |
695 | return false; | |
696 | } | |
43b45780 | 697 | c = sched->events[sched->state.event]->hw.constraint; |
1e2ad28f RR |
698 | } while (c->weight != sched->state.weight); |
699 | ||
700 | sched->state.counter = 0; /* start with first counter */ | |
701 | ||
702 | return true; | |
703 | } | |
704 | ||
705 | /* | |
706 | * Assign a counter for each event. | |
707 | */ | |
43b45780 | 708 | int perf_assign_events(struct perf_event **events, int n, |
4b4969b1 | 709 | int wmin, int wmax, int *assign) |
1e2ad28f RR |
710 | { |
711 | struct perf_sched sched; | |
712 | ||
43b45780 | 713 | perf_sched_init(&sched, events, n, wmin, wmax); |
1e2ad28f RR |
714 | |
715 | do { | |
716 | if (!perf_sched_find_counter(&sched)) | |
717 | break; /* failed */ | |
718 | if (assign) | |
719 | assign[sched.state.event] = sched.state.counter; | |
720 | } while (perf_sched_next_event(&sched)); | |
721 | ||
722 | return sched.state.unassigned; | |
723 | } | |
4a3dc121 | 724 | EXPORT_SYMBOL_GPL(perf_assign_events); |
1e2ad28f | 725 | |
de0428a7 | 726 | int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) |
1da53e02 | 727 | { |
43b45780 | 728 | struct event_constraint *c; |
1da53e02 | 729 | unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
2f7f73a5 | 730 | struct perf_event *e; |
1e2ad28f | 731 | int i, wmin, wmax, num = 0; |
1da53e02 SE |
732 | struct hw_perf_event *hwc; |
733 | ||
734 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); | |
735 | ||
1e2ad28f | 736 | for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) { |
43b45780 | 737 | hwc = &cpuc->event_list[i]->hw; |
b622d644 | 738 | c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]); |
43b45780 AH |
739 | hwc->constraint = c; |
740 | ||
1e2ad28f RR |
741 | wmin = min(wmin, c->weight); |
742 | wmax = max(wmax, c->weight); | |
1da53e02 SE |
743 | } |
744 | ||
8113070d SE |
745 | /* |
746 | * fastpath, try to reuse previous register | |
747 | */ | |
c933c1a6 | 748 | for (i = 0; i < n; i++) { |
8113070d | 749 | hwc = &cpuc->event_list[i]->hw; |
43b45780 | 750 | c = hwc->constraint; |
8113070d SE |
751 | |
752 | /* never assigned */ | |
753 | if (hwc->idx == -1) | |
754 | break; | |
755 | ||
756 | /* constraint still honored */ | |
63b14649 | 757 | if (!test_bit(hwc->idx, c->idxmsk)) |
8113070d SE |
758 | break; |
759 | ||
760 | /* not already used */ | |
761 | if (test_bit(hwc->idx, used_mask)) | |
762 | break; | |
763 | ||
34538ee7 | 764 | __set_bit(hwc->idx, used_mask); |
8113070d SE |
765 | if (assign) |
766 | assign[i] = hwc->idx; | |
767 | } | |
8113070d | 768 | |
1e2ad28f RR |
769 | /* slow path */ |
770 | if (i != n) | |
43b45780 AH |
771 | num = perf_assign_events(cpuc->event_list, n, wmin, |
772 | wmax, assign); | |
8113070d | 773 | |
2f7f73a5 SE |
774 | /* |
775 | * Mark the event as committed, so we do not put_constraint() | |
776 | * in case new events are added and fail scheduling. | |
777 | */ | |
778 | if (!num && assign) { | |
779 | for (i = 0; i < n; i++) { | |
780 | e = cpuc->event_list[i]; | |
781 | e->hw.flags |= PERF_X86_EVENT_COMMITTED; | |
782 | } | |
783 | } | |
1da53e02 SE |
784 | /* |
785 | * scheduling failed or is just a simulation, | |
786 | * free resources if necessary | |
787 | */ | |
788 | if (!assign || num) { | |
789 | for (i = 0; i < n; i++) { | |
2f7f73a5 SE |
790 | e = cpuc->event_list[i]; |
791 | /* | |
792 | * do not put_constraint() on comitted events, | |
793 | * because they are good to go | |
794 | */ | |
795 | if ((e->hw.flags & PERF_X86_EVENT_COMMITTED)) | |
796 | continue; | |
797 | ||
1da53e02 | 798 | if (x86_pmu.put_event_constraints) |
2f7f73a5 | 799 | x86_pmu.put_event_constraints(cpuc, e); |
1da53e02 SE |
800 | } |
801 | } | |
aa2bc1ad | 802 | return num ? -EINVAL : 0; |
1da53e02 SE |
803 | } |
804 | ||
805 | /* | |
806 | * dogrp: true if must collect siblings events (group) | |
807 | * returns total number of events and error code | |
808 | */ | |
809 | static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp) | |
810 | { | |
811 | struct perf_event *event; | |
812 | int n, max_count; | |
813 | ||
948b1bb8 | 814 | max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed; |
1da53e02 SE |
815 | |
816 | /* current number of events already accepted */ | |
817 | n = cpuc->n_events; | |
818 | ||
819 | if (is_x86_event(leader)) { | |
820 | if (n >= max_count) | |
aa2bc1ad | 821 | return -EINVAL; |
1da53e02 SE |
822 | cpuc->event_list[n] = leader; |
823 | n++; | |
824 | } | |
825 | if (!dogrp) | |
826 | return n; | |
827 | ||
828 | list_for_each_entry(event, &leader->sibling_list, group_entry) { | |
829 | if (!is_x86_event(event) || | |
8113070d | 830 | event->state <= PERF_EVENT_STATE_OFF) |
1da53e02 SE |
831 | continue; |
832 | ||
833 | if (n >= max_count) | |
aa2bc1ad | 834 | return -EINVAL; |
1da53e02 SE |
835 | |
836 | cpuc->event_list[n] = event; | |
837 | n++; | |
838 | } | |
839 | return n; | |
840 | } | |
841 | ||
1da53e02 | 842 | static inline void x86_assign_hw_event(struct perf_event *event, |
447a194b | 843 | struct cpu_hw_events *cpuc, int i) |
1da53e02 | 844 | { |
447a194b SE |
845 | struct hw_perf_event *hwc = &event->hw; |
846 | ||
847 | hwc->idx = cpuc->assign[i]; | |
848 | hwc->last_cpu = smp_processor_id(); | |
849 | hwc->last_tag = ++cpuc->tags[i]; | |
1da53e02 | 850 | |
15c7ad51 | 851 | if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) { |
1da53e02 SE |
852 | hwc->config_base = 0; |
853 | hwc->event_base = 0; | |
15c7ad51 | 854 | } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) { |
1da53e02 | 855 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; |
15c7ad51 RR |
856 | hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED); |
857 | hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30; | |
1da53e02 | 858 | } else { |
73d6e522 RR |
859 | hwc->config_base = x86_pmu_config_addr(hwc->idx); |
860 | hwc->event_base = x86_pmu_event_addr(hwc->idx); | |
0fbdad07 | 861 | hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx); |
1da53e02 SE |
862 | } |
863 | } | |
864 | ||
447a194b SE |
865 | static inline int match_prev_assignment(struct hw_perf_event *hwc, |
866 | struct cpu_hw_events *cpuc, | |
867 | int i) | |
868 | { | |
869 | return hwc->idx == cpuc->assign[i] && | |
870 | hwc->last_cpu == smp_processor_id() && | |
871 | hwc->last_tag == cpuc->tags[i]; | |
872 | } | |
873 | ||
a4eaf7f1 | 874 | static void x86_pmu_start(struct perf_event *event, int flags); |
2e841873 | 875 | |
a4eaf7f1 | 876 | static void x86_pmu_enable(struct pmu *pmu) |
ee06094f | 877 | { |
1da53e02 SE |
878 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
879 | struct perf_event *event; | |
880 | struct hw_perf_event *hwc; | |
11164cd4 | 881 | int i, added = cpuc->n_added; |
1da53e02 | 882 | |
85cf9dba | 883 | if (!x86_pmu_initialized()) |
2b9ff0db | 884 | return; |
1a6e21f7 PZ |
885 | |
886 | if (cpuc->enabled) | |
887 | return; | |
888 | ||
1da53e02 | 889 | if (cpuc->n_added) { |
19925ce7 | 890 | int n_running = cpuc->n_events - cpuc->n_added; |
1da53e02 SE |
891 | /* |
892 | * apply assignment obtained either from | |
893 | * hw_perf_group_sched_in() or x86_pmu_enable() | |
894 | * | |
895 | * step1: save events moving to new counters | |
1da53e02 | 896 | */ |
19925ce7 | 897 | for (i = 0; i < n_running; i++) { |
1da53e02 SE |
898 | event = cpuc->event_list[i]; |
899 | hwc = &event->hw; | |
900 | ||
447a194b SE |
901 | /* |
902 | * we can avoid reprogramming counter if: | |
903 | * - assigned same counter as last time | |
904 | * - running on same CPU as last time | |
905 | * - no other event has used the counter since | |
906 | */ | |
907 | if (hwc->idx == -1 || | |
908 | match_prev_assignment(hwc, cpuc, i)) | |
1da53e02 SE |
909 | continue; |
910 | ||
a4eaf7f1 PZ |
911 | /* |
912 | * Ensure we don't accidentally enable a stopped | |
913 | * counter simply because we rescheduled. | |
914 | */ | |
915 | if (hwc->state & PERF_HES_STOPPED) | |
916 | hwc->state |= PERF_HES_ARCH; | |
917 | ||
918 | x86_pmu_stop(event, PERF_EF_UPDATE); | |
1da53e02 SE |
919 | } |
920 | ||
c347a2f1 PZ |
921 | /* |
922 | * step2: reprogram moved events into new counters | |
923 | */ | |
1da53e02 | 924 | for (i = 0; i < cpuc->n_events; i++) { |
1da53e02 SE |
925 | event = cpuc->event_list[i]; |
926 | hwc = &event->hw; | |
927 | ||
45e16a68 | 928 | if (!match_prev_assignment(hwc, cpuc, i)) |
447a194b | 929 | x86_assign_hw_event(event, cpuc, i); |
45e16a68 PZ |
930 | else if (i < n_running) |
931 | continue; | |
1da53e02 | 932 | |
a4eaf7f1 PZ |
933 | if (hwc->state & PERF_HES_ARCH) |
934 | continue; | |
935 | ||
936 | x86_pmu_start(event, PERF_EF_RELOAD); | |
1da53e02 SE |
937 | } |
938 | cpuc->n_added = 0; | |
939 | perf_events_lapic_init(); | |
940 | } | |
1a6e21f7 PZ |
941 | |
942 | cpuc->enabled = 1; | |
943 | barrier(); | |
944 | ||
11164cd4 | 945 | x86_pmu.enable_all(added); |
ee06094f | 946 | } |
ee06094f | 947 | |
245b2e70 | 948 | static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); |
241771ef | 949 | |
ee06094f IM |
950 | /* |
951 | * Set the next IRQ period, based on the hwc->period_left value. | |
cdd6c482 | 952 | * To be called with the event disabled in hw: |
ee06094f | 953 | */ |
de0428a7 | 954 | int x86_perf_event_set_period(struct perf_event *event) |
241771ef | 955 | { |
07088edb | 956 | struct hw_perf_event *hwc = &event->hw; |
e7850595 | 957 | s64 left = local64_read(&hwc->period_left); |
e4abb5d4 | 958 | s64 period = hwc->sample_period; |
7645a24c | 959 | int ret = 0, idx = hwc->idx; |
ee06094f | 960 | |
15c7ad51 | 961 | if (idx == INTEL_PMC_IDX_FIXED_BTS) |
30dd568c MM |
962 | return 0; |
963 | ||
ee06094f | 964 | /* |
af901ca1 | 965 | * If we are way outside a reasonable range then just skip forward: |
ee06094f IM |
966 | */ |
967 | if (unlikely(left <= -period)) { | |
968 | left = period; | |
e7850595 | 969 | local64_set(&hwc->period_left, left); |
9e350de3 | 970 | hwc->last_period = period; |
e4abb5d4 | 971 | ret = 1; |
ee06094f IM |
972 | } |
973 | ||
974 | if (unlikely(left <= 0)) { | |
975 | left += period; | |
e7850595 | 976 | local64_set(&hwc->period_left, left); |
9e350de3 | 977 | hwc->last_period = period; |
e4abb5d4 | 978 | ret = 1; |
ee06094f | 979 | } |
1c80f4b5 | 980 | /* |
dfc65094 | 981 | * Quirk: certain CPUs dont like it if just 1 hw_event is left: |
1c80f4b5 IM |
982 | */ |
983 | if (unlikely(left < 2)) | |
984 | left = 2; | |
241771ef | 985 | |
e4abb5d4 PZ |
986 | if (left > x86_pmu.max_period) |
987 | left = x86_pmu.max_period; | |
988 | ||
c46e665f AK |
989 | if (x86_pmu.limit_period) |
990 | left = x86_pmu.limit_period(event, left); | |
991 | ||
245b2e70 | 992 | per_cpu(pmc_prev_left[idx], smp_processor_id()) = left; |
ee06094f IM |
993 | |
994 | /* | |
cdd6c482 | 995 | * The hw event starts counting from this event offset, |
ee06094f IM |
996 | * mark it to be able to extra future deltas: |
997 | */ | |
e7850595 | 998 | local64_set(&hwc->prev_count, (u64)-left); |
ee06094f | 999 | |
73d6e522 | 1000 | wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac CG |
1001 | |
1002 | /* | |
1003 | * Due to erratum on certan cpu we need | |
1004 | * a second write to be sure the register | |
1005 | * is updated properly | |
1006 | */ | |
1007 | if (x86_pmu.perfctr_second_write) { | |
73d6e522 | 1008 | wrmsrl(hwc->event_base, |
948b1bb8 | 1009 | (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac | 1010 | } |
e4abb5d4 | 1011 | |
cdd6c482 | 1012 | perf_event_update_userpage(event); |
194002b2 | 1013 | |
e4abb5d4 | 1014 | return ret; |
2f18d1e8 IM |
1015 | } |
1016 | ||
de0428a7 | 1017 | void x86_pmu_enable_event(struct perf_event *event) |
7c90cc45 | 1018 | { |
0a3aee0d | 1019 | if (__this_cpu_read(cpu_hw_events.enabled)) |
31fa58af RR |
1020 | __x86_pmu_enable_event(&event->hw, |
1021 | ARCH_PERFMON_EVENTSEL_ENABLE); | |
241771ef IM |
1022 | } |
1023 | ||
b690081d | 1024 | /* |
a4eaf7f1 | 1025 | * Add a single event to the PMU. |
1da53e02 SE |
1026 | * |
1027 | * The event is added to the group of enabled events | |
1028 | * but only if it can be scehduled with existing events. | |
fe9081cc | 1029 | */ |
a4eaf7f1 | 1030 | static int x86_pmu_add(struct perf_event *event, int flags) |
fe9081cc PZ |
1031 | { |
1032 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1da53e02 SE |
1033 | struct hw_perf_event *hwc; |
1034 | int assign[X86_PMC_IDX_MAX]; | |
1035 | int n, n0, ret; | |
fe9081cc | 1036 | |
1da53e02 | 1037 | hwc = &event->hw; |
fe9081cc | 1038 | |
33696fc0 | 1039 | perf_pmu_disable(event->pmu); |
1da53e02 | 1040 | n0 = cpuc->n_events; |
24cd7f54 PZ |
1041 | ret = n = collect_events(cpuc, event, false); |
1042 | if (ret < 0) | |
1043 | goto out; | |
53b441a5 | 1044 | |
a4eaf7f1 PZ |
1045 | hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; |
1046 | if (!(flags & PERF_EF_START)) | |
1047 | hwc->state |= PERF_HES_ARCH; | |
1048 | ||
4d1c52b0 LM |
1049 | /* |
1050 | * If group events scheduling transaction was started, | |
0d2eb44f | 1051 | * skip the schedulability test here, it will be performed |
c347a2f1 | 1052 | * at commit time (->commit_txn) as a whole. |
4d1c52b0 | 1053 | */ |
8d2cacbb | 1054 | if (cpuc->group_flag & PERF_EVENT_TXN) |
24cd7f54 | 1055 | goto done_collect; |
4d1c52b0 | 1056 | |
a072738e | 1057 | ret = x86_pmu.schedule_events(cpuc, n, assign); |
1da53e02 | 1058 | if (ret) |
24cd7f54 | 1059 | goto out; |
1da53e02 SE |
1060 | /* |
1061 | * copy new assignment, now we know it is possible | |
1062 | * will be used by hw_perf_enable() | |
1063 | */ | |
1064 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
7e2ae347 | 1065 | |
24cd7f54 | 1066 | done_collect: |
c347a2f1 PZ |
1067 | /* |
1068 | * Commit the collect_events() state. See x86_pmu_del() and | |
1069 | * x86_pmu_*_txn(). | |
1070 | */ | |
1da53e02 | 1071 | cpuc->n_events = n; |
356e1f2e | 1072 | cpuc->n_added += n - n0; |
90151c35 | 1073 | cpuc->n_txn += n - n0; |
95cdd2e7 | 1074 | |
24cd7f54 PZ |
1075 | ret = 0; |
1076 | out: | |
33696fc0 | 1077 | perf_pmu_enable(event->pmu); |
24cd7f54 | 1078 | return ret; |
241771ef IM |
1079 | } |
1080 | ||
a4eaf7f1 | 1081 | static void x86_pmu_start(struct perf_event *event, int flags) |
d76a0812 | 1082 | { |
c08053e6 PZ |
1083 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
1084 | int idx = event->hw.idx; | |
1085 | ||
a4eaf7f1 PZ |
1086 | if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) |
1087 | return; | |
1088 | ||
1089 | if (WARN_ON_ONCE(idx == -1)) | |
1090 | return; | |
1091 | ||
1092 | if (flags & PERF_EF_RELOAD) { | |
1093 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); | |
1094 | x86_perf_event_set_period(event); | |
1095 | } | |
1096 | ||
1097 | event->hw.state = 0; | |
d76a0812 | 1098 | |
c08053e6 PZ |
1099 | cpuc->events[idx] = event; |
1100 | __set_bit(idx, cpuc->active_mask); | |
63e6be6d | 1101 | __set_bit(idx, cpuc->running); |
aff3d91a | 1102 | x86_pmu.enable(event); |
c08053e6 | 1103 | perf_event_update_userpage(event); |
a78ac325 PZ |
1104 | } |
1105 | ||
cdd6c482 | 1106 | void perf_event_print_debug(void) |
241771ef | 1107 | { |
2f18d1e8 | 1108 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
ca037701 | 1109 | u64 pebs; |
cdd6c482 | 1110 | struct cpu_hw_events *cpuc; |
5bb9efe3 | 1111 | unsigned long flags; |
1e125676 IM |
1112 | int cpu, idx; |
1113 | ||
948b1bb8 | 1114 | if (!x86_pmu.num_counters) |
1e125676 | 1115 | return; |
241771ef | 1116 | |
5bb9efe3 | 1117 | local_irq_save(flags); |
241771ef IM |
1118 | |
1119 | cpu = smp_processor_id(); | |
cdd6c482 | 1120 | cpuc = &per_cpu(cpu_hw_events, cpu); |
241771ef | 1121 | |
faa28ae0 | 1122 | if (x86_pmu.version >= 2) { |
a1ef58f4 JSR |
1123 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
1124 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
1125 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
1126 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); | |
ca037701 | 1127 | rdmsrl(MSR_IA32_PEBS_ENABLE, pebs); |
a1ef58f4 JSR |
1128 | |
1129 | pr_info("\n"); | |
1130 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
1131 | pr_info("CPU#%d: status: %016llx\n", cpu, status); | |
1132 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); | |
1133 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); | |
ca037701 | 1134 | pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs); |
f87ad35d | 1135 | } |
7645a24c | 1136 | pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); |
241771ef | 1137 | |
948b1bb8 | 1138 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
41bf4989 RR |
1139 | rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl); |
1140 | rdmsrl(x86_pmu_event_addr(idx), pmc_count); | |
241771ef | 1141 | |
245b2e70 | 1142 | prev_left = per_cpu(pmc_prev_left[idx], cpu); |
241771ef | 1143 | |
a1ef58f4 | 1144 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 1145 | cpu, idx, pmc_ctrl); |
a1ef58f4 | 1146 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 1147 | cpu, idx, pmc_count); |
a1ef58f4 | 1148 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 1149 | cpu, idx, prev_left); |
241771ef | 1150 | } |
948b1bb8 | 1151 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { |
2f18d1e8 IM |
1152 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
1153 | ||
a1ef58f4 | 1154 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
2f18d1e8 IM |
1155 | cpu, idx, pmc_count); |
1156 | } | |
5bb9efe3 | 1157 | local_irq_restore(flags); |
241771ef IM |
1158 | } |
1159 | ||
de0428a7 | 1160 | void x86_pmu_stop(struct perf_event *event, int flags) |
241771ef | 1161 | { |
d76a0812 | 1162 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
cdd6c482 | 1163 | struct hw_perf_event *hwc = &event->hw; |
241771ef | 1164 | |
a4eaf7f1 PZ |
1165 | if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) { |
1166 | x86_pmu.disable(event); | |
1167 | cpuc->events[hwc->idx] = NULL; | |
1168 | WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); | |
1169 | hwc->state |= PERF_HES_STOPPED; | |
1170 | } | |
30dd568c | 1171 | |
a4eaf7f1 PZ |
1172 | if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { |
1173 | /* | |
1174 | * Drain the remaining delta count out of a event | |
1175 | * that we are disabling: | |
1176 | */ | |
1177 | x86_perf_event_update(event); | |
1178 | hwc->state |= PERF_HES_UPTODATE; | |
1179 | } | |
2e841873 PZ |
1180 | } |
1181 | ||
a4eaf7f1 | 1182 | static void x86_pmu_del(struct perf_event *event, int flags) |
2e841873 PZ |
1183 | { |
1184 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1185 | int i; | |
1186 | ||
2f7f73a5 SE |
1187 | /* |
1188 | * event is descheduled | |
1189 | */ | |
1190 | event->hw.flags &= ~PERF_X86_EVENT_COMMITTED; | |
1191 | ||
90151c35 SE |
1192 | /* |
1193 | * If we're called during a txn, we don't need to do anything. | |
1194 | * The events never got scheduled and ->cancel_txn will truncate | |
1195 | * the event_list. | |
c347a2f1 PZ |
1196 | * |
1197 | * XXX assumes any ->del() called during a TXN will only be on | |
1198 | * an event added during that same TXN. | |
90151c35 | 1199 | */ |
8d2cacbb | 1200 | if (cpuc->group_flag & PERF_EVENT_TXN) |
90151c35 SE |
1201 | return; |
1202 | ||
c347a2f1 PZ |
1203 | /* |
1204 | * Not a TXN, therefore cleanup properly. | |
1205 | */ | |
a4eaf7f1 | 1206 | x86_pmu_stop(event, PERF_EF_UPDATE); |
194002b2 | 1207 | |
1da53e02 | 1208 | for (i = 0; i < cpuc->n_events; i++) { |
c347a2f1 PZ |
1209 | if (event == cpuc->event_list[i]) |
1210 | break; | |
1211 | } | |
1da53e02 | 1212 | |
c347a2f1 PZ |
1213 | if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */ |
1214 | return; | |
26e61e89 | 1215 | |
c347a2f1 PZ |
1216 | /* If we have a newly added event; make sure to decrease n_added. */ |
1217 | if (i >= cpuc->n_events - cpuc->n_added) | |
1218 | --cpuc->n_added; | |
1da53e02 | 1219 | |
c347a2f1 PZ |
1220 | if (x86_pmu.put_event_constraints) |
1221 | x86_pmu.put_event_constraints(cpuc, event); | |
1222 | ||
1223 | /* Delete the array entry. */ | |
1224 | while (++i < cpuc->n_events) | |
1225 | cpuc->event_list[i-1] = cpuc->event_list[i]; | |
1226 | --cpuc->n_events; | |
1da53e02 | 1227 | |
cdd6c482 | 1228 | perf_event_update_userpage(event); |
241771ef IM |
1229 | } |
1230 | ||
de0428a7 | 1231 | int x86_pmu_handle_irq(struct pt_regs *regs) |
a29aa8a7 | 1232 | { |
df1a132b | 1233 | struct perf_sample_data data; |
cdd6c482 IM |
1234 | struct cpu_hw_events *cpuc; |
1235 | struct perf_event *event; | |
11d1578f | 1236 | int idx, handled = 0; |
9029a5e3 IM |
1237 | u64 val; |
1238 | ||
cdd6c482 | 1239 | cpuc = &__get_cpu_var(cpu_hw_events); |
962bf7a6 | 1240 | |
2bce5dac DZ |
1241 | /* |
1242 | * Some chipsets need to unmask the LVTPC in a particular spot | |
1243 | * inside the nmi handler. As a result, the unmasking was pushed | |
1244 | * into all the nmi handlers. | |
1245 | * | |
1246 | * This generic handler doesn't seem to have any issues where the | |
1247 | * unmasking occurs so it was left at the top. | |
1248 | */ | |
1249 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
1250 | ||
948b1bb8 | 1251 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
63e6be6d RR |
1252 | if (!test_bit(idx, cpuc->active_mask)) { |
1253 | /* | |
1254 | * Though we deactivated the counter some cpus | |
1255 | * might still deliver spurious interrupts still | |
1256 | * in flight. Catch them: | |
1257 | */ | |
1258 | if (__test_and_clear_bit(idx, cpuc->running)) | |
1259 | handled++; | |
a29aa8a7 | 1260 | continue; |
63e6be6d | 1261 | } |
962bf7a6 | 1262 | |
cdd6c482 | 1263 | event = cpuc->events[idx]; |
a4016a79 | 1264 | |
cc2ad4ba | 1265 | val = x86_perf_event_update(event); |
948b1bb8 | 1266 | if (val & (1ULL << (x86_pmu.cntval_bits - 1))) |
48e22d56 | 1267 | continue; |
962bf7a6 | 1268 | |
9e350de3 | 1269 | /* |
cdd6c482 | 1270 | * event overflow |
9e350de3 | 1271 | */ |
4177c42a | 1272 | handled++; |
fd0d000b | 1273 | perf_sample_data_init(&data, 0, event->hw.last_period); |
9e350de3 | 1274 | |
07088edb | 1275 | if (!x86_perf_event_set_period(event)) |
e4abb5d4 PZ |
1276 | continue; |
1277 | ||
a8b0ca17 | 1278 | if (perf_event_overflow(event, &data, regs)) |
a4eaf7f1 | 1279 | x86_pmu_stop(event, 0); |
a29aa8a7 | 1280 | } |
962bf7a6 | 1281 | |
9e350de3 PZ |
1282 | if (handled) |
1283 | inc_irq_stat(apic_perf_irqs); | |
1284 | ||
a29aa8a7 RR |
1285 | return handled; |
1286 | } | |
39d81eab | 1287 | |
cdd6c482 | 1288 | void perf_events_lapic_init(void) |
241771ef | 1289 | { |
04da8a43 | 1290 | if (!x86_pmu.apic || !x86_pmu_initialized()) |
241771ef | 1291 | return; |
85cf9dba | 1292 | |
241771ef | 1293 | /* |
c323d95f | 1294 | * Always use NMI for PMU |
241771ef | 1295 | */ |
c323d95f | 1296 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
241771ef IM |
1297 | } |
1298 | ||
9326638c | 1299 | static int |
9c48f1c6 | 1300 | perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs) |
241771ef | 1301 | { |
14c63f17 DH |
1302 | u64 start_clock; |
1303 | u64 finish_clock; | |
e8a923cc | 1304 | int ret; |
14c63f17 | 1305 | |
cdd6c482 | 1306 | if (!atomic_read(&active_events)) |
9c48f1c6 | 1307 | return NMI_DONE; |
4177c42a | 1308 | |
e8a923cc | 1309 | start_clock = sched_clock(); |
14c63f17 | 1310 | ret = x86_pmu.handle_irq(regs); |
e8a923cc | 1311 | finish_clock = sched_clock(); |
14c63f17 DH |
1312 | |
1313 | perf_sample_event_took(finish_clock - start_clock); | |
1314 | ||
1315 | return ret; | |
241771ef | 1316 | } |
9326638c | 1317 | NOKPROBE_SYMBOL(perf_event_nmi_handler); |
241771ef | 1318 | |
de0428a7 KW |
1319 | struct event_constraint emptyconstraint; |
1320 | struct event_constraint unconstrained; | |
f87ad35d | 1321 | |
148f9bb8 | 1322 | static int |
3f6da390 PZ |
1323 | x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) |
1324 | { | |
1325 | unsigned int cpu = (long)hcpu; | |
7fdba1ca | 1326 | struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); |
b38b24ea | 1327 | int ret = NOTIFY_OK; |
3f6da390 PZ |
1328 | |
1329 | switch (action & ~CPU_TASKS_FROZEN) { | |
1330 | case CPU_UP_PREPARE: | |
7fdba1ca | 1331 | cpuc->kfree_on_online = NULL; |
3f6da390 | 1332 | if (x86_pmu.cpu_prepare) |
b38b24ea | 1333 | ret = x86_pmu.cpu_prepare(cpu); |
3f6da390 PZ |
1334 | break; |
1335 | ||
1336 | case CPU_STARTING: | |
0c9d42ed PZ |
1337 | if (x86_pmu.attr_rdpmc) |
1338 | set_in_cr4(X86_CR4_PCE); | |
3f6da390 PZ |
1339 | if (x86_pmu.cpu_starting) |
1340 | x86_pmu.cpu_starting(cpu); | |
1341 | break; | |
1342 | ||
7fdba1ca PZ |
1343 | case CPU_ONLINE: |
1344 | kfree(cpuc->kfree_on_online); | |
1345 | break; | |
1346 | ||
3f6da390 PZ |
1347 | case CPU_DYING: |
1348 | if (x86_pmu.cpu_dying) | |
1349 | x86_pmu.cpu_dying(cpu); | |
1350 | break; | |
1351 | ||
b38b24ea | 1352 | case CPU_UP_CANCELED: |
3f6da390 PZ |
1353 | case CPU_DEAD: |
1354 | if (x86_pmu.cpu_dead) | |
1355 | x86_pmu.cpu_dead(cpu); | |
1356 | break; | |
1357 | ||
1358 | default: | |
1359 | break; | |
1360 | } | |
1361 | ||
b38b24ea | 1362 | return ret; |
3f6da390 PZ |
1363 | } |
1364 | ||
12558038 CG |
1365 | static void __init pmu_check_apic(void) |
1366 | { | |
1367 | if (cpu_has_apic) | |
1368 | return; | |
1369 | ||
1370 | x86_pmu.apic = 0; | |
1371 | pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n"); | |
1372 | pr_info("no hardware sampling interrupt available.\n"); | |
c184c980 VW |
1373 | |
1374 | /* | |
1375 | * If we have a PMU initialized but no APIC | |
1376 | * interrupts, we cannot sample hardware | |
1377 | * events (user-space has to fall back and | |
1378 | * sample via a hrtimer based software event): | |
1379 | */ | |
1380 | pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT; | |
1381 | ||
12558038 CG |
1382 | } |
1383 | ||
641cc938 JO |
1384 | static struct attribute_group x86_pmu_format_group = { |
1385 | .name = "format", | |
1386 | .attrs = NULL, | |
1387 | }; | |
1388 | ||
8300daa2 JO |
1389 | /* |
1390 | * Remove all undefined events (x86_pmu.event_map(id) == 0) | |
1391 | * out of events_attr attributes. | |
1392 | */ | |
1393 | static void __init filter_events(struct attribute **attrs) | |
1394 | { | |
3a54aaa0 SE |
1395 | struct device_attribute *d; |
1396 | struct perf_pmu_events_attr *pmu_attr; | |
8300daa2 JO |
1397 | int i, j; |
1398 | ||
1399 | for (i = 0; attrs[i]; i++) { | |
3a54aaa0 SE |
1400 | d = (struct device_attribute *)attrs[i]; |
1401 | pmu_attr = container_of(d, struct perf_pmu_events_attr, attr); | |
1402 | /* str trumps id */ | |
1403 | if (pmu_attr->event_str) | |
1404 | continue; | |
8300daa2 JO |
1405 | if (x86_pmu.event_map(i)) |
1406 | continue; | |
1407 | ||
1408 | for (j = i; attrs[j]; j++) | |
1409 | attrs[j] = attrs[j + 1]; | |
1410 | ||
1411 | /* Check the shifted attr. */ | |
1412 | i--; | |
1413 | } | |
1414 | } | |
1415 | ||
1a6461b1 AK |
1416 | /* Merge two pointer arrays */ |
1417 | static __init struct attribute **merge_attr(struct attribute **a, struct attribute **b) | |
1418 | { | |
1419 | struct attribute **new; | |
1420 | int j, i; | |
1421 | ||
1422 | for (j = 0; a[j]; j++) | |
1423 | ; | |
1424 | for (i = 0; b[i]; i++) | |
1425 | j++; | |
1426 | j++; | |
1427 | ||
1428 | new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL); | |
1429 | if (!new) | |
1430 | return NULL; | |
1431 | ||
1432 | j = 0; | |
1433 | for (i = 0; a[i]; i++) | |
1434 | new[j++] = a[i]; | |
1435 | for (i = 0; b[i]; i++) | |
1436 | new[j++] = b[i]; | |
1437 | new[j] = NULL; | |
1438 | ||
1439 | return new; | |
1440 | } | |
1441 | ||
f20093ee | 1442 | ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, |
a4747393 JO |
1443 | char *page) |
1444 | { | |
1445 | struct perf_pmu_events_attr *pmu_attr = \ | |
1446 | container_of(attr, struct perf_pmu_events_attr, attr); | |
a4747393 | 1447 | u64 config = x86_pmu.event_map(pmu_attr->id); |
a4747393 | 1448 | |
3a54aaa0 SE |
1449 | /* string trumps id */ |
1450 | if (pmu_attr->event_str) | |
1451 | return sprintf(page, "%s", pmu_attr->event_str); | |
a4747393 | 1452 | |
3a54aaa0 SE |
1453 | return x86_pmu.events_sysfs_show(page, config); |
1454 | } | |
a4747393 JO |
1455 | |
1456 | EVENT_ATTR(cpu-cycles, CPU_CYCLES ); | |
1457 | EVENT_ATTR(instructions, INSTRUCTIONS ); | |
1458 | EVENT_ATTR(cache-references, CACHE_REFERENCES ); | |
1459 | EVENT_ATTR(cache-misses, CACHE_MISSES ); | |
1460 | EVENT_ATTR(branch-instructions, BRANCH_INSTRUCTIONS ); | |
1461 | EVENT_ATTR(branch-misses, BRANCH_MISSES ); | |
1462 | EVENT_ATTR(bus-cycles, BUS_CYCLES ); | |
1463 | EVENT_ATTR(stalled-cycles-frontend, STALLED_CYCLES_FRONTEND ); | |
1464 | EVENT_ATTR(stalled-cycles-backend, STALLED_CYCLES_BACKEND ); | |
1465 | EVENT_ATTR(ref-cycles, REF_CPU_CYCLES ); | |
1466 | ||
1467 | static struct attribute *empty_attrs; | |
1468 | ||
95d18aa2 | 1469 | static struct attribute *events_attr[] = { |
a4747393 JO |
1470 | EVENT_PTR(CPU_CYCLES), |
1471 | EVENT_PTR(INSTRUCTIONS), | |
1472 | EVENT_PTR(CACHE_REFERENCES), | |
1473 | EVENT_PTR(CACHE_MISSES), | |
1474 | EVENT_PTR(BRANCH_INSTRUCTIONS), | |
1475 | EVENT_PTR(BRANCH_MISSES), | |
1476 | EVENT_PTR(BUS_CYCLES), | |
1477 | EVENT_PTR(STALLED_CYCLES_FRONTEND), | |
1478 | EVENT_PTR(STALLED_CYCLES_BACKEND), | |
1479 | EVENT_PTR(REF_CPU_CYCLES), | |
1480 | NULL, | |
1481 | }; | |
1482 | ||
1483 | static struct attribute_group x86_pmu_events_group = { | |
1484 | .name = "events", | |
1485 | .attrs = events_attr, | |
1486 | }; | |
1487 | ||
0bf79d44 | 1488 | ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event) |
43c032fe | 1489 | { |
43c032fe JO |
1490 | u64 umask = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8; |
1491 | u64 cmask = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24; | |
1492 | bool edge = (config & ARCH_PERFMON_EVENTSEL_EDGE); | |
1493 | bool pc = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL); | |
1494 | bool any = (config & ARCH_PERFMON_EVENTSEL_ANY); | |
1495 | bool inv = (config & ARCH_PERFMON_EVENTSEL_INV); | |
1496 | ssize_t ret; | |
1497 | ||
1498 | /* | |
1499 | * We have whole page size to spend and just little data | |
1500 | * to write, so we can safely use sprintf. | |
1501 | */ | |
1502 | ret = sprintf(page, "event=0x%02llx", event); | |
1503 | ||
1504 | if (umask) | |
1505 | ret += sprintf(page + ret, ",umask=0x%02llx", umask); | |
1506 | ||
1507 | if (edge) | |
1508 | ret += sprintf(page + ret, ",edge"); | |
1509 | ||
1510 | if (pc) | |
1511 | ret += sprintf(page + ret, ",pc"); | |
1512 | ||
1513 | if (any) | |
1514 | ret += sprintf(page + ret, ",any"); | |
1515 | ||
1516 | if (inv) | |
1517 | ret += sprintf(page + ret, ",inv"); | |
1518 | ||
1519 | if (cmask) | |
1520 | ret += sprintf(page + ret, ",cmask=0x%02llx", cmask); | |
1521 | ||
1522 | ret += sprintf(page + ret, "\n"); | |
1523 | ||
1524 | return ret; | |
1525 | } | |
1526 | ||
dda99116 | 1527 | static int __init init_hw_perf_events(void) |
b56a3802 | 1528 | { |
c1d6f42f | 1529 | struct x86_pmu_quirk *quirk; |
72eae04d RR |
1530 | int err; |
1531 | ||
cdd6c482 | 1532 | pr_info("Performance Events: "); |
1123e3ad | 1533 | |
b56a3802 JSR |
1534 | switch (boot_cpu_data.x86_vendor) { |
1535 | case X86_VENDOR_INTEL: | |
72eae04d | 1536 | err = intel_pmu_init(); |
b56a3802 | 1537 | break; |
f87ad35d | 1538 | case X86_VENDOR_AMD: |
72eae04d | 1539 | err = amd_pmu_init(); |
f87ad35d | 1540 | break; |
4138960a | 1541 | default: |
8a3da6c7 | 1542 | err = -ENOTSUPP; |
b56a3802 | 1543 | } |
1123e3ad | 1544 | if (err != 0) { |
cdd6c482 | 1545 | pr_cont("no PMU driver, software events only.\n"); |
004417a6 | 1546 | return 0; |
1123e3ad | 1547 | } |
b56a3802 | 1548 | |
12558038 CG |
1549 | pmu_check_apic(); |
1550 | ||
33c6d6a7 | 1551 | /* sanity check that the hardware exists or is emulated */ |
4407204c | 1552 | if (!check_hw_exists()) |
004417a6 | 1553 | return 0; |
33c6d6a7 | 1554 | |
1123e3ad | 1555 | pr_cont("%s PMU driver.\n", x86_pmu.name); |
faa28ae0 | 1556 | |
e97df763 PZ |
1557 | x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */ |
1558 | ||
c1d6f42f PZ |
1559 | for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next) |
1560 | quirk->func(); | |
3c44780b | 1561 | |
a1eac7ac RR |
1562 | if (!x86_pmu.intel_ctrl) |
1563 | x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1; | |
241771ef | 1564 | |
cdd6c482 | 1565 | perf_events_lapic_init(); |
9c48f1c6 | 1566 | register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI"); |
1123e3ad | 1567 | |
63b14649 | 1568 | unconstrained = (struct event_constraint) |
948b1bb8 | 1569 | __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1, |
9fac2cf3 | 1570 | 0, x86_pmu.num_counters, 0, 0); |
63b14649 | 1571 | |
641cc938 | 1572 | x86_pmu_format_group.attrs = x86_pmu.format_attrs; |
0c9d42ed | 1573 | |
f20093ee SE |
1574 | if (x86_pmu.event_attrs) |
1575 | x86_pmu_events_group.attrs = x86_pmu.event_attrs; | |
1576 | ||
a4747393 JO |
1577 | if (!x86_pmu.events_sysfs_show) |
1578 | x86_pmu_events_group.attrs = &empty_attrs; | |
8300daa2 JO |
1579 | else |
1580 | filter_events(x86_pmu_events_group.attrs); | |
a4747393 | 1581 | |
1a6461b1 AK |
1582 | if (x86_pmu.cpu_events) { |
1583 | struct attribute **tmp; | |
1584 | ||
1585 | tmp = merge_attr(x86_pmu_events_group.attrs, x86_pmu.cpu_events); | |
1586 | if (!WARN_ON(!tmp)) | |
1587 | x86_pmu_events_group.attrs = tmp; | |
1588 | } | |
1589 | ||
57c0c15b | 1590 | pr_info("... version: %d\n", x86_pmu.version); |
948b1bb8 RR |
1591 | pr_info("... bit width: %d\n", x86_pmu.cntval_bits); |
1592 | pr_info("... generic registers: %d\n", x86_pmu.num_counters); | |
1593 | pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask); | |
57c0c15b | 1594 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); |
948b1bb8 | 1595 | pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed); |
d6dc0b4e | 1596 | pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl); |
3f6da390 | 1597 | |
2e80a82a | 1598 | perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); |
3f6da390 | 1599 | perf_cpu_notifier(x86_pmu_notifier); |
004417a6 PZ |
1600 | |
1601 | return 0; | |
241771ef | 1602 | } |
004417a6 | 1603 | early_initcall(init_hw_perf_events); |
621a01ea | 1604 | |
cdd6c482 | 1605 | static inline void x86_pmu_read(struct perf_event *event) |
ee06094f | 1606 | { |
cc2ad4ba | 1607 | x86_perf_event_update(event); |
ee06094f IM |
1608 | } |
1609 | ||
4d1c52b0 LM |
1610 | /* |
1611 | * Start group events scheduling transaction | |
1612 | * Set the flag to make pmu::enable() not perform the | |
1613 | * schedulability test, it will be performed at commit time | |
1614 | */ | |
51b0fe39 | 1615 | static void x86_pmu_start_txn(struct pmu *pmu) |
4d1c52b0 | 1616 | { |
33696fc0 | 1617 | perf_pmu_disable(pmu); |
0a3aee0d TH |
1618 | __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN); |
1619 | __this_cpu_write(cpu_hw_events.n_txn, 0); | |
4d1c52b0 LM |
1620 | } |
1621 | ||
1622 | /* | |
1623 | * Stop group events scheduling transaction | |
1624 | * Clear the flag and pmu::enable() will perform the | |
1625 | * schedulability test. | |
1626 | */ | |
51b0fe39 | 1627 | static void x86_pmu_cancel_txn(struct pmu *pmu) |
4d1c52b0 | 1628 | { |
0a3aee0d | 1629 | __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN); |
90151c35 | 1630 | /* |
c347a2f1 PZ |
1631 | * Truncate collected array by the number of events added in this |
1632 | * transaction. See x86_pmu_add() and x86_pmu_*_txn(). | |
90151c35 | 1633 | */ |
0a3aee0d TH |
1634 | __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn)); |
1635 | __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn)); | |
33696fc0 | 1636 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1637 | } |
1638 | ||
1639 | /* | |
1640 | * Commit group events scheduling transaction | |
1641 | * Perform the group schedulability test as a whole | |
1642 | * Return 0 if success | |
c347a2f1 PZ |
1643 | * |
1644 | * Does not cancel the transaction on failure; expects the caller to do this. | |
4d1c52b0 | 1645 | */ |
51b0fe39 | 1646 | static int x86_pmu_commit_txn(struct pmu *pmu) |
4d1c52b0 LM |
1647 | { |
1648 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1649 | int assign[X86_PMC_IDX_MAX]; | |
1650 | int n, ret; | |
1651 | ||
1652 | n = cpuc->n_events; | |
1653 | ||
1654 | if (!x86_pmu_initialized()) | |
1655 | return -EAGAIN; | |
1656 | ||
1657 | ret = x86_pmu.schedule_events(cpuc, n, assign); | |
1658 | if (ret) | |
1659 | return ret; | |
1660 | ||
1661 | /* | |
1662 | * copy new assignment, now we know it is possible | |
1663 | * will be used by hw_perf_enable() | |
1664 | */ | |
1665 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
1666 | ||
8d2cacbb | 1667 | cpuc->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 1668 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1669 | return 0; |
1670 | } | |
cd8a38d3 SE |
1671 | /* |
1672 | * a fake_cpuc is used to validate event groups. Due to | |
1673 | * the extra reg logic, we need to also allocate a fake | |
1674 | * per_core and per_cpu structure. Otherwise, group events | |
1675 | * using extra reg may conflict without the kernel being | |
1676 | * able to catch this when the last event gets added to | |
1677 | * the group. | |
1678 | */ | |
1679 | static void free_fake_cpuc(struct cpu_hw_events *cpuc) | |
1680 | { | |
1681 | kfree(cpuc->shared_regs); | |
1682 | kfree(cpuc); | |
1683 | } | |
1684 | ||
1685 | static struct cpu_hw_events *allocate_fake_cpuc(void) | |
1686 | { | |
1687 | struct cpu_hw_events *cpuc; | |
1688 | int cpu = raw_smp_processor_id(); | |
1689 | ||
1690 | cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL); | |
1691 | if (!cpuc) | |
1692 | return ERR_PTR(-ENOMEM); | |
1693 | ||
1694 | /* only needed, if we have extra_regs */ | |
1695 | if (x86_pmu.extra_regs) { | |
1696 | cpuc->shared_regs = allocate_shared_regs(cpu); | |
1697 | if (!cpuc->shared_regs) | |
1698 | goto error; | |
1699 | } | |
b430f7c4 | 1700 | cpuc->is_fake = 1; |
cd8a38d3 SE |
1701 | return cpuc; |
1702 | error: | |
1703 | free_fake_cpuc(cpuc); | |
1704 | return ERR_PTR(-ENOMEM); | |
1705 | } | |
4d1c52b0 | 1706 | |
ca037701 PZ |
1707 | /* |
1708 | * validate that we can schedule this event | |
1709 | */ | |
1710 | static int validate_event(struct perf_event *event) | |
1711 | { | |
1712 | struct cpu_hw_events *fake_cpuc; | |
1713 | struct event_constraint *c; | |
1714 | int ret = 0; | |
1715 | ||
cd8a38d3 SE |
1716 | fake_cpuc = allocate_fake_cpuc(); |
1717 | if (IS_ERR(fake_cpuc)) | |
1718 | return PTR_ERR(fake_cpuc); | |
ca037701 PZ |
1719 | |
1720 | c = x86_pmu.get_event_constraints(fake_cpuc, event); | |
1721 | ||
1722 | if (!c || !c->weight) | |
aa2bc1ad | 1723 | ret = -EINVAL; |
ca037701 PZ |
1724 | |
1725 | if (x86_pmu.put_event_constraints) | |
1726 | x86_pmu.put_event_constraints(fake_cpuc, event); | |
1727 | ||
cd8a38d3 | 1728 | free_fake_cpuc(fake_cpuc); |
ca037701 PZ |
1729 | |
1730 | return ret; | |
1731 | } | |
1732 | ||
1da53e02 SE |
1733 | /* |
1734 | * validate a single event group | |
1735 | * | |
1736 | * validation include: | |
184f412c IM |
1737 | * - check events are compatible which each other |
1738 | * - events do not compete for the same counter | |
1739 | * - number of events <= number of counters | |
1da53e02 SE |
1740 | * |
1741 | * validation ensures the group can be loaded onto the | |
1742 | * PMU if it was the only group available. | |
1743 | */ | |
fe9081cc PZ |
1744 | static int validate_group(struct perf_event *event) |
1745 | { | |
1da53e02 | 1746 | struct perf_event *leader = event->group_leader; |
502568d5 | 1747 | struct cpu_hw_events *fake_cpuc; |
aa2bc1ad | 1748 | int ret = -EINVAL, n; |
fe9081cc | 1749 | |
cd8a38d3 SE |
1750 | fake_cpuc = allocate_fake_cpuc(); |
1751 | if (IS_ERR(fake_cpuc)) | |
1752 | return PTR_ERR(fake_cpuc); | |
1da53e02 SE |
1753 | /* |
1754 | * the event is not yet connected with its | |
1755 | * siblings therefore we must first collect | |
1756 | * existing siblings, then add the new event | |
1757 | * before we can simulate the scheduling | |
1758 | */ | |
502568d5 | 1759 | n = collect_events(fake_cpuc, leader, true); |
1da53e02 | 1760 | if (n < 0) |
cd8a38d3 | 1761 | goto out; |
fe9081cc | 1762 | |
502568d5 PZ |
1763 | fake_cpuc->n_events = n; |
1764 | n = collect_events(fake_cpuc, event, false); | |
1da53e02 | 1765 | if (n < 0) |
cd8a38d3 | 1766 | goto out; |
fe9081cc | 1767 | |
502568d5 | 1768 | fake_cpuc->n_events = n; |
1da53e02 | 1769 | |
a072738e | 1770 | ret = x86_pmu.schedule_events(fake_cpuc, n, NULL); |
502568d5 | 1771 | |
502568d5 | 1772 | out: |
cd8a38d3 | 1773 | free_fake_cpuc(fake_cpuc); |
502568d5 | 1774 | return ret; |
fe9081cc PZ |
1775 | } |
1776 | ||
dda99116 | 1777 | static int x86_pmu_event_init(struct perf_event *event) |
621a01ea | 1778 | { |
51b0fe39 | 1779 | struct pmu *tmp; |
621a01ea IM |
1780 | int err; |
1781 | ||
b0a873eb PZ |
1782 | switch (event->attr.type) { |
1783 | case PERF_TYPE_RAW: | |
1784 | case PERF_TYPE_HARDWARE: | |
1785 | case PERF_TYPE_HW_CACHE: | |
1786 | break; | |
1787 | ||
1788 | default: | |
1789 | return -ENOENT; | |
1790 | } | |
1791 | ||
1792 | err = __x86_pmu_event_init(event); | |
fe9081cc | 1793 | if (!err) { |
8113070d SE |
1794 | /* |
1795 | * we temporarily connect event to its pmu | |
1796 | * such that validate_group() can classify | |
1797 | * it as an x86 event using is_x86_event() | |
1798 | */ | |
1799 | tmp = event->pmu; | |
1800 | event->pmu = &pmu; | |
1801 | ||
fe9081cc PZ |
1802 | if (event->group_leader != event) |
1803 | err = validate_group(event); | |
ca037701 PZ |
1804 | else |
1805 | err = validate_event(event); | |
8113070d SE |
1806 | |
1807 | event->pmu = tmp; | |
fe9081cc | 1808 | } |
a1792cda | 1809 | if (err) { |
cdd6c482 IM |
1810 | if (event->destroy) |
1811 | event->destroy(event); | |
a1792cda | 1812 | } |
621a01ea | 1813 | |
b0a873eb | 1814 | return err; |
621a01ea | 1815 | } |
d7d59fb3 | 1816 | |
fe4a3308 PZ |
1817 | static int x86_pmu_event_idx(struct perf_event *event) |
1818 | { | |
1819 | int idx = event->hw.idx; | |
1820 | ||
c7206205 PZ |
1821 | if (!x86_pmu.attr_rdpmc) |
1822 | return 0; | |
1823 | ||
15c7ad51 RR |
1824 | if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) { |
1825 | idx -= INTEL_PMC_IDX_FIXED; | |
fe4a3308 PZ |
1826 | idx |= 1 << 30; |
1827 | } | |
1828 | ||
1829 | return idx + 1; | |
1830 | } | |
1831 | ||
0c9d42ed PZ |
1832 | static ssize_t get_attr_rdpmc(struct device *cdev, |
1833 | struct device_attribute *attr, | |
1834 | char *buf) | |
1835 | { | |
1836 | return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc); | |
1837 | } | |
1838 | ||
1839 | static void change_rdpmc(void *info) | |
1840 | { | |
1841 | bool enable = !!(unsigned long)info; | |
1842 | ||
1843 | if (enable) | |
1844 | set_in_cr4(X86_CR4_PCE); | |
1845 | else | |
1846 | clear_in_cr4(X86_CR4_PCE); | |
1847 | } | |
1848 | ||
1849 | static ssize_t set_attr_rdpmc(struct device *cdev, | |
1850 | struct device_attribute *attr, | |
1851 | const char *buf, size_t count) | |
1852 | { | |
e2b297fc SK |
1853 | unsigned long val; |
1854 | ssize_t ret; | |
1855 | ||
1856 | ret = kstrtoul(buf, 0, &val); | |
1857 | if (ret) | |
1858 | return ret; | |
e97df763 PZ |
1859 | |
1860 | if (x86_pmu.attr_rdpmc_broken) | |
1861 | return -ENOTSUPP; | |
0c9d42ed PZ |
1862 | |
1863 | if (!!val != !!x86_pmu.attr_rdpmc) { | |
1864 | x86_pmu.attr_rdpmc = !!val; | |
0e9f2204 | 1865 | on_each_cpu(change_rdpmc, (void *)val, 1); |
0c9d42ed PZ |
1866 | } |
1867 | ||
1868 | return count; | |
1869 | } | |
1870 | ||
1871 | static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc); | |
1872 | ||
1873 | static struct attribute *x86_pmu_attrs[] = { | |
1874 | &dev_attr_rdpmc.attr, | |
1875 | NULL, | |
1876 | }; | |
1877 | ||
1878 | static struct attribute_group x86_pmu_attr_group = { | |
1879 | .attrs = x86_pmu_attrs, | |
1880 | }; | |
1881 | ||
1882 | static const struct attribute_group *x86_pmu_attr_groups[] = { | |
1883 | &x86_pmu_attr_group, | |
641cc938 | 1884 | &x86_pmu_format_group, |
a4747393 | 1885 | &x86_pmu_events_group, |
0c9d42ed PZ |
1886 | NULL, |
1887 | }; | |
1888 | ||
d010b332 SE |
1889 | static void x86_pmu_flush_branch_stack(void) |
1890 | { | |
1891 | if (x86_pmu.flush_branch_stack) | |
1892 | x86_pmu.flush_branch_stack(); | |
1893 | } | |
1894 | ||
c93dc84c PZ |
1895 | void perf_check_microcode(void) |
1896 | { | |
1897 | if (x86_pmu.check_microcode) | |
1898 | x86_pmu.check_microcode(); | |
1899 | } | |
1900 | EXPORT_SYMBOL_GPL(perf_check_microcode); | |
1901 | ||
b0a873eb | 1902 | static struct pmu pmu = { |
d010b332 SE |
1903 | .pmu_enable = x86_pmu_enable, |
1904 | .pmu_disable = x86_pmu_disable, | |
a4eaf7f1 | 1905 | |
c93dc84c | 1906 | .attr_groups = x86_pmu_attr_groups, |
0c9d42ed | 1907 | |
c93dc84c | 1908 | .event_init = x86_pmu_event_init, |
a4eaf7f1 | 1909 | |
d010b332 SE |
1910 | .add = x86_pmu_add, |
1911 | .del = x86_pmu_del, | |
1912 | .start = x86_pmu_start, | |
1913 | .stop = x86_pmu_stop, | |
1914 | .read = x86_pmu_read, | |
a4eaf7f1 | 1915 | |
c93dc84c PZ |
1916 | .start_txn = x86_pmu_start_txn, |
1917 | .cancel_txn = x86_pmu_cancel_txn, | |
1918 | .commit_txn = x86_pmu_commit_txn, | |
fe4a3308 | 1919 | |
c93dc84c | 1920 | .event_idx = x86_pmu_event_idx, |
d010b332 | 1921 | .flush_branch_stack = x86_pmu_flush_branch_stack, |
b0a873eb PZ |
1922 | }; |
1923 | ||
c7206205 | 1924 | void arch_perf_update_userpage(struct perf_event_mmap_page *userpg, u64 now) |
e3f3541c | 1925 | { |
20d1c86a PZ |
1926 | struct cyc2ns_data *data; |
1927 | ||
fa731587 PZ |
1928 | userpg->cap_user_time = 0; |
1929 | userpg->cap_user_time_zero = 0; | |
1930 | userpg->cap_user_rdpmc = x86_pmu.attr_rdpmc; | |
c7206205 PZ |
1931 | userpg->pmc_width = x86_pmu.cntval_bits; |
1932 | ||
35af99e6 | 1933 | if (!sched_clock_stable()) |
e3f3541c PZ |
1934 | return; |
1935 | ||
20d1c86a PZ |
1936 | data = cyc2ns_read_begin(); |
1937 | ||
fa731587 | 1938 | userpg->cap_user_time = 1; |
20d1c86a PZ |
1939 | userpg->time_mult = data->cyc2ns_mul; |
1940 | userpg->time_shift = data->cyc2ns_shift; | |
1941 | userpg->time_offset = data->cyc2ns_offset - now; | |
c73deb6a | 1942 | |
d8b11a0c | 1943 | userpg->cap_user_time_zero = 1; |
20d1c86a PZ |
1944 | userpg->time_zero = data->cyc2ns_offset; |
1945 | ||
1946 | cyc2ns_read_end(data); | |
e3f3541c PZ |
1947 | } |
1948 | ||
d7d59fb3 PZ |
1949 | /* |
1950 | * callchain support | |
1951 | */ | |
1952 | ||
d7d59fb3 PZ |
1953 | static int backtrace_stack(void *data, char *name) |
1954 | { | |
038e836e | 1955 | return 0; |
d7d59fb3 PZ |
1956 | } |
1957 | ||
1958 | static void backtrace_address(void *data, unsigned long addr, int reliable) | |
1959 | { | |
1960 | struct perf_callchain_entry *entry = data; | |
1961 | ||
70791ce9 | 1962 | perf_callchain_store(entry, addr); |
d7d59fb3 PZ |
1963 | } |
1964 | ||
1965 | static const struct stacktrace_ops backtrace_ops = { | |
d7d59fb3 PZ |
1966 | .stack = backtrace_stack, |
1967 | .address = backtrace_address, | |
06d65bda | 1968 | .walk_stack = print_context_stack_bp, |
d7d59fb3 PZ |
1969 | }; |
1970 | ||
56962b44 FW |
1971 | void |
1972 | perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 | 1973 | { |
927c7a9e FW |
1974 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
1975 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 1976 | return; |
927c7a9e FW |
1977 | } |
1978 | ||
70791ce9 | 1979 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 1980 | |
e8e999cf | 1981 | dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry); |
d7d59fb3 PZ |
1982 | } |
1983 | ||
bc6ca7b3 AS |
1984 | static inline int |
1985 | valid_user_frame(const void __user *fp, unsigned long size) | |
1986 | { | |
1987 | return (__range_not_ok(fp, size, TASK_SIZE) == 0); | |
1988 | } | |
1989 | ||
d07bdfd3 PZ |
1990 | static unsigned long get_segment_base(unsigned int segment) |
1991 | { | |
1992 | struct desc_struct *desc; | |
1993 | int idx = segment >> 3; | |
1994 | ||
1995 | if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) { | |
1996 | if (idx > LDT_ENTRIES) | |
1997 | return 0; | |
1998 | ||
1999 | if (idx > current->active_mm->context.size) | |
2000 | return 0; | |
2001 | ||
2002 | desc = current->active_mm->context.ldt; | |
2003 | } else { | |
2004 | if (idx > GDT_ENTRIES) | |
2005 | return 0; | |
2006 | ||
2007 | desc = __this_cpu_ptr(&gdt_page.gdt[0]); | |
2008 | } | |
2009 | ||
2010 | return get_desc_base(desc + idx); | |
2011 | } | |
2012 | ||
257ef9d2 | 2013 | #ifdef CONFIG_COMPAT |
d1a797f3 PA |
2014 | |
2015 | #include <asm/compat.h> | |
2016 | ||
257ef9d2 TE |
2017 | static inline int |
2018 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
74193ef0 | 2019 | { |
257ef9d2 | 2020 | /* 32-bit process in 64-bit kernel. */ |
d07bdfd3 | 2021 | unsigned long ss_base, cs_base; |
257ef9d2 TE |
2022 | struct stack_frame_ia32 frame; |
2023 | const void __user *fp; | |
74193ef0 | 2024 | |
257ef9d2 TE |
2025 | if (!test_thread_flag(TIF_IA32)) |
2026 | return 0; | |
2027 | ||
d07bdfd3 PZ |
2028 | cs_base = get_segment_base(regs->cs); |
2029 | ss_base = get_segment_base(regs->ss); | |
2030 | ||
2031 | fp = compat_ptr(ss_base + regs->bp); | |
257ef9d2 TE |
2032 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
2033 | unsigned long bytes; | |
2034 | frame.next_frame = 0; | |
2035 | frame.return_address = 0; | |
2036 | ||
2037 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); | |
0a196848 | 2038 | if (bytes != 0) |
257ef9d2 | 2039 | break; |
74193ef0 | 2040 | |
bc6ca7b3 AS |
2041 | if (!valid_user_frame(fp, sizeof(frame))) |
2042 | break; | |
2043 | ||
d07bdfd3 PZ |
2044 | perf_callchain_store(entry, cs_base + frame.return_address); |
2045 | fp = compat_ptr(ss_base + frame.next_frame); | |
257ef9d2 TE |
2046 | } |
2047 | return 1; | |
d7d59fb3 | 2048 | } |
257ef9d2 TE |
2049 | #else |
2050 | static inline int | |
2051 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
2052 | { | |
2053 | return 0; | |
2054 | } | |
2055 | #endif | |
d7d59fb3 | 2056 | |
56962b44 FW |
2057 | void |
2058 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 PZ |
2059 | { |
2060 | struct stack_frame frame; | |
2061 | const void __user *fp; | |
2062 | ||
927c7a9e FW |
2063 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
2064 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 2065 | return; |
927c7a9e | 2066 | } |
5a6cec3a | 2067 | |
d07bdfd3 PZ |
2068 | /* |
2069 | * We don't know what to do with VM86 stacks.. ignore them for now. | |
2070 | */ | |
2071 | if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM)) | |
2072 | return; | |
2073 | ||
74193ef0 | 2074 | fp = (void __user *)regs->bp; |
d7d59fb3 | 2075 | |
70791ce9 | 2076 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 2077 | |
20afc60f AV |
2078 | if (!current->mm) |
2079 | return; | |
2080 | ||
257ef9d2 TE |
2081 | if (perf_callchain_user32(regs, entry)) |
2082 | return; | |
2083 | ||
f9188e02 | 2084 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
257ef9d2 | 2085 | unsigned long bytes; |
038e836e | 2086 | frame.next_frame = NULL; |
d7d59fb3 PZ |
2087 | frame.return_address = 0; |
2088 | ||
257ef9d2 | 2089 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); |
0a196848 | 2090 | if (bytes != 0) |
d7d59fb3 PZ |
2091 | break; |
2092 | ||
bc6ca7b3 AS |
2093 | if (!valid_user_frame(fp, sizeof(frame))) |
2094 | break; | |
2095 | ||
70791ce9 | 2096 | perf_callchain_store(entry, frame.return_address); |
038e836e | 2097 | fp = frame.next_frame; |
d7d59fb3 PZ |
2098 | } |
2099 | } | |
2100 | ||
d07bdfd3 PZ |
2101 | /* |
2102 | * Deal with code segment offsets for the various execution modes: | |
2103 | * | |
2104 | * VM86 - the good olde 16 bit days, where the linear address is | |
2105 | * 20 bits and we use regs->ip + 0x10 * regs->cs. | |
2106 | * | |
2107 | * IA32 - Where we need to look at GDT/LDT segment descriptor tables | |
2108 | * to figure out what the 32bit base address is. | |
2109 | * | |
2110 | * X32 - has TIF_X32 set, but is running in x86_64 | |
2111 | * | |
2112 | * X86_64 - CS,DS,SS,ES are all zero based. | |
2113 | */ | |
2114 | static unsigned long code_segment_base(struct pt_regs *regs) | |
39447b38 | 2115 | { |
d07bdfd3 PZ |
2116 | /* |
2117 | * If we are in VM86 mode, add the segment offset to convert to a | |
2118 | * linear address. | |
2119 | */ | |
2120 | if (regs->flags & X86_VM_MASK) | |
2121 | return 0x10 * regs->cs; | |
2122 | ||
2123 | /* | |
2124 | * For IA32 we look at the GDT/LDT segment base to convert the | |
2125 | * effective IP to a linear address. | |
2126 | */ | |
2127 | #ifdef CONFIG_X86_32 | |
2128 | if (user_mode(regs) && regs->cs != __USER_CS) | |
2129 | return get_segment_base(regs->cs); | |
2130 | #else | |
2131 | if (test_thread_flag(TIF_IA32)) { | |
2132 | if (user_mode(regs) && regs->cs != __USER32_CS) | |
2133 | return get_segment_base(regs->cs); | |
2134 | } | |
2135 | #endif | |
2136 | return 0; | |
2137 | } | |
dcf46b94 | 2138 | |
d07bdfd3 PZ |
2139 | unsigned long perf_instruction_pointer(struct pt_regs *regs) |
2140 | { | |
39447b38 | 2141 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) |
d07bdfd3 | 2142 | return perf_guest_cbs->get_guest_ip(); |
dcf46b94 | 2143 | |
d07bdfd3 | 2144 | return regs->ip + code_segment_base(regs); |
39447b38 ZY |
2145 | } |
2146 | ||
2147 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
2148 | { | |
2149 | int misc = 0; | |
dcf46b94 | 2150 | |
39447b38 | 2151 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
dcf46b94 ZY |
2152 | if (perf_guest_cbs->is_user_mode()) |
2153 | misc |= PERF_RECORD_MISC_GUEST_USER; | |
2154 | else | |
2155 | misc |= PERF_RECORD_MISC_GUEST_KERNEL; | |
2156 | } else { | |
d07bdfd3 | 2157 | if (user_mode(regs)) |
dcf46b94 ZY |
2158 | misc |= PERF_RECORD_MISC_USER; |
2159 | else | |
2160 | misc |= PERF_RECORD_MISC_KERNEL; | |
2161 | } | |
2162 | ||
39447b38 | 2163 | if (regs->flags & PERF_EFLAGS_EXACT) |
ab608344 | 2164 | misc |= PERF_RECORD_MISC_EXACT_IP; |
39447b38 ZY |
2165 | |
2166 | return misc; | |
2167 | } | |
b3d9468a GN |
2168 | |
2169 | void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap) | |
2170 | { | |
2171 | cap->version = x86_pmu.version; | |
2172 | cap->num_counters_gp = x86_pmu.num_counters; | |
2173 | cap->num_counters_fixed = x86_pmu.num_counters_fixed; | |
2174 | cap->bit_width_gp = x86_pmu.cntval_bits; | |
2175 | cap->bit_width_fixed = x86_pmu.cntval_bits; | |
2176 | cap->events_mask = (unsigned int)x86_pmu.events_maskl; | |
2177 | cap->events_mask_len = x86_pmu.events_mask_len; | |
2178 | } | |
2179 | EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability); |