Commit | Line | Data |
---|---|---|
241771ef | 1 | /* |
cdd6c482 | 2 | * Performance events x86 architecture code |
241771ef | 3 | * |
98144511 IM |
4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> | |
30dd568c | 9 | * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> |
1da53e02 | 10 | * Copyright (C) 2009 Google, Inc., Stephane Eranian |
241771ef IM |
11 | * |
12 | * For licencing details see kernel-base/COPYING | |
13 | */ | |
14 | ||
cdd6c482 | 15 | #include <linux/perf_event.h> |
241771ef IM |
16 | #include <linux/capability.h> |
17 | #include <linux/notifier.h> | |
18 | #include <linux/hardirq.h> | |
19 | #include <linux/kprobes.h> | |
4ac13294 | 20 | #include <linux/module.h> |
241771ef IM |
21 | #include <linux/kdebug.h> |
22 | #include <linux/sched.h> | |
d7d59fb3 | 23 | #include <linux/uaccess.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
30dd568c | 25 | #include <linux/cpu.h> |
272d30be | 26 | #include <linux/bitops.h> |
241771ef | 27 | |
241771ef | 28 | #include <asm/apic.h> |
d7d59fb3 | 29 | #include <asm/stacktrace.h> |
4e935e47 | 30 | #include <asm/nmi.h> |
257ef9d2 | 31 | #include <asm/compat.h> |
69092624 | 32 | #include <asm/smp.h> |
c8e5910e | 33 | #include <asm/alternative.h> |
241771ef | 34 | |
de0428a7 KW |
35 | #include "perf_event.h" |
36 | ||
7645a24c PZ |
37 | #if 0 |
38 | #undef wrmsrl | |
39 | #define wrmsrl(msr, val) \ | |
40 | do { \ | |
41 | trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\ | |
42 | (unsigned long)(val)); \ | |
43 | native_write_msr((msr), (u32)((u64)(val)), \ | |
44 | (u32)((u64)(val) >> 32)); \ | |
45 | } while (0) | |
46 | #endif | |
47 | ||
de0428a7 | 48 | struct x86_pmu x86_pmu __read_mostly; |
efc9f05d | 49 | |
de0428a7 | 50 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { |
b0f3f28e PZ |
51 | .enabled = 1, |
52 | }; | |
241771ef | 53 | |
de0428a7 | 54 | u64 __read_mostly hw_cache_event_ids |
8326f44d IM |
55 | [PERF_COUNT_HW_CACHE_MAX] |
56 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
57 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
de0428a7 | 58 | u64 __read_mostly hw_cache_extra_regs |
e994d7d2 AK |
59 | [PERF_COUNT_HW_CACHE_MAX] |
60 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
61 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
8326f44d | 62 | |
ee06094f | 63 | /* |
cdd6c482 IM |
64 | * Propagate event elapsed time into the generic event. |
65 | * Can only be executed on the CPU where the event is active. | |
ee06094f IM |
66 | * Returns the delta events processed. |
67 | */ | |
de0428a7 | 68 | u64 x86_perf_event_update(struct perf_event *event) |
ee06094f | 69 | { |
cc2ad4ba | 70 | struct hw_perf_event *hwc = &event->hw; |
948b1bb8 | 71 | int shift = 64 - x86_pmu.cntval_bits; |
ec3232bd | 72 | u64 prev_raw_count, new_raw_count; |
cc2ad4ba | 73 | int idx = hwc->idx; |
ec3232bd | 74 | s64 delta; |
ee06094f | 75 | |
30dd568c MM |
76 | if (idx == X86_PMC_IDX_FIXED_BTS) |
77 | return 0; | |
78 | ||
ee06094f | 79 | /* |
cdd6c482 | 80 | * Careful: an NMI might modify the previous event value. |
ee06094f IM |
81 | * |
82 | * Our tactic to handle this is to first atomically read and | |
83 | * exchange a new raw count - then add that new-prev delta | |
cdd6c482 | 84 | * count to the generic event atomically: |
ee06094f IM |
85 | */ |
86 | again: | |
e7850595 | 87 | prev_raw_count = local64_read(&hwc->prev_count); |
73d6e522 | 88 | rdmsrl(hwc->event_base, new_raw_count); |
ee06094f | 89 | |
e7850595 | 90 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
ee06094f IM |
91 | new_raw_count) != prev_raw_count) |
92 | goto again; | |
93 | ||
94 | /* | |
95 | * Now we have the new raw value and have updated the prev | |
96 | * timestamp already. We can now calculate the elapsed delta | |
cdd6c482 | 97 | * (event-)time and add that to the generic event. |
ee06094f IM |
98 | * |
99 | * Careful, not all hw sign-extends above the physical width | |
ec3232bd | 100 | * of the count. |
ee06094f | 101 | */ |
ec3232bd PZ |
102 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
103 | delta >>= shift; | |
ee06094f | 104 | |
e7850595 PZ |
105 | local64_add(delta, &event->count); |
106 | local64_sub(delta, &hwc->period_left); | |
4b7bfd0d RR |
107 | |
108 | return new_raw_count; | |
ee06094f IM |
109 | } |
110 | ||
a7e3ed1e AK |
111 | /* |
112 | * Find and validate any extra registers to set up. | |
113 | */ | |
114 | static int x86_pmu_extra_regs(u64 config, struct perf_event *event) | |
115 | { | |
efc9f05d | 116 | struct hw_perf_event_extra *reg; |
a7e3ed1e AK |
117 | struct extra_reg *er; |
118 | ||
efc9f05d | 119 | reg = &event->hw.extra_reg; |
a7e3ed1e AK |
120 | |
121 | if (!x86_pmu.extra_regs) | |
122 | return 0; | |
123 | ||
124 | for (er = x86_pmu.extra_regs; er->msr; er++) { | |
125 | if (er->event != (config & er->config_mask)) | |
126 | continue; | |
127 | if (event->attr.config1 & ~er->valid_mask) | |
128 | return -EINVAL; | |
efc9f05d SE |
129 | |
130 | reg->idx = er->idx; | |
131 | reg->config = event->attr.config1; | |
132 | reg->reg = er->msr; | |
a7e3ed1e AK |
133 | break; |
134 | } | |
135 | return 0; | |
136 | } | |
137 | ||
cdd6c482 | 138 | static atomic_t active_events; |
4e935e47 PZ |
139 | static DEFINE_MUTEX(pmc_reserve_mutex); |
140 | ||
b27ea29c RR |
141 | #ifdef CONFIG_X86_LOCAL_APIC |
142 | ||
4e935e47 PZ |
143 | static bool reserve_pmc_hardware(void) |
144 | { | |
145 | int i; | |
146 | ||
948b1bb8 | 147 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 | 148 | if (!reserve_perfctr_nmi(x86_pmu_event_addr(i))) |
4e935e47 PZ |
149 | goto perfctr_fail; |
150 | } | |
151 | ||
948b1bb8 | 152 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 | 153 | if (!reserve_evntsel_nmi(x86_pmu_config_addr(i))) |
4e935e47 PZ |
154 | goto eventsel_fail; |
155 | } | |
156 | ||
157 | return true; | |
158 | ||
159 | eventsel_fail: | |
160 | for (i--; i >= 0; i--) | |
41bf4989 | 161 | release_evntsel_nmi(x86_pmu_config_addr(i)); |
4e935e47 | 162 | |
948b1bb8 | 163 | i = x86_pmu.num_counters; |
4e935e47 PZ |
164 | |
165 | perfctr_fail: | |
166 | for (i--; i >= 0; i--) | |
41bf4989 | 167 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
4e935e47 | 168 | |
4e935e47 PZ |
169 | return false; |
170 | } | |
171 | ||
172 | static void release_pmc_hardware(void) | |
173 | { | |
174 | int i; | |
175 | ||
948b1bb8 | 176 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 RR |
177 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
178 | release_evntsel_nmi(x86_pmu_config_addr(i)); | |
4e935e47 | 179 | } |
4e935e47 PZ |
180 | } |
181 | ||
b27ea29c RR |
182 | #else |
183 | ||
184 | static bool reserve_pmc_hardware(void) { return true; } | |
185 | static void release_pmc_hardware(void) {} | |
186 | ||
187 | #endif | |
188 | ||
33c6d6a7 DZ |
189 | static bool check_hw_exists(void) |
190 | { | |
191 | u64 val, val_new = 0; | |
4407204c | 192 | int i, reg, ret = 0; |
33c6d6a7 | 193 | |
4407204c PZ |
194 | /* |
195 | * Check to see if the BIOS enabled any of the counters, if so | |
196 | * complain and bail. | |
197 | */ | |
198 | for (i = 0; i < x86_pmu.num_counters; i++) { | |
41bf4989 | 199 | reg = x86_pmu_config_addr(i); |
4407204c PZ |
200 | ret = rdmsrl_safe(reg, &val); |
201 | if (ret) | |
202 | goto msr_fail; | |
203 | if (val & ARCH_PERFMON_EVENTSEL_ENABLE) | |
204 | goto bios_fail; | |
205 | } | |
206 | ||
207 | if (x86_pmu.num_counters_fixed) { | |
208 | reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; | |
209 | ret = rdmsrl_safe(reg, &val); | |
210 | if (ret) | |
211 | goto msr_fail; | |
212 | for (i = 0; i < x86_pmu.num_counters_fixed; i++) { | |
213 | if (val & (0x03 << i*4)) | |
214 | goto bios_fail; | |
215 | } | |
216 | } | |
217 | ||
218 | /* | |
219 | * Now write a value and read it back to see if it matches, | |
220 | * this is needed to detect certain hardware emulators (qemu/kvm) | |
221 | * that don't trap on the MSR access and always return 0s. | |
222 | */ | |
33c6d6a7 | 223 | val = 0xabcdUL; |
41bf4989 RR |
224 | ret = checking_wrmsrl(x86_pmu_event_addr(0), val); |
225 | ret |= rdmsrl_safe(x86_pmu_event_addr(0), &val_new); | |
33c6d6a7 | 226 | if (ret || val != val_new) |
4407204c | 227 | goto msr_fail; |
33c6d6a7 DZ |
228 | |
229 | return true; | |
4407204c PZ |
230 | |
231 | bios_fail: | |
45daae57 IM |
232 | /* |
233 | * We still allow the PMU driver to operate: | |
234 | */ | |
235 | printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n"); | |
4407204c | 236 | printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg, val); |
45daae57 IM |
237 | |
238 | return true; | |
4407204c PZ |
239 | |
240 | msr_fail: | |
241 | printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n"); | |
45daae57 | 242 | |
4407204c | 243 | return false; |
33c6d6a7 DZ |
244 | } |
245 | ||
cdd6c482 | 246 | static void hw_perf_event_destroy(struct perf_event *event) |
4e935e47 | 247 | { |
cdd6c482 | 248 | if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) { |
4e935e47 | 249 | release_pmc_hardware(); |
ca037701 | 250 | release_ds_buffers(); |
4e935e47 PZ |
251 | mutex_unlock(&pmc_reserve_mutex); |
252 | } | |
253 | } | |
254 | ||
85cf9dba RR |
255 | static inline int x86_pmu_initialized(void) |
256 | { | |
257 | return x86_pmu.handle_irq != NULL; | |
258 | } | |
259 | ||
8326f44d | 260 | static inline int |
e994d7d2 | 261 | set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event) |
8326f44d | 262 | { |
e994d7d2 | 263 | struct perf_event_attr *attr = &event->attr; |
8326f44d IM |
264 | unsigned int cache_type, cache_op, cache_result; |
265 | u64 config, val; | |
266 | ||
267 | config = attr->config; | |
268 | ||
269 | cache_type = (config >> 0) & 0xff; | |
270 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
271 | return -EINVAL; | |
272 | ||
273 | cache_op = (config >> 8) & 0xff; | |
274 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
275 | return -EINVAL; | |
276 | ||
277 | cache_result = (config >> 16) & 0xff; | |
278 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
279 | return -EINVAL; | |
280 | ||
281 | val = hw_cache_event_ids[cache_type][cache_op][cache_result]; | |
282 | ||
283 | if (val == 0) | |
284 | return -ENOENT; | |
285 | ||
286 | if (val == -1) | |
287 | return -EINVAL; | |
288 | ||
289 | hwc->config |= val; | |
e994d7d2 AK |
290 | attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result]; |
291 | return x86_pmu_extra_regs(val, event); | |
8326f44d IM |
292 | } |
293 | ||
de0428a7 | 294 | int x86_setup_perfctr(struct perf_event *event) |
c1726f34 RR |
295 | { |
296 | struct perf_event_attr *attr = &event->attr; | |
297 | struct hw_perf_event *hwc = &event->hw; | |
298 | u64 config; | |
299 | ||
6c7e550f | 300 | if (!is_sampling_event(event)) { |
c1726f34 RR |
301 | hwc->sample_period = x86_pmu.max_period; |
302 | hwc->last_period = hwc->sample_period; | |
e7850595 | 303 | local64_set(&hwc->period_left, hwc->sample_period); |
c1726f34 RR |
304 | } else { |
305 | /* | |
306 | * If we have a PMU initialized but no APIC | |
307 | * interrupts, we cannot sample hardware | |
308 | * events (user-space has to fall back and | |
309 | * sample via a hrtimer based software event): | |
310 | */ | |
311 | if (!x86_pmu.apic) | |
312 | return -EOPNOTSUPP; | |
313 | } | |
314 | ||
315 | if (attr->type == PERF_TYPE_RAW) | |
ed13ec58 | 316 | return x86_pmu_extra_regs(event->attr.config, event); |
c1726f34 RR |
317 | |
318 | if (attr->type == PERF_TYPE_HW_CACHE) | |
e994d7d2 | 319 | return set_ext_hw_attr(hwc, event); |
c1726f34 RR |
320 | |
321 | if (attr->config >= x86_pmu.max_events) | |
322 | return -EINVAL; | |
323 | ||
324 | /* | |
325 | * The generic map: | |
326 | */ | |
327 | config = x86_pmu.event_map(attr->config); | |
328 | ||
329 | if (config == 0) | |
330 | return -ENOENT; | |
331 | ||
332 | if (config == -1LL) | |
333 | return -EINVAL; | |
334 | ||
335 | /* | |
336 | * Branch tracing: | |
337 | */ | |
18a073a3 PZ |
338 | if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS && |
339 | !attr->freq && hwc->sample_period == 1) { | |
c1726f34 | 340 | /* BTS is not supported by this architecture. */ |
6809b6ea | 341 | if (!x86_pmu.bts_active) |
c1726f34 RR |
342 | return -EOPNOTSUPP; |
343 | ||
344 | /* BTS is currently only allowed for user-mode. */ | |
345 | if (!attr->exclude_kernel) | |
346 | return -EOPNOTSUPP; | |
347 | } | |
348 | ||
349 | hwc->config |= config; | |
350 | ||
351 | return 0; | |
352 | } | |
4261e0e0 | 353 | |
de0428a7 | 354 | int x86_pmu_hw_config(struct perf_event *event) |
a072738e | 355 | { |
ab608344 PZ |
356 | if (event->attr.precise_ip) { |
357 | int precise = 0; | |
358 | ||
359 | /* Support for constant skid */ | |
6809b6ea | 360 | if (x86_pmu.pebs_active) { |
ab608344 PZ |
361 | precise++; |
362 | ||
5553be26 PZ |
363 | /* Support for IP fixup */ |
364 | if (x86_pmu.lbr_nr) | |
365 | precise++; | |
366 | } | |
ab608344 PZ |
367 | |
368 | if (event->attr.precise_ip > precise) | |
369 | return -EOPNOTSUPP; | |
370 | } | |
371 | ||
a072738e CG |
372 | /* |
373 | * Generate PMC IRQs: | |
374 | * (keep 'enabled' bit clear for now) | |
375 | */ | |
b4cdc5c2 | 376 | event->hw.config = ARCH_PERFMON_EVENTSEL_INT; |
a072738e CG |
377 | |
378 | /* | |
379 | * Count user and OS events unless requested not to | |
380 | */ | |
b4cdc5c2 PZ |
381 | if (!event->attr.exclude_user) |
382 | event->hw.config |= ARCH_PERFMON_EVENTSEL_USR; | |
383 | if (!event->attr.exclude_kernel) | |
384 | event->hw.config |= ARCH_PERFMON_EVENTSEL_OS; | |
a072738e | 385 | |
b4cdc5c2 PZ |
386 | if (event->attr.type == PERF_TYPE_RAW) |
387 | event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK; | |
a072738e | 388 | |
9d0fcba6 | 389 | return x86_setup_perfctr(event); |
a098f448 RR |
390 | } |
391 | ||
241771ef | 392 | /* |
0d48696f | 393 | * Setup the hardware configuration for a given attr_type |
241771ef | 394 | */ |
b0a873eb | 395 | static int __x86_pmu_event_init(struct perf_event *event) |
241771ef | 396 | { |
4e935e47 | 397 | int err; |
241771ef | 398 | |
85cf9dba RR |
399 | if (!x86_pmu_initialized()) |
400 | return -ENODEV; | |
241771ef | 401 | |
4e935e47 | 402 | err = 0; |
cdd6c482 | 403 | if (!atomic_inc_not_zero(&active_events)) { |
4e935e47 | 404 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 | 405 | if (atomic_read(&active_events) == 0) { |
30dd568c MM |
406 | if (!reserve_pmc_hardware()) |
407 | err = -EBUSY; | |
f80c9e30 PZ |
408 | else |
409 | reserve_ds_buffers(); | |
30dd568c MM |
410 | } |
411 | if (!err) | |
cdd6c482 | 412 | atomic_inc(&active_events); |
4e935e47 PZ |
413 | mutex_unlock(&pmc_reserve_mutex); |
414 | } | |
415 | if (err) | |
416 | return err; | |
417 | ||
cdd6c482 | 418 | event->destroy = hw_perf_event_destroy; |
a1792cda | 419 | |
4261e0e0 RR |
420 | event->hw.idx = -1; |
421 | event->hw.last_cpu = -1; | |
422 | event->hw.last_tag = ~0ULL; | |
b690081d | 423 | |
efc9f05d SE |
424 | /* mark unused */ |
425 | event->hw.extra_reg.idx = EXTRA_REG_NONE; | |
426 | ||
9d0fcba6 | 427 | return x86_pmu.hw_config(event); |
4261e0e0 RR |
428 | } |
429 | ||
de0428a7 | 430 | void x86_pmu_disable_all(void) |
f87ad35d | 431 | { |
cdd6c482 | 432 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
9e35ad38 PZ |
433 | int idx; |
434 | ||
948b1bb8 | 435 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
b0f3f28e PZ |
436 | u64 val; |
437 | ||
43f6201a | 438 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 439 | continue; |
41bf4989 | 440 | rdmsrl(x86_pmu_config_addr(idx), val); |
bb1165d6 | 441 | if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE)) |
4295ee62 | 442 | continue; |
bb1165d6 | 443 | val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; |
41bf4989 | 444 | wrmsrl(x86_pmu_config_addr(idx), val); |
f87ad35d | 445 | } |
f87ad35d JSR |
446 | } |
447 | ||
a4eaf7f1 | 448 | static void x86_pmu_disable(struct pmu *pmu) |
b56a3802 | 449 | { |
1da53e02 SE |
450 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
451 | ||
85cf9dba | 452 | if (!x86_pmu_initialized()) |
9e35ad38 | 453 | return; |
1da53e02 | 454 | |
1a6e21f7 PZ |
455 | if (!cpuc->enabled) |
456 | return; | |
457 | ||
458 | cpuc->n_added = 0; | |
459 | cpuc->enabled = 0; | |
460 | barrier(); | |
1da53e02 SE |
461 | |
462 | x86_pmu.disable_all(); | |
b56a3802 | 463 | } |
241771ef | 464 | |
de0428a7 | 465 | void x86_pmu_enable_all(int added) |
f87ad35d | 466 | { |
cdd6c482 | 467 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
f87ad35d JSR |
468 | int idx; |
469 | ||
948b1bb8 | 470 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
d45dd923 | 471 | struct hw_perf_event *hwc = &cpuc->events[idx]->hw; |
b0f3f28e | 472 | |
43f6201a | 473 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 474 | continue; |
984b838c | 475 | |
d45dd923 | 476 | __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); |
f87ad35d JSR |
477 | } |
478 | } | |
479 | ||
51b0fe39 | 480 | static struct pmu pmu; |
1da53e02 SE |
481 | |
482 | static inline int is_x86_event(struct perf_event *event) | |
483 | { | |
484 | return event->pmu == &pmu; | |
485 | } | |
486 | ||
1e2ad28f RR |
487 | /* |
488 | * Event scheduler state: | |
489 | * | |
490 | * Assign events iterating over all events and counters, beginning | |
491 | * with events with least weights first. Keep the current iterator | |
492 | * state in struct sched_state. | |
493 | */ | |
494 | struct sched_state { | |
495 | int weight; | |
496 | int event; /* event index */ | |
497 | int counter; /* counter index */ | |
498 | int unassigned; /* number of events to be assigned left */ | |
499 | unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
500 | }; | |
501 | ||
bc1738f6 RR |
502 | /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */ |
503 | #define SCHED_STATES_MAX 2 | |
504 | ||
1e2ad28f RR |
505 | struct perf_sched { |
506 | int max_weight; | |
507 | int max_events; | |
508 | struct event_constraint **constraints; | |
509 | struct sched_state state; | |
bc1738f6 RR |
510 | int saved_states; |
511 | struct sched_state saved[SCHED_STATES_MAX]; | |
1e2ad28f RR |
512 | }; |
513 | ||
514 | /* | |
515 | * Initialize interator that runs through all events and counters. | |
516 | */ | |
517 | static void perf_sched_init(struct perf_sched *sched, struct event_constraint **c, | |
518 | int num, int wmin, int wmax) | |
519 | { | |
520 | int idx; | |
521 | ||
522 | memset(sched, 0, sizeof(*sched)); | |
523 | sched->max_events = num; | |
524 | sched->max_weight = wmax; | |
525 | sched->constraints = c; | |
526 | ||
527 | for (idx = 0; idx < num; idx++) { | |
528 | if (c[idx]->weight == wmin) | |
529 | break; | |
530 | } | |
531 | ||
532 | sched->state.event = idx; /* start with min weight */ | |
533 | sched->state.weight = wmin; | |
534 | sched->state.unassigned = num; | |
535 | } | |
536 | ||
bc1738f6 RR |
537 | static void perf_sched_save_state(struct perf_sched *sched) |
538 | { | |
539 | if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX)) | |
540 | return; | |
541 | ||
542 | sched->saved[sched->saved_states] = sched->state; | |
543 | sched->saved_states++; | |
544 | } | |
545 | ||
546 | static bool perf_sched_restore_state(struct perf_sched *sched) | |
547 | { | |
548 | if (!sched->saved_states) | |
549 | return false; | |
550 | ||
551 | sched->saved_states--; | |
552 | sched->state = sched->saved[sched->saved_states]; | |
553 | ||
554 | /* continue with next counter: */ | |
555 | clear_bit(sched->state.counter++, sched->state.used); | |
556 | ||
557 | return true; | |
558 | } | |
559 | ||
1e2ad28f RR |
560 | /* |
561 | * Select a counter for the current event to schedule. Return true on | |
562 | * success. | |
563 | */ | |
bc1738f6 | 564 | static bool __perf_sched_find_counter(struct perf_sched *sched) |
1e2ad28f RR |
565 | { |
566 | struct event_constraint *c; | |
567 | int idx; | |
568 | ||
569 | if (!sched->state.unassigned) | |
570 | return false; | |
571 | ||
572 | if (sched->state.event >= sched->max_events) | |
573 | return false; | |
574 | ||
575 | c = sched->constraints[sched->state.event]; | |
576 | ||
4defea85 PZ |
577 | /* Prefer fixed purpose counters */ |
578 | if (x86_pmu.num_counters_fixed) { | |
579 | idx = X86_PMC_IDX_FIXED; | |
580 | for_each_set_bit_cont(idx, c->idxmsk, X86_PMC_IDX_MAX) { | |
581 | if (!__test_and_set_bit(idx, sched->state.used)) | |
582 | goto done; | |
583 | } | |
584 | } | |
1e2ad28f RR |
585 | /* Grab the first unused counter starting with idx */ |
586 | idx = sched->state.counter; | |
4defea85 | 587 | for_each_set_bit_cont(idx, c->idxmsk, X86_PMC_IDX_FIXED) { |
1e2ad28f | 588 | if (!__test_and_set_bit(idx, sched->state.used)) |
4defea85 | 589 | goto done; |
1e2ad28f | 590 | } |
1e2ad28f | 591 | |
4defea85 PZ |
592 | return false; |
593 | ||
594 | done: | |
595 | sched->state.counter = idx; | |
1e2ad28f | 596 | |
bc1738f6 RR |
597 | if (c->overlap) |
598 | perf_sched_save_state(sched); | |
599 | ||
600 | return true; | |
601 | } | |
602 | ||
603 | static bool perf_sched_find_counter(struct perf_sched *sched) | |
604 | { | |
605 | while (!__perf_sched_find_counter(sched)) { | |
606 | if (!perf_sched_restore_state(sched)) | |
607 | return false; | |
608 | } | |
609 | ||
1e2ad28f RR |
610 | return true; |
611 | } | |
612 | ||
613 | /* | |
614 | * Go through all unassigned events and find the next one to schedule. | |
615 | * Take events with the least weight first. Return true on success. | |
616 | */ | |
617 | static bool perf_sched_next_event(struct perf_sched *sched) | |
618 | { | |
619 | struct event_constraint *c; | |
620 | ||
621 | if (!sched->state.unassigned || !--sched->state.unassigned) | |
622 | return false; | |
623 | ||
624 | do { | |
625 | /* next event */ | |
626 | sched->state.event++; | |
627 | if (sched->state.event >= sched->max_events) { | |
628 | /* next weight */ | |
629 | sched->state.event = 0; | |
630 | sched->state.weight++; | |
631 | if (sched->state.weight > sched->max_weight) | |
632 | return false; | |
633 | } | |
634 | c = sched->constraints[sched->state.event]; | |
635 | } while (c->weight != sched->state.weight); | |
636 | ||
637 | sched->state.counter = 0; /* start with first counter */ | |
638 | ||
639 | return true; | |
640 | } | |
641 | ||
642 | /* | |
643 | * Assign a counter for each event. | |
644 | */ | |
645 | static int perf_assign_events(struct event_constraint **constraints, int n, | |
646 | int wmin, int wmax, int *assign) | |
647 | { | |
648 | struct perf_sched sched; | |
649 | ||
650 | perf_sched_init(&sched, constraints, n, wmin, wmax); | |
651 | ||
652 | do { | |
653 | if (!perf_sched_find_counter(&sched)) | |
654 | break; /* failed */ | |
655 | if (assign) | |
656 | assign[sched.state.event] = sched.state.counter; | |
657 | } while (perf_sched_next_event(&sched)); | |
658 | ||
659 | return sched.state.unassigned; | |
660 | } | |
661 | ||
de0428a7 | 662 | int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) |
1da53e02 | 663 | { |
63b14649 | 664 | struct event_constraint *c, *constraints[X86_PMC_IDX_MAX]; |
1da53e02 | 665 | unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
1e2ad28f | 666 | int i, wmin, wmax, num = 0; |
1da53e02 SE |
667 | struct hw_perf_event *hwc; |
668 | ||
669 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); | |
670 | ||
1e2ad28f | 671 | for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) { |
b622d644 PZ |
672 | c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]); |
673 | constraints[i] = c; | |
1e2ad28f RR |
674 | wmin = min(wmin, c->weight); |
675 | wmax = max(wmax, c->weight); | |
1da53e02 SE |
676 | } |
677 | ||
8113070d SE |
678 | /* |
679 | * fastpath, try to reuse previous register | |
680 | */ | |
c933c1a6 | 681 | for (i = 0; i < n; i++) { |
8113070d | 682 | hwc = &cpuc->event_list[i]->hw; |
81269a08 | 683 | c = constraints[i]; |
8113070d SE |
684 | |
685 | /* never assigned */ | |
686 | if (hwc->idx == -1) | |
687 | break; | |
688 | ||
689 | /* constraint still honored */ | |
63b14649 | 690 | if (!test_bit(hwc->idx, c->idxmsk)) |
8113070d SE |
691 | break; |
692 | ||
693 | /* not already used */ | |
694 | if (test_bit(hwc->idx, used_mask)) | |
695 | break; | |
696 | ||
34538ee7 | 697 | __set_bit(hwc->idx, used_mask); |
8113070d SE |
698 | if (assign) |
699 | assign[i] = hwc->idx; | |
700 | } | |
8113070d | 701 | |
1e2ad28f RR |
702 | /* slow path */ |
703 | if (i != n) | |
704 | num = perf_assign_events(constraints, n, wmin, wmax, assign); | |
8113070d | 705 | |
1da53e02 SE |
706 | /* |
707 | * scheduling failed or is just a simulation, | |
708 | * free resources if necessary | |
709 | */ | |
710 | if (!assign || num) { | |
711 | for (i = 0; i < n; i++) { | |
712 | if (x86_pmu.put_event_constraints) | |
713 | x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]); | |
714 | } | |
715 | } | |
aa2bc1ad | 716 | return num ? -EINVAL : 0; |
1da53e02 SE |
717 | } |
718 | ||
719 | /* | |
720 | * dogrp: true if must collect siblings events (group) | |
721 | * returns total number of events and error code | |
722 | */ | |
723 | static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp) | |
724 | { | |
725 | struct perf_event *event; | |
726 | int n, max_count; | |
727 | ||
948b1bb8 | 728 | max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed; |
1da53e02 SE |
729 | |
730 | /* current number of events already accepted */ | |
731 | n = cpuc->n_events; | |
732 | ||
733 | if (is_x86_event(leader)) { | |
734 | if (n >= max_count) | |
aa2bc1ad | 735 | return -EINVAL; |
1da53e02 SE |
736 | cpuc->event_list[n] = leader; |
737 | n++; | |
738 | } | |
739 | if (!dogrp) | |
740 | return n; | |
741 | ||
742 | list_for_each_entry(event, &leader->sibling_list, group_entry) { | |
743 | if (!is_x86_event(event) || | |
8113070d | 744 | event->state <= PERF_EVENT_STATE_OFF) |
1da53e02 SE |
745 | continue; |
746 | ||
747 | if (n >= max_count) | |
aa2bc1ad | 748 | return -EINVAL; |
1da53e02 SE |
749 | |
750 | cpuc->event_list[n] = event; | |
751 | n++; | |
752 | } | |
753 | return n; | |
754 | } | |
755 | ||
1da53e02 | 756 | static inline void x86_assign_hw_event(struct perf_event *event, |
447a194b | 757 | struct cpu_hw_events *cpuc, int i) |
1da53e02 | 758 | { |
447a194b SE |
759 | struct hw_perf_event *hwc = &event->hw; |
760 | ||
761 | hwc->idx = cpuc->assign[i]; | |
762 | hwc->last_cpu = smp_processor_id(); | |
763 | hwc->last_tag = ++cpuc->tags[i]; | |
1da53e02 SE |
764 | |
765 | if (hwc->idx == X86_PMC_IDX_FIXED_BTS) { | |
766 | hwc->config_base = 0; | |
767 | hwc->event_base = 0; | |
768 | } else if (hwc->idx >= X86_PMC_IDX_FIXED) { | |
769 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; | |
fc66c521 | 770 | hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - X86_PMC_IDX_FIXED); |
1da53e02 | 771 | } else { |
73d6e522 RR |
772 | hwc->config_base = x86_pmu_config_addr(hwc->idx); |
773 | hwc->event_base = x86_pmu_event_addr(hwc->idx); | |
1da53e02 SE |
774 | } |
775 | } | |
776 | ||
447a194b SE |
777 | static inline int match_prev_assignment(struct hw_perf_event *hwc, |
778 | struct cpu_hw_events *cpuc, | |
779 | int i) | |
780 | { | |
781 | return hwc->idx == cpuc->assign[i] && | |
782 | hwc->last_cpu == smp_processor_id() && | |
783 | hwc->last_tag == cpuc->tags[i]; | |
784 | } | |
785 | ||
a4eaf7f1 | 786 | static void x86_pmu_start(struct perf_event *event, int flags); |
2e841873 | 787 | |
a4eaf7f1 | 788 | static void x86_pmu_enable(struct pmu *pmu) |
ee06094f | 789 | { |
1da53e02 SE |
790 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
791 | struct perf_event *event; | |
792 | struct hw_perf_event *hwc; | |
11164cd4 | 793 | int i, added = cpuc->n_added; |
1da53e02 | 794 | |
85cf9dba | 795 | if (!x86_pmu_initialized()) |
2b9ff0db | 796 | return; |
1a6e21f7 PZ |
797 | |
798 | if (cpuc->enabled) | |
799 | return; | |
800 | ||
1da53e02 | 801 | if (cpuc->n_added) { |
19925ce7 | 802 | int n_running = cpuc->n_events - cpuc->n_added; |
1da53e02 SE |
803 | /* |
804 | * apply assignment obtained either from | |
805 | * hw_perf_group_sched_in() or x86_pmu_enable() | |
806 | * | |
807 | * step1: save events moving to new counters | |
808 | * step2: reprogram moved events into new counters | |
809 | */ | |
19925ce7 | 810 | for (i = 0; i < n_running; i++) { |
1da53e02 SE |
811 | event = cpuc->event_list[i]; |
812 | hwc = &event->hw; | |
813 | ||
447a194b SE |
814 | /* |
815 | * we can avoid reprogramming counter if: | |
816 | * - assigned same counter as last time | |
817 | * - running on same CPU as last time | |
818 | * - no other event has used the counter since | |
819 | */ | |
820 | if (hwc->idx == -1 || | |
821 | match_prev_assignment(hwc, cpuc, i)) | |
1da53e02 SE |
822 | continue; |
823 | ||
a4eaf7f1 PZ |
824 | /* |
825 | * Ensure we don't accidentally enable a stopped | |
826 | * counter simply because we rescheduled. | |
827 | */ | |
828 | if (hwc->state & PERF_HES_STOPPED) | |
829 | hwc->state |= PERF_HES_ARCH; | |
830 | ||
831 | x86_pmu_stop(event, PERF_EF_UPDATE); | |
1da53e02 SE |
832 | } |
833 | ||
834 | for (i = 0; i < cpuc->n_events; i++) { | |
1da53e02 SE |
835 | event = cpuc->event_list[i]; |
836 | hwc = &event->hw; | |
837 | ||
45e16a68 | 838 | if (!match_prev_assignment(hwc, cpuc, i)) |
447a194b | 839 | x86_assign_hw_event(event, cpuc, i); |
45e16a68 PZ |
840 | else if (i < n_running) |
841 | continue; | |
1da53e02 | 842 | |
a4eaf7f1 PZ |
843 | if (hwc->state & PERF_HES_ARCH) |
844 | continue; | |
845 | ||
846 | x86_pmu_start(event, PERF_EF_RELOAD); | |
1da53e02 SE |
847 | } |
848 | cpuc->n_added = 0; | |
849 | perf_events_lapic_init(); | |
850 | } | |
1a6e21f7 PZ |
851 | |
852 | cpuc->enabled = 1; | |
853 | barrier(); | |
854 | ||
11164cd4 | 855 | x86_pmu.enable_all(added); |
ee06094f | 856 | } |
ee06094f | 857 | |
245b2e70 | 858 | static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); |
241771ef | 859 | |
ee06094f IM |
860 | /* |
861 | * Set the next IRQ period, based on the hwc->period_left value. | |
cdd6c482 | 862 | * To be called with the event disabled in hw: |
ee06094f | 863 | */ |
de0428a7 | 864 | int x86_perf_event_set_period(struct perf_event *event) |
241771ef | 865 | { |
07088edb | 866 | struct hw_perf_event *hwc = &event->hw; |
e7850595 | 867 | s64 left = local64_read(&hwc->period_left); |
e4abb5d4 | 868 | s64 period = hwc->sample_period; |
7645a24c | 869 | int ret = 0, idx = hwc->idx; |
ee06094f | 870 | |
30dd568c MM |
871 | if (idx == X86_PMC_IDX_FIXED_BTS) |
872 | return 0; | |
873 | ||
ee06094f | 874 | /* |
af901ca1 | 875 | * If we are way outside a reasonable range then just skip forward: |
ee06094f IM |
876 | */ |
877 | if (unlikely(left <= -period)) { | |
878 | left = period; | |
e7850595 | 879 | local64_set(&hwc->period_left, left); |
9e350de3 | 880 | hwc->last_period = period; |
e4abb5d4 | 881 | ret = 1; |
ee06094f IM |
882 | } |
883 | ||
884 | if (unlikely(left <= 0)) { | |
885 | left += period; | |
e7850595 | 886 | local64_set(&hwc->period_left, left); |
9e350de3 | 887 | hwc->last_period = period; |
e4abb5d4 | 888 | ret = 1; |
ee06094f | 889 | } |
1c80f4b5 | 890 | /* |
dfc65094 | 891 | * Quirk: certain CPUs dont like it if just 1 hw_event is left: |
1c80f4b5 IM |
892 | */ |
893 | if (unlikely(left < 2)) | |
894 | left = 2; | |
241771ef | 895 | |
e4abb5d4 PZ |
896 | if (left > x86_pmu.max_period) |
897 | left = x86_pmu.max_period; | |
898 | ||
245b2e70 | 899 | per_cpu(pmc_prev_left[idx], smp_processor_id()) = left; |
ee06094f IM |
900 | |
901 | /* | |
cdd6c482 | 902 | * The hw event starts counting from this event offset, |
ee06094f IM |
903 | * mark it to be able to extra future deltas: |
904 | */ | |
e7850595 | 905 | local64_set(&hwc->prev_count, (u64)-left); |
ee06094f | 906 | |
73d6e522 | 907 | wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac CG |
908 | |
909 | /* | |
910 | * Due to erratum on certan cpu we need | |
911 | * a second write to be sure the register | |
912 | * is updated properly | |
913 | */ | |
914 | if (x86_pmu.perfctr_second_write) { | |
73d6e522 | 915 | wrmsrl(hwc->event_base, |
948b1bb8 | 916 | (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac | 917 | } |
e4abb5d4 | 918 | |
cdd6c482 | 919 | perf_event_update_userpage(event); |
194002b2 | 920 | |
e4abb5d4 | 921 | return ret; |
2f18d1e8 IM |
922 | } |
923 | ||
de0428a7 | 924 | void x86_pmu_enable_event(struct perf_event *event) |
7c90cc45 | 925 | { |
0a3aee0d | 926 | if (__this_cpu_read(cpu_hw_events.enabled)) |
31fa58af RR |
927 | __x86_pmu_enable_event(&event->hw, |
928 | ARCH_PERFMON_EVENTSEL_ENABLE); | |
241771ef IM |
929 | } |
930 | ||
b690081d | 931 | /* |
a4eaf7f1 | 932 | * Add a single event to the PMU. |
1da53e02 SE |
933 | * |
934 | * The event is added to the group of enabled events | |
935 | * but only if it can be scehduled with existing events. | |
fe9081cc | 936 | */ |
a4eaf7f1 | 937 | static int x86_pmu_add(struct perf_event *event, int flags) |
fe9081cc PZ |
938 | { |
939 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1da53e02 SE |
940 | struct hw_perf_event *hwc; |
941 | int assign[X86_PMC_IDX_MAX]; | |
942 | int n, n0, ret; | |
fe9081cc | 943 | |
1da53e02 | 944 | hwc = &event->hw; |
fe9081cc | 945 | |
33696fc0 | 946 | perf_pmu_disable(event->pmu); |
1da53e02 | 947 | n0 = cpuc->n_events; |
24cd7f54 PZ |
948 | ret = n = collect_events(cpuc, event, false); |
949 | if (ret < 0) | |
950 | goto out; | |
53b441a5 | 951 | |
a4eaf7f1 PZ |
952 | hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; |
953 | if (!(flags & PERF_EF_START)) | |
954 | hwc->state |= PERF_HES_ARCH; | |
955 | ||
4d1c52b0 LM |
956 | /* |
957 | * If group events scheduling transaction was started, | |
0d2eb44f | 958 | * skip the schedulability test here, it will be performed |
a4eaf7f1 | 959 | * at commit time (->commit_txn) as a whole |
4d1c52b0 | 960 | */ |
8d2cacbb | 961 | if (cpuc->group_flag & PERF_EVENT_TXN) |
24cd7f54 | 962 | goto done_collect; |
4d1c52b0 | 963 | |
a072738e | 964 | ret = x86_pmu.schedule_events(cpuc, n, assign); |
1da53e02 | 965 | if (ret) |
24cd7f54 | 966 | goto out; |
1da53e02 SE |
967 | /* |
968 | * copy new assignment, now we know it is possible | |
969 | * will be used by hw_perf_enable() | |
970 | */ | |
971 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
7e2ae347 | 972 | |
24cd7f54 | 973 | done_collect: |
1da53e02 | 974 | cpuc->n_events = n; |
356e1f2e | 975 | cpuc->n_added += n - n0; |
90151c35 | 976 | cpuc->n_txn += n - n0; |
95cdd2e7 | 977 | |
24cd7f54 PZ |
978 | ret = 0; |
979 | out: | |
33696fc0 | 980 | perf_pmu_enable(event->pmu); |
24cd7f54 | 981 | return ret; |
241771ef IM |
982 | } |
983 | ||
a4eaf7f1 | 984 | static void x86_pmu_start(struct perf_event *event, int flags) |
d76a0812 | 985 | { |
c08053e6 PZ |
986 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
987 | int idx = event->hw.idx; | |
988 | ||
a4eaf7f1 PZ |
989 | if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) |
990 | return; | |
991 | ||
992 | if (WARN_ON_ONCE(idx == -1)) | |
993 | return; | |
994 | ||
995 | if (flags & PERF_EF_RELOAD) { | |
996 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); | |
997 | x86_perf_event_set_period(event); | |
998 | } | |
999 | ||
1000 | event->hw.state = 0; | |
d76a0812 | 1001 | |
c08053e6 PZ |
1002 | cpuc->events[idx] = event; |
1003 | __set_bit(idx, cpuc->active_mask); | |
63e6be6d | 1004 | __set_bit(idx, cpuc->running); |
aff3d91a | 1005 | x86_pmu.enable(event); |
c08053e6 | 1006 | perf_event_update_userpage(event); |
a78ac325 PZ |
1007 | } |
1008 | ||
cdd6c482 | 1009 | void perf_event_print_debug(void) |
241771ef | 1010 | { |
2f18d1e8 | 1011 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
ca037701 | 1012 | u64 pebs; |
cdd6c482 | 1013 | struct cpu_hw_events *cpuc; |
5bb9efe3 | 1014 | unsigned long flags; |
1e125676 IM |
1015 | int cpu, idx; |
1016 | ||
948b1bb8 | 1017 | if (!x86_pmu.num_counters) |
1e125676 | 1018 | return; |
241771ef | 1019 | |
5bb9efe3 | 1020 | local_irq_save(flags); |
241771ef IM |
1021 | |
1022 | cpu = smp_processor_id(); | |
cdd6c482 | 1023 | cpuc = &per_cpu(cpu_hw_events, cpu); |
241771ef | 1024 | |
faa28ae0 | 1025 | if (x86_pmu.version >= 2) { |
a1ef58f4 JSR |
1026 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
1027 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
1028 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
1029 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); | |
ca037701 | 1030 | rdmsrl(MSR_IA32_PEBS_ENABLE, pebs); |
a1ef58f4 JSR |
1031 | |
1032 | pr_info("\n"); | |
1033 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
1034 | pr_info("CPU#%d: status: %016llx\n", cpu, status); | |
1035 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); | |
1036 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); | |
ca037701 | 1037 | pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs); |
f87ad35d | 1038 | } |
7645a24c | 1039 | pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); |
241771ef | 1040 | |
948b1bb8 | 1041 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
41bf4989 RR |
1042 | rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl); |
1043 | rdmsrl(x86_pmu_event_addr(idx), pmc_count); | |
241771ef | 1044 | |
245b2e70 | 1045 | prev_left = per_cpu(pmc_prev_left[idx], cpu); |
241771ef | 1046 | |
a1ef58f4 | 1047 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 1048 | cpu, idx, pmc_ctrl); |
a1ef58f4 | 1049 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 1050 | cpu, idx, pmc_count); |
a1ef58f4 | 1051 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 1052 | cpu, idx, prev_left); |
241771ef | 1053 | } |
948b1bb8 | 1054 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { |
2f18d1e8 IM |
1055 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
1056 | ||
a1ef58f4 | 1057 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
2f18d1e8 IM |
1058 | cpu, idx, pmc_count); |
1059 | } | |
5bb9efe3 | 1060 | local_irq_restore(flags); |
241771ef IM |
1061 | } |
1062 | ||
de0428a7 | 1063 | void x86_pmu_stop(struct perf_event *event, int flags) |
241771ef | 1064 | { |
d76a0812 | 1065 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
cdd6c482 | 1066 | struct hw_perf_event *hwc = &event->hw; |
241771ef | 1067 | |
a4eaf7f1 PZ |
1068 | if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) { |
1069 | x86_pmu.disable(event); | |
1070 | cpuc->events[hwc->idx] = NULL; | |
1071 | WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); | |
1072 | hwc->state |= PERF_HES_STOPPED; | |
1073 | } | |
30dd568c | 1074 | |
a4eaf7f1 PZ |
1075 | if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { |
1076 | /* | |
1077 | * Drain the remaining delta count out of a event | |
1078 | * that we are disabling: | |
1079 | */ | |
1080 | x86_perf_event_update(event); | |
1081 | hwc->state |= PERF_HES_UPTODATE; | |
1082 | } | |
2e841873 PZ |
1083 | } |
1084 | ||
a4eaf7f1 | 1085 | static void x86_pmu_del(struct perf_event *event, int flags) |
2e841873 PZ |
1086 | { |
1087 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1088 | int i; | |
1089 | ||
90151c35 SE |
1090 | /* |
1091 | * If we're called during a txn, we don't need to do anything. | |
1092 | * The events never got scheduled and ->cancel_txn will truncate | |
1093 | * the event_list. | |
1094 | */ | |
8d2cacbb | 1095 | if (cpuc->group_flag & PERF_EVENT_TXN) |
90151c35 SE |
1096 | return; |
1097 | ||
a4eaf7f1 | 1098 | x86_pmu_stop(event, PERF_EF_UPDATE); |
194002b2 | 1099 | |
1da53e02 SE |
1100 | for (i = 0; i < cpuc->n_events; i++) { |
1101 | if (event == cpuc->event_list[i]) { | |
1102 | ||
1103 | if (x86_pmu.put_event_constraints) | |
1104 | x86_pmu.put_event_constraints(cpuc, event); | |
1105 | ||
1106 | while (++i < cpuc->n_events) | |
1107 | cpuc->event_list[i-1] = cpuc->event_list[i]; | |
1108 | ||
1109 | --cpuc->n_events; | |
6c9687ab | 1110 | break; |
1da53e02 SE |
1111 | } |
1112 | } | |
cdd6c482 | 1113 | perf_event_update_userpage(event); |
241771ef IM |
1114 | } |
1115 | ||
de0428a7 | 1116 | int x86_pmu_handle_irq(struct pt_regs *regs) |
a29aa8a7 | 1117 | { |
df1a132b | 1118 | struct perf_sample_data data; |
cdd6c482 IM |
1119 | struct cpu_hw_events *cpuc; |
1120 | struct perf_event *event; | |
11d1578f | 1121 | int idx, handled = 0; |
9029a5e3 IM |
1122 | u64 val; |
1123 | ||
dc1d628a | 1124 | perf_sample_data_init(&data, 0); |
df1a132b | 1125 | |
cdd6c482 | 1126 | cpuc = &__get_cpu_var(cpu_hw_events); |
962bf7a6 | 1127 | |
2bce5dac DZ |
1128 | /* |
1129 | * Some chipsets need to unmask the LVTPC in a particular spot | |
1130 | * inside the nmi handler. As a result, the unmasking was pushed | |
1131 | * into all the nmi handlers. | |
1132 | * | |
1133 | * This generic handler doesn't seem to have any issues where the | |
1134 | * unmasking occurs so it was left at the top. | |
1135 | */ | |
1136 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
1137 | ||
948b1bb8 | 1138 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
63e6be6d RR |
1139 | if (!test_bit(idx, cpuc->active_mask)) { |
1140 | /* | |
1141 | * Though we deactivated the counter some cpus | |
1142 | * might still deliver spurious interrupts still | |
1143 | * in flight. Catch them: | |
1144 | */ | |
1145 | if (__test_and_clear_bit(idx, cpuc->running)) | |
1146 | handled++; | |
a29aa8a7 | 1147 | continue; |
63e6be6d | 1148 | } |
962bf7a6 | 1149 | |
cdd6c482 | 1150 | event = cpuc->events[idx]; |
a4016a79 | 1151 | |
cc2ad4ba | 1152 | val = x86_perf_event_update(event); |
948b1bb8 | 1153 | if (val & (1ULL << (x86_pmu.cntval_bits - 1))) |
48e22d56 | 1154 | continue; |
962bf7a6 | 1155 | |
9e350de3 | 1156 | /* |
cdd6c482 | 1157 | * event overflow |
9e350de3 | 1158 | */ |
4177c42a | 1159 | handled++; |
cdd6c482 | 1160 | data.period = event->hw.last_period; |
9e350de3 | 1161 | |
07088edb | 1162 | if (!x86_perf_event_set_period(event)) |
e4abb5d4 PZ |
1163 | continue; |
1164 | ||
a8b0ca17 | 1165 | if (perf_event_overflow(event, &data, regs)) |
a4eaf7f1 | 1166 | x86_pmu_stop(event, 0); |
a29aa8a7 | 1167 | } |
962bf7a6 | 1168 | |
9e350de3 PZ |
1169 | if (handled) |
1170 | inc_irq_stat(apic_perf_irqs); | |
1171 | ||
a29aa8a7 RR |
1172 | return handled; |
1173 | } | |
39d81eab | 1174 | |
cdd6c482 | 1175 | void perf_events_lapic_init(void) |
241771ef | 1176 | { |
04da8a43 | 1177 | if (!x86_pmu.apic || !x86_pmu_initialized()) |
241771ef | 1178 | return; |
85cf9dba | 1179 | |
241771ef | 1180 | /* |
c323d95f | 1181 | * Always use NMI for PMU |
241771ef | 1182 | */ |
c323d95f | 1183 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
241771ef IM |
1184 | } |
1185 | ||
1186 | static int __kprobes | |
9c48f1c6 | 1187 | perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs) |
241771ef | 1188 | { |
cdd6c482 | 1189 | if (!atomic_read(&active_events)) |
9c48f1c6 | 1190 | return NMI_DONE; |
4177c42a | 1191 | |
9c48f1c6 | 1192 | return x86_pmu.handle_irq(regs); |
241771ef IM |
1193 | } |
1194 | ||
de0428a7 KW |
1195 | struct event_constraint emptyconstraint; |
1196 | struct event_constraint unconstrained; | |
f87ad35d | 1197 | |
3f6da390 PZ |
1198 | static int __cpuinit |
1199 | x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) | |
1200 | { | |
1201 | unsigned int cpu = (long)hcpu; | |
7fdba1ca | 1202 | struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); |
b38b24ea | 1203 | int ret = NOTIFY_OK; |
3f6da390 PZ |
1204 | |
1205 | switch (action & ~CPU_TASKS_FROZEN) { | |
1206 | case CPU_UP_PREPARE: | |
7fdba1ca | 1207 | cpuc->kfree_on_online = NULL; |
3f6da390 | 1208 | if (x86_pmu.cpu_prepare) |
b38b24ea | 1209 | ret = x86_pmu.cpu_prepare(cpu); |
3f6da390 PZ |
1210 | break; |
1211 | ||
1212 | case CPU_STARTING: | |
fe4a3308 | 1213 | set_in_cr4(X86_CR4_PCE); |
3f6da390 PZ |
1214 | if (x86_pmu.cpu_starting) |
1215 | x86_pmu.cpu_starting(cpu); | |
1216 | break; | |
1217 | ||
7fdba1ca PZ |
1218 | case CPU_ONLINE: |
1219 | kfree(cpuc->kfree_on_online); | |
1220 | break; | |
1221 | ||
3f6da390 PZ |
1222 | case CPU_DYING: |
1223 | if (x86_pmu.cpu_dying) | |
1224 | x86_pmu.cpu_dying(cpu); | |
1225 | break; | |
1226 | ||
b38b24ea | 1227 | case CPU_UP_CANCELED: |
3f6da390 PZ |
1228 | case CPU_DEAD: |
1229 | if (x86_pmu.cpu_dead) | |
1230 | x86_pmu.cpu_dead(cpu); | |
1231 | break; | |
1232 | ||
1233 | default: | |
1234 | break; | |
1235 | } | |
1236 | ||
b38b24ea | 1237 | return ret; |
3f6da390 PZ |
1238 | } |
1239 | ||
12558038 CG |
1240 | static void __init pmu_check_apic(void) |
1241 | { | |
1242 | if (cpu_has_apic) | |
1243 | return; | |
1244 | ||
1245 | x86_pmu.apic = 0; | |
1246 | pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n"); | |
1247 | pr_info("no hardware sampling interrupt available.\n"); | |
1248 | } | |
1249 | ||
dda99116 | 1250 | static int __init init_hw_perf_events(void) |
b56a3802 | 1251 | { |
c1d6f42f | 1252 | struct x86_pmu_quirk *quirk; |
b622d644 | 1253 | struct event_constraint *c; |
72eae04d RR |
1254 | int err; |
1255 | ||
cdd6c482 | 1256 | pr_info("Performance Events: "); |
1123e3ad | 1257 | |
b56a3802 JSR |
1258 | switch (boot_cpu_data.x86_vendor) { |
1259 | case X86_VENDOR_INTEL: | |
72eae04d | 1260 | err = intel_pmu_init(); |
b56a3802 | 1261 | break; |
f87ad35d | 1262 | case X86_VENDOR_AMD: |
72eae04d | 1263 | err = amd_pmu_init(); |
f87ad35d | 1264 | break; |
4138960a | 1265 | default: |
004417a6 | 1266 | return 0; |
b56a3802 | 1267 | } |
1123e3ad | 1268 | if (err != 0) { |
cdd6c482 | 1269 | pr_cont("no PMU driver, software events only.\n"); |
004417a6 | 1270 | return 0; |
1123e3ad | 1271 | } |
b56a3802 | 1272 | |
12558038 CG |
1273 | pmu_check_apic(); |
1274 | ||
33c6d6a7 | 1275 | /* sanity check that the hardware exists or is emulated */ |
4407204c | 1276 | if (!check_hw_exists()) |
004417a6 | 1277 | return 0; |
33c6d6a7 | 1278 | |
1123e3ad | 1279 | pr_cont("%s PMU driver.\n", x86_pmu.name); |
faa28ae0 | 1280 | |
c1d6f42f PZ |
1281 | for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next) |
1282 | quirk->func(); | |
3c44780b | 1283 | |
948b1bb8 | 1284 | if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) { |
cdd6c482 | 1285 | WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", |
948b1bb8 RR |
1286 | x86_pmu.num_counters, X86_PMC_MAX_GENERIC); |
1287 | x86_pmu.num_counters = X86_PMC_MAX_GENERIC; | |
241771ef | 1288 | } |
948b1bb8 | 1289 | x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1; |
241771ef | 1290 | |
948b1bb8 | 1291 | if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) { |
cdd6c482 | 1292 | WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", |
948b1bb8 RR |
1293 | x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED); |
1294 | x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED; | |
703e937c | 1295 | } |
862a1a5f | 1296 | |
d6dc0b4e | 1297 | x86_pmu.intel_ctrl |= |
948b1bb8 | 1298 | ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED; |
241771ef | 1299 | |
cdd6c482 | 1300 | perf_events_lapic_init(); |
9c48f1c6 | 1301 | register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI"); |
1123e3ad | 1302 | |
63b14649 | 1303 | unconstrained = (struct event_constraint) |
948b1bb8 | 1304 | __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1, |
bc1738f6 | 1305 | 0, x86_pmu.num_counters, 0); |
63b14649 | 1306 | |
b622d644 | 1307 | if (x86_pmu.event_constraints) { |
cd09c0c4 SE |
1308 | /* |
1309 | * event on fixed counter2 (REF_CYCLES) only works on this | |
1310 | * counter, so do not extend mask to generic counters | |
1311 | */ | |
b622d644 | 1312 | for_each_event_constraint(c, x86_pmu.event_constraints) { |
cd09c0c4 SE |
1313 | if (c->cmask != X86_RAW_EVENT_MASK |
1314 | || c->idxmsk64 == X86_PMC_MSK_FIXED_REF_CYCLES) { | |
b622d644 | 1315 | continue; |
cd09c0c4 | 1316 | } |
b622d644 | 1317 | |
948b1bb8 RR |
1318 | c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1; |
1319 | c->weight += x86_pmu.num_counters; | |
b622d644 PZ |
1320 | } |
1321 | } | |
1322 | ||
57c0c15b | 1323 | pr_info("... version: %d\n", x86_pmu.version); |
948b1bb8 RR |
1324 | pr_info("... bit width: %d\n", x86_pmu.cntval_bits); |
1325 | pr_info("... generic registers: %d\n", x86_pmu.num_counters); | |
1326 | pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask); | |
57c0c15b | 1327 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); |
948b1bb8 | 1328 | pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed); |
d6dc0b4e | 1329 | pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl); |
3f6da390 | 1330 | |
2e80a82a | 1331 | perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); |
3f6da390 | 1332 | perf_cpu_notifier(x86_pmu_notifier); |
004417a6 PZ |
1333 | |
1334 | return 0; | |
241771ef | 1335 | } |
004417a6 | 1336 | early_initcall(init_hw_perf_events); |
621a01ea | 1337 | |
cdd6c482 | 1338 | static inline void x86_pmu_read(struct perf_event *event) |
ee06094f | 1339 | { |
cc2ad4ba | 1340 | x86_perf_event_update(event); |
ee06094f IM |
1341 | } |
1342 | ||
4d1c52b0 LM |
1343 | /* |
1344 | * Start group events scheduling transaction | |
1345 | * Set the flag to make pmu::enable() not perform the | |
1346 | * schedulability test, it will be performed at commit time | |
1347 | */ | |
51b0fe39 | 1348 | static void x86_pmu_start_txn(struct pmu *pmu) |
4d1c52b0 | 1349 | { |
33696fc0 | 1350 | perf_pmu_disable(pmu); |
0a3aee0d TH |
1351 | __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN); |
1352 | __this_cpu_write(cpu_hw_events.n_txn, 0); | |
4d1c52b0 LM |
1353 | } |
1354 | ||
1355 | /* | |
1356 | * Stop group events scheduling transaction | |
1357 | * Clear the flag and pmu::enable() will perform the | |
1358 | * schedulability test. | |
1359 | */ | |
51b0fe39 | 1360 | static void x86_pmu_cancel_txn(struct pmu *pmu) |
4d1c52b0 | 1361 | { |
0a3aee0d | 1362 | __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN); |
90151c35 SE |
1363 | /* |
1364 | * Truncate the collected events. | |
1365 | */ | |
0a3aee0d TH |
1366 | __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn)); |
1367 | __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn)); | |
33696fc0 | 1368 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1369 | } |
1370 | ||
1371 | /* | |
1372 | * Commit group events scheduling transaction | |
1373 | * Perform the group schedulability test as a whole | |
1374 | * Return 0 if success | |
1375 | */ | |
51b0fe39 | 1376 | static int x86_pmu_commit_txn(struct pmu *pmu) |
4d1c52b0 LM |
1377 | { |
1378 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1379 | int assign[X86_PMC_IDX_MAX]; | |
1380 | int n, ret; | |
1381 | ||
1382 | n = cpuc->n_events; | |
1383 | ||
1384 | if (!x86_pmu_initialized()) | |
1385 | return -EAGAIN; | |
1386 | ||
1387 | ret = x86_pmu.schedule_events(cpuc, n, assign); | |
1388 | if (ret) | |
1389 | return ret; | |
1390 | ||
1391 | /* | |
1392 | * copy new assignment, now we know it is possible | |
1393 | * will be used by hw_perf_enable() | |
1394 | */ | |
1395 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
1396 | ||
8d2cacbb | 1397 | cpuc->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 1398 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1399 | return 0; |
1400 | } | |
cd8a38d3 SE |
1401 | /* |
1402 | * a fake_cpuc is used to validate event groups. Due to | |
1403 | * the extra reg logic, we need to also allocate a fake | |
1404 | * per_core and per_cpu structure. Otherwise, group events | |
1405 | * using extra reg may conflict without the kernel being | |
1406 | * able to catch this when the last event gets added to | |
1407 | * the group. | |
1408 | */ | |
1409 | static void free_fake_cpuc(struct cpu_hw_events *cpuc) | |
1410 | { | |
1411 | kfree(cpuc->shared_regs); | |
1412 | kfree(cpuc); | |
1413 | } | |
1414 | ||
1415 | static struct cpu_hw_events *allocate_fake_cpuc(void) | |
1416 | { | |
1417 | struct cpu_hw_events *cpuc; | |
1418 | int cpu = raw_smp_processor_id(); | |
1419 | ||
1420 | cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL); | |
1421 | if (!cpuc) | |
1422 | return ERR_PTR(-ENOMEM); | |
1423 | ||
1424 | /* only needed, if we have extra_regs */ | |
1425 | if (x86_pmu.extra_regs) { | |
1426 | cpuc->shared_regs = allocate_shared_regs(cpu); | |
1427 | if (!cpuc->shared_regs) | |
1428 | goto error; | |
1429 | } | |
1430 | return cpuc; | |
1431 | error: | |
1432 | free_fake_cpuc(cpuc); | |
1433 | return ERR_PTR(-ENOMEM); | |
1434 | } | |
4d1c52b0 | 1435 | |
ca037701 PZ |
1436 | /* |
1437 | * validate that we can schedule this event | |
1438 | */ | |
1439 | static int validate_event(struct perf_event *event) | |
1440 | { | |
1441 | struct cpu_hw_events *fake_cpuc; | |
1442 | struct event_constraint *c; | |
1443 | int ret = 0; | |
1444 | ||
cd8a38d3 SE |
1445 | fake_cpuc = allocate_fake_cpuc(); |
1446 | if (IS_ERR(fake_cpuc)) | |
1447 | return PTR_ERR(fake_cpuc); | |
ca037701 PZ |
1448 | |
1449 | c = x86_pmu.get_event_constraints(fake_cpuc, event); | |
1450 | ||
1451 | if (!c || !c->weight) | |
aa2bc1ad | 1452 | ret = -EINVAL; |
ca037701 PZ |
1453 | |
1454 | if (x86_pmu.put_event_constraints) | |
1455 | x86_pmu.put_event_constraints(fake_cpuc, event); | |
1456 | ||
cd8a38d3 | 1457 | free_fake_cpuc(fake_cpuc); |
ca037701 PZ |
1458 | |
1459 | return ret; | |
1460 | } | |
1461 | ||
1da53e02 SE |
1462 | /* |
1463 | * validate a single event group | |
1464 | * | |
1465 | * validation include: | |
184f412c IM |
1466 | * - check events are compatible which each other |
1467 | * - events do not compete for the same counter | |
1468 | * - number of events <= number of counters | |
1da53e02 SE |
1469 | * |
1470 | * validation ensures the group can be loaded onto the | |
1471 | * PMU if it was the only group available. | |
1472 | */ | |
fe9081cc PZ |
1473 | static int validate_group(struct perf_event *event) |
1474 | { | |
1da53e02 | 1475 | struct perf_event *leader = event->group_leader; |
502568d5 | 1476 | struct cpu_hw_events *fake_cpuc; |
aa2bc1ad | 1477 | int ret = -EINVAL, n; |
fe9081cc | 1478 | |
cd8a38d3 SE |
1479 | fake_cpuc = allocate_fake_cpuc(); |
1480 | if (IS_ERR(fake_cpuc)) | |
1481 | return PTR_ERR(fake_cpuc); | |
1da53e02 SE |
1482 | /* |
1483 | * the event is not yet connected with its | |
1484 | * siblings therefore we must first collect | |
1485 | * existing siblings, then add the new event | |
1486 | * before we can simulate the scheduling | |
1487 | */ | |
502568d5 | 1488 | n = collect_events(fake_cpuc, leader, true); |
1da53e02 | 1489 | if (n < 0) |
cd8a38d3 | 1490 | goto out; |
fe9081cc | 1491 | |
502568d5 PZ |
1492 | fake_cpuc->n_events = n; |
1493 | n = collect_events(fake_cpuc, event, false); | |
1da53e02 | 1494 | if (n < 0) |
cd8a38d3 | 1495 | goto out; |
fe9081cc | 1496 | |
502568d5 | 1497 | fake_cpuc->n_events = n; |
1da53e02 | 1498 | |
a072738e | 1499 | ret = x86_pmu.schedule_events(fake_cpuc, n, NULL); |
502568d5 | 1500 | |
502568d5 | 1501 | out: |
cd8a38d3 | 1502 | free_fake_cpuc(fake_cpuc); |
502568d5 | 1503 | return ret; |
fe9081cc PZ |
1504 | } |
1505 | ||
dda99116 | 1506 | static int x86_pmu_event_init(struct perf_event *event) |
621a01ea | 1507 | { |
51b0fe39 | 1508 | struct pmu *tmp; |
621a01ea IM |
1509 | int err; |
1510 | ||
b0a873eb PZ |
1511 | switch (event->attr.type) { |
1512 | case PERF_TYPE_RAW: | |
1513 | case PERF_TYPE_HARDWARE: | |
1514 | case PERF_TYPE_HW_CACHE: | |
1515 | break; | |
1516 | ||
1517 | default: | |
1518 | return -ENOENT; | |
1519 | } | |
1520 | ||
1521 | err = __x86_pmu_event_init(event); | |
fe9081cc | 1522 | if (!err) { |
8113070d SE |
1523 | /* |
1524 | * we temporarily connect event to its pmu | |
1525 | * such that validate_group() can classify | |
1526 | * it as an x86 event using is_x86_event() | |
1527 | */ | |
1528 | tmp = event->pmu; | |
1529 | event->pmu = &pmu; | |
1530 | ||
fe9081cc PZ |
1531 | if (event->group_leader != event) |
1532 | err = validate_group(event); | |
ca037701 PZ |
1533 | else |
1534 | err = validate_event(event); | |
8113070d SE |
1535 | |
1536 | event->pmu = tmp; | |
fe9081cc | 1537 | } |
a1792cda | 1538 | if (err) { |
cdd6c482 IM |
1539 | if (event->destroy) |
1540 | event->destroy(event); | |
a1792cda | 1541 | } |
621a01ea | 1542 | |
b0a873eb | 1543 | return err; |
621a01ea | 1544 | } |
d7d59fb3 | 1545 | |
fe4a3308 PZ |
1546 | static int x86_pmu_event_idx(struct perf_event *event) |
1547 | { | |
1548 | int idx = event->hw.idx; | |
1549 | ||
1550 | if (x86_pmu.num_counters_fixed && idx >= X86_PMC_IDX_FIXED) { | |
1551 | idx -= X86_PMC_IDX_FIXED; | |
1552 | idx |= 1 << 30; | |
1553 | } | |
1554 | ||
1555 | return idx + 1; | |
1556 | } | |
1557 | ||
b0a873eb | 1558 | static struct pmu pmu = { |
a4eaf7f1 PZ |
1559 | .pmu_enable = x86_pmu_enable, |
1560 | .pmu_disable = x86_pmu_disable, | |
1561 | ||
b0a873eb | 1562 | .event_init = x86_pmu_event_init, |
a4eaf7f1 PZ |
1563 | |
1564 | .add = x86_pmu_add, | |
1565 | .del = x86_pmu_del, | |
b0a873eb PZ |
1566 | .start = x86_pmu_start, |
1567 | .stop = x86_pmu_stop, | |
1568 | .read = x86_pmu_read, | |
a4eaf7f1 | 1569 | |
b0a873eb PZ |
1570 | .start_txn = x86_pmu_start_txn, |
1571 | .cancel_txn = x86_pmu_cancel_txn, | |
1572 | .commit_txn = x86_pmu_commit_txn, | |
fe4a3308 PZ |
1573 | |
1574 | .event_idx = x86_pmu_event_idx, | |
b0a873eb PZ |
1575 | }; |
1576 | ||
d7d59fb3 PZ |
1577 | /* |
1578 | * callchain support | |
1579 | */ | |
1580 | ||
d7d59fb3 PZ |
1581 | static int backtrace_stack(void *data, char *name) |
1582 | { | |
038e836e | 1583 | return 0; |
d7d59fb3 PZ |
1584 | } |
1585 | ||
1586 | static void backtrace_address(void *data, unsigned long addr, int reliable) | |
1587 | { | |
1588 | struct perf_callchain_entry *entry = data; | |
1589 | ||
70791ce9 | 1590 | perf_callchain_store(entry, addr); |
d7d59fb3 PZ |
1591 | } |
1592 | ||
1593 | static const struct stacktrace_ops backtrace_ops = { | |
d7d59fb3 PZ |
1594 | .stack = backtrace_stack, |
1595 | .address = backtrace_address, | |
06d65bda | 1596 | .walk_stack = print_context_stack_bp, |
d7d59fb3 PZ |
1597 | }; |
1598 | ||
56962b44 FW |
1599 | void |
1600 | perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 | 1601 | { |
927c7a9e FW |
1602 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
1603 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 1604 | return; |
927c7a9e FW |
1605 | } |
1606 | ||
70791ce9 | 1607 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 1608 | |
e8e999cf | 1609 | dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry); |
d7d59fb3 PZ |
1610 | } |
1611 | ||
257ef9d2 TE |
1612 | #ifdef CONFIG_COMPAT |
1613 | static inline int | |
1614 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
74193ef0 | 1615 | { |
257ef9d2 TE |
1616 | /* 32-bit process in 64-bit kernel. */ |
1617 | struct stack_frame_ia32 frame; | |
1618 | const void __user *fp; | |
74193ef0 | 1619 | |
257ef9d2 TE |
1620 | if (!test_thread_flag(TIF_IA32)) |
1621 | return 0; | |
1622 | ||
1623 | fp = compat_ptr(regs->bp); | |
1624 | while (entry->nr < PERF_MAX_STACK_DEPTH) { | |
1625 | unsigned long bytes; | |
1626 | frame.next_frame = 0; | |
1627 | frame.return_address = 0; | |
1628 | ||
1629 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); | |
1630 | if (bytes != sizeof(frame)) | |
1631 | break; | |
74193ef0 | 1632 | |
257ef9d2 TE |
1633 | if (fp < compat_ptr(regs->sp)) |
1634 | break; | |
74193ef0 | 1635 | |
70791ce9 | 1636 | perf_callchain_store(entry, frame.return_address); |
257ef9d2 TE |
1637 | fp = compat_ptr(frame.next_frame); |
1638 | } | |
1639 | return 1; | |
d7d59fb3 | 1640 | } |
257ef9d2 TE |
1641 | #else |
1642 | static inline int | |
1643 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1644 | { | |
1645 | return 0; | |
1646 | } | |
1647 | #endif | |
d7d59fb3 | 1648 | |
56962b44 FW |
1649 | void |
1650 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 PZ |
1651 | { |
1652 | struct stack_frame frame; | |
1653 | const void __user *fp; | |
1654 | ||
927c7a9e FW |
1655 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
1656 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 1657 | return; |
927c7a9e | 1658 | } |
5a6cec3a | 1659 | |
74193ef0 | 1660 | fp = (void __user *)regs->bp; |
d7d59fb3 | 1661 | |
70791ce9 | 1662 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 1663 | |
20afc60f AV |
1664 | if (!current->mm) |
1665 | return; | |
1666 | ||
257ef9d2 TE |
1667 | if (perf_callchain_user32(regs, entry)) |
1668 | return; | |
1669 | ||
f9188e02 | 1670 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
257ef9d2 | 1671 | unsigned long bytes; |
038e836e | 1672 | frame.next_frame = NULL; |
d7d59fb3 PZ |
1673 | frame.return_address = 0; |
1674 | ||
257ef9d2 TE |
1675 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); |
1676 | if (bytes != sizeof(frame)) | |
d7d59fb3 PZ |
1677 | break; |
1678 | ||
5a6cec3a | 1679 | if ((unsigned long)fp < regs->sp) |
d7d59fb3 PZ |
1680 | break; |
1681 | ||
70791ce9 | 1682 | perf_callchain_store(entry, frame.return_address); |
038e836e | 1683 | fp = frame.next_frame; |
d7d59fb3 PZ |
1684 | } |
1685 | } | |
1686 | ||
39447b38 ZY |
1687 | unsigned long perf_instruction_pointer(struct pt_regs *regs) |
1688 | { | |
1689 | unsigned long ip; | |
dcf46b94 | 1690 | |
39447b38 ZY |
1691 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) |
1692 | ip = perf_guest_cbs->get_guest_ip(); | |
1693 | else | |
1694 | ip = instruction_pointer(regs); | |
dcf46b94 | 1695 | |
39447b38 ZY |
1696 | return ip; |
1697 | } | |
1698 | ||
1699 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
1700 | { | |
1701 | int misc = 0; | |
dcf46b94 | 1702 | |
39447b38 | 1703 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
dcf46b94 ZY |
1704 | if (perf_guest_cbs->is_user_mode()) |
1705 | misc |= PERF_RECORD_MISC_GUEST_USER; | |
1706 | else | |
1707 | misc |= PERF_RECORD_MISC_GUEST_KERNEL; | |
1708 | } else { | |
1709 | if (user_mode(regs)) | |
1710 | misc |= PERF_RECORD_MISC_USER; | |
1711 | else | |
1712 | misc |= PERF_RECORD_MISC_KERNEL; | |
1713 | } | |
1714 | ||
39447b38 | 1715 | if (regs->flags & PERF_EFLAGS_EXACT) |
ab608344 | 1716 | misc |= PERF_RECORD_MISC_EXACT_IP; |
39447b38 ZY |
1717 | |
1718 | return misc; | |
1719 | } | |
b3d9468a GN |
1720 | |
1721 | void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap) | |
1722 | { | |
1723 | cap->version = x86_pmu.version; | |
1724 | cap->num_counters_gp = x86_pmu.num_counters; | |
1725 | cap->num_counters_fixed = x86_pmu.num_counters_fixed; | |
1726 | cap->bit_width_gp = x86_pmu.cntval_bits; | |
1727 | cap->bit_width_fixed = x86_pmu.cntval_bits; | |
1728 | cap->events_mask = (unsigned int)x86_pmu.events_maskl; | |
1729 | cap->events_mask_len = x86_pmu.events_mask_len; | |
1730 | } | |
1731 | EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability); |