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de0428a7 KW |
1 | /* |
2 | * Performance events x86 architecture header | |
3 | * | |
4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> | |
5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> | |
9 | * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> | |
10 | * Copyright (C) 2009 Google, Inc., Stephane Eranian | |
11 | * | |
12 | * For licencing details see kernel-base/COPYING | |
13 | */ | |
14 | ||
15 | #include <linux/perf_event.h> | |
16 | ||
1c2ac3fd PZ |
17 | #if 0 |
18 | #undef wrmsrl | |
19 | #define wrmsrl(msr, val) \ | |
20 | do { \ | |
21 | unsigned int _msr = (msr); \ | |
22 | u64 _val = (val); \ | |
23 | trace_printk("wrmsrl(%x, %Lx)\n", (unsigned int)(_msr), \ | |
24 | (unsigned long long)(_val)); \ | |
25 | native_write_msr((_msr), (u32)(_val), (u32)(_val >> 32)); \ | |
26 | } while (0) | |
27 | #endif | |
28 | ||
de0428a7 KW |
29 | /* |
30 | * | NHM/WSM | SNB | | |
31 | * register ------------------------------- | |
32 | * | HT | no HT | HT | no HT | | |
33 | *----------------------------------------- | |
34 | * offcore | core | core | cpu | core | | |
35 | * lbr_sel | core | core | cpu | core | | |
36 | * ld_lat | cpu | core | cpu | core | | |
37 | *----------------------------------------- | |
38 | * | |
39 | * Given that there is a small number of shared regs, | |
40 | * we can pre-allocate their slot in the per-cpu | |
41 | * per-core reg tables. | |
42 | */ | |
43 | enum extra_reg_type { | |
44 | EXTRA_REG_NONE = -1, /* not used */ | |
45 | ||
46 | EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */ | |
47 | EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */ | |
b36817e8 | 48 | EXTRA_REG_LBR = 2, /* lbr_select */ |
f20093ee | 49 | EXTRA_REG_LDLAT = 3, /* ld_lat_threshold */ |
de0428a7 KW |
50 | |
51 | EXTRA_REG_MAX /* number of entries needed */ | |
52 | }; | |
53 | ||
54 | struct event_constraint { | |
55 | union { | |
56 | unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
57 | u64 idxmsk64; | |
58 | }; | |
59 | u64 code; | |
60 | u64 cmask; | |
61 | int weight; | |
bc1738f6 | 62 | int overlap; |
9fac2cf3 | 63 | int flags; |
de0428a7 | 64 | }; |
f20093ee | 65 | /* |
2f7f73a5 | 66 | * struct hw_perf_event.flags flags |
f20093ee SE |
67 | */ |
68 | #define PERF_X86_EVENT_PEBS_LDLAT 0x1 /* ld+ldlat data address sampling */ | |
9ad64c0f | 69 | #define PERF_X86_EVENT_PEBS_ST 0x2 /* st data address sampling */ |
f9134f36 | 70 | #define PERF_X86_EVENT_PEBS_ST_HSW 0x4 /* haswell style st data sampling */ |
2f7f73a5 | 71 | #define PERF_X86_EVENT_COMMITTED 0x8 /* event passed commit_txn */ |
de0428a7 KW |
72 | |
73 | struct amd_nb { | |
74 | int nb_id; /* NorthBridge id */ | |
75 | int refcnt; /* reference count */ | |
76 | struct perf_event *owners[X86_PMC_IDX_MAX]; | |
77 | struct event_constraint event_constraints[X86_PMC_IDX_MAX]; | |
78 | }; | |
79 | ||
80 | /* The maximal number of PEBS events: */ | |
70ab7003 | 81 | #define MAX_PEBS_EVENTS 8 |
de0428a7 KW |
82 | |
83 | /* | |
84 | * A debug store configuration. | |
85 | * | |
86 | * We only support architectures that use 64bit fields. | |
87 | */ | |
88 | struct debug_store { | |
89 | u64 bts_buffer_base; | |
90 | u64 bts_index; | |
91 | u64 bts_absolute_maximum; | |
92 | u64 bts_interrupt_threshold; | |
93 | u64 pebs_buffer_base; | |
94 | u64 pebs_index; | |
95 | u64 pebs_absolute_maximum; | |
96 | u64 pebs_interrupt_threshold; | |
97 | u64 pebs_event_reset[MAX_PEBS_EVENTS]; | |
98 | }; | |
99 | ||
100 | /* | |
101 | * Per register state. | |
102 | */ | |
103 | struct er_account { | |
104 | raw_spinlock_t lock; /* per-core: protect structure */ | |
105 | u64 config; /* extra MSR config */ | |
106 | u64 reg; /* extra MSR number */ | |
107 | atomic_t ref; /* reference count */ | |
108 | }; | |
109 | ||
110 | /* | |
111 | * Per core/cpu state | |
112 | * | |
113 | * Used to coordinate shared registers between HT threads or | |
114 | * among events on a single PMU. | |
115 | */ | |
116 | struct intel_shared_regs { | |
117 | struct er_account regs[EXTRA_REG_MAX]; | |
118 | int refcnt; /* per-core: #HT threads */ | |
119 | unsigned core_id; /* per-core: core id */ | |
120 | }; | |
121 | ||
122 | #define MAX_LBR_ENTRIES 16 | |
123 | ||
124 | struct cpu_hw_events { | |
125 | /* | |
126 | * Generic x86 PMC bits | |
127 | */ | |
128 | struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */ | |
129 | unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
130 | unsigned long running[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
131 | int enabled; | |
132 | ||
133 | int n_events; | |
134 | int n_added; | |
135 | int n_txn; | |
136 | int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */ | |
137 | u64 tags[X86_PMC_IDX_MAX]; | |
138 | struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */ | |
139 | ||
140 | unsigned int group_flag; | |
5a425294 | 141 | int is_fake; |
de0428a7 KW |
142 | |
143 | /* | |
144 | * Intel DebugStore bits | |
145 | */ | |
146 | struct debug_store *ds; | |
147 | u64 pebs_enabled; | |
148 | ||
149 | /* | |
150 | * Intel LBR bits | |
151 | */ | |
152 | int lbr_users; | |
153 | void *lbr_context; | |
154 | struct perf_branch_stack lbr_stack; | |
155 | struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES]; | |
b36817e8 | 156 | struct er_account *lbr_sel; |
3e702ff6 | 157 | u64 br_sel; |
de0428a7 | 158 | |
144d31e6 GN |
159 | /* |
160 | * Intel host/guest exclude bits | |
161 | */ | |
162 | u64 intel_ctrl_guest_mask; | |
163 | u64 intel_ctrl_host_mask; | |
164 | struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX]; | |
165 | ||
2b9e344d PZ |
166 | /* |
167 | * Intel checkpoint mask | |
168 | */ | |
169 | u64 intel_cp_status; | |
170 | ||
de0428a7 KW |
171 | /* |
172 | * manage shared (per-core, per-cpu) registers | |
173 | * used on Intel NHM/WSM/SNB | |
174 | */ | |
175 | struct intel_shared_regs *shared_regs; | |
176 | ||
177 | /* | |
178 | * AMD specific bits | |
179 | */ | |
1018faa6 JR |
180 | struct amd_nb *amd_nb; |
181 | /* Inverted mask of bits to clear in the perf_ctr ctrl registers */ | |
182 | u64 perf_ctr_virt_mask; | |
de0428a7 KW |
183 | |
184 | void *kfree_on_online; | |
185 | }; | |
186 | ||
9fac2cf3 | 187 | #define __EVENT_CONSTRAINT(c, n, m, w, o, f) {\ |
de0428a7 KW |
188 | { .idxmsk64 = (n) }, \ |
189 | .code = (c), \ | |
190 | .cmask = (m), \ | |
191 | .weight = (w), \ | |
bc1738f6 | 192 | .overlap = (o), \ |
9fac2cf3 | 193 | .flags = f, \ |
de0428a7 KW |
194 | } |
195 | ||
196 | #define EVENT_CONSTRAINT(c, n, m) \ | |
9fac2cf3 | 197 | __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0) |
bc1738f6 RR |
198 | |
199 | /* | |
200 | * The overlap flag marks event constraints with overlapping counter | |
201 | * masks. This is the case if the counter mask of such an event is not | |
202 | * a subset of any other counter mask of a constraint with an equal or | |
203 | * higher weight, e.g.: | |
204 | * | |
205 | * c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0); | |
206 | * c_another1 = EVENT_CONSTRAINT(0, 0x07, 0); | |
207 | * c_another2 = EVENT_CONSTRAINT(0, 0x38, 0); | |
208 | * | |
209 | * The event scheduler may not select the correct counter in the first | |
210 | * cycle because it needs to know which subsequent events will be | |
211 | * scheduled. It may fail to schedule the events then. So we set the | |
212 | * overlap flag for such constraints to give the scheduler a hint which | |
213 | * events to select for counter rescheduling. | |
214 | * | |
215 | * Care must be taken as the rescheduling algorithm is O(n!) which | |
216 | * will increase scheduling cycles for an over-commited system | |
217 | * dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros | |
218 | * and its counter masks must be kept at a minimum. | |
219 | */ | |
220 | #define EVENT_CONSTRAINT_OVERLAP(c, n, m) \ | |
9fac2cf3 | 221 | __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1, 0) |
de0428a7 KW |
222 | |
223 | /* | |
224 | * Constraint on the Event code. | |
225 | */ | |
226 | #define INTEL_EVENT_CONSTRAINT(c, n) \ | |
227 | EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT) | |
228 | ||
229 | /* | |
230 | * Constraint on the Event code + UMask + fixed-mask | |
231 | * | |
232 | * filter mask to validate fixed counter events. | |
233 | * the following filters disqualify for fixed counters: | |
234 | * - inv | |
235 | * - edge | |
236 | * - cnt-mask | |
3a632cb2 AK |
237 | * - in_tx |
238 | * - in_tx_checkpointed | |
de0428a7 KW |
239 | * The other filters are supported by fixed counters. |
240 | * The any-thread option is supported starting with v3. | |
241 | */ | |
3a632cb2 | 242 | #define FIXED_EVENT_FLAGS (X86_RAW_EVENT_MASK|HSW_IN_TX|HSW_IN_TX_CHECKPOINTED) |
de0428a7 | 243 | #define FIXED_EVENT_CONSTRAINT(c, n) \ |
3a632cb2 | 244 | EVENT_CONSTRAINT(c, (1ULL << (32+n)), FIXED_EVENT_FLAGS) |
de0428a7 KW |
245 | |
246 | /* | |
247 | * Constraint on the Event code + UMask | |
248 | */ | |
249 | #define INTEL_UEVENT_CONSTRAINT(c, n) \ | |
250 | EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK) | |
251 | ||
f20093ee SE |
252 | #define INTEL_PLD_CONSTRAINT(c, n) \ |
253 | __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \ | |
254 | HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LDLAT) | |
255 | ||
9ad64c0f SE |
256 | #define INTEL_PST_CONSTRAINT(c, n) \ |
257 | __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \ | |
258 | HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST) | |
259 | ||
f9134f36 AK |
260 | /* DataLA version of store sampling without extra enable bit. */ |
261 | #define INTEL_PST_HSW_CONSTRAINT(c, n) \ | |
262 | __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \ | |
263 | HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW) | |
264 | ||
de0428a7 KW |
265 | #define EVENT_CONSTRAINT_END \ |
266 | EVENT_CONSTRAINT(0, 0, 0) | |
267 | ||
268 | #define for_each_event_constraint(e, c) \ | |
269 | for ((e) = (c); (e)->weight; (e)++) | |
270 | ||
271 | /* | |
272 | * Extra registers for specific events. | |
273 | * | |
274 | * Some events need large masks and require external MSRs. | |
275 | * Those extra MSRs end up being shared for all events on | |
276 | * a PMU and sometimes between PMU of sibling HT threads. | |
277 | * In either case, the kernel needs to handle conflicting | |
278 | * accesses to those extra, shared, regs. The data structure | |
279 | * to manage those registers is stored in cpu_hw_event. | |
280 | */ | |
281 | struct extra_reg { | |
282 | unsigned int event; | |
283 | unsigned int msr; | |
284 | u64 config_mask; | |
285 | u64 valid_mask; | |
286 | int idx; /* per_xxx->regs[] reg index */ | |
287 | }; | |
288 | ||
289 | #define EVENT_EXTRA_REG(e, ms, m, vm, i) { \ | |
290 | .event = (e), \ | |
291 | .msr = (ms), \ | |
292 | .config_mask = (m), \ | |
293 | .valid_mask = (vm), \ | |
f20093ee | 294 | .idx = EXTRA_REG_##i, \ |
de0428a7 KW |
295 | } |
296 | ||
297 | #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \ | |
298 | EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx) | |
299 | ||
f20093ee SE |
300 | #define INTEL_UEVENT_EXTRA_REG(event, msr, vm, idx) \ |
301 | EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \ | |
302 | ARCH_PERFMON_EVENTSEL_UMASK, vm, idx) | |
303 | ||
304 | #define INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(c) \ | |
305 | INTEL_UEVENT_EXTRA_REG(c, \ | |
306 | MSR_PEBS_LD_LAT_THRESHOLD, \ | |
307 | 0xffff, \ | |
308 | LDLAT) | |
309 | ||
de0428a7 KW |
310 | #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0) |
311 | ||
312 | union perf_capabilities { | |
313 | struct { | |
314 | u64 lbr_format:6; | |
315 | u64 pebs_trap:1; | |
316 | u64 pebs_arch_reg:1; | |
317 | u64 pebs_format:4; | |
318 | u64 smm_freeze:1; | |
069e0c3c AK |
319 | /* |
320 | * PMU supports separate counter range for writing | |
321 | * values > 32bit. | |
322 | */ | |
323 | u64 full_width_write:1; | |
de0428a7 KW |
324 | }; |
325 | u64 capabilities; | |
326 | }; | |
327 | ||
c1d6f42f PZ |
328 | struct x86_pmu_quirk { |
329 | struct x86_pmu_quirk *next; | |
330 | void (*func)(void); | |
331 | }; | |
332 | ||
f9b4eeb8 PZ |
333 | union x86_pmu_config { |
334 | struct { | |
335 | u64 event:8, | |
336 | umask:8, | |
337 | usr:1, | |
338 | os:1, | |
339 | edge:1, | |
340 | pc:1, | |
341 | interrupt:1, | |
342 | __reserved1:1, | |
343 | en:1, | |
344 | inv:1, | |
345 | cmask:8, | |
346 | event2:4, | |
347 | __reserved2:4, | |
348 | go:1, | |
349 | ho:1; | |
350 | } bits; | |
351 | u64 value; | |
352 | }; | |
353 | ||
354 | #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value | |
355 | ||
de0428a7 KW |
356 | /* |
357 | * struct x86_pmu - generic x86 pmu | |
358 | */ | |
359 | struct x86_pmu { | |
360 | /* | |
361 | * Generic x86 PMC bits | |
362 | */ | |
363 | const char *name; | |
364 | int version; | |
365 | int (*handle_irq)(struct pt_regs *); | |
366 | void (*disable_all)(void); | |
367 | void (*enable_all)(int added); | |
368 | void (*enable)(struct perf_event *); | |
369 | void (*disable)(struct perf_event *); | |
370 | int (*hw_config)(struct perf_event *event); | |
371 | int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign); | |
372 | unsigned eventsel; | |
373 | unsigned perfctr; | |
4c1fd17a | 374 | int (*addr_offset)(int index, bool eventsel); |
0fbdad07 | 375 | int (*rdpmc_index)(int index); |
de0428a7 KW |
376 | u64 (*event_map)(int); |
377 | int max_events; | |
378 | int num_counters; | |
379 | int num_counters_fixed; | |
380 | int cntval_bits; | |
381 | u64 cntval_mask; | |
ffb871bc GN |
382 | union { |
383 | unsigned long events_maskl; | |
384 | unsigned long events_mask[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT)]; | |
385 | }; | |
386 | int events_mask_len; | |
de0428a7 KW |
387 | int apic; |
388 | u64 max_period; | |
389 | struct event_constraint * | |
390 | (*get_event_constraints)(struct cpu_hw_events *cpuc, | |
391 | struct perf_event *event); | |
392 | ||
393 | void (*put_event_constraints)(struct cpu_hw_events *cpuc, | |
394 | struct perf_event *event); | |
395 | struct event_constraint *event_constraints; | |
c1d6f42f | 396 | struct x86_pmu_quirk *quirks; |
de0428a7 | 397 | int perfctr_second_write; |
72db5596 | 398 | bool late_ack; |
de0428a7 | 399 | |
0c9d42ed PZ |
400 | /* |
401 | * sysfs attrs | |
402 | */ | |
403 | int attr_rdpmc; | |
641cc938 | 404 | struct attribute **format_attrs; |
f20093ee | 405 | struct attribute **event_attrs; |
0c9d42ed | 406 | |
a4747393 | 407 | ssize_t (*events_sysfs_show)(char *page, u64 config); |
1a6461b1 | 408 | struct attribute **cpu_events; |
a4747393 | 409 | |
0c9d42ed PZ |
410 | /* |
411 | * CPU Hotplug hooks | |
412 | */ | |
de0428a7 KW |
413 | int (*cpu_prepare)(int cpu); |
414 | void (*cpu_starting)(int cpu); | |
415 | void (*cpu_dying)(int cpu); | |
416 | void (*cpu_dead)(int cpu); | |
c93dc84c PZ |
417 | |
418 | void (*check_microcode)(void); | |
d010b332 | 419 | void (*flush_branch_stack)(void); |
de0428a7 KW |
420 | |
421 | /* | |
422 | * Intel Arch Perfmon v2+ | |
423 | */ | |
424 | u64 intel_ctrl; | |
425 | union perf_capabilities intel_cap; | |
426 | ||
427 | /* | |
428 | * Intel DebugStore bits | |
429 | */ | |
597ed953 | 430 | unsigned int bts :1, |
3e0091e2 PZ |
431 | bts_active :1, |
432 | pebs :1, | |
433 | pebs_active :1, | |
434 | pebs_broken :1; | |
de0428a7 KW |
435 | int pebs_record_size; |
436 | void (*drain_pebs)(struct pt_regs *regs); | |
437 | struct event_constraint *pebs_constraints; | |
0780c927 | 438 | void (*pebs_aliases)(struct perf_event *event); |
70ab7003 | 439 | int max_pebs_events; |
de0428a7 KW |
440 | |
441 | /* | |
442 | * Intel LBR | |
443 | */ | |
444 | unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */ | |
445 | int lbr_nr; /* hardware stack size */ | |
b36817e8 SE |
446 | u64 lbr_sel_mask; /* LBR_SELECT valid bits */ |
447 | const int *lbr_sel_map; /* lbr_select mappings */ | |
de0428a7 KW |
448 | |
449 | /* | |
450 | * Extra registers for events | |
451 | */ | |
452 | struct extra_reg *extra_regs; | |
453 | unsigned int er_flags; | |
144d31e6 GN |
454 | |
455 | /* | |
456 | * Intel host/guest support (KVM) | |
457 | */ | |
458 | struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr); | |
de0428a7 KW |
459 | }; |
460 | ||
c1d6f42f PZ |
461 | #define x86_add_quirk(func_) \ |
462 | do { \ | |
463 | static struct x86_pmu_quirk __quirk __initdata = { \ | |
464 | .func = func_, \ | |
465 | }; \ | |
466 | __quirk.next = x86_pmu.quirks; \ | |
467 | x86_pmu.quirks = &__quirk; \ | |
468 | } while (0) | |
469 | ||
de0428a7 KW |
470 | #define ERF_NO_HT_SHARING 1 |
471 | #define ERF_HAS_RSP_1 2 | |
472 | ||
3a54aaa0 SE |
473 | #define EVENT_VAR(_id) event_attr_##_id |
474 | #define EVENT_PTR(_id) &event_attr_##_id.attr.attr | |
475 | ||
476 | #define EVENT_ATTR(_name, _id) \ | |
477 | static struct perf_pmu_events_attr EVENT_VAR(_id) = { \ | |
478 | .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \ | |
479 | .id = PERF_COUNT_HW_##_id, \ | |
480 | .event_str = NULL, \ | |
481 | }; | |
482 | ||
483 | #define EVENT_ATTR_STR(_name, v, str) \ | |
484 | static struct perf_pmu_events_attr event_attr_##v = { \ | |
485 | .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \ | |
486 | .id = 0, \ | |
487 | .event_str = str, \ | |
488 | }; | |
489 | ||
de0428a7 KW |
490 | extern struct x86_pmu x86_pmu __read_mostly; |
491 | ||
492 | DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events); | |
493 | ||
494 | int x86_perf_event_set_period(struct perf_event *event); | |
495 | ||
496 | /* | |
497 | * Generalized hw caching related hw_event table, filled | |
498 | * in on a per model basis. A value of 0 means | |
499 | * 'not supported', -1 means 'hw_event makes no sense on | |
500 | * this CPU', any other value means the raw hw_event | |
501 | * ID. | |
502 | */ | |
503 | ||
504 | #define C(x) PERF_COUNT_HW_CACHE_##x | |
505 | ||
506 | extern u64 __read_mostly hw_cache_event_ids | |
507 | [PERF_COUNT_HW_CACHE_MAX] | |
508 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
509 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
510 | extern u64 __read_mostly hw_cache_extra_regs | |
511 | [PERF_COUNT_HW_CACHE_MAX] | |
512 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
513 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
514 | ||
515 | u64 x86_perf_event_update(struct perf_event *event); | |
516 | ||
de0428a7 KW |
517 | static inline unsigned int x86_pmu_config_addr(int index) |
518 | { | |
4c1fd17a JS |
519 | return x86_pmu.eventsel + (x86_pmu.addr_offset ? |
520 | x86_pmu.addr_offset(index, true) : index); | |
de0428a7 KW |
521 | } |
522 | ||
523 | static inline unsigned int x86_pmu_event_addr(int index) | |
524 | { | |
4c1fd17a JS |
525 | return x86_pmu.perfctr + (x86_pmu.addr_offset ? |
526 | x86_pmu.addr_offset(index, false) : index); | |
de0428a7 KW |
527 | } |
528 | ||
0fbdad07 JS |
529 | static inline int x86_pmu_rdpmc_index(int index) |
530 | { | |
531 | return x86_pmu.rdpmc_index ? x86_pmu.rdpmc_index(index) : index; | |
532 | } | |
533 | ||
de0428a7 KW |
534 | int x86_setup_perfctr(struct perf_event *event); |
535 | ||
536 | int x86_pmu_hw_config(struct perf_event *event); | |
537 | ||
538 | void x86_pmu_disable_all(void); | |
539 | ||
540 | static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, | |
541 | u64 enable_mask) | |
542 | { | |
1018faa6 JR |
543 | u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask); |
544 | ||
de0428a7 KW |
545 | if (hwc->extra_reg.reg) |
546 | wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config); | |
1018faa6 | 547 | wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask); |
de0428a7 KW |
548 | } |
549 | ||
550 | void x86_pmu_enable_all(int added); | |
551 | ||
43b45780 | 552 | int perf_assign_events(struct perf_event **events, int n, |
4b4969b1 | 553 | int wmin, int wmax, int *assign); |
de0428a7 KW |
554 | int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign); |
555 | ||
556 | void x86_pmu_stop(struct perf_event *event, int flags); | |
557 | ||
558 | static inline void x86_pmu_disable_event(struct perf_event *event) | |
559 | { | |
560 | struct hw_perf_event *hwc = &event->hw; | |
561 | ||
562 | wrmsrl(hwc->config_base, hwc->config); | |
563 | } | |
564 | ||
565 | void x86_pmu_enable_event(struct perf_event *event); | |
566 | ||
567 | int x86_pmu_handle_irq(struct pt_regs *regs); | |
568 | ||
569 | extern struct event_constraint emptyconstraint; | |
570 | ||
571 | extern struct event_constraint unconstrained; | |
572 | ||
3e702ff6 SE |
573 | static inline bool kernel_ip(unsigned long ip) |
574 | { | |
575 | #ifdef CONFIG_X86_32 | |
576 | return ip > PAGE_OFFSET; | |
577 | #else | |
578 | return (long)ip < 0; | |
579 | #endif | |
580 | } | |
581 | ||
d07bdfd3 PZ |
582 | /* |
583 | * Not all PMUs provide the right context information to place the reported IP | |
584 | * into full context. Specifically segment registers are typically not | |
585 | * supplied. | |
586 | * | |
587 | * Assuming the address is a linear address (it is for IBS), we fake the CS and | |
588 | * vm86 mode using the known zero-based code segment and 'fix up' the registers | |
589 | * to reflect this. | |
590 | * | |
591 | * Intel PEBS/LBR appear to typically provide the effective address, nothing | |
592 | * much we can do about that but pray and treat it like a linear address. | |
593 | */ | |
594 | static inline void set_linear_ip(struct pt_regs *regs, unsigned long ip) | |
595 | { | |
596 | regs->cs = kernel_ip(ip) ? __KERNEL_CS : __USER_CS; | |
597 | if (regs->flags & X86_VM_MASK) | |
598 | regs->flags ^= (PERF_EFLAGS_VM | X86_VM_MASK); | |
599 | regs->ip = ip; | |
600 | } | |
601 | ||
0bf79d44 | 602 | ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event); |
20550a43 | 603 | ssize_t intel_event_sysfs_show(char *page, u64 config); |
43c032fe | 604 | |
de0428a7 KW |
605 | #ifdef CONFIG_CPU_SUP_AMD |
606 | ||
607 | int amd_pmu_init(void); | |
608 | ||
609 | #else /* CONFIG_CPU_SUP_AMD */ | |
610 | ||
611 | static inline int amd_pmu_init(void) | |
612 | { | |
613 | return 0; | |
614 | } | |
615 | ||
616 | #endif /* CONFIG_CPU_SUP_AMD */ | |
617 | ||
618 | #ifdef CONFIG_CPU_SUP_INTEL | |
619 | ||
620 | int intel_pmu_save_and_restart(struct perf_event *event); | |
621 | ||
622 | struct event_constraint * | |
623 | x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event); | |
624 | ||
625 | struct intel_shared_regs *allocate_shared_regs(int cpu); | |
626 | ||
627 | int intel_pmu_init(void); | |
628 | ||
629 | void init_debug_store_on_cpu(int cpu); | |
630 | ||
631 | void fini_debug_store_on_cpu(int cpu); | |
632 | ||
633 | void release_ds_buffers(void); | |
634 | ||
635 | void reserve_ds_buffers(void); | |
636 | ||
637 | extern struct event_constraint bts_constraint; | |
638 | ||
639 | void intel_pmu_enable_bts(u64 config); | |
640 | ||
641 | void intel_pmu_disable_bts(void); | |
642 | ||
643 | int intel_pmu_drain_bts_buffer(void); | |
644 | ||
645 | extern struct event_constraint intel_core2_pebs_event_constraints[]; | |
646 | ||
647 | extern struct event_constraint intel_atom_pebs_event_constraints[]; | |
648 | ||
1fa64180 YZ |
649 | extern struct event_constraint intel_slm_pebs_event_constraints[]; |
650 | ||
de0428a7 KW |
651 | extern struct event_constraint intel_nehalem_pebs_event_constraints[]; |
652 | ||
653 | extern struct event_constraint intel_westmere_pebs_event_constraints[]; | |
654 | ||
655 | extern struct event_constraint intel_snb_pebs_event_constraints[]; | |
656 | ||
20a36e39 SE |
657 | extern struct event_constraint intel_ivb_pebs_event_constraints[]; |
658 | ||
3044318f AK |
659 | extern struct event_constraint intel_hsw_pebs_event_constraints[]; |
660 | ||
de0428a7 KW |
661 | struct event_constraint *intel_pebs_constraints(struct perf_event *event); |
662 | ||
663 | void intel_pmu_pebs_enable(struct perf_event *event); | |
664 | ||
665 | void intel_pmu_pebs_disable(struct perf_event *event); | |
666 | ||
667 | void intel_pmu_pebs_enable_all(void); | |
668 | ||
669 | void intel_pmu_pebs_disable_all(void); | |
670 | ||
671 | void intel_ds_init(void); | |
672 | ||
673 | void intel_pmu_lbr_reset(void); | |
674 | ||
675 | void intel_pmu_lbr_enable(struct perf_event *event); | |
676 | ||
677 | void intel_pmu_lbr_disable(struct perf_event *event); | |
678 | ||
679 | void intel_pmu_lbr_enable_all(void); | |
680 | ||
681 | void intel_pmu_lbr_disable_all(void); | |
682 | ||
683 | void intel_pmu_lbr_read(void); | |
684 | ||
685 | void intel_pmu_lbr_init_core(void); | |
686 | ||
687 | void intel_pmu_lbr_init_nhm(void); | |
688 | ||
689 | void intel_pmu_lbr_init_atom(void); | |
690 | ||
c5cc2cd9 SE |
691 | void intel_pmu_lbr_init_snb(void); |
692 | ||
60ce0fbd SE |
693 | int intel_pmu_setup_lbr_filter(struct perf_event *event); |
694 | ||
de0428a7 KW |
695 | int p4_pmu_init(void); |
696 | ||
697 | int p6_pmu_init(void); | |
698 | ||
e717bf4e VW |
699 | int knc_pmu_init(void); |
700 | ||
f20093ee SE |
701 | ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, |
702 | char *page); | |
703 | ||
de0428a7 KW |
704 | #else /* CONFIG_CPU_SUP_INTEL */ |
705 | ||
706 | static inline void reserve_ds_buffers(void) | |
707 | { | |
708 | } | |
709 | ||
710 | static inline void release_ds_buffers(void) | |
711 | { | |
712 | } | |
713 | ||
714 | static inline int intel_pmu_init(void) | |
715 | { | |
716 | return 0; | |
717 | } | |
718 | ||
719 | static inline struct intel_shared_regs *allocate_shared_regs(int cpu) | |
720 | { | |
721 | return NULL; | |
722 | } | |
723 | ||
724 | #endif /* CONFIG_CPU_SUP_INTEL */ |