Commit | Line | Data |
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de0428a7 KW |
1 | /* |
2 | * Performance events x86 architecture header | |
3 | * | |
4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> | |
5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> | |
9 | * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> | |
10 | * Copyright (C) 2009 Google, Inc., Stephane Eranian | |
11 | * | |
12 | * For licencing details see kernel-base/COPYING | |
13 | */ | |
14 | ||
15 | #include <linux/perf_event.h> | |
16 | ||
1c2ac3fd PZ |
17 | #if 0 |
18 | #undef wrmsrl | |
19 | #define wrmsrl(msr, val) \ | |
20 | do { \ | |
21 | unsigned int _msr = (msr); \ | |
22 | u64 _val = (val); \ | |
23 | trace_printk("wrmsrl(%x, %Lx)\n", (unsigned int)(_msr), \ | |
24 | (unsigned long long)(_val)); \ | |
25 | native_write_msr((_msr), (u32)(_val), (u32)(_val >> 32)); \ | |
26 | } while (0) | |
27 | #endif | |
28 | ||
de0428a7 KW |
29 | /* |
30 | * | NHM/WSM | SNB | | |
31 | * register ------------------------------- | |
32 | * | HT | no HT | HT | no HT | | |
33 | *----------------------------------------- | |
34 | * offcore | core | core | cpu | core | | |
35 | * lbr_sel | core | core | cpu | core | | |
36 | * ld_lat | cpu | core | cpu | core | | |
37 | *----------------------------------------- | |
38 | * | |
39 | * Given that there is a small number of shared regs, | |
40 | * we can pre-allocate their slot in the per-cpu | |
41 | * per-core reg tables. | |
42 | */ | |
43 | enum extra_reg_type { | |
44 | EXTRA_REG_NONE = -1, /* not used */ | |
45 | ||
46 | EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */ | |
47 | EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */ | |
b36817e8 | 48 | EXTRA_REG_LBR = 2, /* lbr_select */ |
f20093ee | 49 | EXTRA_REG_LDLAT = 3, /* ld_lat_threshold */ |
de0428a7 KW |
50 | |
51 | EXTRA_REG_MAX /* number of entries needed */ | |
52 | }; | |
53 | ||
54 | struct event_constraint { | |
55 | union { | |
56 | unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
57 | u64 idxmsk64; | |
58 | }; | |
59 | u64 code; | |
60 | u64 cmask; | |
61 | int weight; | |
bc1738f6 | 62 | int overlap; |
9fac2cf3 | 63 | int flags; |
de0428a7 | 64 | }; |
f20093ee | 65 | /* |
2f7f73a5 | 66 | * struct hw_perf_event.flags flags |
f20093ee | 67 | */ |
c857eb56 PZ |
68 | #define PERF_X86_EVENT_PEBS_LDLAT 0x0001 /* ld+ldlat data address sampling */ |
69 | #define PERF_X86_EVENT_PEBS_ST 0x0002 /* st data address sampling */ | |
70 | #define PERF_X86_EVENT_PEBS_ST_HSW 0x0004 /* haswell style datala, store */ | |
71 | #define PERF_X86_EVENT_COMMITTED 0x0008 /* event passed commit_txn */ | |
72 | #define PERF_X86_EVENT_PEBS_LD_HSW 0x0010 /* haswell style datala, load */ | |
73 | #define PERF_X86_EVENT_PEBS_NA_HSW 0x0020 /* haswell style datala, unknown */ | |
74 | #define PERF_X86_EVENT_EXCL 0x0040 /* HT exclusivity on counter */ | |
75 | #define PERF_X86_EVENT_DYNAMIC 0x0080 /* dynamic alloc'd constraint */ | |
76 | #define PERF_X86_EVENT_RDPMC_ALLOWED 0x0100 /* grant rdpmc permission */ | |
7911d3f7 | 77 | |
de0428a7 KW |
78 | |
79 | struct amd_nb { | |
80 | int nb_id; /* NorthBridge id */ | |
81 | int refcnt; /* reference count */ | |
82 | struct perf_event *owners[X86_PMC_IDX_MAX]; | |
83 | struct event_constraint event_constraints[X86_PMC_IDX_MAX]; | |
84 | }; | |
85 | ||
86 | /* The maximal number of PEBS events: */ | |
70ab7003 | 87 | #define MAX_PEBS_EVENTS 8 |
de0428a7 KW |
88 | |
89 | /* | |
90 | * A debug store configuration. | |
91 | * | |
92 | * We only support architectures that use 64bit fields. | |
93 | */ | |
94 | struct debug_store { | |
95 | u64 bts_buffer_base; | |
96 | u64 bts_index; | |
97 | u64 bts_absolute_maximum; | |
98 | u64 bts_interrupt_threshold; | |
99 | u64 pebs_buffer_base; | |
100 | u64 pebs_index; | |
101 | u64 pebs_absolute_maximum; | |
102 | u64 pebs_interrupt_threshold; | |
103 | u64 pebs_event_reset[MAX_PEBS_EVENTS]; | |
104 | }; | |
105 | ||
106 | /* | |
107 | * Per register state. | |
108 | */ | |
109 | struct er_account { | |
110 | raw_spinlock_t lock; /* per-core: protect structure */ | |
111 | u64 config; /* extra MSR config */ | |
112 | u64 reg; /* extra MSR number */ | |
113 | atomic_t ref; /* reference count */ | |
114 | }; | |
115 | ||
116 | /* | |
117 | * Per core/cpu state | |
118 | * | |
119 | * Used to coordinate shared registers between HT threads or | |
120 | * among events on a single PMU. | |
121 | */ | |
122 | struct intel_shared_regs { | |
123 | struct er_account regs[EXTRA_REG_MAX]; | |
124 | int refcnt; /* per-core: #HT threads */ | |
125 | unsigned core_id; /* per-core: core id */ | |
126 | }; | |
127 | ||
6f6539ca MD |
128 | enum intel_excl_state_type { |
129 | INTEL_EXCL_UNUSED = 0, /* counter is unused */ | |
130 | INTEL_EXCL_SHARED = 1, /* counter can be used by both threads */ | |
131 | INTEL_EXCL_EXCLUSIVE = 2, /* counter can be used by one thread only */ | |
132 | }; | |
133 | ||
134 | struct intel_excl_states { | |
135 | enum intel_excl_state_type init_state[X86_PMC_IDX_MAX]; | |
136 | enum intel_excl_state_type state[X86_PMC_IDX_MAX]; | |
c02cdbf6 SE |
137 | int num_alloc_cntrs;/* #counters allocated */ |
138 | int max_alloc_cntrs;/* max #counters allowed */ | |
e979121b | 139 | bool sched_started; /* true if scheduling has started */ |
6f6539ca MD |
140 | }; |
141 | ||
142 | struct intel_excl_cntrs { | |
143 | raw_spinlock_t lock; | |
144 | ||
145 | struct intel_excl_states states[2]; | |
146 | ||
147 | int refcnt; /* per-core: #HT threads */ | |
148 | unsigned core_id; /* per-core: core id */ | |
149 | }; | |
150 | ||
de0428a7 KW |
151 | #define MAX_LBR_ENTRIES 16 |
152 | ||
90413464 SE |
153 | enum { |
154 | X86_PERF_KFREE_SHARED = 0, | |
155 | X86_PERF_KFREE_EXCL = 1, | |
156 | X86_PERF_KFREE_MAX | |
157 | }; | |
158 | ||
de0428a7 KW |
159 | struct cpu_hw_events { |
160 | /* | |
161 | * Generic x86 PMC bits | |
162 | */ | |
163 | struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */ | |
164 | unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
165 | unsigned long running[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
166 | int enabled; | |
167 | ||
c347a2f1 PZ |
168 | int n_events; /* the # of events in the below arrays */ |
169 | int n_added; /* the # last events in the below arrays; | |
170 | they've never been enabled yet */ | |
171 | int n_txn; /* the # last events in the below arrays; | |
172 | added in the current transaction */ | |
de0428a7 KW |
173 | int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */ |
174 | u64 tags[X86_PMC_IDX_MAX]; | |
b371b594 | 175 | |
de0428a7 | 176 | struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */ |
b371b594 PZ |
177 | struct event_constraint *event_constraint[X86_PMC_IDX_MAX]; |
178 | ||
de0428a7 KW |
179 | |
180 | unsigned int group_flag; | |
5a425294 | 181 | int is_fake; |
de0428a7 KW |
182 | |
183 | /* | |
184 | * Intel DebugStore bits | |
185 | */ | |
186 | struct debug_store *ds; | |
187 | u64 pebs_enabled; | |
188 | ||
189 | /* | |
190 | * Intel LBR bits | |
191 | */ | |
192 | int lbr_users; | |
193 | void *lbr_context; | |
194 | struct perf_branch_stack lbr_stack; | |
195 | struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES]; | |
b36817e8 | 196 | struct er_account *lbr_sel; |
3e702ff6 | 197 | u64 br_sel; |
de0428a7 | 198 | |
144d31e6 GN |
199 | /* |
200 | * Intel host/guest exclude bits | |
201 | */ | |
202 | u64 intel_ctrl_guest_mask; | |
203 | u64 intel_ctrl_host_mask; | |
204 | struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX]; | |
205 | ||
2b9e344d PZ |
206 | /* |
207 | * Intel checkpoint mask | |
208 | */ | |
209 | u64 intel_cp_status; | |
210 | ||
de0428a7 KW |
211 | /* |
212 | * manage shared (per-core, per-cpu) registers | |
213 | * used on Intel NHM/WSM/SNB | |
214 | */ | |
215 | struct intel_shared_regs *shared_regs; | |
6f6539ca MD |
216 | /* |
217 | * manage exclusive counter access between hyperthread | |
218 | */ | |
219 | struct event_constraint *constraint_list; /* in enable order */ | |
220 | struct intel_excl_cntrs *excl_cntrs; | |
221 | int excl_thread_id; /* 0 or 1 */ | |
de0428a7 KW |
222 | |
223 | /* | |
224 | * AMD specific bits | |
225 | */ | |
1018faa6 JR |
226 | struct amd_nb *amd_nb; |
227 | /* Inverted mask of bits to clear in the perf_ctr ctrl registers */ | |
228 | u64 perf_ctr_virt_mask; | |
de0428a7 | 229 | |
90413464 | 230 | void *kfree_on_online[X86_PERF_KFREE_MAX]; |
de0428a7 KW |
231 | }; |
232 | ||
9fac2cf3 | 233 | #define __EVENT_CONSTRAINT(c, n, m, w, o, f) {\ |
de0428a7 KW |
234 | { .idxmsk64 = (n) }, \ |
235 | .code = (c), \ | |
236 | .cmask = (m), \ | |
237 | .weight = (w), \ | |
bc1738f6 | 238 | .overlap = (o), \ |
9fac2cf3 | 239 | .flags = f, \ |
de0428a7 KW |
240 | } |
241 | ||
242 | #define EVENT_CONSTRAINT(c, n, m) \ | |
9fac2cf3 | 243 | __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0) |
bc1738f6 | 244 | |
6f6539ca MD |
245 | #define INTEL_EXCLEVT_CONSTRAINT(c, n) \ |
246 | __EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT, HWEIGHT(n),\ | |
247 | 0, PERF_X86_EVENT_EXCL) | |
248 | ||
bc1738f6 RR |
249 | /* |
250 | * The overlap flag marks event constraints with overlapping counter | |
251 | * masks. This is the case if the counter mask of such an event is not | |
252 | * a subset of any other counter mask of a constraint with an equal or | |
253 | * higher weight, e.g.: | |
254 | * | |
255 | * c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0); | |
256 | * c_another1 = EVENT_CONSTRAINT(0, 0x07, 0); | |
257 | * c_another2 = EVENT_CONSTRAINT(0, 0x38, 0); | |
258 | * | |
259 | * The event scheduler may not select the correct counter in the first | |
260 | * cycle because it needs to know which subsequent events will be | |
261 | * scheduled. It may fail to schedule the events then. So we set the | |
262 | * overlap flag for such constraints to give the scheduler a hint which | |
263 | * events to select for counter rescheduling. | |
264 | * | |
265 | * Care must be taken as the rescheduling algorithm is O(n!) which | |
266 | * will increase scheduling cycles for an over-commited system | |
267 | * dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros | |
268 | * and its counter masks must be kept at a minimum. | |
269 | */ | |
270 | #define EVENT_CONSTRAINT_OVERLAP(c, n, m) \ | |
9fac2cf3 | 271 | __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1, 0) |
de0428a7 KW |
272 | |
273 | /* | |
274 | * Constraint on the Event code. | |
275 | */ | |
276 | #define INTEL_EVENT_CONSTRAINT(c, n) \ | |
277 | EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT) | |
278 | ||
279 | /* | |
280 | * Constraint on the Event code + UMask + fixed-mask | |
281 | * | |
282 | * filter mask to validate fixed counter events. | |
283 | * the following filters disqualify for fixed counters: | |
284 | * - inv | |
285 | * - edge | |
286 | * - cnt-mask | |
3a632cb2 AK |
287 | * - in_tx |
288 | * - in_tx_checkpointed | |
de0428a7 KW |
289 | * The other filters are supported by fixed counters. |
290 | * The any-thread option is supported starting with v3. | |
291 | */ | |
3a632cb2 | 292 | #define FIXED_EVENT_FLAGS (X86_RAW_EVENT_MASK|HSW_IN_TX|HSW_IN_TX_CHECKPOINTED) |
de0428a7 | 293 | #define FIXED_EVENT_CONSTRAINT(c, n) \ |
3a632cb2 | 294 | EVENT_CONSTRAINT(c, (1ULL << (32+n)), FIXED_EVENT_FLAGS) |
de0428a7 KW |
295 | |
296 | /* | |
297 | * Constraint on the Event code + UMask | |
298 | */ | |
299 | #define INTEL_UEVENT_CONSTRAINT(c, n) \ | |
300 | EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK) | |
301 | ||
7550ddff AK |
302 | /* Like UEVENT_CONSTRAINT, but match flags too */ |
303 | #define INTEL_FLAGS_UEVENT_CONSTRAINT(c, n) \ | |
304 | EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS) | |
305 | ||
e979121b MD |
306 | #define INTEL_EXCLUEVT_CONSTRAINT(c, n) \ |
307 | __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \ | |
308 | HWEIGHT(n), 0, PERF_X86_EVENT_EXCL) | |
309 | ||
f20093ee | 310 | #define INTEL_PLD_CONSTRAINT(c, n) \ |
86a04461 | 311 | __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ |
f20093ee SE |
312 | HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LDLAT) |
313 | ||
9ad64c0f | 314 | #define INTEL_PST_CONSTRAINT(c, n) \ |
86a04461 | 315 | __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ |
9ad64c0f SE |
316 | HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST) |
317 | ||
86a04461 AK |
318 | /* Event constraint, but match on all event flags too. */ |
319 | #define INTEL_FLAGS_EVENT_CONSTRAINT(c, n) \ | |
320 | EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS) | |
321 | ||
322 | /* Check only flags, but allow all event/umask */ | |
323 | #define INTEL_ALL_EVENT_CONSTRAINT(code, n) \ | |
324 | EVENT_CONSTRAINT(code, n, X86_ALL_EVENT_FLAGS) | |
325 | ||
326 | /* Check flags and event code, and set the HSW store flag */ | |
327 | #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_ST(code, n) \ | |
328 | __EVENT_CONSTRAINT(code, n, \ | |
329 | ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ | |
330 | HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW) | |
331 | ||
332 | /* Check flags and event code, and set the HSW load flag */ | |
333 | #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(code, n) \ | |
b63b4b45 | 334 | __EVENT_CONSTRAINT(code, n, \ |
86a04461 AK |
335 | ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ |
336 | HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) | |
337 | ||
b63b4b45 MD |
338 | #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(code, n) \ |
339 | __EVENT_CONSTRAINT(code, n, \ | |
340 | ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ | |
341 | HWEIGHT(n), 0, \ | |
342 | PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL) | |
343 | ||
86a04461 AK |
344 | /* Check flags and event code/umask, and set the HSW store flag */ |
345 | #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(code, n) \ | |
346 | __EVENT_CONSTRAINT(code, n, \ | |
347 | INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ | |
f9134f36 AK |
348 | HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW) |
349 | ||
b63b4b45 MD |
350 | #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(code, n) \ |
351 | __EVENT_CONSTRAINT(code, n, \ | |
352 | INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ | |
353 | HWEIGHT(n), 0, \ | |
354 | PERF_X86_EVENT_PEBS_ST_HSW|PERF_X86_EVENT_EXCL) | |
355 | ||
86a04461 AK |
356 | /* Check flags and event code/umask, and set the HSW load flag */ |
357 | #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(code, n) \ | |
358 | __EVENT_CONSTRAINT(code, n, \ | |
359 | INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ | |
360 | HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) | |
361 | ||
b63b4b45 MD |
362 | #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(code, n) \ |
363 | __EVENT_CONSTRAINT(code, n, \ | |
364 | INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ | |
365 | HWEIGHT(n), 0, \ | |
366 | PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL) | |
367 | ||
86a04461 AK |
368 | /* Check flags and event code/umask, and set the HSW N/A flag */ |
369 | #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(code, n) \ | |
370 | __EVENT_CONSTRAINT(code, n, \ | |
371 | INTEL_ARCH_EVENT_MASK|INTEL_ARCH_EVENT_MASK, \ | |
372 | HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_NA_HSW) | |
373 | ||
374 | ||
cf30d52e MD |
375 | /* |
376 | * We define the end marker as having a weight of -1 | |
377 | * to enable blacklisting of events using a counter bitmask | |
378 | * of zero and thus a weight of zero. | |
379 | * The end marker has a weight that cannot possibly be | |
380 | * obtained from counting the bits in the bitmask. | |
381 | */ | |
382 | #define EVENT_CONSTRAINT_END { .weight = -1 } | |
de0428a7 | 383 | |
cf30d52e MD |
384 | /* |
385 | * Check for end marker with weight == -1 | |
386 | */ | |
de0428a7 | 387 | #define for_each_event_constraint(e, c) \ |
cf30d52e | 388 | for ((e) = (c); (e)->weight != -1; (e)++) |
de0428a7 KW |
389 | |
390 | /* | |
391 | * Extra registers for specific events. | |
392 | * | |
393 | * Some events need large masks and require external MSRs. | |
394 | * Those extra MSRs end up being shared for all events on | |
395 | * a PMU and sometimes between PMU of sibling HT threads. | |
396 | * In either case, the kernel needs to handle conflicting | |
397 | * accesses to those extra, shared, regs. The data structure | |
398 | * to manage those registers is stored in cpu_hw_event. | |
399 | */ | |
400 | struct extra_reg { | |
401 | unsigned int event; | |
402 | unsigned int msr; | |
403 | u64 config_mask; | |
404 | u64 valid_mask; | |
405 | int idx; /* per_xxx->regs[] reg index */ | |
338b522c | 406 | bool extra_msr_access; |
de0428a7 KW |
407 | }; |
408 | ||
409 | #define EVENT_EXTRA_REG(e, ms, m, vm, i) { \ | |
338b522c KL |
410 | .event = (e), \ |
411 | .msr = (ms), \ | |
412 | .config_mask = (m), \ | |
413 | .valid_mask = (vm), \ | |
414 | .idx = EXTRA_REG_##i, \ | |
415 | .extra_msr_access = true, \ | |
de0428a7 KW |
416 | } |
417 | ||
418 | #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \ | |
419 | EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx) | |
420 | ||
f20093ee SE |
421 | #define INTEL_UEVENT_EXTRA_REG(event, msr, vm, idx) \ |
422 | EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \ | |
423 | ARCH_PERFMON_EVENTSEL_UMASK, vm, idx) | |
424 | ||
425 | #define INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(c) \ | |
426 | INTEL_UEVENT_EXTRA_REG(c, \ | |
427 | MSR_PEBS_LD_LAT_THRESHOLD, \ | |
428 | 0xffff, \ | |
429 | LDLAT) | |
430 | ||
de0428a7 KW |
431 | #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0) |
432 | ||
433 | union perf_capabilities { | |
434 | struct { | |
435 | u64 lbr_format:6; | |
436 | u64 pebs_trap:1; | |
437 | u64 pebs_arch_reg:1; | |
438 | u64 pebs_format:4; | |
439 | u64 smm_freeze:1; | |
069e0c3c AK |
440 | /* |
441 | * PMU supports separate counter range for writing | |
442 | * values > 32bit. | |
443 | */ | |
444 | u64 full_width_write:1; | |
de0428a7 KW |
445 | }; |
446 | u64 capabilities; | |
447 | }; | |
448 | ||
c1d6f42f PZ |
449 | struct x86_pmu_quirk { |
450 | struct x86_pmu_quirk *next; | |
451 | void (*func)(void); | |
452 | }; | |
453 | ||
f9b4eeb8 PZ |
454 | union x86_pmu_config { |
455 | struct { | |
456 | u64 event:8, | |
457 | umask:8, | |
458 | usr:1, | |
459 | os:1, | |
460 | edge:1, | |
461 | pc:1, | |
462 | interrupt:1, | |
463 | __reserved1:1, | |
464 | en:1, | |
465 | inv:1, | |
466 | cmask:8, | |
467 | event2:4, | |
468 | __reserved2:4, | |
469 | go:1, | |
470 | ho:1; | |
471 | } bits; | |
472 | u64 value; | |
473 | }; | |
474 | ||
475 | #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value | |
476 | ||
48070342 AS |
477 | enum { |
478 | x86_lbr_exclusive_lbr, | |
8062382c | 479 | x86_lbr_exclusive_bts, |
48070342 AS |
480 | x86_lbr_exclusive_pt, |
481 | x86_lbr_exclusive_max, | |
482 | }; | |
483 | ||
de0428a7 KW |
484 | /* |
485 | * struct x86_pmu - generic x86 pmu | |
486 | */ | |
487 | struct x86_pmu { | |
488 | /* | |
489 | * Generic x86 PMC bits | |
490 | */ | |
491 | const char *name; | |
492 | int version; | |
493 | int (*handle_irq)(struct pt_regs *); | |
494 | void (*disable_all)(void); | |
495 | void (*enable_all)(int added); | |
496 | void (*enable)(struct perf_event *); | |
497 | void (*disable)(struct perf_event *); | |
498 | int (*hw_config)(struct perf_event *event); | |
499 | int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign); | |
500 | unsigned eventsel; | |
501 | unsigned perfctr; | |
4c1fd17a | 502 | int (*addr_offset)(int index, bool eventsel); |
0fbdad07 | 503 | int (*rdpmc_index)(int index); |
de0428a7 KW |
504 | u64 (*event_map)(int); |
505 | int max_events; | |
506 | int num_counters; | |
507 | int num_counters_fixed; | |
508 | int cntval_bits; | |
509 | u64 cntval_mask; | |
ffb871bc GN |
510 | union { |
511 | unsigned long events_maskl; | |
512 | unsigned long events_mask[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT)]; | |
513 | }; | |
514 | int events_mask_len; | |
de0428a7 KW |
515 | int apic; |
516 | u64 max_period; | |
517 | struct event_constraint * | |
518 | (*get_event_constraints)(struct cpu_hw_events *cpuc, | |
79cba822 | 519 | int idx, |
de0428a7 KW |
520 | struct perf_event *event); |
521 | ||
522 | void (*put_event_constraints)(struct cpu_hw_events *cpuc, | |
523 | struct perf_event *event); | |
c5362c0c | 524 | |
b371b594 | 525 | void (*commit_scheduling)(struct cpu_hw_events *cpuc, int idx, int cntr); |
c5362c0c MD |
526 | |
527 | void (*start_scheduling)(struct cpu_hw_events *cpuc); | |
528 | ||
529 | void (*stop_scheduling)(struct cpu_hw_events *cpuc); | |
530 | ||
de0428a7 | 531 | struct event_constraint *event_constraints; |
c1d6f42f | 532 | struct x86_pmu_quirk *quirks; |
de0428a7 | 533 | int perfctr_second_write; |
72db5596 | 534 | bool late_ack; |
294fe0f5 | 535 | unsigned (*limit_period)(struct perf_event *event, unsigned l); |
de0428a7 | 536 | |
0c9d42ed PZ |
537 | /* |
538 | * sysfs attrs | |
539 | */ | |
e97df763 | 540 | int attr_rdpmc_broken; |
0c9d42ed | 541 | int attr_rdpmc; |
641cc938 | 542 | struct attribute **format_attrs; |
f20093ee | 543 | struct attribute **event_attrs; |
0c9d42ed | 544 | |
a4747393 | 545 | ssize_t (*events_sysfs_show)(char *page, u64 config); |
1a6461b1 | 546 | struct attribute **cpu_events; |
a4747393 | 547 | |
0c9d42ed PZ |
548 | /* |
549 | * CPU Hotplug hooks | |
550 | */ | |
de0428a7 KW |
551 | int (*cpu_prepare)(int cpu); |
552 | void (*cpu_starting)(int cpu); | |
553 | void (*cpu_dying)(int cpu); | |
554 | void (*cpu_dead)(int cpu); | |
c93dc84c PZ |
555 | |
556 | void (*check_microcode)(void); | |
ba532500 YZ |
557 | void (*sched_task)(struct perf_event_context *ctx, |
558 | bool sched_in); | |
de0428a7 KW |
559 | |
560 | /* | |
561 | * Intel Arch Perfmon v2+ | |
562 | */ | |
563 | u64 intel_ctrl; | |
564 | union perf_capabilities intel_cap; | |
565 | ||
566 | /* | |
567 | * Intel DebugStore bits | |
568 | */ | |
597ed953 | 569 | unsigned int bts :1, |
3e0091e2 PZ |
570 | bts_active :1, |
571 | pebs :1, | |
572 | pebs_active :1, | |
573 | pebs_broken :1; | |
de0428a7 KW |
574 | int pebs_record_size; |
575 | void (*drain_pebs)(struct pt_regs *regs); | |
576 | struct event_constraint *pebs_constraints; | |
0780c927 | 577 | void (*pebs_aliases)(struct perf_event *event); |
70ab7003 | 578 | int max_pebs_events; |
de0428a7 KW |
579 | |
580 | /* | |
581 | * Intel LBR | |
582 | */ | |
583 | unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */ | |
584 | int lbr_nr; /* hardware stack size */ | |
b36817e8 SE |
585 | u64 lbr_sel_mask; /* LBR_SELECT valid bits */ |
586 | const int *lbr_sel_map; /* lbr_select mappings */ | |
b7af41a1 | 587 | bool lbr_double_abort; /* duplicated lbr aborts */ |
de0428a7 | 588 | |
48070342 AS |
589 | /* |
590 | * Intel PT/LBR/BTS are exclusive | |
591 | */ | |
592 | atomic_t lbr_exclusive[x86_lbr_exclusive_max]; | |
593 | ||
de0428a7 KW |
594 | /* |
595 | * Extra registers for events | |
596 | */ | |
597 | struct extra_reg *extra_regs; | |
9a5e3fb5 | 598 | unsigned int flags; |
144d31e6 GN |
599 | |
600 | /* | |
601 | * Intel host/guest support (KVM) | |
602 | */ | |
603 | struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr); | |
de0428a7 KW |
604 | }; |
605 | ||
e18bf526 YZ |
606 | struct x86_perf_task_context { |
607 | u64 lbr_from[MAX_LBR_ENTRIES]; | |
608 | u64 lbr_to[MAX_LBR_ENTRIES]; | |
609 | int lbr_callstack_users; | |
610 | int lbr_stack_state; | |
611 | }; | |
612 | ||
c1d6f42f PZ |
613 | #define x86_add_quirk(func_) \ |
614 | do { \ | |
615 | static struct x86_pmu_quirk __quirk __initdata = { \ | |
616 | .func = func_, \ | |
617 | }; \ | |
618 | __quirk.next = x86_pmu.quirks; \ | |
619 | x86_pmu.quirks = &__quirk; \ | |
620 | } while (0) | |
621 | ||
9a5e3fb5 SE |
622 | /* |
623 | * x86_pmu flags | |
624 | */ | |
625 | #define PMU_FL_NO_HT_SHARING 0x1 /* no hyper-threading resource sharing */ | |
626 | #define PMU_FL_HAS_RSP_1 0x2 /* has 2 equivalent offcore_rsp regs */ | |
6f6539ca | 627 | #define PMU_FL_EXCL_CNTRS 0x4 /* has exclusive counter requirements */ |
b37609c3 | 628 | #define PMU_FL_EXCL_ENABLED 0x8 /* exclusive counter active */ |
de0428a7 | 629 | |
3a54aaa0 SE |
630 | #define EVENT_VAR(_id) event_attr_##_id |
631 | #define EVENT_PTR(_id) &event_attr_##_id.attr.attr | |
632 | ||
633 | #define EVENT_ATTR(_name, _id) \ | |
634 | static struct perf_pmu_events_attr EVENT_VAR(_id) = { \ | |
635 | .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \ | |
636 | .id = PERF_COUNT_HW_##_id, \ | |
637 | .event_str = NULL, \ | |
638 | }; | |
639 | ||
640 | #define EVENT_ATTR_STR(_name, v, str) \ | |
641 | static struct perf_pmu_events_attr event_attr_##v = { \ | |
642 | .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \ | |
643 | .id = 0, \ | |
644 | .event_str = str, \ | |
645 | }; | |
646 | ||
de0428a7 KW |
647 | extern struct x86_pmu x86_pmu __read_mostly; |
648 | ||
e9d7f7cd YZ |
649 | static inline bool x86_pmu_has_lbr_callstack(void) |
650 | { | |
651 | return x86_pmu.lbr_sel_map && | |
652 | x86_pmu.lbr_sel_map[PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] > 0; | |
653 | } | |
654 | ||
de0428a7 KW |
655 | DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events); |
656 | ||
657 | int x86_perf_event_set_period(struct perf_event *event); | |
658 | ||
659 | /* | |
660 | * Generalized hw caching related hw_event table, filled | |
661 | * in on a per model basis. A value of 0 means | |
662 | * 'not supported', -1 means 'hw_event makes no sense on | |
663 | * this CPU', any other value means the raw hw_event | |
664 | * ID. | |
665 | */ | |
666 | ||
667 | #define C(x) PERF_COUNT_HW_CACHE_##x | |
668 | ||
669 | extern u64 __read_mostly hw_cache_event_ids | |
670 | [PERF_COUNT_HW_CACHE_MAX] | |
671 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
672 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
673 | extern u64 __read_mostly hw_cache_extra_regs | |
674 | [PERF_COUNT_HW_CACHE_MAX] | |
675 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
676 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
677 | ||
678 | u64 x86_perf_event_update(struct perf_event *event); | |
679 | ||
de0428a7 KW |
680 | static inline unsigned int x86_pmu_config_addr(int index) |
681 | { | |
4c1fd17a JS |
682 | return x86_pmu.eventsel + (x86_pmu.addr_offset ? |
683 | x86_pmu.addr_offset(index, true) : index); | |
de0428a7 KW |
684 | } |
685 | ||
686 | static inline unsigned int x86_pmu_event_addr(int index) | |
687 | { | |
4c1fd17a JS |
688 | return x86_pmu.perfctr + (x86_pmu.addr_offset ? |
689 | x86_pmu.addr_offset(index, false) : index); | |
de0428a7 KW |
690 | } |
691 | ||
0fbdad07 JS |
692 | static inline int x86_pmu_rdpmc_index(int index) |
693 | { | |
694 | return x86_pmu.rdpmc_index ? x86_pmu.rdpmc_index(index) : index; | |
695 | } | |
696 | ||
48070342 AS |
697 | int x86_add_exclusive(unsigned int what); |
698 | ||
699 | void x86_del_exclusive(unsigned int what); | |
700 | ||
701 | void hw_perf_lbr_event_destroy(struct perf_event *event); | |
702 | ||
de0428a7 KW |
703 | int x86_setup_perfctr(struct perf_event *event); |
704 | ||
705 | int x86_pmu_hw_config(struct perf_event *event); | |
706 | ||
707 | void x86_pmu_disable_all(void); | |
708 | ||
709 | static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, | |
710 | u64 enable_mask) | |
711 | { | |
1018faa6 JR |
712 | u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask); |
713 | ||
de0428a7 KW |
714 | if (hwc->extra_reg.reg) |
715 | wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config); | |
1018faa6 | 716 | wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask); |
de0428a7 KW |
717 | } |
718 | ||
719 | void x86_pmu_enable_all(int added); | |
720 | ||
b371b594 | 721 | int perf_assign_events(struct event_constraint **constraints, int n, |
4b4969b1 | 722 | int wmin, int wmax, int *assign); |
de0428a7 KW |
723 | int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign); |
724 | ||
725 | void x86_pmu_stop(struct perf_event *event, int flags); | |
726 | ||
727 | static inline void x86_pmu_disable_event(struct perf_event *event) | |
728 | { | |
729 | struct hw_perf_event *hwc = &event->hw; | |
730 | ||
731 | wrmsrl(hwc->config_base, hwc->config); | |
732 | } | |
733 | ||
734 | void x86_pmu_enable_event(struct perf_event *event); | |
735 | ||
736 | int x86_pmu_handle_irq(struct pt_regs *regs); | |
737 | ||
738 | extern struct event_constraint emptyconstraint; | |
739 | ||
740 | extern struct event_constraint unconstrained; | |
741 | ||
3e702ff6 SE |
742 | static inline bool kernel_ip(unsigned long ip) |
743 | { | |
744 | #ifdef CONFIG_X86_32 | |
745 | return ip > PAGE_OFFSET; | |
746 | #else | |
747 | return (long)ip < 0; | |
748 | #endif | |
749 | } | |
750 | ||
d07bdfd3 PZ |
751 | /* |
752 | * Not all PMUs provide the right context information to place the reported IP | |
753 | * into full context. Specifically segment registers are typically not | |
754 | * supplied. | |
755 | * | |
756 | * Assuming the address is a linear address (it is for IBS), we fake the CS and | |
757 | * vm86 mode using the known zero-based code segment and 'fix up' the registers | |
758 | * to reflect this. | |
759 | * | |
760 | * Intel PEBS/LBR appear to typically provide the effective address, nothing | |
761 | * much we can do about that but pray and treat it like a linear address. | |
762 | */ | |
763 | static inline void set_linear_ip(struct pt_regs *regs, unsigned long ip) | |
764 | { | |
765 | regs->cs = kernel_ip(ip) ? __KERNEL_CS : __USER_CS; | |
766 | if (regs->flags & X86_VM_MASK) | |
767 | regs->flags ^= (PERF_EFLAGS_VM | X86_VM_MASK); | |
768 | regs->ip = ip; | |
769 | } | |
770 | ||
0bf79d44 | 771 | ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event); |
20550a43 | 772 | ssize_t intel_event_sysfs_show(char *page, u64 config); |
43c032fe | 773 | |
de0428a7 KW |
774 | #ifdef CONFIG_CPU_SUP_AMD |
775 | ||
776 | int amd_pmu_init(void); | |
777 | ||
778 | #else /* CONFIG_CPU_SUP_AMD */ | |
779 | ||
780 | static inline int amd_pmu_init(void) | |
781 | { | |
782 | return 0; | |
783 | } | |
784 | ||
785 | #endif /* CONFIG_CPU_SUP_AMD */ | |
786 | ||
787 | #ifdef CONFIG_CPU_SUP_INTEL | |
788 | ||
48070342 AS |
789 | static inline bool intel_pmu_needs_lbr_smpl(struct perf_event *event) |
790 | { | |
791 | /* user explicitly requested branch sampling */ | |
792 | if (has_branch_stack(event)) | |
793 | return true; | |
794 | ||
795 | /* implicit branch sampling to correct PEBS skid */ | |
796 | if (x86_pmu.intel_cap.pebs_trap && event->attr.precise_ip > 1 && | |
797 | x86_pmu.intel_cap.pebs_format < 2) | |
798 | return true; | |
799 | ||
800 | return false; | |
801 | } | |
802 | ||
803 | static inline bool intel_pmu_has_bts(struct perf_event *event) | |
804 | { | |
805 | if (event->attr.config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS && | |
806 | !event->attr.freq && event->hw.sample_period == 1) | |
807 | return true; | |
808 | ||
809 | return false; | |
810 | } | |
811 | ||
de0428a7 KW |
812 | int intel_pmu_save_and_restart(struct perf_event *event); |
813 | ||
814 | struct event_constraint * | |
79cba822 SE |
815 | x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, |
816 | struct perf_event *event); | |
de0428a7 KW |
817 | |
818 | struct intel_shared_regs *allocate_shared_regs(int cpu); | |
819 | ||
820 | int intel_pmu_init(void); | |
821 | ||
822 | void init_debug_store_on_cpu(int cpu); | |
823 | ||
824 | void fini_debug_store_on_cpu(int cpu); | |
825 | ||
826 | void release_ds_buffers(void); | |
827 | ||
828 | void reserve_ds_buffers(void); | |
829 | ||
830 | extern struct event_constraint bts_constraint; | |
831 | ||
832 | void intel_pmu_enable_bts(u64 config); | |
833 | ||
834 | void intel_pmu_disable_bts(void); | |
835 | ||
836 | int intel_pmu_drain_bts_buffer(void); | |
837 | ||
838 | extern struct event_constraint intel_core2_pebs_event_constraints[]; | |
839 | ||
840 | extern struct event_constraint intel_atom_pebs_event_constraints[]; | |
841 | ||
1fa64180 YZ |
842 | extern struct event_constraint intel_slm_pebs_event_constraints[]; |
843 | ||
de0428a7 KW |
844 | extern struct event_constraint intel_nehalem_pebs_event_constraints[]; |
845 | ||
846 | extern struct event_constraint intel_westmere_pebs_event_constraints[]; | |
847 | ||
848 | extern struct event_constraint intel_snb_pebs_event_constraints[]; | |
849 | ||
20a36e39 SE |
850 | extern struct event_constraint intel_ivb_pebs_event_constraints[]; |
851 | ||
3044318f AK |
852 | extern struct event_constraint intel_hsw_pebs_event_constraints[]; |
853 | ||
de0428a7 KW |
854 | struct event_constraint *intel_pebs_constraints(struct perf_event *event); |
855 | ||
856 | void intel_pmu_pebs_enable(struct perf_event *event); | |
857 | ||
858 | void intel_pmu_pebs_disable(struct perf_event *event); | |
859 | ||
860 | void intel_pmu_pebs_enable_all(void); | |
861 | ||
862 | void intel_pmu_pebs_disable_all(void); | |
863 | ||
864 | void intel_ds_init(void); | |
865 | ||
2a0ad3b3 YZ |
866 | void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in); |
867 | ||
de0428a7 KW |
868 | void intel_pmu_lbr_reset(void); |
869 | ||
870 | void intel_pmu_lbr_enable(struct perf_event *event); | |
871 | ||
872 | void intel_pmu_lbr_disable(struct perf_event *event); | |
873 | ||
1a78d937 | 874 | void intel_pmu_lbr_enable_all(bool pmi); |
de0428a7 KW |
875 | |
876 | void intel_pmu_lbr_disable_all(void); | |
877 | ||
878 | void intel_pmu_lbr_read(void); | |
879 | ||
880 | void intel_pmu_lbr_init_core(void); | |
881 | ||
882 | void intel_pmu_lbr_init_nhm(void); | |
883 | ||
884 | void intel_pmu_lbr_init_atom(void); | |
885 | ||
c5cc2cd9 SE |
886 | void intel_pmu_lbr_init_snb(void); |
887 | ||
e9d7f7cd YZ |
888 | void intel_pmu_lbr_init_hsw(void); |
889 | ||
60ce0fbd SE |
890 | int intel_pmu_setup_lbr_filter(struct perf_event *event); |
891 | ||
52ca9ced AS |
892 | void intel_pt_interrupt(void); |
893 | ||
8062382c AS |
894 | int intel_bts_interrupt(void); |
895 | ||
896 | void intel_bts_enable_local(void); | |
897 | ||
898 | void intel_bts_disable_local(void); | |
899 | ||
de0428a7 KW |
900 | int p4_pmu_init(void); |
901 | ||
902 | int p6_pmu_init(void); | |
903 | ||
e717bf4e VW |
904 | int knc_pmu_init(void); |
905 | ||
f20093ee SE |
906 | ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, |
907 | char *page); | |
908 | ||
b37609c3 SE |
909 | static inline int is_ht_workaround_enabled(void) |
910 | { | |
911 | return !!(x86_pmu.flags & PMU_FL_EXCL_ENABLED); | |
912 | } | |
de0428a7 KW |
913 | #else /* CONFIG_CPU_SUP_INTEL */ |
914 | ||
915 | static inline void reserve_ds_buffers(void) | |
916 | { | |
917 | } | |
918 | ||
919 | static inline void release_ds_buffers(void) | |
920 | { | |
921 | } | |
922 | ||
923 | static inline int intel_pmu_init(void) | |
924 | { | |
925 | return 0; | |
926 | } | |
927 | ||
928 | static inline struct intel_shared_regs *allocate_shared_regs(int cpu) | |
929 | { | |
930 | return NULL; | |
931 | } | |
932 | ||
933 | #endif /* CONFIG_CPU_SUP_INTEL */ |