Commit | Line | Data |
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de0428a7 KW |
1 | /* |
2 | * Performance events x86 architecture header | |
3 | * | |
4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> | |
5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> | |
9 | * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> | |
10 | * Copyright (C) 2009 Google, Inc., Stephane Eranian | |
11 | * | |
12 | * For licencing details see kernel-base/COPYING | |
13 | */ | |
14 | ||
15 | #include <linux/perf_event.h> | |
16 | ||
1c2ac3fd PZ |
17 | #if 0 |
18 | #undef wrmsrl | |
19 | #define wrmsrl(msr, val) \ | |
20 | do { \ | |
21 | unsigned int _msr = (msr); \ | |
22 | u64 _val = (val); \ | |
23 | trace_printk("wrmsrl(%x, %Lx)\n", (unsigned int)(_msr), \ | |
24 | (unsigned long long)(_val)); \ | |
25 | native_write_msr((_msr), (u32)(_val), (u32)(_val >> 32)); \ | |
26 | } while (0) | |
27 | #endif | |
28 | ||
de0428a7 KW |
29 | /* |
30 | * | NHM/WSM | SNB | | |
31 | * register ------------------------------- | |
32 | * | HT | no HT | HT | no HT | | |
33 | *----------------------------------------- | |
34 | * offcore | core | core | cpu | core | | |
35 | * lbr_sel | core | core | cpu | core | | |
36 | * ld_lat | cpu | core | cpu | core | | |
37 | *----------------------------------------- | |
38 | * | |
39 | * Given that there is a small number of shared regs, | |
40 | * we can pre-allocate their slot in the per-cpu | |
41 | * per-core reg tables. | |
42 | */ | |
43 | enum extra_reg_type { | |
44 | EXTRA_REG_NONE = -1, /* not used */ | |
45 | ||
46 | EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */ | |
47 | EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */ | |
b36817e8 | 48 | EXTRA_REG_LBR = 2, /* lbr_select */ |
f20093ee | 49 | EXTRA_REG_LDLAT = 3, /* ld_lat_threshold */ |
de0428a7 KW |
50 | |
51 | EXTRA_REG_MAX /* number of entries needed */ | |
52 | }; | |
53 | ||
54 | struct event_constraint { | |
55 | union { | |
56 | unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
57 | u64 idxmsk64; | |
58 | }; | |
59 | u64 code; | |
60 | u64 cmask; | |
61 | int weight; | |
bc1738f6 | 62 | int overlap; |
9fac2cf3 | 63 | int flags; |
de0428a7 | 64 | }; |
f20093ee | 65 | /* |
2f7f73a5 | 66 | * struct hw_perf_event.flags flags |
f20093ee SE |
67 | */ |
68 | #define PERF_X86_EVENT_PEBS_LDLAT 0x1 /* ld+ldlat data address sampling */ | |
9ad64c0f | 69 | #define PERF_X86_EVENT_PEBS_ST 0x2 /* st data address sampling */ |
86a04461 | 70 | #define PERF_X86_EVENT_PEBS_ST_HSW 0x4 /* haswell style datala, store */ |
2f7f73a5 | 71 | #define PERF_X86_EVENT_COMMITTED 0x8 /* event passed commit_txn */ |
86a04461 AK |
72 | #define PERF_X86_EVENT_PEBS_LD_HSW 0x10 /* haswell style datala, load */ |
73 | #define PERF_X86_EVENT_PEBS_NA_HSW 0x20 /* haswell style datala, unknown */ | |
7911d3f7 AL |
74 | #define PERF_X86_EVENT_RDPMC_ALLOWED 0x40 /* grant rdpmc permission */ |
75 | ||
de0428a7 KW |
76 | |
77 | struct amd_nb { | |
78 | int nb_id; /* NorthBridge id */ | |
79 | int refcnt; /* reference count */ | |
80 | struct perf_event *owners[X86_PMC_IDX_MAX]; | |
81 | struct event_constraint event_constraints[X86_PMC_IDX_MAX]; | |
82 | }; | |
83 | ||
84 | /* The maximal number of PEBS events: */ | |
70ab7003 | 85 | #define MAX_PEBS_EVENTS 8 |
de0428a7 KW |
86 | |
87 | /* | |
88 | * A debug store configuration. | |
89 | * | |
90 | * We only support architectures that use 64bit fields. | |
91 | */ | |
92 | struct debug_store { | |
93 | u64 bts_buffer_base; | |
94 | u64 bts_index; | |
95 | u64 bts_absolute_maximum; | |
96 | u64 bts_interrupt_threshold; | |
97 | u64 pebs_buffer_base; | |
98 | u64 pebs_index; | |
99 | u64 pebs_absolute_maximum; | |
100 | u64 pebs_interrupt_threshold; | |
101 | u64 pebs_event_reset[MAX_PEBS_EVENTS]; | |
102 | }; | |
103 | ||
104 | /* | |
105 | * Per register state. | |
106 | */ | |
107 | struct er_account { | |
108 | raw_spinlock_t lock; /* per-core: protect structure */ | |
109 | u64 config; /* extra MSR config */ | |
110 | u64 reg; /* extra MSR number */ | |
111 | atomic_t ref; /* reference count */ | |
112 | }; | |
113 | ||
114 | /* | |
115 | * Per core/cpu state | |
116 | * | |
117 | * Used to coordinate shared registers between HT threads or | |
118 | * among events on a single PMU. | |
119 | */ | |
120 | struct intel_shared_regs { | |
121 | struct er_account regs[EXTRA_REG_MAX]; | |
122 | int refcnt; /* per-core: #HT threads */ | |
123 | unsigned core_id; /* per-core: core id */ | |
124 | }; | |
125 | ||
126 | #define MAX_LBR_ENTRIES 16 | |
127 | ||
90413464 SE |
128 | enum { |
129 | X86_PERF_KFREE_SHARED = 0, | |
130 | X86_PERF_KFREE_EXCL = 1, | |
131 | X86_PERF_KFREE_MAX | |
132 | }; | |
133 | ||
de0428a7 KW |
134 | struct cpu_hw_events { |
135 | /* | |
136 | * Generic x86 PMC bits | |
137 | */ | |
138 | struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */ | |
139 | unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
140 | unsigned long running[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
141 | int enabled; | |
142 | ||
c347a2f1 PZ |
143 | int n_events; /* the # of events in the below arrays */ |
144 | int n_added; /* the # last events in the below arrays; | |
145 | they've never been enabled yet */ | |
146 | int n_txn; /* the # last events in the below arrays; | |
147 | added in the current transaction */ | |
de0428a7 KW |
148 | int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */ |
149 | u64 tags[X86_PMC_IDX_MAX]; | |
150 | struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */ | |
151 | ||
152 | unsigned int group_flag; | |
5a425294 | 153 | int is_fake; |
de0428a7 KW |
154 | |
155 | /* | |
156 | * Intel DebugStore bits | |
157 | */ | |
158 | struct debug_store *ds; | |
159 | u64 pebs_enabled; | |
160 | ||
161 | /* | |
162 | * Intel LBR bits | |
163 | */ | |
164 | int lbr_users; | |
165 | void *lbr_context; | |
166 | struct perf_branch_stack lbr_stack; | |
167 | struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES]; | |
b36817e8 | 168 | struct er_account *lbr_sel; |
3e702ff6 | 169 | u64 br_sel; |
de0428a7 | 170 | |
144d31e6 GN |
171 | /* |
172 | * Intel host/guest exclude bits | |
173 | */ | |
174 | u64 intel_ctrl_guest_mask; | |
175 | u64 intel_ctrl_host_mask; | |
176 | struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX]; | |
177 | ||
2b9e344d PZ |
178 | /* |
179 | * Intel checkpoint mask | |
180 | */ | |
181 | u64 intel_cp_status; | |
182 | ||
de0428a7 KW |
183 | /* |
184 | * manage shared (per-core, per-cpu) registers | |
185 | * used on Intel NHM/WSM/SNB | |
186 | */ | |
187 | struct intel_shared_regs *shared_regs; | |
188 | ||
189 | /* | |
190 | * AMD specific bits | |
191 | */ | |
1018faa6 JR |
192 | struct amd_nb *amd_nb; |
193 | /* Inverted mask of bits to clear in the perf_ctr ctrl registers */ | |
194 | u64 perf_ctr_virt_mask; | |
de0428a7 | 195 | |
90413464 | 196 | void *kfree_on_online[X86_PERF_KFREE_MAX]; |
de0428a7 KW |
197 | }; |
198 | ||
9fac2cf3 | 199 | #define __EVENT_CONSTRAINT(c, n, m, w, o, f) {\ |
de0428a7 KW |
200 | { .idxmsk64 = (n) }, \ |
201 | .code = (c), \ | |
202 | .cmask = (m), \ | |
203 | .weight = (w), \ | |
bc1738f6 | 204 | .overlap = (o), \ |
9fac2cf3 | 205 | .flags = f, \ |
de0428a7 KW |
206 | } |
207 | ||
208 | #define EVENT_CONSTRAINT(c, n, m) \ | |
9fac2cf3 | 209 | __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0) |
bc1738f6 RR |
210 | |
211 | /* | |
212 | * The overlap flag marks event constraints with overlapping counter | |
213 | * masks. This is the case if the counter mask of such an event is not | |
214 | * a subset of any other counter mask of a constraint with an equal or | |
215 | * higher weight, e.g.: | |
216 | * | |
217 | * c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0); | |
218 | * c_another1 = EVENT_CONSTRAINT(0, 0x07, 0); | |
219 | * c_another2 = EVENT_CONSTRAINT(0, 0x38, 0); | |
220 | * | |
221 | * The event scheduler may not select the correct counter in the first | |
222 | * cycle because it needs to know which subsequent events will be | |
223 | * scheduled. It may fail to schedule the events then. So we set the | |
224 | * overlap flag for such constraints to give the scheduler a hint which | |
225 | * events to select for counter rescheduling. | |
226 | * | |
227 | * Care must be taken as the rescheduling algorithm is O(n!) which | |
228 | * will increase scheduling cycles for an over-commited system | |
229 | * dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros | |
230 | * and its counter masks must be kept at a minimum. | |
231 | */ | |
232 | #define EVENT_CONSTRAINT_OVERLAP(c, n, m) \ | |
9fac2cf3 | 233 | __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1, 0) |
de0428a7 KW |
234 | |
235 | /* | |
236 | * Constraint on the Event code. | |
237 | */ | |
238 | #define INTEL_EVENT_CONSTRAINT(c, n) \ | |
239 | EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT) | |
240 | ||
241 | /* | |
242 | * Constraint on the Event code + UMask + fixed-mask | |
243 | * | |
244 | * filter mask to validate fixed counter events. | |
245 | * the following filters disqualify for fixed counters: | |
246 | * - inv | |
247 | * - edge | |
248 | * - cnt-mask | |
3a632cb2 AK |
249 | * - in_tx |
250 | * - in_tx_checkpointed | |
de0428a7 KW |
251 | * The other filters are supported by fixed counters. |
252 | * The any-thread option is supported starting with v3. | |
253 | */ | |
3a632cb2 | 254 | #define FIXED_EVENT_FLAGS (X86_RAW_EVENT_MASK|HSW_IN_TX|HSW_IN_TX_CHECKPOINTED) |
de0428a7 | 255 | #define FIXED_EVENT_CONSTRAINT(c, n) \ |
3a632cb2 | 256 | EVENT_CONSTRAINT(c, (1ULL << (32+n)), FIXED_EVENT_FLAGS) |
de0428a7 KW |
257 | |
258 | /* | |
259 | * Constraint on the Event code + UMask | |
260 | */ | |
261 | #define INTEL_UEVENT_CONSTRAINT(c, n) \ | |
262 | EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK) | |
263 | ||
7550ddff AK |
264 | /* Like UEVENT_CONSTRAINT, but match flags too */ |
265 | #define INTEL_FLAGS_UEVENT_CONSTRAINT(c, n) \ | |
266 | EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS) | |
267 | ||
f20093ee | 268 | #define INTEL_PLD_CONSTRAINT(c, n) \ |
86a04461 | 269 | __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ |
f20093ee SE |
270 | HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LDLAT) |
271 | ||
9ad64c0f | 272 | #define INTEL_PST_CONSTRAINT(c, n) \ |
86a04461 | 273 | __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ |
9ad64c0f SE |
274 | HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST) |
275 | ||
86a04461 AK |
276 | /* Event constraint, but match on all event flags too. */ |
277 | #define INTEL_FLAGS_EVENT_CONSTRAINT(c, n) \ | |
278 | EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS) | |
279 | ||
280 | /* Check only flags, but allow all event/umask */ | |
281 | #define INTEL_ALL_EVENT_CONSTRAINT(code, n) \ | |
282 | EVENT_CONSTRAINT(code, n, X86_ALL_EVENT_FLAGS) | |
283 | ||
284 | /* Check flags and event code, and set the HSW store flag */ | |
285 | #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_ST(code, n) \ | |
286 | __EVENT_CONSTRAINT(code, n, \ | |
287 | ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ | |
288 | HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW) | |
289 | ||
290 | /* Check flags and event code, and set the HSW load flag */ | |
291 | #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(code, n) \ | |
292 | __EVENT_CONSTRAINT(code, n, \ | |
293 | ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ | |
294 | HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) | |
295 | ||
296 | /* Check flags and event code/umask, and set the HSW store flag */ | |
297 | #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(code, n) \ | |
298 | __EVENT_CONSTRAINT(code, n, \ | |
299 | INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ | |
f9134f36 AK |
300 | HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW) |
301 | ||
86a04461 AK |
302 | /* Check flags and event code/umask, and set the HSW load flag */ |
303 | #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(code, n) \ | |
304 | __EVENT_CONSTRAINT(code, n, \ | |
305 | INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ | |
306 | HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) | |
307 | ||
308 | /* Check flags and event code/umask, and set the HSW N/A flag */ | |
309 | #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(code, n) \ | |
310 | __EVENT_CONSTRAINT(code, n, \ | |
311 | INTEL_ARCH_EVENT_MASK|INTEL_ARCH_EVENT_MASK, \ | |
312 | HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_NA_HSW) | |
313 | ||
314 | ||
cf30d52e MD |
315 | /* |
316 | * We define the end marker as having a weight of -1 | |
317 | * to enable blacklisting of events using a counter bitmask | |
318 | * of zero and thus a weight of zero. | |
319 | * The end marker has a weight that cannot possibly be | |
320 | * obtained from counting the bits in the bitmask. | |
321 | */ | |
322 | #define EVENT_CONSTRAINT_END { .weight = -1 } | |
de0428a7 | 323 | |
cf30d52e MD |
324 | /* |
325 | * Check for end marker with weight == -1 | |
326 | */ | |
de0428a7 | 327 | #define for_each_event_constraint(e, c) \ |
cf30d52e | 328 | for ((e) = (c); (e)->weight != -1; (e)++) |
de0428a7 KW |
329 | |
330 | /* | |
331 | * Extra registers for specific events. | |
332 | * | |
333 | * Some events need large masks and require external MSRs. | |
334 | * Those extra MSRs end up being shared for all events on | |
335 | * a PMU and sometimes between PMU of sibling HT threads. | |
336 | * In either case, the kernel needs to handle conflicting | |
337 | * accesses to those extra, shared, regs. The data structure | |
338 | * to manage those registers is stored in cpu_hw_event. | |
339 | */ | |
340 | struct extra_reg { | |
341 | unsigned int event; | |
342 | unsigned int msr; | |
343 | u64 config_mask; | |
344 | u64 valid_mask; | |
345 | int idx; /* per_xxx->regs[] reg index */ | |
338b522c | 346 | bool extra_msr_access; |
de0428a7 KW |
347 | }; |
348 | ||
349 | #define EVENT_EXTRA_REG(e, ms, m, vm, i) { \ | |
338b522c KL |
350 | .event = (e), \ |
351 | .msr = (ms), \ | |
352 | .config_mask = (m), \ | |
353 | .valid_mask = (vm), \ | |
354 | .idx = EXTRA_REG_##i, \ | |
355 | .extra_msr_access = true, \ | |
de0428a7 KW |
356 | } |
357 | ||
358 | #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \ | |
359 | EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx) | |
360 | ||
f20093ee SE |
361 | #define INTEL_UEVENT_EXTRA_REG(event, msr, vm, idx) \ |
362 | EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \ | |
363 | ARCH_PERFMON_EVENTSEL_UMASK, vm, idx) | |
364 | ||
365 | #define INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(c) \ | |
366 | INTEL_UEVENT_EXTRA_REG(c, \ | |
367 | MSR_PEBS_LD_LAT_THRESHOLD, \ | |
368 | 0xffff, \ | |
369 | LDLAT) | |
370 | ||
de0428a7 KW |
371 | #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0) |
372 | ||
373 | union perf_capabilities { | |
374 | struct { | |
375 | u64 lbr_format:6; | |
376 | u64 pebs_trap:1; | |
377 | u64 pebs_arch_reg:1; | |
378 | u64 pebs_format:4; | |
379 | u64 smm_freeze:1; | |
069e0c3c AK |
380 | /* |
381 | * PMU supports separate counter range for writing | |
382 | * values > 32bit. | |
383 | */ | |
384 | u64 full_width_write:1; | |
de0428a7 KW |
385 | }; |
386 | u64 capabilities; | |
387 | }; | |
388 | ||
c1d6f42f PZ |
389 | struct x86_pmu_quirk { |
390 | struct x86_pmu_quirk *next; | |
391 | void (*func)(void); | |
392 | }; | |
393 | ||
f9b4eeb8 PZ |
394 | union x86_pmu_config { |
395 | struct { | |
396 | u64 event:8, | |
397 | umask:8, | |
398 | usr:1, | |
399 | os:1, | |
400 | edge:1, | |
401 | pc:1, | |
402 | interrupt:1, | |
403 | __reserved1:1, | |
404 | en:1, | |
405 | inv:1, | |
406 | cmask:8, | |
407 | event2:4, | |
408 | __reserved2:4, | |
409 | go:1, | |
410 | ho:1; | |
411 | } bits; | |
412 | u64 value; | |
413 | }; | |
414 | ||
415 | #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value | |
416 | ||
48070342 AS |
417 | enum { |
418 | x86_lbr_exclusive_lbr, | |
8062382c | 419 | x86_lbr_exclusive_bts, |
48070342 AS |
420 | x86_lbr_exclusive_pt, |
421 | x86_lbr_exclusive_max, | |
422 | }; | |
423 | ||
de0428a7 KW |
424 | /* |
425 | * struct x86_pmu - generic x86 pmu | |
426 | */ | |
427 | struct x86_pmu { | |
428 | /* | |
429 | * Generic x86 PMC bits | |
430 | */ | |
431 | const char *name; | |
432 | int version; | |
433 | int (*handle_irq)(struct pt_regs *); | |
434 | void (*disable_all)(void); | |
435 | void (*enable_all)(int added); | |
436 | void (*enable)(struct perf_event *); | |
437 | void (*disable)(struct perf_event *); | |
438 | int (*hw_config)(struct perf_event *event); | |
439 | int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign); | |
440 | unsigned eventsel; | |
441 | unsigned perfctr; | |
4c1fd17a | 442 | int (*addr_offset)(int index, bool eventsel); |
0fbdad07 | 443 | int (*rdpmc_index)(int index); |
de0428a7 KW |
444 | u64 (*event_map)(int); |
445 | int max_events; | |
446 | int num_counters; | |
447 | int num_counters_fixed; | |
448 | int cntval_bits; | |
449 | u64 cntval_mask; | |
ffb871bc GN |
450 | union { |
451 | unsigned long events_maskl; | |
452 | unsigned long events_mask[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT)]; | |
453 | }; | |
454 | int events_mask_len; | |
de0428a7 KW |
455 | int apic; |
456 | u64 max_period; | |
457 | struct event_constraint * | |
458 | (*get_event_constraints)(struct cpu_hw_events *cpuc, | |
459 | struct perf_event *event); | |
460 | ||
461 | void (*put_event_constraints)(struct cpu_hw_events *cpuc, | |
462 | struct perf_event *event); | |
c5362c0c MD |
463 | |
464 | void (*commit_scheduling)(struct cpu_hw_events *cpuc, | |
465 | struct perf_event *event, | |
466 | int cntr); | |
467 | ||
468 | void (*start_scheduling)(struct cpu_hw_events *cpuc); | |
469 | ||
470 | void (*stop_scheduling)(struct cpu_hw_events *cpuc); | |
471 | ||
de0428a7 | 472 | struct event_constraint *event_constraints; |
c1d6f42f | 473 | struct x86_pmu_quirk *quirks; |
de0428a7 | 474 | int perfctr_second_write; |
72db5596 | 475 | bool late_ack; |
294fe0f5 | 476 | unsigned (*limit_period)(struct perf_event *event, unsigned l); |
de0428a7 | 477 | |
0c9d42ed PZ |
478 | /* |
479 | * sysfs attrs | |
480 | */ | |
e97df763 | 481 | int attr_rdpmc_broken; |
0c9d42ed | 482 | int attr_rdpmc; |
641cc938 | 483 | struct attribute **format_attrs; |
f20093ee | 484 | struct attribute **event_attrs; |
0c9d42ed | 485 | |
a4747393 | 486 | ssize_t (*events_sysfs_show)(char *page, u64 config); |
1a6461b1 | 487 | struct attribute **cpu_events; |
a4747393 | 488 | |
0c9d42ed PZ |
489 | /* |
490 | * CPU Hotplug hooks | |
491 | */ | |
de0428a7 KW |
492 | int (*cpu_prepare)(int cpu); |
493 | void (*cpu_starting)(int cpu); | |
494 | void (*cpu_dying)(int cpu); | |
495 | void (*cpu_dead)(int cpu); | |
c93dc84c PZ |
496 | |
497 | void (*check_microcode)(void); | |
ba532500 YZ |
498 | void (*sched_task)(struct perf_event_context *ctx, |
499 | bool sched_in); | |
de0428a7 KW |
500 | |
501 | /* | |
502 | * Intel Arch Perfmon v2+ | |
503 | */ | |
504 | u64 intel_ctrl; | |
505 | union perf_capabilities intel_cap; | |
506 | ||
507 | /* | |
508 | * Intel DebugStore bits | |
509 | */ | |
597ed953 | 510 | unsigned int bts :1, |
3e0091e2 PZ |
511 | bts_active :1, |
512 | pebs :1, | |
513 | pebs_active :1, | |
514 | pebs_broken :1; | |
de0428a7 KW |
515 | int pebs_record_size; |
516 | void (*drain_pebs)(struct pt_regs *regs); | |
517 | struct event_constraint *pebs_constraints; | |
0780c927 | 518 | void (*pebs_aliases)(struct perf_event *event); |
70ab7003 | 519 | int max_pebs_events; |
de0428a7 KW |
520 | |
521 | /* | |
522 | * Intel LBR | |
523 | */ | |
524 | unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */ | |
525 | int lbr_nr; /* hardware stack size */ | |
b36817e8 SE |
526 | u64 lbr_sel_mask; /* LBR_SELECT valid bits */ |
527 | const int *lbr_sel_map; /* lbr_select mappings */ | |
b7af41a1 | 528 | bool lbr_double_abort; /* duplicated lbr aborts */ |
de0428a7 | 529 | |
48070342 AS |
530 | /* |
531 | * Intel PT/LBR/BTS are exclusive | |
532 | */ | |
533 | atomic_t lbr_exclusive[x86_lbr_exclusive_max]; | |
534 | ||
de0428a7 KW |
535 | /* |
536 | * Extra registers for events | |
537 | */ | |
538 | struct extra_reg *extra_regs; | |
9a5e3fb5 | 539 | unsigned int flags; |
144d31e6 GN |
540 | |
541 | /* | |
542 | * Intel host/guest support (KVM) | |
543 | */ | |
544 | struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr); | |
de0428a7 KW |
545 | }; |
546 | ||
e18bf526 YZ |
547 | struct x86_perf_task_context { |
548 | u64 lbr_from[MAX_LBR_ENTRIES]; | |
549 | u64 lbr_to[MAX_LBR_ENTRIES]; | |
550 | int lbr_callstack_users; | |
551 | int lbr_stack_state; | |
552 | }; | |
553 | ||
c1d6f42f PZ |
554 | #define x86_add_quirk(func_) \ |
555 | do { \ | |
556 | static struct x86_pmu_quirk __quirk __initdata = { \ | |
557 | .func = func_, \ | |
558 | }; \ | |
559 | __quirk.next = x86_pmu.quirks; \ | |
560 | x86_pmu.quirks = &__quirk; \ | |
561 | } while (0) | |
562 | ||
9a5e3fb5 SE |
563 | /* |
564 | * x86_pmu flags | |
565 | */ | |
566 | #define PMU_FL_NO_HT_SHARING 0x1 /* no hyper-threading resource sharing */ | |
567 | #define PMU_FL_HAS_RSP_1 0x2 /* has 2 equivalent offcore_rsp regs */ | |
de0428a7 | 568 | |
3a54aaa0 SE |
569 | #define EVENT_VAR(_id) event_attr_##_id |
570 | #define EVENT_PTR(_id) &event_attr_##_id.attr.attr | |
571 | ||
572 | #define EVENT_ATTR(_name, _id) \ | |
573 | static struct perf_pmu_events_attr EVENT_VAR(_id) = { \ | |
574 | .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \ | |
575 | .id = PERF_COUNT_HW_##_id, \ | |
576 | .event_str = NULL, \ | |
577 | }; | |
578 | ||
579 | #define EVENT_ATTR_STR(_name, v, str) \ | |
580 | static struct perf_pmu_events_attr event_attr_##v = { \ | |
581 | .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \ | |
582 | .id = 0, \ | |
583 | .event_str = str, \ | |
584 | }; | |
585 | ||
de0428a7 KW |
586 | extern struct x86_pmu x86_pmu __read_mostly; |
587 | ||
e9d7f7cd YZ |
588 | static inline bool x86_pmu_has_lbr_callstack(void) |
589 | { | |
590 | return x86_pmu.lbr_sel_map && | |
591 | x86_pmu.lbr_sel_map[PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] > 0; | |
592 | } | |
593 | ||
de0428a7 KW |
594 | DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events); |
595 | ||
596 | int x86_perf_event_set_period(struct perf_event *event); | |
597 | ||
598 | /* | |
599 | * Generalized hw caching related hw_event table, filled | |
600 | * in on a per model basis. A value of 0 means | |
601 | * 'not supported', -1 means 'hw_event makes no sense on | |
602 | * this CPU', any other value means the raw hw_event | |
603 | * ID. | |
604 | */ | |
605 | ||
606 | #define C(x) PERF_COUNT_HW_CACHE_##x | |
607 | ||
608 | extern u64 __read_mostly hw_cache_event_ids | |
609 | [PERF_COUNT_HW_CACHE_MAX] | |
610 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
611 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
612 | extern u64 __read_mostly hw_cache_extra_regs | |
613 | [PERF_COUNT_HW_CACHE_MAX] | |
614 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
615 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
616 | ||
617 | u64 x86_perf_event_update(struct perf_event *event); | |
618 | ||
de0428a7 KW |
619 | static inline unsigned int x86_pmu_config_addr(int index) |
620 | { | |
4c1fd17a JS |
621 | return x86_pmu.eventsel + (x86_pmu.addr_offset ? |
622 | x86_pmu.addr_offset(index, true) : index); | |
de0428a7 KW |
623 | } |
624 | ||
625 | static inline unsigned int x86_pmu_event_addr(int index) | |
626 | { | |
4c1fd17a JS |
627 | return x86_pmu.perfctr + (x86_pmu.addr_offset ? |
628 | x86_pmu.addr_offset(index, false) : index); | |
de0428a7 KW |
629 | } |
630 | ||
0fbdad07 JS |
631 | static inline int x86_pmu_rdpmc_index(int index) |
632 | { | |
633 | return x86_pmu.rdpmc_index ? x86_pmu.rdpmc_index(index) : index; | |
634 | } | |
635 | ||
48070342 AS |
636 | int x86_add_exclusive(unsigned int what); |
637 | ||
638 | void x86_del_exclusive(unsigned int what); | |
639 | ||
640 | void hw_perf_lbr_event_destroy(struct perf_event *event); | |
641 | ||
de0428a7 KW |
642 | int x86_setup_perfctr(struct perf_event *event); |
643 | ||
644 | int x86_pmu_hw_config(struct perf_event *event); | |
645 | ||
646 | void x86_pmu_disable_all(void); | |
647 | ||
648 | static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, | |
649 | u64 enable_mask) | |
650 | { | |
1018faa6 JR |
651 | u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask); |
652 | ||
de0428a7 KW |
653 | if (hwc->extra_reg.reg) |
654 | wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config); | |
1018faa6 | 655 | wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask); |
de0428a7 KW |
656 | } |
657 | ||
658 | void x86_pmu_enable_all(int added); | |
659 | ||
43b45780 | 660 | int perf_assign_events(struct perf_event **events, int n, |
4b4969b1 | 661 | int wmin, int wmax, int *assign); |
de0428a7 KW |
662 | int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign); |
663 | ||
664 | void x86_pmu_stop(struct perf_event *event, int flags); | |
665 | ||
666 | static inline void x86_pmu_disable_event(struct perf_event *event) | |
667 | { | |
668 | struct hw_perf_event *hwc = &event->hw; | |
669 | ||
670 | wrmsrl(hwc->config_base, hwc->config); | |
671 | } | |
672 | ||
673 | void x86_pmu_enable_event(struct perf_event *event); | |
674 | ||
675 | int x86_pmu_handle_irq(struct pt_regs *regs); | |
676 | ||
677 | extern struct event_constraint emptyconstraint; | |
678 | ||
679 | extern struct event_constraint unconstrained; | |
680 | ||
3e702ff6 SE |
681 | static inline bool kernel_ip(unsigned long ip) |
682 | { | |
683 | #ifdef CONFIG_X86_32 | |
684 | return ip > PAGE_OFFSET; | |
685 | #else | |
686 | return (long)ip < 0; | |
687 | #endif | |
688 | } | |
689 | ||
d07bdfd3 PZ |
690 | /* |
691 | * Not all PMUs provide the right context information to place the reported IP | |
692 | * into full context. Specifically segment registers are typically not | |
693 | * supplied. | |
694 | * | |
695 | * Assuming the address is a linear address (it is for IBS), we fake the CS and | |
696 | * vm86 mode using the known zero-based code segment and 'fix up' the registers | |
697 | * to reflect this. | |
698 | * | |
699 | * Intel PEBS/LBR appear to typically provide the effective address, nothing | |
700 | * much we can do about that but pray and treat it like a linear address. | |
701 | */ | |
702 | static inline void set_linear_ip(struct pt_regs *regs, unsigned long ip) | |
703 | { | |
704 | regs->cs = kernel_ip(ip) ? __KERNEL_CS : __USER_CS; | |
705 | if (regs->flags & X86_VM_MASK) | |
706 | regs->flags ^= (PERF_EFLAGS_VM | X86_VM_MASK); | |
707 | regs->ip = ip; | |
708 | } | |
709 | ||
0bf79d44 | 710 | ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event); |
20550a43 | 711 | ssize_t intel_event_sysfs_show(char *page, u64 config); |
43c032fe | 712 | |
de0428a7 KW |
713 | #ifdef CONFIG_CPU_SUP_AMD |
714 | ||
715 | int amd_pmu_init(void); | |
716 | ||
717 | #else /* CONFIG_CPU_SUP_AMD */ | |
718 | ||
719 | static inline int amd_pmu_init(void) | |
720 | { | |
721 | return 0; | |
722 | } | |
723 | ||
724 | #endif /* CONFIG_CPU_SUP_AMD */ | |
725 | ||
726 | #ifdef CONFIG_CPU_SUP_INTEL | |
727 | ||
48070342 AS |
728 | static inline bool intel_pmu_needs_lbr_smpl(struct perf_event *event) |
729 | { | |
730 | /* user explicitly requested branch sampling */ | |
731 | if (has_branch_stack(event)) | |
732 | return true; | |
733 | ||
734 | /* implicit branch sampling to correct PEBS skid */ | |
735 | if (x86_pmu.intel_cap.pebs_trap && event->attr.precise_ip > 1 && | |
736 | x86_pmu.intel_cap.pebs_format < 2) | |
737 | return true; | |
738 | ||
739 | return false; | |
740 | } | |
741 | ||
742 | static inline bool intel_pmu_has_bts(struct perf_event *event) | |
743 | { | |
744 | if (event->attr.config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS && | |
745 | !event->attr.freq && event->hw.sample_period == 1) | |
746 | return true; | |
747 | ||
748 | return false; | |
749 | } | |
750 | ||
de0428a7 KW |
751 | int intel_pmu_save_and_restart(struct perf_event *event); |
752 | ||
753 | struct event_constraint * | |
754 | x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event); | |
755 | ||
756 | struct intel_shared_regs *allocate_shared_regs(int cpu); | |
757 | ||
758 | int intel_pmu_init(void); | |
759 | ||
760 | void init_debug_store_on_cpu(int cpu); | |
761 | ||
762 | void fini_debug_store_on_cpu(int cpu); | |
763 | ||
764 | void release_ds_buffers(void); | |
765 | ||
766 | void reserve_ds_buffers(void); | |
767 | ||
768 | extern struct event_constraint bts_constraint; | |
769 | ||
770 | void intel_pmu_enable_bts(u64 config); | |
771 | ||
772 | void intel_pmu_disable_bts(void); | |
773 | ||
774 | int intel_pmu_drain_bts_buffer(void); | |
775 | ||
776 | extern struct event_constraint intel_core2_pebs_event_constraints[]; | |
777 | ||
778 | extern struct event_constraint intel_atom_pebs_event_constraints[]; | |
779 | ||
1fa64180 YZ |
780 | extern struct event_constraint intel_slm_pebs_event_constraints[]; |
781 | ||
de0428a7 KW |
782 | extern struct event_constraint intel_nehalem_pebs_event_constraints[]; |
783 | ||
784 | extern struct event_constraint intel_westmere_pebs_event_constraints[]; | |
785 | ||
786 | extern struct event_constraint intel_snb_pebs_event_constraints[]; | |
787 | ||
20a36e39 SE |
788 | extern struct event_constraint intel_ivb_pebs_event_constraints[]; |
789 | ||
3044318f AK |
790 | extern struct event_constraint intel_hsw_pebs_event_constraints[]; |
791 | ||
de0428a7 KW |
792 | struct event_constraint *intel_pebs_constraints(struct perf_event *event); |
793 | ||
794 | void intel_pmu_pebs_enable(struct perf_event *event); | |
795 | ||
796 | void intel_pmu_pebs_disable(struct perf_event *event); | |
797 | ||
798 | void intel_pmu_pebs_enable_all(void); | |
799 | ||
800 | void intel_pmu_pebs_disable_all(void); | |
801 | ||
802 | void intel_ds_init(void); | |
803 | ||
2a0ad3b3 YZ |
804 | void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in); |
805 | ||
de0428a7 KW |
806 | void intel_pmu_lbr_reset(void); |
807 | ||
808 | void intel_pmu_lbr_enable(struct perf_event *event); | |
809 | ||
810 | void intel_pmu_lbr_disable(struct perf_event *event); | |
811 | ||
812 | void intel_pmu_lbr_enable_all(void); | |
813 | ||
814 | void intel_pmu_lbr_disable_all(void); | |
815 | ||
816 | void intel_pmu_lbr_read(void); | |
817 | ||
818 | void intel_pmu_lbr_init_core(void); | |
819 | ||
820 | void intel_pmu_lbr_init_nhm(void); | |
821 | ||
822 | void intel_pmu_lbr_init_atom(void); | |
823 | ||
c5cc2cd9 SE |
824 | void intel_pmu_lbr_init_snb(void); |
825 | ||
e9d7f7cd YZ |
826 | void intel_pmu_lbr_init_hsw(void); |
827 | ||
60ce0fbd SE |
828 | int intel_pmu_setup_lbr_filter(struct perf_event *event); |
829 | ||
52ca9ced AS |
830 | void intel_pt_interrupt(void); |
831 | ||
8062382c AS |
832 | int intel_bts_interrupt(void); |
833 | ||
834 | void intel_bts_enable_local(void); | |
835 | ||
836 | void intel_bts_disable_local(void); | |
837 | ||
de0428a7 KW |
838 | int p4_pmu_init(void); |
839 | ||
840 | int p6_pmu_init(void); | |
841 | ||
e717bf4e VW |
842 | int knc_pmu_init(void); |
843 | ||
f20093ee SE |
844 | ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, |
845 | char *page); | |
846 | ||
de0428a7 KW |
847 | #else /* CONFIG_CPU_SUP_INTEL */ |
848 | ||
849 | static inline void reserve_ds_buffers(void) | |
850 | { | |
851 | } | |
852 | ||
853 | static inline void release_ds_buffers(void) | |
854 | { | |
855 | } | |
856 | ||
857 | static inline int intel_pmu_init(void) | |
858 | { | |
859 | return 0; | |
860 | } | |
861 | ||
862 | static inline struct intel_shared_regs *allocate_shared_regs(int cpu) | |
863 | { | |
864 | return NULL; | |
865 | } | |
866 | ||
867 | #endif /* CONFIG_CPU_SUP_INTEL */ |