Commit | Line | Data |
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de0428a7 KW |
1 | #include <linux/bitops.h> |
2 | #include <linux/types.h> | |
3 | #include <linux/slab.h> | |
ca037701 | 4 | |
de0428a7 | 5 | #include <asm/perf_event.h> |
3e702ff6 | 6 | #include <asm/insn.h> |
de0428a7 KW |
7 | |
8 | #include "perf_event.h" | |
ca037701 PZ |
9 | |
10 | /* The size of a BTS record in bytes: */ | |
11 | #define BTS_RECORD_SIZE 24 | |
12 | ||
13 | #define BTS_BUFFER_SIZE (PAGE_SIZE << 4) | |
14 | #define PEBS_BUFFER_SIZE PAGE_SIZE | |
9536c8d2 | 15 | #define PEBS_FIXUP_SIZE PAGE_SIZE |
ca037701 PZ |
16 | |
17 | /* | |
18 | * pebs_record_32 for p4 and core not supported | |
19 | ||
20 | struct pebs_record_32 { | |
21 | u32 flags, ip; | |
22 | u32 ax, bc, cx, dx; | |
23 | u32 si, di, bp, sp; | |
24 | }; | |
25 | ||
26 | */ | |
27 | ||
f20093ee SE |
28 | union intel_x86_pebs_dse { |
29 | u64 val; | |
30 | struct { | |
31 | unsigned int ld_dse:4; | |
32 | unsigned int ld_stlb_miss:1; | |
33 | unsigned int ld_locked:1; | |
34 | unsigned int ld_reserved:26; | |
35 | }; | |
36 | struct { | |
37 | unsigned int st_l1d_hit:1; | |
38 | unsigned int st_reserved1:3; | |
39 | unsigned int st_stlb_miss:1; | |
40 | unsigned int st_locked:1; | |
41 | unsigned int st_reserved2:26; | |
42 | }; | |
43 | }; | |
44 | ||
45 | ||
46 | /* | |
47 | * Map PEBS Load Latency Data Source encodings to generic | |
48 | * memory data source information | |
49 | */ | |
50 | #define P(a, b) PERF_MEM_S(a, b) | |
51 | #define OP_LH (P(OP, LOAD) | P(LVL, HIT)) | |
52 | #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS)) | |
53 | ||
54 | static const u64 pebs_data_source[] = { | |
55 | P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | P(SNOOP, NA),/* 0x00:ukn L3 */ | |
56 | OP_LH | P(LVL, L1) | P(SNOOP, NONE), /* 0x01: L1 local */ | |
57 | OP_LH | P(LVL, LFB) | P(SNOOP, NONE), /* 0x02: LFB hit */ | |
58 | OP_LH | P(LVL, L2) | P(SNOOP, NONE), /* 0x03: L2 hit */ | |
59 | OP_LH | P(LVL, L3) | P(SNOOP, NONE), /* 0x04: L3 hit */ | |
60 | OP_LH | P(LVL, L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */ | |
61 | OP_LH | P(LVL, L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */ | |
62 | OP_LH | P(LVL, L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */ | |
63 | OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */ | |
64 | OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/ | |
65 | OP_LH | P(LVL, LOC_RAM) | P(SNOOP, HIT), /* 0x0a: L3 miss, shared */ | |
66 | OP_LH | P(LVL, REM_RAM1) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */ | |
67 | OP_LH | P(LVL, LOC_RAM) | SNOOP_NONE_MISS,/* 0x0c: L3 miss, excl */ | |
68 | OP_LH | P(LVL, REM_RAM1) | SNOOP_NONE_MISS,/* 0x0d: L3 miss, excl */ | |
69 | OP_LH | P(LVL, IO) | P(SNOOP, NONE), /* 0x0e: I/O */ | |
70 | OP_LH | P(LVL, UNC) | P(SNOOP, NONE), /* 0x0f: uncached */ | |
71 | }; | |
72 | ||
9ad64c0f SE |
73 | static u64 precise_store_data(u64 status) |
74 | { | |
75 | union intel_x86_pebs_dse dse; | |
76 | u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2); | |
77 | ||
78 | dse.val = status; | |
79 | ||
80 | /* | |
81 | * bit 4: TLB access | |
82 | * 1 = stored missed 2nd level TLB | |
83 | * | |
84 | * so it either hit the walker or the OS | |
85 | * otherwise hit 2nd level TLB | |
86 | */ | |
87 | if (dse.st_stlb_miss) | |
88 | val |= P(TLB, MISS); | |
89 | else | |
90 | val |= P(TLB, HIT); | |
91 | ||
92 | /* | |
93 | * bit 0: hit L1 data cache | |
94 | * if not set, then all we know is that | |
95 | * it missed L1D | |
96 | */ | |
97 | if (dse.st_l1d_hit) | |
98 | val |= P(LVL, HIT); | |
99 | else | |
100 | val |= P(LVL, MISS); | |
101 | ||
102 | /* | |
103 | * bit 5: Locked prefix | |
104 | */ | |
105 | if (dse.st_locked) | |
106 | val |= P(LOCK, LOCKED); | |
107 | ||
108 | return val; | |
109 | } | |
110 | ||
c8aab2e0 | 111 | static u64 precise_datala_hsw(struct perf_event *event, u64 status) |
f9134f36 AK |
112 | { |
113 | union perf_mem_data_src dse; | |
114 | ||
770eee1f SE |
115 | dse.val = PERF_MEM_NA; |
116 | ||
117 | if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) | |
118 | dse.mem_op = PERF_MEM_OP_STORE; | |
119 | else if (event->hw.flags & PERF_X86_EVENT_PEBS_LD_HSW) | |
120 | dse.mem_op = PERF_MEM_OP_LOAD; | |
722e76e6 SE |
121 | |
122 | /* | |
123 | * L1 info only valid for following events: | |
124 | * | |
125 | * MEM_UOPS_RETIRED.STLB_MISS_STORES | |
126 | * MEM_UOPS_RETIRED.LOCK_STORES | |
127 | * MEM_UOPS_RETIRED.SPLIT_STORES | |
128 | * MEM_UOPS_RETIRED.ALL_STORES | |
129 | */ | |
c8aab2e0 SE |
130 | if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) { |
131 | if (status & 1) | |
132 | dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT; | |
133 | else | |
134 | dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_MISS; | |
135 | } | |
f9134f36 AK |
136 | return dse.val; |
137 | } | |
138 | ||
f20093ee SE |
139 | static u64 load_latency_data(u64 status) |
140 | { | |
141 | union intel_x86_pebs_dse dse; | |
142 | u64 val; | |
143 | int model = boot_cpu_data.x86_model; | |
144 | int fam = boot_cpu_data.x86; | |
145 | ||
146 | dse.val = status; | |
147 | ||
148 | /* | |
149 | * use the mapping table for bit 0-3 | |
150 | */ | |
151 | val = pebs_data_source[dse.ld_dse]; | |
152 | ||
153 | /* | |
154 | * Nehalem models do not support TLB, Lock infos | |
155 | */ | |
156 | if (fam == 0x6 && (model == 26 || model == 30 | |
157 | || model == 31 || model == 46)) { | |
158 | val |= P(TLB, NA) | P(LOCK, NA); | |
159 | return val; | |
160 | } | |
161 | /* | |
162 | * bit 4: TLB access | |
163 | * 0 = did not miss 2nd level TLB | |
164 | * 1 = missed 2nd level TLB | |
165 | */ | |
166 | if (dse.ld_stlb_miss) | |
167 | val |= P(TLB, MISS) | P(TLB, L2); | |
168 | else | |
169 | val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2); | |
170 | ||
171 | /* | |
172 | * bit 5: locked prefix | |
173 | */ | |
174 | if (dse.ld_locked) | |
175 | val |= P(LOCK, LOCKED); | |
176 | ||
177 | return val; | |
178 | } | |
179 | ||
ca037701 PZ |
180 | struct pebs_record_core { |
181 | u64 flags, ip; | |
182 | u64 ax, bx, cx, dx; | |
183 | u64 si, di, bp, sp; | |
184 | u64 r8, r9, r10, r11; | |
185 | u64 r12, r13, r14, r15; | |
186 | }; | |
187 | ||
188 | struct pebs_record_nhm { | |
189 | u64 flags, ip; | |
190 | u64 ax, bx, cx, dx; | |
191 | u64 si, di, bp, sp; | |
192 | u64 r8, r9, r10, r11; | |
193 | u64 r12, r13, r14, r15; | |
194 | u64 status, dla, dse, lat; | |
195 | }; | |
196 | ||
130768b8 AK |
197 | /* |
198 | * Same as pebs_record_nhm, with two additional fields. | |
199 | */ | |
200 | struct pebs_record_hsw { | |
748e86aa AK |
201 | u64 flags, ip; |
202 | u64 ax, bx, cx, dx; | |
203 | u64 si, di, bp, sp; | |
204 | u64 r8, r9, r10, r11; | |
205 | u64 r12, r13, r14, r15; | |
206 | u64 status, dla, dse, lat; | |
d2beea4a | 207 | u64 real_ip, tsx_tuning; |
748e86aa AK |
208 | }; |
209 | ||
210 | union hsw_tsx_tuning { | |
211 | struct { | |
212 | u32 cycles_last_block : 32, | |
213 | hle_abort : 1, | |
214 | rtm_abort : 1, | |
215 | instruction_abort : 1, | |
216 | non_instruction_abort : 1, | |
217 | retry : 1, | |
218 | data_conflict : 1, | |
219 | capacity_writes : 1, | |
220 | capacity_reads : 1; | |
221 | }; | |
222 | u64 value; | |
130768b8 AK |
223 | }; |
224 | ||
a405bad5 AK |
225 | #define PEBS_HSW_TSX_FLAGS 0xff00000000ULL |
226 | ||
de0428a7 | 227 | void init_debug_store_on_cpu(int cpu) |
ca037701 PZ |
228 | { |
229 | struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds; | |
230 | ||
231 | if (!ds) | |
232 | return; | |
233 | ||
234 | wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, | |
235 | (u32)((u64)(unsigned long)ds), | |
236 | (u32)((u64)(unsigned long)ds >> 32)); | |
237 | } | |
238 | ||
de0428a7 | 239 | void fini_debug_store_on_cpu(int cpu) |
ca037701 PZ |
240 | { |
241 | if (!per_cpu(cpu_hw_events, cpu).ds) | |
242 | return; | |
243 | ||
244 | wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0); | |
245 | } | |
246 | ||
9536c8d2 PZ |
247 | static DEFINE_PER_CPU(void *, insn_buffer); |
248 | ||
5ee25c87 PZ |
249 | static int alloc_pebs_buffer(int cpu) |
250 | { | |
251 | struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds; | |
96681fc3 | 252 | int node = cpu_to_node(cpu); |
3569c0d7 | 253 | int max; |
9536c8d2 | 254 | void *buffer, *ibuffer; |
5ee25c87 PZ |
255 | |
256 | if (!x86_pmu.pebs) | |
257 | return 0; | |
258 | ||
7bfb7e6b | 259 | buffer = kzalloc_node(PEBS_BUFFER_SIZE, GFP_KERNEL, node); |
5ee25c87 PZ |
260 | if (unlikely(!buffer)) |
261 | return -ENOMEM; | |
262 | ||
9536c8d2 PZ |
263 | /* |
264 | * HSW+ already provides us the eventing ip; no need to allocate this | |
265 | * buffer then. | |
266 | */ | |
267 | if (x86_pmu.intel_cap.pebs_format < 2) { | |
268 | ibuffer = kzalloc_node(PEBS_FIXUP_SIZE, GFP_KERNEL, node); | |
269 | if (!ibuffer) { | |
270 | kfree(buffer); | |
271 | return -ENOMEM; | |
272 | } | |
273 | per_cpu(insn_buffer, cpu) = ibuffer; | |
274 | } | |
275 | ||
5ee25c87 PZ |
276 | max = PEBS_BUFFER_SIZE / x86_pmu.pebs_record_size; |
277 | ||
278 | ds->pebs_buffer_base = (u64)(unsigned long)buffer; | |
279 | ds->pebs_index = ds->pebs_buffer_base; | |
280 | ds->pebs_absolute_maximum = ds->pebs_buffer_base + | |
281 | max * x86_pmu.pebs_record_size; | |
282 | ||
5ee25c87 PZ |
283 | return 0; |
284 | } | |
285 | ||
b39f88ac PZ |
286 | static void release_pebs_buffer(int cpu) |
287 | { | |
288 | struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds; | |
289 | ||
290 | if (!ds || !x86_pmu.pebs) | |
291 | return; | |
292 | ||
9536c8d2 PZ |
293 | kfree(per_cpu(insn_buffer, cpu)); |
294 | per_cpu(insn_buffer, cpu) = NULL; | |
295 | ||
b39f88ac PZ |
296 | kfree((void *)(unsigned long)ds->pebs_buffer_base); |
297 | ds->pebs_buffer_base = 0; | |
298 | } | |
299 | ||
5ee25c87 PZ |
300 | static int alloc_bts_buffer(int cpu) |
301 | { | |
302 | struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds; | |
96681fc3 | 303 | int node = cpu_to_node(cpu); |
5ee25c87 PZ |
304 | int max, thresh; |
305 | void *buffer; | |
306 | ||
307 | if (!x86_pmu.bts) | |
308 | return 0; | |
309 | ||
44851541 DR |
310 | buffer = kzalloc_node(BTS_BUFFER_SIZE, GFP_KERNEL | __GFP_NOWARN, node); |
311 | if (unlikely(!buffer)) { | |
312 | WARN_ONCE(1, "%s: BTS buffer allocation failure\n", __func__); | |
5ee25c87 | 313 | return -ENOMEM; |
44851541 | 314 | } |
5ee25c87 PZ |
315 | |
316 | max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE; | |
317 | thresh = max / 16; | |
318 | ||
319 | ds->bts_buffer_base = (u64)(unsigned long)buffer; | |
320 | ds->bts_index = ds->bts_buffer_base; | |
321 | ds->bts_absolute_maximum = ds->bts_buffer_base + | |
322 | max * BTS_RECORD_SIZE; | |
323 | ds->bts_interrupt_threshold = ds->bts_absolute_maximum - | |
324 | thresh * BTS_RECORD_SIZE; | |
325 | ||
326 | return 0; | |
327 | } | |
328 | ||
b39f88ac PZ |
329 | static void release_bts_buffer(int cpu) |
330 | { | |
331 | struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds; | |
332 | ||
333 | if (!ds || !x86_pmu.bts) | |
334 | return; | |
335 | ||
336 | kfree((void *)(unsigned long)ds->bts_buffer_base); | |
337 | ds->bts_buffer_base = 0; | |
338 | } | |
339 | ||
65af94ba PZ |
340 | static int alloc_ds_buffer(int cpu) |
341 | { | |
96681fc3 | 342 | int node = cpu_to_node(cpu); |
65af94ba PZ |
343 | struct debug_store *ds; |
344 | ||
7bfb7e6b | 345 | ds = kzalloc_node(sizeof(*ds), GFP_KERNEL, node); |
65af94ba PZ |
346 | if (unlikely(!ds)) |
347 | return -ENOMEM; | |
348 | ||
349 | per_cpu(cpu_hw_events, cpu).ds = ds; | |
350 | ||
351 | return 0; | |
352 | } | |
353 | ||
354 | static void release_ds_buffer(int cpu) | |
355 | { | |
356 | struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds; | |
357 | ||
358 | if (!ds) | |
359 | return; | |
360 | ||
361 | per_cpu(cpu_hw_events, cpu).ds = NULL; | |
362 | kfree(ds); | |
363 | } | |
364 | ||
de0428a7 | 365 | void release_ds_buffers(void) |
ca037701 PZ |
366 | { |
367 | int cpu; | |
368 | ||
369 | if (!x86_pmu.bts && !x86_pmu.pebs) | |
370 | return; | |
371 | ||
372 | get_online_cpus(); | |
ca037701 PZ |
373 | for_each_online_cpu(cpu) |
374 | fini_debug_store_on_cpu(cpu); | |
375 | ||
376 | for_each_possible_cpu(cpu) { | |
b39f88ac PZ |
377 | release_pebs_buffer(cpu); |
378 | release_bts_buffer(cpu); | |
65af94ba | 379 | release_ds_buffer(cpu); |
ca037701 | 380 | } |
ca037701 PZ |
381 | put_online_cpus(); |
382 | } | |
383 | ||
de0428a7 | 384 | void reserve_ds_buffers(void) |
ca037701 | 385 | { |
6809b6ea PZ |
386 | int bts_err = 0, pebs_err = 0; |
387 | int cpu; | |
388 | ||
389 | x86_pmu.bts_active = 0; | |
390 | x86_pmu.pebs_active = 0; | |
ca037701 PZ |
391 | |
392 | if (!x86_pmu.bts && !x86_pmu.pebs) | |
f80c9e30 | 393 | return; |
ca037701 | 394 | |
6809b6ea PZ |
395 | if (!x86_pmu.bts) |
396 | bts_err = 1; | |
397 | ||
398 | if (!x86_pmu.pebs) | |
399 | pebs_err = 1; | |
400 | ||
ca037701 PZ |
401 | get_online_cpus(); |
402 | ||
403 | for_each_possible_cpu(cpu) { | |
6809b6ea PZ |
404 | if (alloc_ds_buffer(cpu)) { |
405 | bts_err = 1; | |
406 | pebs_err = 1; | |
407 | } | |
ca037701 | 408 | |
6809b6ea PZ |
409 | if (!bts_err && alloc_bts_buffer(cpu)) |
410 | bts_err = 1; | |
411 | ||
412 | if (!pebs_err && alloc_pebs_buffer(cpu)) | |
413 | pebs_err = 1; | |
5ee25c87 | 414 | |
6809b6ea | 415 | if (bts_err && pebs_err) |
5ee25c87 | 416 | break; |
6809b6ea PZ |
417 | } |
418 | ||
419 | if (bts_err) { | |
420 | for_each_possible_cpu(cpu) | |
421 | release_bts_buffer(cpu); | |
422 | } | |
ca037701 | 423 | |
6809b6ea PZ |
424 | if (pebs_err) { |
425 | for_each_possible_cpu(cpu) | |
426 | release_pebs_buffer(cpu); | |
ca037701 PZ |
427 | } |
428 | ||
6809b6ea PZ |
429 | if (bts_err && pebs_err) { |
430 | for_each_possible_cpu(cpu) | |
431 | release_ds_buffer(cpu); | |
432 | } else { | |
433 | if (x86_pmu.bts && !bts_err) | |
434 | x86_pmu.bts_active = 1; | |
435 | ||
436 | if (x86_pmu.pebs && !pebs_err) | |
437 | x86_pmu.pebs_active = 1; | |
438 | ||
ca037701 PZ |
439 | for_each_online_cpu(cpu) |
440 | init_debug_store_on_cpu(cpu); | |
441 | } | |
442 | ||
443 | put_online_cpus(); | |
ca037701 PZ |
444 | } |
445 | ||
446 | /* | |
447 | * BTS | |
448 | */ | |
449 | ||
de0428a7 | 450 | struct event_constraint bts_constraint = |
15c7ad51 | 451 | EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0); |
ca037701 | 452 | |
de0428a7 | 453 | void intel_pmu_enable_bts(u64 config) |
ca037701 PZ |
454 | { |
455 | unsigned long debugctlmsr; | |
456 | ||
457 | debugctlmsr = get_debugctlmsr(); | |
458 | ||
7c5ecaf7 PZ |
459 | debugctlmsr |= DEBUGCTLMSR_TR; |
460 | debugctlmsr |= DEBUGCTLMSR_BTS; | |
8062382c AS |
461 | if (config & ARCH_PERFMON_EVENTSEL_INT) |
462 | debugctlmsr |= DEBUGCTLMSR_BTINT; | |
ca037701 PZ |
463 | |
464 | if (!(config & ARCH_PERFMON_EVENTSEL_OS)) | |
7c5ecaf7 | 465 | debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS; |
ca037701 PZ |
466 | |
467 | if (!(config & ARCH_PERFMON_EVENTSEL_USR)) | |
7c5ecaf7 | 468 | debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR; |
ca037701 PZ |
469 | |
470 | update_debugctlmsr(debugctlmsr); | |
471 | } | |
472 | ||
de0428a7 | 473 | void intel_pmu_disable_bts(void) |
ca037701 | 474 | { |
89cbc767 | 475 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
ca037701 PZ |
476 | unsigned long debugctlmsr; |
477 | ||
478 | if (!cpuc->ds) | |
479 | return; | |
480 | ||
481 | debugctlmsr = get_debugctlmsr(); | |
482 | ||
483 | debugctlmsr &= | |
7c5ecaf7 PZ |
484 | ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT | |
485 | DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR); | |
ca037701 PZ |
486 | |
487 | update_debugctlmsr(debugctlmsr); | |
488 | } | |
489 | ||
de0428a7 | 490 | int intel_pmu_drain_bts_buffer(void) |
ca037701 | 491 | { |
89cbc767 | 492 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
ca037701 PZ |
493 | struct debug_store *ds = cpuc->ds; |
494 | struct bts_record { | |
495 | u64 from; | |
496 | u64 to; | |
497 | u64 flags; | |
498 | }; | |
15c7ad51 | 499 | struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; |
ca037701 PZ |
500 | struct bts_record *at, *top; |
501 | struct perf_output_handle handle; | |
502 | struct perf_event_header header; | |
503 | struct perf_sample_data data; | |
504 | struct pt_regs regs; | |
505 | ||
506 | if (!event) | |
b0b2072d | 507 | return 0; |
ca037701 | 508 | |
6809b6ea | 509 | if (!x86_pmu.bts_active) |
b0b2072d | 510 | return 0; |
ca037701 PZ |
511 | |
512 | at = (struct bts_record *)(unsigned long)ds->bts_buffer_base; | |
513 | top = (struct bts_record *)(unsigned long)ds->bts_index; | |
514 | ||
515 | if (top <= at) | |
b0b2072d | 516 | return 0; |
ca037701 | 517 | |
0e48026a SE |
518 | memset(®s, 0, sizeof(regs)); |
519 | ||
ca037701 PZ |
520 | ds->bts_index = ds->bts_buffer_base; |
521 | ||
fd0d000b | 522 | perf_sample_data_init(&data, 0, event->hw.last_period); |
ca037701 PZ |
523 | |
524 | /* | |
525 | * Prepare a generic sample, i.e. fill in the invariant fields. | |
526 | * We will overwrite the from and to address before we output | |
527 | * the sample. | |
528 | */ | |
529 | perf_prepare_sample(&header, &data, event, ®s); | |
530 | ||
a7ac67ea | 531 | if (perf_output_begin(&handle, event, header.size * (top - at))) |
b0b2072d | 532 | return 1; |
ca037701 PZ |
533 | |
534 | for (; at < top; at++) { | |
535 | data.ip = at->from; | |
536 | data.addr = at->to; | |
537 | ||
538 | perf_output_sample(&handle, &header, &data, event); | |
539 | } | |
540 | ||
541 | perf_output_end(&handle); | |
542 | ||
543 | /* There's new data available. */ | |
544 | event->hw.interrupts++; | |
545 | event->pending_kill = POLL_IN; | |
b0b2072d | 546 | return 1; |
ca037701 PZ |
547 | } |
548 | ||
549 | /* | |
550 | * PEBS | |
551 | */ | |
de0428a7 | 552 | struct event_constraint intel_core2_pebs_event_constraints[] = { |
af4bdcf6 AK |
553 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */ |
554 | INTEL_FLAGS_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */ | |
555 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */ | |
556 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */ | |
557 | INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */ | |
517e6341 PZ |
558 | /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ |
559 | INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01), | |
ca037701 PZ |
560 | EVENT_CONSTRAINT_END |
561 | }; | |
562 | ||
de0428a7 | 563 | struct event_constraint intel_atom_pebs_event_constraints[] = { |
af4bdcf6 AK |
564 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */ |
565 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */ | |
566 | INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */ | |
517e6341 PZ |
567 | /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ |
568 | INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01), | |
17e31629 SE |
569 | EVENT_CONSTRAINT_END |
570 | }; | |
571 | ||
1fa64180 | 572 | struct event_constraint intel_slm_pebs_event_constraints[] = { |
33636732 KL |
573 | /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ |
574 | INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x1), | |
86a04461 AK |
575 | /* Allow all events as PEBS with no flags */ |
576 | INTEL_ALL_EVENT_CONSTRAINT(0, 0x1), | |
1fa64180 YZ |
577 | EVENT_CONSTRAINT_END |
578 | }; | |
579 | ||
de0428a7 | 580 | struct event_constraint intel_nehalem_pebs_event_constraints[] = { |
f20093ee | 581 | INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */ |
af4bdcf6 AK |
582 | INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */ |
583 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */ | |
584 | INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INST_RETIRED.ANY */ | |
7d5d02da | 585 | INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */ |
af4bdcf6 AK |
586 | INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */ |
587 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */ | |
588 | INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */ | |
589 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */ | |
590 | INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */ | |
591 | INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */ | |
517e6341 PZ |
592 | /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ |
593 | INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f), | |
17e31629 SE |
594 | EVENT_CONSTRAINT_END |
595 | }; | |
596 | ||
de0428a7 | 597 | struct event_constraint intel_westmere_pebs_event_constraints[] = { |
f20093ee | 598 | INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */ |
af4bdcf6 AK |
599 | INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */ |
600 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */ | |
601 | INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INSTR_RETIRED.* */ | |
7d5d02da | 602 | INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */ |
af4bdcf6 AK |
603 | INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */ |
604 | INTEL_FLAGS_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */ | |
605 | INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */ | |
606 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */ | |
607 | INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */ | |
608 | INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */ | |
517e6341 PZ |
609 | /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ |
610 | INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f), | |
ca037701 PZ |
611 | EVENT_CONSTRAINT_END |
612 | }; | |
613 | ||
de0428a7 | 614 | struct event_constraint intel_snb_pebs_event_constraints[] = { |
0dbc9479 | 615 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */ |
f20093ee | 616 | INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */ |
9ad64c0f | 617 | INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */ |
86a04461 AK |
618 | /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */ |
619 | INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf), | |
b63b4b45 MD |
620 | INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */ |
621 | INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ | |
622 | INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ | |
623 | INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ | |
86a04461 AK |
624 | /* Allow all events as PEBS with no flags */ |
625 | INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), | |
b06b3d49 LM |
626 | EVENT_CONSTRAINT_END |
627 | }; | |
628 | ||
20a36e39 | 629 | struct event_constraint intel_ivb_pebs_event_constraints[] = { |
0dbc9479 | 630 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */ |
f20093ee | 631 | INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */ |
9ad64c0f | 632 | INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */ |
86a04461 AK |
633 | /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */ |
634 | INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf), | |
b63b4b45 MD |
635 | INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */ |
636 | INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ | |
637 | INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ | |
638 | INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ | |
86a04461 AK |
639 | /* Allow all events as PEBS with no flags */ |
640 | INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), | |
20a36e39 SE |
641 | EVENT_CONSTRAINT_END |
642 | }; | |
643 | ||
3044318f | 644 | struct event_constraint intel_hsw_pebs_event_constraints[] = { |
0dbc9479 | 645 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */ |
86a04461 AK |
646 | INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */ |
647 | /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */ | |
648 | INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf), | |
649 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */ | |
b63b4b45 MD |
650 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */ |
651 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */ | |
652 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */ | |
653 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */ | |
654 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */ | |
655 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */ | |
656 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */ | |
657 | INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ | |
658 | INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */ | |
659 | INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */ | |
86a04461 AK |
660 | /* Allow all events as PEBS with no flags */ |
661 | INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), | |
3044318f AK |
662 | EVENT_CONSTRAINT_END |
663 | }; | |
664 | ||
de0428a7 | 665 | struct event_constraint *intel_pebs_constraints(struct perf_event *event) |
ca037701 PZ |
666 | { |
667 | struct event_constraint *c; | |
668 | ||
ab608344 | 669 | if (!event->attr.precise_ip) |
ca037701 PZ |
670 | return NULL; |
671 | ||
672 | if (x86_pmu.pebs_constraints) { | |
673 | for_each_event_constraint(c, x86_pmu.pebs_constraints) { | |
9fac2cf3 SE |
674 | if ((event->hw.config & c->cmask) == c->code) { |
675 | event->hw.flags |= c->flags; | |
ca037701 | 676 | return c; |
9fac2cf3 | 677 | } |
ca037701 PZ |
678 | } |
679 | } | |
680 | ||
681 | return &emptyconstraint; | |
682 | } | |
683 | ||
3569c0d7 YZ |
684 | static inline bool pebs_is_enabled(struct cpu_hw_events *cpuc) |
685 | { | |
686 | return (cpuc->pebs_enabled & ((1ULL << MAX_PEBS_EVENTS) - 1)); | |
687 | } | |
688 | ||
de0428a7 | 689 | void intel_pmu_pebs_enable(struct perf_event *event) |
ca037701 | 690 | { |
89cbc767 | 691 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
ef21f683 | 692 | struct hw_perf_event *hwc = &event->hw; |
851559e3 | 693 | struct debug_store *ds = cpuc->ds; |
3569c0d7 YZ |
694 | bool first_pebs; |
695 | u64 threshold; | |
ca037701 PZ |
696 | |
697 | hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT; | |
698 | ||
3569c0d7 | 699 | first_pebs = !pebs_is_enabled(cpuc); |
ad0e6cfe | 700 | cpuc->pebs_enabled |= 1ULL << hwc->idx; |
f20093ee SE |
701 | |
702 | if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) | |
703 | cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32); | |
9ad64c0f SE |
704 | else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST) |
705 | cpuc->pebs_enabled |= 1ULL << 63; | |
851559e3 | 706 | |
3569c0d7 YZ |
707 | /* |
708 | * When the event is constrained enough we can use a larger | |
709 | * threshold and run the event with less frequent PMI. | |
710 | */ | |
711 | if (hwc->flags & PERF_X86_EVENT_FREERUNNING) { | |
712 | threshold = ds->pebs_absolute_maximum - | |
713 | x86_pmu.max_pebs_events * x86_pmu.pebs_record_size; | |
714 | } else { | |
715 | threshold = ds->pebs_buffer_base + x86_pmu.pebs_record_size; | |
716 | } | |
717 | ||
851559e3 YZ |
718 | /* Use auto-reload if possible to save a MSR write in the PMI */ |
719 | if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) { | |
720 | ds->pebs_event_reset[hwc->idx] = | |
721 | (u64)(-hwc->sample_period) & x86_pmu.cntval_mask; | |
722 | } | |
3569c0d7 YZ |
723 | |
724 | if (first_pebs || ds->pebs_interrupt_threshold > threshold) | |
725 | ds->pebs_interrupt_threshold = threshold; | |
ca037701 PZ |
726 | } |
727 | ||
de0428a7 | 728 | void intel_pmu_pebs_disable(struct perf_event *event) |
ca037701 | 729 | { |
89cbc767 | 730 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
ef21f683 | 731 | struct hw_perf_event *hwc = &event->hw; |
ca037701 | 732 | |
ad0e6cfe | 733 | cpuc->pebs_enabled &= ~(1ULL << hwc->idx); |
983433b5 | 734 | |
b371b594 | 735 | if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) |
983433b5 | 736 | cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32)); |
b371b594 | 737 | else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST) |
983433b5 SE |
738 | cpuc->pebs_enabled &= ~(1ULL << 63); |
739 | ||
4807e3d5 | 740 | if (cpuc->enabled) |
ad0e6cfe | 741 | wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); |
ca037701 PZ |
742 | |
743 | hwc->config |= ARCH_PERFMON_EVENTSEL_INT; | |
744 | } | |
745 | ||
de0428a7 | 746 | void intel_pmu_pebs_enable_all(void) |
ca037701 | 747 | { |
89cbc767 | 748 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
ca037701 PZ |
749 | |
750 | if (cpuc->pebs_enabled) | |
751 | wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); | |
752 | } | |
753 | ||
de0428a7 | 754 | void intel_pmu_pebs_disable_all(void) |
ca037701 | 755 | { |
89cbc767 | 756 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
ca037701 PZ |
757 | |
758 | if (cpuc->pebs_enabled) | |
759 | wrmsrl(MSR_IA32_PEBS_ENABLE, 0); | |
760 | } | |
761 | ||
ef21f683 PZ |
762 | static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs) |
763 | { | |
89cbc767 | 764 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
ef21f683 PZ |
765 | unsigned long from = cpuc->lbr_entries[0].from; |
766 | unsigned long old_to, to = cpuc->lbr_entries[0].to; | |
767 | unsigned long ip = regs->ip; | |
57d1c0c0 | 768 | int is_64bit = 0; |
9536c8d2 | 769 | void *kaddr; |
6ba48ff4 | 770 | int size; |
ef21f683 | 771 | |
8db909a7 PZ |
772 | /* |
773 | * We don't need to fixup if the PEBS assist is fault like | |
774 | */ | |
775 | if (!x86_pmu.intel_cap.pebs_trap) | |
776 | return 1; | |
777 | ||
a562b187 PZ |
778 | /* |
779 | * No LBR entry, no basic block, no rewinding | |
780 | */ | |
ef21f683 PZ |
781 | if (!cpuc->lbr_stack.nr || !from || !to) |
782 | return 0; | |
783 | ||
a562b187 PZ |
784 | /* |
785 | * Basic blocks should never cross user/kernel boundaries | |
786 | */ | |
787 | if (kernel_ip(ip) != kernel_ip(to)) | |
788 | return 0; | |
789 | ||
790 | /* | |
791 | * unsigned math, either ip is before the start (impossible) or | |
792 | * the basic block is larger than 1 page (sanity) | |
793 | */ | |
9536c8d2 | 794 | if ((ip - to) > PEBS_FIXUP_SIZE) |
ef21f683 PZ |
795 | return 0; |
796 | ||
797 | /* | |
798 | * We sampled a branch insn, rewind using the LBR stack | |
799 | */ | |
800 | if (ip == to) { | |
d07bdfd3 | 801 | set_linear_ip(regs, from); |
ef21f683 PZ |
802 | return 1; |
803 | } | |
804 | ||
6ba48ff4 | 805 | size = ip - to; |
9536c8d2 | 806 | if (!kernel_ip(ip)) { |
6ba48ff4 | 807 | int bytes; |
9536c8d2 PZ |
808 | u8 *buf = this_cpu_read(insn_buffer); |
809 | ||
6ba48ff4 | 810 | /* 'size' must fit our buffer, see above */ |
9536c8d2 | 811 | bytes = copy_from_user_nmi(buf, (void __user *)to, size); |
0a196848 | 812 | if (bytes != 0) |
9536c8d2 PZ |
813 | return 0; |
814 | ||
815 | kaddr = buf; | |
816 | } else { | |
817 | kaddr = (void *)to; | |
818 | } | |
819 | ||
ef21f683 PZ |
820 | do { |
821 | struct insn insn; | |
ef21f683 PZ |
822 | |
823 | old_to = to; | |
ef21f683 | 824 | |
57d1c0c0 PZ |
825 | #ifdef CONFIG_X86_64 |
826 | is_64bit = kernel_ip(to) || !test_thread_flag(TIF_IA32); | |
827 | #endif | |
6ba48ff4 | 828 | insn_init(&insn, kaddr, size, is_64bit); |
ef21f683 | 829 | insn_get_length(&insn); |
6ba48ff4 DH |
830 | /* |
831 | * Make sure there was not a problem decoding the | |
832 | * instruction and getting the length. This is | |
833 | * doubly important because we have an infinite | |
834 | * loop if insn.length=0. | |
835 | */ | |
836 | if (!insn.length) | |
837 | break; | |
9536c8d2 | 838 | |
ef21f683 | 839 | to += insn.length; |
9536c8d2 | 840 | kaddr += insn.length; |
6ba48ff4 | 841 | size -= insn.length; |
ef21f683 PZ |
842 | } while (to < ip); |
843 | ||
844 | if (to == ip) { | |
d07bdfd3 | 845 | set_linear_ip(regs, old_to); |
ef21f683 PZ |
846 | return 1; |
847 | } | |
848 | ||
a562b187 PZ |
849 | /* |
850 | * Even though we decoded the basic block, the instruction stream | |
851 | * never matched the given IP, either the TO or the IP got corrupted. | |
852 | */ | |
ef21f683 PZ |
853 | return 0; |
854 | } | |
855 | ||
748e86aa AK |
856 | static inline u64 intel_hsw_weight(struct pebs_record_hsw *pebs) |
857 | { | |
858 | if (pebs->tsx_tuning) { | |
859 | union hsw_tsx_tuning tsx = { .value = pebs->tsx_tuning }; | |
860 | return tsx.cycles_last_block; | |
861 | } | |
862 | return 0; | |
863 | } | |
864 | ||
a405bad5 AK |
865 | static inline u64 intel_hsw_transaction(struct pebs_record_hsw *pebs) |
866 | { | |
867 | u64 txn = (pebs->tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32; | |
868 | ||
869 | /* For RTM XABORTs also log the abort code from AX */ | |
870 | if ((txn & PERF_TXN_TRANSACTION) && (pebs->ax & 1)) | |
871 | txn |= ((pebs->ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT; | |
872 | return txn; | |
873 | } | |
874 | ||
43cf7631 YZ |
875 | static void setup_pebs_sample_data(struct perf_event *event, |
876 | struct pt_regs *iregs, void *__pebs, | |
877 | struct perf_sample_data *data, | |
878 | struct pt_regs *regs) | |
2b0b5c6f | 879 | { |
c8aab2e0 SE |
880 | #define PERF_X86_EVENT_PEBS_HSW_PREC \ |
881 | (PERF_X86_EVENT_PEBS_ST_HSW | \ | |
882 | PERF_X86_EVENT_PEBS_LD_HSW | \ | |
883 | PERF_X86_EVENT_PEBS_NA_HSW) | |
2b0b5c6f | 884 | /* |
d2beea4a PZ |
885 | * We cast to the biggest pebs_record but are careful not to |
886 | * unconditionally access the 'extra' entries. | |
2b0b5c6f | 887 | */ |
89cbc767 | 888 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
748e86aa | 889 | struct pebs_record_hsw *pebs = __pebs; |
f20093ee | 890 | u64 sample_type; |
c8aab2e0 SE |
891 | int fll, fst, dsrc; |
892 | int fl = event->hw.flags; | |
2b0b5c6f | 893 | |
21509084 YZ |
894 | if (pebs == NULL) |
895 | return; | |
896 | ||
c8aab2e0 SE |
897 | sample_type = event->attr.sample_type; |
898 | dsrc = sample_type & PERF_SAMPLE_DATA_SRC; | |
899 | ||
900 | fll = fl & PERF_X86_EVENT_PEBS_LDLAT; | |
901 | fst = fl & (PERF_X86_EVENT_PEBS_ST | PERF_X86_EVENT_PEBS_HSW_PREC); | |
f20093ee | 902 | |
43cf7631 | 903 | perf_sample_data_init(data, 0, event->hw.last_period); |
2b0b5c6f | 904 | |
43cf7631 | 905 | data->period = event->hw.last_period; |
f20093ee SE |
906 | |
907 | /* | |
c8aab2e0 | 908 | * Use latency for weight (only avail with PEBS-LL) |
f20093ee | 909 | */ |
c8aab2e0 | 910 | if (fll && (sample_type & PERF_SAMPLE_WEIGHT)) |
43cf7631 | 911 | data->weight = pebs->lat; |
c8aab2e0 SE |
912 | |
913 | /* | |
914 | * data.data_src encodes the data source | |
915 | */ | |
916 | if (dsrc) { | |
917 | u64 val = PERF_MEM_NA; | |
918 | if (fll) | |
919 | val = load_latency_data(pebs->dse); | |
920 | else if (fst && (fl & PERF_X86_EVENT_PEBS_HSW_PREC)) | |
921 | val = precise_datala_hsw(event, pebs->dse); | |
922 | else if (fst) | |
923 | val = precise_store_data(pebs->dse); | |
43cf7631 | 924 | data->data_src.val = val; |
f20093ee SE |
925 | } |
926 | ||
2b0b5c6f PZ |
927 | /* |
928 | * We use the interrupt regs as a base because the PEBS record | |
929 | * does not contain a full regs set, specifically it seems to | |
930 | * lack segment descriptors, which get used by things like | |
931 | * user_mode(). | |
932 | * | |
933 | * In the simple case fix up only the IP and BP,SP regs, for | |
934 | * PERF_SAMPLE_IP and PERF_SAMPLE_CALLCHAIN to function properly. | |
935 | * A possible PERF_SAMPLE_REGS will have to transfer all regs. | |
936 | */ | |
43cf7631 YZ |
937 | *regs = *iregs; |
938 | regs->flags = pebs->flags; | |
939 | set_linear_ip(regs, pebs->ip); | |
940 | regs->bp = pebs->bp; | |
941 | regs->sp = pebs->sp; | |
2b0b5c6f | 942 | |
aea48559 | 943 | if (sample_type & PERF_SAMPLE_REGS_INTR) { |
43cf7631 YZ |
944 | regs->ax = pebs->ax; |
945 | regs->bx = pebs->bx; | |
946 | regs->cx = pebs->cx; | |
947 | regs->dx = pebs->dx; | |
948 | regs->si = pebs->si; | |
949 | regs->di = pebs->di; | |
950 | regs->bp = pebs->bp; | |
951 | regs->sp = pebs->sp; | |
952 | ||
953 | regs->flags = pebs->flags; | |
aea48559 | 954 | #ifndef CONFIG_X86_32 |
43cf7631 YZ |
955 | regs->r8 = pebs->r8; |
956 | regs->r9 = pebs->r9; | |
957 | regs->r10 = pebs->r10; | |
958 | regs->r11 = pebs->r11; | |
959 | regs->r12 = pebs->r12; | |
960 | regs->r13 = pebs->r13; | |
961 | regs->r14 = pebs->r14; | |
962 | regs->r15 = pebs->r15; | |
aea48559 SE |
963 | #endif |
964 | } | |
965 | ||
130768b8 | 966 | if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format >= 2) { |
43cf7631 YZ |
967 | regs->ip = pebs->real_ip; |
968 | regs->flags |= PERF_EFLAGS_EXACT; | |
969 | } else if (event->attr.precise_ip > 1 && intel_pmu_pebs_fixup_ip(regs)) | |
970 | regs->flags |= PERF_EFLAGS_EXACT; | |
2b0b5c6f | 971 | else |
43cf7631 | 972 | regs->flags &= ~PERF_EFLAGS_EXACT; |
2b0b5c6f | 973 | |
c8aab2e0 | 974 | if ((sample_type & PERF_SAMPLE_ADDR) && |
d2beea4a | 975 | x86_pmu.intel_cap.pebs_format >= 1) |
43cf7631 | 976 | data->addr = pebs->dla; |
f9134f36 | 977 | |
a405bad5 AK |
978 | if (x86_pmu.intel_cap.pebs_format >= 2) { |
979 | /* Only set the TSX weight when no memory weight. */ | |
c8aab2e0 | 980 | if ((sample_type & PERF_SAMPLE_WEIGHT) && !fll) |
43cf7631 | 981 | data->weight = intel_hsw_weight(pebs); |
a405bad5 | 982 | |
c8aab2e0 | 983 | if (sample_type & PERF_SAMPLE_TRANSACTION) |
43cf7631 | 984 | data->txn = intel_hsw_transaction(pebs); |
a405bad5 | 985 | } |
748e86aa | 986 | |
60ce0fbd | 987 | if (has_branch_stack(event)) |
43cf7631 YZ |
988 | data->br_stack = &cpuc->lbr_stack; |
989 | } | |
990 | ||
21509084 YZ |
991 | static inline void * |
992 | get_next_pebs_record_by_bit(void *base, void *top, int bit) | |
993 | { | |
994 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); | |
995 | void *at; | |
996 | u64 pebs_status; | |
997 | ||
998 | if (base == NULL) | |
999 | return NULL; | |
1000 | ||
1001 | for (at = base; at < top; at += x86_pmu.pebs_record_size) { | |
1002 | struct pebs_record_nhm *p = at; | |
1003 | ||
1004 | if (test_bit(bit, (unsigned long *)&p->status)) { | |
1005 | ||
1006 | if (p->status == (1 << bit)) | |
1007 | return at; | |
1008 | ||
1009 | /* clear non-PEBS bit and re-check */ | |
1010 | pebs_status = p->status & cpuc->pebs_enabled; | |
1011 | pebs_status &= (1ULL << MAX_PEBS_EVENTS) - 1; | |
1012 | if (pebs_status == (1 << bit)) | |
1013 | return at; | |
1014 | } | |
1015 | } | |
1016 | return NULL; | |
1017 | } | |
1018 | ||
43cf7631 | 1019 | static void __intel_pmu_pebs_event(struct perf_event *event, |
21509084 YZ |
1020 | struct pt_regs *iregs, |
1021 | void *base, void *top, | |
1022 | int bit, int count) | |
43cf7631 YZ |
1023 | { |
1024 | struct perf_sample_data data; | |
1025 | struct pt_regs regs; | |
21509084 YZ |
1026 | int i; |
1027 | void *at = get_next_pebs_record_by_bit(base, top, bit); | |
43cf7631 | 1028 | |
21509084 YZ |
1029 | if (!intel_pmu_save_and_restart(event) && |
1030 | !(event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)) | |
43cf7631 YZ |
1031 | return; |
1032 | ||
21509084 YZ |
1033 | if (count > 1) { |
1034 | for (i = 0; i < count - 1; i++) { | |
1035 | setup_pebs_sample_data(event, iregs, at, &data, ®s); | |
1036 | perf_event_output(event, &data, ®s); | |
1037 | at += x86_pmu.pebs_record_size; | |
1038 | at = get_next_pebs_record_by_bit(at, top, bit); | |
1039 | } | |
1040 | } | |
1041 | ||
1042 | setup_pebs_sample_data(event, iregs, at, &data, ®s); | |
60ce0fbd | 1043 | |
21509084 YZ |
1044 | /* |
1045 | * All but the last records are processed. | |
1046 | * The last one is left to be able to call the overflow handler. | |
1047 | */ | |
1048 | if (perf_event_overflow(event, &data, ®s)) { | |
a4eaf7f1 | 1049 | x86_pmu_stop(event, 0); |
21509084 YZ |
1050 | return; |
1051 | } | |
1052 | ||
2b0b5c6f PZ |
1053 | } |
1054 | ||
ca037701 PZ |
1055 | static void intel_pmu_drain_pebs_core(struct pt_regs *iregs) |
1056 | { | |
89cbc767 | 1057 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
ca037701 PZ |
1058 | struct debug_store *ds = cpuc->ds; |
1059 | struct perf_event *event = cpuc->events[0]; /* PMC0 only */ | |
1060 | struct pebs_record_core *at, *top; | |
ca037701 PZ |
1061 | int n; |
1062 | ||
6809b6ea | 1063 | if (!x86_pmu.pebs_active) |
ca037701 PZ |
1064 | return; |
1065 | ||
ca037701 PZ |
1066 | at = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base; |
1067 | top = (struct pebs_record_core *)(unsigned long)ds->pebs_index; | |
1068 | ||
d80c7502 PZ |
1069 | /* |
1070 | * Whatever else happens, drain the thing | |
1071 | */ | |
1072 | ds->pebs_index = ds->pebs_buffer_base; | |
1073 | ||
1074 | if (!test_bit(0, cpuc->active_mask)) | |
8f4aebd2 | 1075 | return; |
ca037701 | 1076 | |
d80c7502 PZ |
1077 | WARN_ON_ONCE(!event); |
1078 | ||
ab608344 | 1079 | if (!event->attr.precise_ip) |
d80c7502 PZ |
1080 | return; |
1081 | ||
21509084 | 1082 | n = (top - at) / x86_pmu.pebs_record_size; |
d80c7502 PZ |
1083 | if (n <= 0) |
1084 | return; | |
ca037701 | 1085 | |
21509084 | 1086 | __intel_pmu_pebs_event(event, iregs, at, top, 0, n); |
ca037701 PZ |
1087 | } |
1088 | ||
d2beea4a | 1089 | static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs) |
ca037701 | 1090 | { |
89cbc767 | 1091 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
ca037701 | 1092 | struct debug_store *ds = cpuc->ds; |
21509084 YZ |
1093 | struct perf_event *event; |
1094 | void *base, *at, *top; | |
eb8417aa | 1095 | int bit; |
21509084 | 1096 | short counts[MAX_PEBS_EVENTS] = {}; |
d2beea4a PZ |
1097 | |
1098 | if (!x86_pmu.pebs_active) | |
1099 | return; | |
1100 | ||
21509084 | 1101 | base = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base; |
d2beea4a | 1102 | top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index; |
ca037701 | 1103 | |
ca037701 PZ |
1104 | ds->pebs_index = ds->pebs_buffer_base; |
1105 | ||
21509084 | 1106 | if (unlikely(base >= top)) |
d2beea4a PZ |
1107 | return; |
1108 | ||
21509084 | 1109 | for (at = base; at < top; at += x86_pmu.pebs_record_size) { |
130768b8 | 1110 | struct pebs_record_nhm *p = at; |
ca037701 | 1111 | |
21509084 YZ |
1112 | bit = find_first_bit((unsigned long *)&p->status, |
1113 | x86_pmu.max_pebs_events); | |
1114 | if (bit >= x86_pmu.max_pebs_events) | |
1115 | continue; | |
1116 | if (!test_bit(bit, cpuc->active_mask)) | |
1117 | continue; | |
1118 | /* | |
1119 | * The PEBS hardware does not deal well with the situation | |
1120 | * when events happen near to each other and multiple bits | |
1121 | * are set. But it should happen rarely. | |
1122 | * | |
1123 | * If these events include one PEBS and multiple non-PEBS | |
1124 | * events, it doesn't impact PEBS record. The record will | |
1125 | * be handled normally. (slow path) | |
1126 | * | |
1127 | * If these events include two or more PEBS events, the | |
1128 | * records for the events can be collapsed into a single | |
1129 | * one, and it's not possible to reconstruct all events | |
1130 | * that caused the PEBS record. It's called collision. | |
1131 | * If collision happened, the record will be dropped. | |
1132 | * | |
1133 | */ | |
1134 | if (p->status != (1 << bit)) { | |
1135 | u64 pebs_status; | |
12ab854d | 1136 | |
21509084 YZ |
1137 | /* slow path */ |
1138 | pebs_status = p->status & cpuc->pebs_enabled; | |
1139 | pebs_status &= (1ULL << MAX_PEBS_EVENTS) - 1; | |
1140 | if (pebs_status != (1 << bit)) | |
12ab854d | 1141 | continue; |
ca037701 | 1142 | } |
21509084 YZ |
1143 | counts[bit]++; |
1144 | } | |
ca037701 | 1145 | |
21509084 YZ |
1146 | for (bit = 0; bit < x86_pmu.max_pebs_events; bit++) { |
1147 | if (counts[bit] == 0) | |
ca037701 | 1148 | continue; |
21509084 YZ |
1149 | event = cpuc->events[bit]; |
1150 | WARN_ON_ONCE(!event); | |
1151 | WARN_ON_ONCE(!event->attr.precise_ip); | |
ca037701 | 1152 | |
21509084 | 1153 | __intel_pmu_pebs_event(event, iregs, base, top, bit, counts[bit]); |
ca037701 | 1154 | } |
ca037701 PZ |
1155 | } |
1156 | ||
1157 | /* | |
1158 | * BTS, PEBS probe and setup | |
1159 | */ | |
1160 | ||
066ce64c | 1161 | void __init intel_ds_init(void) |
ca037701 PZ |
1162 | { |
1163 | /* | |
1164 | * No support for 32bit formats | |
1165 | */ | |
1166 | if (!boot_cpu_has(X86_FEATURE_DTES64)) | |
1167 | return; | |
1168 | ||
1169 | x86_pmu.bts = boot_cpu_has(X86_FEATURE_BTS); | |
1170 | x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS); | |
1171 | if (x86_pmu.pebs) { | |
8db909a7 PZ |
1172 | char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-'; |
1173 | int format = x86_pmu.intel_cap.pebs_format; | |
ca037701 PZ |
1174 | |
1175 | switch (format) { | |
1176 | case 0: | |
8db909a7 | 1177 | printk(KERN_CONT "PEBS fmt0%c, ", pebs_type); |
ca037701 PZ |
1178 | x86_pmu.pebs_record_size = sizeof(struct pebs_record_core); |
1179 | x86_pmu.drain_pebs = intel_pmu_drain_pebs_core; | |
ca037701 PZ |
1180 | break; |
1181 | ||
1182 | case 1: | |
8db909a7 | 1183 | printk(KERN_CONT "PEBS fmt1%c, ", pebs_type); |
ca037701 PZ |
1184 | x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm); |
1185 | x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm; | |
ca037701 PZ |
1186 | break; |
1187 | ||
130768b8 AK |
1188 | case 2: |
1189 | pr_cont("PEBS fmt2%c, ", pebs_type); | |
1190 | x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw); | |
d2beea4a | 1191 | x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm; |
130768b8 AK |
1192 | break; |
1193 | ||
ca037701 | 1194 | default: |
8db909a7 | 1195 | printk(KERN_CONT "no PEBS fmt%d%c, ", format, pebs_type); |
ca037701 | 1196 | x86_pmu.pebs = 0; |
ca037701 PZ |
1197 | } |
1198 | } | |
1199 | } | |
1d9d8639 SE |
1200 | |
1201 | void perf_restore_debug_store(void) | |
1202 | { | |
2a6e06b2 LT |
1203 | struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds); |
1204 | ||
1d9d8639 SE |
1205 | if (!x86_pmu.bts && !x86_pmu.pebs) |
1206 | return; | |
1207 | ||
2a6e06b2 | 1208 | wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds); |
1d9d8639 | 1209 | } |