Commit | Line | Data |
---|---|---|
ca037701 PZ |
1 | #ifdef CONFIG_CPU_SUP_INTEL |
2 | ||
3 | /* The maximal number of PEBS events: */ | |
4 | #define MAX_PEBS_EVENTS 4 | |
5 | ||
6 | /* The size of a BTS record in bytes: */ | |
7 | #define BTS_RECORD_SIZE 24 | |
8 | ||
9 | #define BTS_BUFFER_SIZE (PAGE_SIZE << 4) | |
10 | #define PEBS_BUFFER_SIZE PAGE_SIZE | |
11 | ||
12 | /* | |
13 | * pebs_record_32 for p4 and core not supported | |
14 | ||
15 | struct pebs_record_32 { | |
16 | u32 flags, ip; | |
17 | u32 ax, bc, cx, dx; | |
18 | u32 si, di, bp, sp; | |
19 | }; | |
20 | ||
21 | */ | |
22 | ||
23 | struct pebs_record_core { | |
24 | u64 flags, ip; | |
25 | u64 ax, bx, cx, dx; | |
26 | u64 si, di, bp, sp; | |
27 | u64 r8, r9, r10, r11; | |
28 | u64 r12, r13, r14, r15; | |
29 | }; | |
30 | ||
31 | struct pebs_record_nhm { | |
32 | u64 flags, ip; | |
33 | u64 ax, bx, cx, dx; | |
34 | u64 si, di, bp, sp; | |
35 | u64 r8, r9, r10, r11; | |
36 | u64 r12, r13, r14, r15; | |
37 | u64 status, dla, dse, lat; | |
38 | }; | |
39 | ||
40 | /* | |
41 | * Bits in the debugctlmsr controlling branch tracing. | |
42 | */ | |
43 | #define X86_DEBUGCTL_TR (1 << 6) | |
44 | #define X86_DEBUGCTL_BTS (1 << 7) | |
45 | #define X86_DEBUGCTL_BTINT (1 << 8) | |
46 | #define X86_DEBUGCTL_BTS_OFF_OS (1 << 9) | |
47 | #define X86_DEBUGCTL_BTS_OFF_USR (1 << 10) | |
48 | ||
49 | /* | |
50 | * A debug store configuration. | |
51 | * | |
52 | * We only support architectures that use 64bit fields. | |
53 | */ | |
54 | struct debug_store { | |
55 | u64 bts_buffer_base; | |
56 | u64 bts_index; | |
57 | u64 bts_absolute_maximum; | |
58 | u64 bts_interrupt_threshold; | |
59 | u64 pebs_buffer_base; | |
60 | u64 pebs_index; | |
61 | u64 pebs_absolute_maximum; | |
62 | u64 pebs_interrupt_threshold; | |
63 | u64 pebs_event_reset[MAX_PEBS_EVENTS]; | |
64 | }; | |
65 | ||
66 | static void init_debug_store_on_cpu(int cpu) | |
67 | { | |
68 | struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds; | |
69 | ||
70 | if (!ds) | |
71 | return; | |
72 | ||
73 | wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, | |
74 | (u32)((u64)(unsigned long)ds), | |
75 | (u32)((u64)(unsigned long)ds >> 32)); | |
76 | } | |
77 | ||
78 | static void fini_debug_store_on_cpu(int cpu) | |
79 | { | |
80 | if (!per_cpu(cpu_hw_events, cpu).ds) | |
81 | return; | |
82 | ||
83 | wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0); | |
84 | } | |
85 | ||
86 | static void release_ds_buffers(void) | |
87 | { | |
88 | int cpu; | |
89 | ||
90 | if (!x86_pmu.bts && !x86_pmu.pebs) | |
91 | return; | |
92 | ||
93 | get_online_cpus(); | |
94 | ||
95 | for_each_online_cpu(cpu) | |
96 | fini_debug_store_on_cpu(cpu); | |
97 | ||
98 | for_each_possible_cpu(cpu) { | |
99 | struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds; | |
100 | ||
101 | if (!ds) | |
102 | continue; | |
103 | ||
104 | per_cpu(cpu_hw_events, cpu).ds = NULL; | |
105 | ||
106 | kfree((void *)(unsigned long)ds->pebs_buffer_base); | |
107 | kfree((void *)(unsigned long)ds->bts_buffer_base); | |
108 | kfree(ds); | |
109 | } | |
110 | ||
111 | put_online_cpus(); | |
112 | } | |
113 | ||
114 | static int reserve_ds_buffers(void) | |
115 | { | |
116 | int cpu, err = 0; | |
117 | ||
118 | if (!x86_pmu.bts && !x86_pmu.pebs) | |
119 | return 0; | |
120 | ||
121 | get_online_cpus(); | |
122 | ||
123 | for_each_possible_cpu(cpu) { | |
124 | struct debug_store *ds; | |
125 | void *buffer; | |
126 | int max, thresh; | |
127 | ||
128 | err = -ENOMEM; | |
129 | ds = kzalloc(sizeof(*ds), GFP_KERNEL); | |
130 | if (unlikely(!ds)) { | |
131 | kfree(buffer); | |
132 | break; | |
133 | } | |
134 | per_cpu(cpu_hw_events, cpu).ds = ds; | |
135 | ||
136 | if (x86_pmu.bts) { | |
137 | buffer = kzalloc(BTS_BUFFER_SIZE, GFP_KERNEL); | |
138 | if (unlikely(!buffer)) | |
139 | break; | |
140 | ||
141 | max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE; | |
142 | thresh = max / 16; | |
143 | ||
144 | ds->bts_buffer_base = (u64)(unsigned long)buffer; | |
145 | ds->bts_index = ds->bts_buffer_base; | |
146 | ds->bts_absolute_maximum = ds->bts_buffer_base + | |
147 | max * BTS_RECORD_SIZE; | |
148 | ds->bts_interrupt_threshold = ds->bts_absolute_maximum - | |
149 | thresh * BTS_RECORD_SIZE; | |
150 | } | |
151 | ||
152 | if (x86_pmu.pebs) { | |
153 | buffer = kzalloc(PEBS_BUFFER_SIZE, GFP_KERNEL); | |
154 | if (unlikely(!buffer)) | |
155 | break; | |
156 | ||
157 | max = PEBS_BUFFER_SIZE / x86_pmu.pebs_record_size; | |
158 | ||
159 | ds->pebs_buffer_base = (u64)(unsigned long)buffer; | |
160 | ds->pebs_index = ds->pebs_buffer_base; | |
161 | ds->pebs_absolute_maximum = ds->pebs_buffer_base + | |
162 | max * x86_pmu.pebs_record_size; | |
163 | /* | |
164 | * Always use single record PEBS | |
165 | */ | |
166 | ds->pebs_interrupt_threshold = ds->pebs_buffer_base + | |
167 | x86_pmu.pebs_record_size; | |
168 | } | |
169 | ||
170 | err = 0; | |
171 | } | |
172 | ||
173 | if (err) | |
174 | release_ds_buffers(); | |
175 | else { | |
176 | for_each_online_cpu(cpu) | |
177 | init_debug_store_on_cpu(cpu); | |
178 | } | |
179 | ||
180 | put_online_cpus(); | |
181 | ||
182 | return err; | |
183 | } | |
184 | ||
185 | /* | |
186 | * BTS | |
187 | */ | |
188 | ||
189 | static struct event_constraint bts_constraint = | |
190 | EVENT_CONSTRAINT(0, 1ULL << X86_PMC_IDX_FIXED_BTS, 0); | |
191 | ||
192 | static void intel_pmu_enable_bts(u64 config) | |
193 | { | |
194 | unsigned long debugctlmsr; | |
195 | ||
196 | debugctlmsr = get_debugctlmsr(); | |
197 | ||
198 | debugctlmsr |= X86_DEBUGCTL_TR; | |
199 | debugctlmsr |= X86_DEBUGCTL_BTS; | |
200 | debugctlmsr |= X86_DEBUGCTL_BTINT; | |
201 | ||
202 | if (!(config & ARCH_PERFMON_EVENTSEL_OS)) | |
203 | debugctlmsr |= X86_DEBUGCTL_BTS_OFF_OS; | |
204 | ||
205 | if (!(config & ARCH_PERFMON_EVENTSEL_USR)) | |
206 | debugctlmsr |= X86_DEBUGCTL_BTS_OFF_USR; | |
207 | ||
208 | update_debugctlmsr(debugctlmsr); | |
209 | } | |
210 | ||
211 | static void intel_pmu_disable_bts(void) | |
212 | { | |
213 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
214 | unsigned long debugctlmsr; | |
215 | ||
216 | if (!cpuc->ds) | |
217 | return; | |
218 | ||
219 | debugctlmsr = get_debugctlmsr(); | |
220 | ||
221 | debugctlmsr &= | |
222 | ~(X86_DEBUGCTL_TR | X86_DEBUGCTL_BTS | X86_DEBUGCTL_BTINT | | |
223 | X86_DEBUGCTL_BTS_OFF_OS | X86_DEBUGCTL_BTS_OFF_USR); | |
224 | ||
225 | update_debugctlmsr(debugctlmsr); | |
226 | } | |
227 | ||
228 | static void intel_pmu_drain_bts_buffer(void) | |
229 | { | |
230 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
231 | struct debug_store *ds = cpuc->ds; | |
232 | struct bts_record { | |
233 | u64 from; | |
234 | u64 to; | |
235 | u64 flags; | |
236 | }; | |
237 | struct perf_event *event = cpuc->events[X86_PMC_IDX_FIXED_BTS]; | |
238 | struct bts_record *at, *top; | |
239 | struct perf_output_handle handle; | |
240 | struct perf_event_header header; | |
241 | struct perf_sample_data data; | |
242 | struct pt_regs regs; | |
243 | ||
244 | if (!event) | |
245 | return; | |
246 | ||
247 | if (!ds) | |
248 | return; | |
249 | ||
250 | at = (struct bts_record *)(unsigned long)ds->bts_buffer_base; | |
251 | top = (struct bts_record *)(unsigned long)ds->bts_index; | |
252 | ||
253 | if (top <= at) | |
254 | return; | |
255 | ||
256 | ds->bts_index = ds->bts_buffer_base; | |
257 | ||
258 | perf_sample_data_init(&data, 0); | |
259 | data.period = event->hw.last_period; | |
260 | regs.ip = 0; | |
261 | ||
262 | /* | |
263 | * Prepare a generic sample, i.e. fill in the invariant fields. | |
264 | * We will overwrite the from and to address before we output | |
265 | * the sample. | |
266 | */ | |
267 | perf_prepare_sample(&header, &data, event, ®s); | |
268 | ||
269 | if (perf_output_begin(&handle, event, header.size * (top - at), 1, 1)) | |
270 | return; | |
271 | ||
272 | for (; at < top; at++) { | |
273 | data.ip = at->from; | |
274 | data.addr = at->to; | |
275 | ||
276 | perf_output_sample(&handle, &header, &data, event); | |
277 | } | |
278 | ||
279 | perf_output_end(&handle); | |
280 | ||
281 | /* There's new data available. */ | |
282 | event->hw.interrupts++; | |
283 | event->pending_kill = POLL_IN; | |
284 | } | |
285 | ||
286 | /* | |
287 | * PEBS | |
288 | */ | |
289 | ||
290 | static struct event_constraint intel_core_pebs_events[] = { | |
291 | PEBS_EVENT_CONSTRAINT(0x00c0, 0x1), /* INSTR_RETIRED.ANY */ | |
292 | PEBS_EVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */ | |
293 | PEBS_EVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */ | |
294 | PEBS_EVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */ | |
295 | PEBS_EVENT_CONSTRAINT(0x01cb, 0x1), /* MEM_LOAD_RETIRED.L1D_MISS */ | |
296 | PEBS_EVENT_CONSTRAINT(0x02cb, 0x1), /* MEM_LOAD_RETIRED.L1D_LINE_MISS */ | |
297 | PEBS_EVENT_CONSTRAINT(0x04cb, 0x1), /* MEM_LOAD_RETIRED.L2_MISS */ | |
298 | PEBS_EVENT_CONSTRAINT(0x08cb, 0x1), /* MEM_LOAD_RETIRED.L2_LINE_MISS */ | |
299 | PEBS_EVENT_CONSTRAINT(0x10cb, 0x1), /* MEM_LOAD_RETIRED.DTLB_MISS */ | |
300 | EVENT_CONSTRAINT_END | |
301 | }; | |
302 | ||
303 | static struct event_constraint intel_nehalem_pebs_events[] = { | |
304 | PEBS_EVENT_CONSTRAINT(0x00c0, 0xf), /* INSTR_RETIRED.ANY */ | |
305 | PEBS_EVENT_CONSTRAINT(0xfec1, 0xf), /* X87_OPS_RETIRED.ANY */ | |
306 | PEBS_EVENT_CONSTRAINT(0x00c5, 0xf), /* BR_INST_RETIRED.MISPRED */ | |
307 | PEBS_EVENT_CONSTRAINT(0x1fc7, 0xf), /* SIMD_INST_RETURED.ANY */ | |
308 | PEBS_EVENT_CONSTRAINT(0x01cb, 0xf), /* MEM_LOAD_RETIRED.L1D_MISS */ | |
309 | PEBS_EVENT_CONSTRAINT(0x02cb, 0xf), /* MEM_LOAD_RETIRED.L1D_LINE_MISS */ | |
310 | PEBS_EVENT_CONSTRAINT(0x04cb, 0xf), /* MEM_LOAD_RETIRED.L2_MISS */ | |
311 | PEBS_EVENT_CONSTRAINT(0x08cb, 0xf), /* MEM_LOAD_RETIRED.L2_LINE_MISS */ | |
312 | PEBS_EVENT_CONSTRAINT(0x10cb, 0xf), /* MEM_LOAD_RETIRED.DTLB_MISS */ | |
313 | EVENT_CONSTRAINT_END | |
314 | }; | |
315 | ||
316 | static struct event_constraint * | |
317 | intel_pebs_constraints(struct perf_event *event) | |
318 | { | |
319 | struct event_constraint *c; | |
320 | ||
321 | if (!event->attr.precise) | |
322 | return NULL; | |
323 | ||
324 | if (x86_pmu.pebs_constraints) { | |
325 | for_each_event_constraint(c, x86_pmu.pebs_constraints) { | |
326 | if ((event->hw.config & c->cmask) == c->code) | |
327 | return c; | |
328 | } | |
329 | } | |
330 | ||
331 | return &emptyconstraint; | |
332 | } | |
333 | ||
ef21f683 | 334 | static void intel_pmu_pebs_enable(struct perf_event *event) |
ca037701 PZ |
335 | { |
336 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
ef21f683 | 337 | struct hw_perf_event *hwc = &event->hw; |
ca037701 PZ |
338 | u64 val = cpuc->pebs_enabled; |
339 | ||
340 | hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT; | |
341 | ||
342 | val |= 1ULL << hwc->idx; | |
343 | wrmsrl(MSR_IA32_PEBS_ENABLE, val); | |
ef21f683 PZ |
344 | |
345 | intel_pmu_lbr_enable(event); | |
ca037701 PZ |
346 | } |
347 | ||
ef21f683 | 348 | static void intel_pmu_pebs_disable(struct perf_event *event) |
ca037701 PZ |
349 | { |
350 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
ef21f683 | 351 | struct hw_perf_event *hwc = &event->hw; |
ca037701 PZ |
352 | u64 val = cpuc->pebs_enabled; |
353 | ||
354 | val &= ~(1ULL << hwc->idx); | |
355 | wrmsrl(MSR_IA32_PEBS_ENABLE, val); | |
356 | ||
357 | hwc->config |= ARCH_PERFMON_EVENTSEL_INT; | |
ef21f683 PZ |
358 | |
359 | intel_pmu_lbr_disable(event); | |
ca037701 PZ |
360 | } |
361 | ||
362 | static void intel_pmu_pebs_enable_all(void) | |
363 | { | |
364 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
365 | ||
366 | if (cpuc->pebs_enabled) | |
367 | wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); | |
368 | } | |
369 | ||
370 | static void intel_pmu_pebs_disable_all(void) | |
371 | { | |
372 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
373 | ||
374 | if (cpuc->pebs_enabled) | |
375 | wrmsrl(MSR_IA32_PEBS_ENABLE, 0); | |
376 | } | |
377 | ||
ef21f683 PZ |
378 | #include <asm/insn.h> |
379 | ||
380 | #define MAX_INSN_SIZE 16 | |
381 | ||
382 | static inline bool kernel_ip(unsigned long ip) | |
383 | { | |
384 | #ifdef CONFIG_X86_32 | |
385 | return ip > PAGE_OFFSET; | |
386 | #else | |
387 | return (long)ip < 0; | |
388 | #endif | |
389 | } | |
390 | ||
391 | static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs) | |
392 | { | |
393 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
394 | unsigned long from = cpuc->lbr_entries[0].from; | |
395 | unsigned long old_to, to = cpuc->lbr_entries[0].to; | |
396 | unsigned long ip = regs->ip; | |
397 | ||
398 | if (!cpuc->lbr_stack.nr || !from || !to) | |
399 | return 0; | |
400 | ||
401 | if (ip < to) | |
402 | return 0; | |
403 | ||
404 | /* | |
405 | * We sampled a branch insn, rewind using the LBR stack | |
406 | */ | |
407 | if (ip == to) { | |
408 | regs->ip = from; | |
409 | return 1; | |
410 | } | |
411 | ||
412 | do { | |
413 | struct insn insn; | |
414 | u8 buf[MAX_INSN_SIZE]; | |
415 | void *kaddr; | |
416 | ||
417 | old_to = to; | |
418 | if (!kernel_ip(ip)) { | |
419 | int bytes, size = min_t(int, MAX_INSN_SIZE, ip - to); | |
420 | ||
421 | bytes = copy_from_user_nmi(buf, (void __user *)to, size); | |
422 | if (bytes != size) | |
423 | return 0; | |
424 | ||
425 | kaddr = buf; | |
426 | } else | |
427 | kaddr = (void *)to; | |
428 | ||
429 | kernel_insn_init(&insn, kaddr); | |
430 | insn_get_length(&insn); | |
431 | to += insn.length; | |
432 | } while (to < ip); | |
433 | ||
434 | if (to == ip) { | |
435 | regs->ip = old_to; | |
436 | return 1; | |
437 | } | |
438 | ||
439 | return 0; | |
440 | } | |
441 | ||
ca037701 PZ |
442 | static int intel_pmu_save_and_restart(struct perf_event *event); |
443 | static void intel_pmu_disable_event(struct perf_event *event); | |
444 | ||
445 | static void intel_pmu_drain_pebs_core(struct pt_regs *iregs) | |
446 | { | |
447 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
448 | struct debug_store *ds = cpuc->ds; | |
449 | struct perf_event *event = cpuc->events[0]; /* PMC0 only */ | |
450 | struct pebs_record_core *at, *top; | |
451 | struct perf_sample_data data; | |
452 | struct pt_regs regs; | |
453 | int n; | |
454 | ||
455 | if (!event || !ds || !x86_pmu.pebs) | |
456 | return; | |
457 | ||
458 | intel_pmu_pebs_disable_all(); | |
459 | ||
460 | at = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base; | |
461 | top = (struct pebs_record_core *)(unsigned long)ds->pebs_index; | |
462 | ||
463 | if (top <= at) | |
464 | goto out; | |
465 | ||
466 | ds->pebs_index = ds->pebs_buffer_base; | |
467 | ||
468 | if (!intel_pmu_save_and_restart(event)) | |
469 | goto out; | |
470 | ||
471 | perf_sample_data_init(&data, 0); | |
472 | data.period = event->hw.last_period; | |
473 | ||
474 | n = top - at; | |
475 | ||
476 | /* | |
477 | * Should not happen, we program the threshold at 1 and do not | |
478 | * set a reset value. | |
479 | */ | |
480 | WARN_ON_ONCE(n > 1); | |
481 | ||
482 | /* | |
483 | * We use the interrupt regs as a base because the PEBS record | |
484 | * does not contain a full regs set, specifically it seems to | |
485 | * lack segment descriptors, which get used by things like | |
486 | * user_mode(). | |
487 | * | |
488 | * In the simple case fix up only the IP and BP,SP regs, for | |
489 | * PERF_SAMPLE_IP and PERF_SAMPLE_CALLCHAIN to function properly. | |
490 | * A possible PERF_SAMPLE_REGS will have to transfer all regs. | |
491 | */ | |
492 | regs = *iregs; | |
493 | regs.ip = at->ip; | |
494 | regs.bp = at->bp; | |
495 | regs.sp = at->sp; | |
496 | ||
ef21f683 PZ |
497 | if (intel_pmu_pebs_fixup_ip(®s)) |
498 | regs.flags |= PERF_EFLAGS_EXACT; | |
499 | else | |
500 | regs.flags &= ~PERF_EFLAGS_EXACT; | |
501 | ||
ca037701 PZ |
502 | if (perf_event_overflow(event, 1, &data, ®s)) |
503 | intel_pmu_disable_event(event); | |
504 | ||
505 | out: | |
506 | intel_pmu_pebs_enable_all(); | |
507 | } | |
508 | ||
509 | static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs) | |
510 | { | |
511 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
512 | struct debug_store *ds = cpuc->ds; | |
513 | struct pebs_record_nhm *at, *top; | |
514 | struct perf_sample_data data; | |
515 | struct perf_event *event = NULL; | |
516 | struct pt_regs regs; | |
517 | int bit, n; | |
518 | ||
519 | if (!ds || !x86_pmu.pebs) | |
520 | return; | |
521 | ||
522 | intel_pmu_pebs_disable_all(); | |
523 | ||
524 | at = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base; | |
525 | top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index; | |
526 | ||
527 | if (top <= at) | |
528 | goto out; | |
529 | ||
530 | ds->pebs_index = ds->pebs_buffer_base; | |
531 | ||
532 | n = top - at; | |
533 | ||
534 | /* | |
535 | * Should not happen, we program the threshold at 1 and do not | |
536 | * set a reset value. | |
537 | */ | |
538 | WARN_ON_ONCE(n > MAX_PEBS_EVENTS); | |
539 | ||
540 | for ( ; at < top; at++) { | |
541 | for_each_bit(bit, (unsigned long *)&at->status, MAX_PEBS_EVENTS) { | |
542 | if (!cpuc->events[bit]->attr.precise) | |
543 | continue; | |
544 | ||
545 | event = cpuc->events[bit]; | |
546 | } | |
547 | ||
548 | if (!event) | |
549 | continue; | |
550 | ||
551 | if (!intel_pmu_save_and_restart(event)) | |
552 | continue; | |
553 | ||
554 | perf_sample_data_init(&data, 0); | |
555 | data.period = event->hw.last_period; | |
556 | ||
557 | /* | |
558 | * See the comment in intel_pmu_drain_pebs_core() | |
559 | */ | |
560 | regs = *iregs; | |
561 | regs.ip = at->ip; | |
562 | regs.bp = at->bp; | |
563 | regs.sp = at->sp; | |
564 | ||
ef21f683 PZ |
565 | if (intel_pmu_pebs_fixup_ip(®s)) |
566 | regs.flags |= PERF_EFLAGS_EXACT; | |
567 | else | |
568 | regs.flags &= ~PERF_EFLAGS_EXACT; | |
569 | ||
ca037701 PZ |
570 | if (perf_event_overflow(event, 1, &data, ®s)) |
571 | intel_pmu_disable_event(event); | |
572 | } | |
573 | out: | |
574 | intel_pmu_pebs_enable_all(); | |
575 | } | |
576 | ||
577 | /* | |
578 | * BTS, PEBS probe and setup | |
579 | */ | |
580 | ||
581 | static void intel_ds_init(void) | |
582 | { | |
583 | /* | |
584 | * No support for 32bit formats | |
585 | */ | |
586 | if (!boot_cpu_has(X86_FEATURE_DTES64)) | |
587 | return; | |
588 | ||
589 | x86_pmu.bts = boot_cpu_has(X86_FEATURE_BTS); | |
590 | x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS); | |
591 | if (x86_pmu.pebs) { | |
592 | int format = 0; | |
593 | ||
594 | if (x86_pmu.version > 1) { | |
595 | u64 capabilities; | |
596 | /* | |
597 | * v2+ has a PEBS format field | |
598 | */ | |
599 | rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities); | |
600 | format = (capabilities >> 8) & 0xf; | |
601 | } | |
602 | ||
603 | switch (format) { | |
604 | case 0: | |
605 | printk(KERN_CONT "PEBS v0, "); | |
606 | x86_pmu.pebs_record_size = sizeof(struct pebs_record_core); | |
607 | x86_pmu.drain_pebs = intel_pmu_drain_pebs_core; | |
608 | x86_pmu.pebs_constraints = intel_core_pebs_events; | |
609 | break; | |
610 | ||
611 | case 1: | |
612 | printk(KERN_CONT "PEBS v1, "); | |
613 | x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm); | |
614 | x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm; | |
615 | x86_pmu.pebs_constraints = intel_nehalem_pebs_events; | |
616 | break; | |
617 | ||
618 | default: | |
619 | printk(KERN_CONT "PEBS unknown format: %d, ", format); | |
620 | x86_pmu.pebs = 0; | |
621 | break; | |
622 | } | |
623 | } | |
624 | } | |
625 | ||
626 | #else /* CONFIG_CPU_SUP_INTEL */ | |
627 | ||
628 | static int reseve_ds_buffers(void) | |
629 | { | |
630 | return 0; | |
631 | } | |
632 | ||
633 | static void release_ds_buffers(void) | |
634 | { | |
635 | } | |
636 | ||
637 | #endif /* CONFIG_CPU_SUP_INTEL */ |