[deliverable/linux.git] / arch / x86 / kernel / cpu / perf_event_msr.c

#include <linux/perf_event.h>

enum perf_msr_id {
	PERF_MSR_TSC			= 0,
	PERF_MSR_APERF			= 1,
	PERF_MSR_MPERF			= 2,
	PERF_MSR_PPERF			= 3,
	PERF_MSR_SMI			= 4,

	PERF_MSR_EVENT_MAX,
};

bool test_aperfmperf(int idx)
{
	return boot_cpu_has(X86_FEATURE_APERFMPERF);
}

bool test_intel(int idx)
{
	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
	    boot_cpu_data.x86 != 6)
		return false;

	switch (boot_cpu_data.x86_model) {
	case 30: /* 45nm Nehalem    */
	case 26: /* 45nm Nehalem-EP */
	case 46: /* 45nm Nehalem-EX */

	case 37: /* 32nm Westmere    */
	case 44: /* 32nm Westmere-EP */
	case 47: /* 32nm Westmere-EX */

	case 42: /* 32nm SandyBridge         */
	case 45: /* 32nm SandyBridge-E/EN/EP */

	case 58: /* 22nm IvyBridge       */
	case 62: /* 22nm IvyBridge-EP/EX */

	case 60: /* 22nm Haswell Core */
	case 63: /* 22nm Haswell Server */
	case 69: /* 22nm Haswell ULT */
	case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */

	case 61: /* 14nm Broadwell Core-M */
	case 86: /* 14nm Broadwell Xeon D */
	case 71: /* 14nm Broadwell + GT3e (Intel Iris Pro graphics) */
	case 79: /* 14nm Broadwell Server */

	case 55: /* 22nm Atom "Silvermont"                */
	case 77: /* 22nm Atom "Silvermont Avoton/Rangely" */
	case 76: /* 14nm Atom "Airmont"                   */
		if (idx == PERF_MSR_SMI)
			return true;
		break;

	case 78: /* 14nm Skylake Mobile */
	case 94: /* 14nm Skylake Desktop */
		if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF)
			return true;
		break;
	}

	return false;
}

struct perf_msr {
	u64	msr;
	struct	perf_pmu_events_attr *attr;
	bool	(*test)(int idx);
};

PMU_EVENT_ATTR_STRING(tsc,   evattr_tsc,   "event=0x00");
PMU_EVENT_ATTR_STRING(aperf, evattr_aperf, "event=0x01");
PMU_EVENT_ATTR_STRING(mperf, evattr_mperf, "event=0x02");
PMU_EVENT_ATTR_STRING(pperf, evattr_pperf, "event=0x03");
PMU_EVENT_ATTR_STRING(smi,   evattr_smi,   "event=0x04");

static struct perf_msr msr[] = {
	[PERF_MSR_TSC]   = { 0,			&evattr_tsc,	NULL,		 },
	[PERF_MSR_APERF] = { MSR_IA32_APERF,	&evattr_aperf,	test_aperfmperf, },
	[PERF_MSR_MPERF] = { MSR_IA32_MPERF,	&evattr_mperf,	test_aperfmperf, },
	[PERF_MSR_PPERF] = { MSR_PPERF,		&evattr_pperf,	test_intel,	 },
	[PERF_MSR_SMI]   = { MSR_SMI_COUNT,	&evattr_smi,	test_intel,	 },
};

static struct attribute *events_attrs[PERF_MSR_EVENT_MAX + 1] = {
	NULL,
};

static struct attribute_group events_attr_group = {
	.name = "events",
	.attrs = events_attrs,
};

PMU_FORMAT_ATTR(event, "config:0-63");
static struct attribute *format_attrs[] = {
	&format_attr_event.attr,
	NULL,
};
static struct attribute_group format_attr_group = {
	.name = "format",
	.attrs = format_attrs,
};

static const struct attribute_group *attr_groups[] = {
	&events_attr_group,
	&format_attr_group,
	NULL,
};

static int msr_event_init(struct perf_event *event)
{
	u64 cfg = event->attr.config;

	if (event->attr.type != event->pmu->type)
		return -ENOENT;

	if (cfg >= PERF_MSR_EVENT_MAX)
		return -EINVAL;

	/* unsupported modes and filters */
	if (event->attr.exclude_user   ||
	    event->attr.exclude_kernel ||
	    event->attr.exclude_hv     ||
	    event->attr.exclude_idle   ||
	    event->attr.exclude_host   ||
	    event->attr.exclude_guest  ||
	    event->attr.sample_period) /* no sampling */
		return -EINVAL;

	if (!msr[cfg].attr)
		return -EINVAL;

	event->hw.idx = -1;
	event->hw.event_base = msr[cfg].msr;
	event->hw.config = cfg;

	return 0;
}

static inline u64 msr_read_counter(struct perf_event *event)
{
	u64 now;

	if (event->hw.event_base)
		rdmsrl(event->hw.event_base, now);
	else
		rdtscll(now);

	return now;
}
static void msr_event_update(struct perf_event *event)
{
	u64 prev, now;
	s64 delta;

	/* Careful, an NMI might modify the previous event value. */
again:
	prev = local64_read(&event->hw.prev_count);
	now = msr_read_counter(event);

	if (local64_cmpxchg(&event->hw.prev_count, prev, now) != prev)
		goto again;

	delta = now - prev;
	if (unlikely(event->hw.event_base == MSR_SMI_COUNT)) {
		delta <<= 32;
		delta >>= 32; /* sign extend */
	}
	local64_add(now - prev, &event->count);
}

static void msr_event_start(struct perf_event *event, int flags)
{
	u64 now;

	now = msr_read_counter(event);
	local64_set(&event->hw.prev_count, now);
}

static void msr_event_stop(struct perf_event *event, int flags)
{
	msr_event_update(event);
}

static void msr_event_del(struct perf_event *event, int flags)
{
	msr_event_stop(event, PERF_EF_UPDATE);
}

static int msr_event_add(struct perf_event *event, int flags)
{
	if (flags & PERF_EF_START)
		msr_event_start(event, flags);

	return 0;
}

static struct pmu pmu_msr = {
	.task_ctx_nr	= perf_sw_context,
	.attr_groups	= attr_groups,
	.event_init	= msr_event_init,
	.add		= msr_event_add,
	.del		= msr_event_del,
	.start		= msr_event_start,
	.stop		= msr_event_stop,
	.read		= msr_event_update,
	.capabilities	= PERF_PMU_CAP_NO_INTERRUPT,
};

static int __init msr_init(void)
{
	int i, j = 0;

	if (!boot_cpu_has(X86_FEATURE_TSC)) {
		pr_cont("no MSR PMU driver.\n");
		return 0;
	}

	/* Probe the MSRs. */
	for (i = PERF_MSR_TSC + 1; i < PERF_MSR_EVENT_MAX; i++) {
		u64 val;

		/*
		 * Virt sucks arse; you cannot tell if a R/O MSR is present :/
		 */
		if (!msr[i].test(i) || rdmsrl_safe(msr[i].msr, &val))
			msr[i].attr = NULL;
	}

	/* List remaining MSRs in the sysfs attrs. */
	for (i = 0; i < PERF_MSR_EVENT_MAX; i++) {
		if (msr[i].attr)
			events_attrs[j++] = &msr[i].attr->attr.attr;
	}
	events_attrs[j] = NULL;

	perf_pmu_register(&pmu_msr, "msr", -1);

	return 0;
}
device_initcall(msr_init);
Commit	Line	Data
b7b7c782 AL	1	#include <linux/perf_event.h>
	2
	3	enum perf_msr_id {
	4	PERF_MSR_TSC = 0,
	5	PERF_MSR_APERF = 1,
	6	PERF_MSR_MPERF = 2,
	7	PERF_MSR_PPERF = 3,
	8	PERF_MSR_SMI = 4,
	9
	10	PERF_MSR_EVENT_MAX,
	11	};
	12
19b3340c PZ	13	bool test_aperfmperf(int idx)
	14	{
	15	return boot_cpu_has(X86_FEATURE_APERFMPERF);
	16	}
	17
	18	bool test_intel(int idx)
	19	{
	20	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL \|\|
	21	boot_cpu_data.x86 != 6)
	22	return false;
	23
	24	switch (boot_cpu_data.x86_model) {
	25	case 30: /* 45nm Nehalem */
	26	case 26: /* 45nm Nehalem-EP */
	27	case 46: /* 45nm Nehalem-EX */
	28
	29	case 37: /* 32nm Westmere */
	30	case 44: /* 32nm Westmere-EP */
	31	case 47: /* 32nm Westmere-EX */
	32
	33	case 42: /* 32nm SandyBridge */
	34	case 45: /* 32nm SandyBridge-E/EN/EP */
	35
	36	case 58: /* 22nm IvyBridge */
	37	case 62: /* 22nm IvyBridge-EP/EX */
	38
	39	case 60: /* 22nm Haswell Core */
	40	case 63: /* 22nm Haswell Server */
	41	case 69: /* 22nm Haswell ULT */
	42	case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */
	43
	44	case 61: /* 14nm Broadwell Core-M */
	45	case 86: /* 14nm Broadwell Xeon D */
	46	case 71: /* 14nm Broadwell + GT3e (Intel Iris Pro graphics) */
	47	case 79: /* 14nm Broadwell Server */
	48
	49	case 55: /* 22nm Atom "Silvermont" */
	50	case 77: /* 22nm Atom "Silvermont Avoton/Rangely" */
	51	case 76: /* 14nm Atom "Airmont" */
	52	if (idx == PERF_MSR_SMI)
	53	return true;
	54	break;
	55
	56	case 78: /* 14nm Skylake Mobile */
	57	case 94: /* 14nm Skylake Desktop */
	58	if (idx == PERF_MSR_SMI \|\| idx == PERF_MSR_PPERF)
	59	return true;
	60	break;
	61	}
	62
	63	return false;
	64	}
	65
b7b7c782	66	struct perf_msr {
b7b7c782	67	u64 msr;
19b3340c PZ	68	struct perf_pmu_events_attr *attr;
19b3340c PZ	69	bool (*test)(int idx);
b7b7c782 AL	70	};
	71
	72	PMU_EVENT_ATTR_STRING(tsc, evattr_tsc, "event=0x00");
	73	PMU_EVENT_ATTR_STRING(aperf, evattr_aperf, "event=0x01");
	74	PMU_EVENT_ATTR_STRING(mperf, evattr_mperf, "event=0x02");
	75	PMU_EVENT_ATTR_STRING(pperf, evattr_pperf, "event=0x03");
	76	PMU_EVENT_ATTR_STRING(smi, evattr_smi, "event=0x04");
	77
19b3340c PZ	78	static struct perf_msr msr[] = {
	79	[PERF_MSR_TSC] = { 0, &evattr_tsc, NULL, },
	80	[PERF_MSR_APERF] = { MSR_IA32_APERF, &evattr_aperf, test_aperfmperf, },
	81	[PERF_MSR_MPERF] = { MSR_IA32_MPERF, &evattr_mperf, test_aperfmperf, },
	82	[PERF_MSR_PPERF] = { MSR_PPERF, &evattr_pperf, test_intel, },
	83	[PERF_MSR_SMI] = { MSR_SMI_COUNT, &evattr_smi, test_intel, },
	84	};
	85
b7b7c782	86	static struct attribute *events_attrs[PERF_MSR_EVENT_MAX + 1] = {
19b3340c	87	NULL,
b7b7c782 AL	88	};
	89
	90	static struct attribute_group events_attr_group = {
	91	.name = "events",
	92	.attrs = events_attrs,
	93	};
	94
	95	PMU_FORMAT_ATTR(event, "config:0-63");
	96	static struct attribute *format_attrs[] = {
	97	&format_attr_event.attr,
	98	NULL,
	99	};
	100	static struct attribute_group format_attr_group = {
	101	.name = "format",
	102	.attrs = format_attrs,
	103	};
	104
	105	static const struct attribute_group *attr_groups[] = {
	106	&events_attr_group,
	107	&format_attr_group,
	108	NULL,
	109	};
	110
	111	static int msr_event_init(struct perf_event *event)
	112	{
	113	u64 cfg = event->attr.config;
	114
	115	if (event->attr.type != event->pmu->type)
	116	return -ENOENT;
	117
	118	if (cfg >= PERF_MSR_EVENT_MAX)
	119	return -EINVAL;
	120
	121	/* unsupported modes and filters */
	122	if (event->attr.exclude_user \|\|
	123	event->attr.exclude_kernel \|\|
	124	event->attr.exclude_hv \|\|
	125	event->attr.exclude_idle \|\|
	126	event->attr.exclude_host \|\|
	127	event->attr.exclude_guest \|\|
	128	event->attr.sample_period) /* no sampling */
	129	return -EINVAL;
	130
19b3340c PZ	131	if (!msr[cfg].attr)
	132	return -EINVAL;
	133
b7b7c782 AL	134	event->hw.idx = -1;
	135	event->hw.event_base = msr[cfg].msr;
	136	event->hw.config = cfg;
	137
	138	return 0;
	139	}
	140
	141	static inline u64 msr_read_counter(struct perf_event *event)
	142	{
	143	u64 now;
	144
	145	if (event->hw.event_base)
	146	rdmsrl(event->hw.event_base, now);
	147	else
82819ffb	148	rdtscll(now);
b7b7c782 AL	149
	150	return now;
	151	}
	152	static void msr_event_update(struct perf_event *event)
	153	{
	154	u64 prev, now;
	155	s64 delta;
	156
	157	/* Careful, an NMI might modify the previous event value. */
	158	again:
	159	prev = local64_read(&event->hw.prev_count);
	160	now = msr_read_counter(event);
	161
	162	if (local64_cmpxchg(&event->hw.prev_count, prev, now) != prev)
	163	goto again;
	164
	165	delta = now - prev;
	166	if (unlikely(event->hw.event_base == MSR_SMI_COUNT)) {
	167	delta <<= 32;
	168	delta >>= 32; /* sign extend */
	169	}
	170	local64_add(now - prev, &event->count);
	171	}
	172
	173	static void msr_event_start(struct perf_event *event, int flags)
	174	{
	175	u64 now;
	176
	177	now = msr_read_counter(event);
	178	local64_set(&event->hw.prev_count, now);
	179	}
	180
	181	static void msr_event_stop(struct perf_event *event, int flags)
	182	{
	183	msr_event_update(event);
	184	}
	185
	186	static void msr_event_del(struct perf_event *event, int flags)
	187	{
	188	msr_event_stop(event, PERF_EF_UPDATE);
	189	}
	190
	191	static int msr_event_add(struct perf_event *event, int flags)
	192	{
	193	if (flags & PERF_EF_START)
	194	msr_event_start(event, flags);
	195
	196	return 0;
	197	}
	198
	199	static struct pmu pmu_msr = {
	200	.task_ctx_nr = perf_sw_context,
	201	.attr_groups = attr_groups,
	202	.event_init = msr_event_init,
	203	.add = msr_event_add,
	204	.del = msr_event_del,
	205	.start = msr_event_start,
	206	.stop = msr_event_stop,
	207	.read = msr_event_update,
	208	.capabilities = PERF_PMU_CAP_NO_INTERRUPT,
	209	};
	210
b7b7c782 AL	211	static int __init msr_init(void)
b7b7c782 AL	212	{
19b3340c	213	int i, j = 0;
b7b7c782	214
19b3340c PZ	215	if (!boot_cpu_has(X86_FEATURE_TSC)) {
	216	pr_cont("no MSR PMU driver.\n");
	217	return 0;
b7b7c782 AL	218	}
b7b7c782 AL	219
19b3340c PZ	220	/* Probe the MSRs. */
	221	for (i = PERF_MSR_TSC + 1; i < PERF_MSR_EVENT_MAX; i++) {
	222	u64 val;
b7b7c782	223
19b3340c PZ	224	/*
	225	* Virt sucks arse; you cannot tell if a R/O MSR is present :/
	226	*/
	227	if (!msr[i].test(i) \|\| rdmsrl_safe(msr[i].msr, &val))
	228	msr[i].attr = NULL;
b7b7c782 AL	229	}
b7b7c782 AL	230
19b3340c PZ	231	/* List remaining MSRs in the sysfs attrs. */
	232	for (i = 0; i < PERF_MSR_EVENT_MAX; i++) {
	233	if (msr[i].attr)
	234	events_attrs[j++] = &msr[i].attr->attr.attr;
b7b7c782	235	}
19b3340c	236	events_attrs[j] = NULL;
b7b7c782 AL	237
	238	perf_pmu_register(&pmu_msr, "msr", -1);
	239
	240	return 0;
	241	}
	242	device_initcall(msr_init);