[deliverable/linux.git] / arch / x86 / kernel / devicetree.c

/*
 * Architecture specific OF callbacks.
 */
#include <linux/bootmem.h>
#include <linux/export.h>
#include <linux/io.h>
#include <linux/irqdomain.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/of.h>
#include <linux/of_fdt.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/of_irq.h>
#include <linux/slab.h>
#include <linux/pci.h>
#include <linux/of_pci.h>
#include <linux/initrd.h>

#include <asm/hpet.h>
#include <asm/apic.h>
#include <asm/pci_x86.h>

__initdata u64 initial_dtb;
char __initdata cmd_line[COMMAND_LINE_SIZE];

int __initdata of_ioapic;

unsigned long pci_address_to_pio(phys_addr_t address)
{
	/*
	 * The ioport address can be directly used by inX / outX
	 */
	BUG_ON(address >= (1 << 16));
	return (unsigned long)address;
}
EXPORT_SYMBOL_GPL(pci_address_to_pio);

void __init early_init_dt_scan_chosen_arch(unsigned long node)
{
	BUG();
}

void __init early_init_dt_add_memory_arch(u64 base, u64 size)
{
	BUG();
}

void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
{
	return __alloc_bootmem(size, align, __pa(MAX_DMA_ADDRESS));
}

void __init add_dtb(u64 data)
{
	initial_dtb = data + offsetof(struct setup_data, data);
}

/*
 * CE4100 ids. Will be moved to machine_device_initcall() once we have it.
 */
static struct of_device_id __initdata ce4100_ids[] = {
	{ .compatible = "intel,ce4100-cp", },
	{ .compatible = "isa", },
	{ .compatible = "pci", },
	{},
};

static int __init add_bus_probe(void)
{
	if (!of_have_populated_dt())
		return 0;

	return of_platform_bus_probe(NULL, ce4100_ids, NULL);
}
module_init(add_bus_probe);

#ifdef CONFIG_PCI
struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
{
	struct device_node *np;

	for_each_node_by_type(np, "pci") {
		const void *prop;
		unsigned int bus_min;

		prop = of_get_property(np, "bus-range", NULL);
		if (!prop)
			continue;
		bus_min = be32_to_cpup(prop);
		if (bus->number == bus_min)
			return np;
	}
	return NULL;
}

static int x86_of_pci_irq_enable(struct pci_dev *dev)
{
	struct of_irq oirq;
	u32 virq;
	int ret;
	u8 pin;

	ret = pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
	if (ret)
		return ret;
	if (!pin)
		return 0;

	ret = of_irq_map_pci(dev, &oirq);
	if (ret)
		return ret;

	virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
			oirq.size);
	if (virq == 0)
		return -EINVAL;
	dev->irq = virq;
	return 0;
}

static void x86_of_pci_irq_disable(struct pci_dev *dev)
{
}

void x86_of_pci_init(void)
{
	pcibios_enable_irq = x86_of_pci_irq_enable;
	pcibios_disable_irq = x86_of_pci_irq_disable;
}
#endif

static void __init dtb_setup_hpet(void)
{
#ifdef CONFIG_HPET_TIMER
	struct device_node *dn;
	struct resource r;
	int ret;

	dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-hpet");
	if (!dn)
		return;
	ret = of_address_to_resource(dn, 0, &r);
	if (ret) {
		WARN_ON(1);
		return;
	}
	hpet_address = r.start;
#endif
}

static void __init dtb_lapic_setup(void)
{
#ifdef CONFIG_X86_LOCAL_APIC
	struct device_node *dn;
	struct resource r;
	int ret;

	dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-lapic");
	if (!dn)
		return;

	ret = of_address_to_resource(dn, 0, &r);
	if (WARN_ON(ret))
		return;

	/* Did the boot loader setup the local APIC ? */
	if (!cpu_has_apic) {
		if (apic_force_enable(r.start))
			return;
	}
	smp_found_config = 1;
	pic_mode = 1;
	register_lapic_address(r.start);
	generic_processor_info(boot_cpu_physical_apicid,
			       GET_APIC_VERSION(apic_read(APIC_LVR)));
#endif
}

#ifdef CONFIG_X86_IO_APIC
static unsigned int ioapic_id;

static void __init dtb_add_ioapic(struct device_node *dn)
{
	struct resource r;
	int ret;

	ret = of_address_to_resource(dn, 0, &r);
	if (ret) {
		printk(KERN_ERR "Can't obtain address from node %s.\n",
				dn->full_name);
		return;
	}
	mp_register_ioapic(++ioapic_id, r.start, gsi_top);
}

static void __init dtb_ioapic_setup(void)
{
	struct device_node *dn;

	for_each_compatible_node(dn, NULL, "intel,ce4100-ioapic")
		dtb_add_ioapic(dn);

	if (nr_ioapics) {
		of_ioapic = 1;
		return;
	}
	printk(KERN_ERR "Error: No information about IO-APIC in OF.\n");
}
#else
static void __init dtb_ioapic_setup(void) {}
#endif

static void __init dtb_apic_setup(void)
{
	dtb_lapic_setup();
	dtb_ioapic_setup();
}

#ifdef CONFIG_OF_FLATTREE
static void __init x86_flattree_get_config(void)
{
	u32 size, map_len;
	struct boot_param_header *dt;

	if (!initial_dtb)
		return;

	map_len = max(PAGE_SIZE - (initial_dtb & ~PAGE_MASK),
			(u64)sizeof(struct boot_param_header));

	dt = early_memremap(initial_dtb, map_len);
	size = be32_to_cpu(dt->totalsize);
	if (map_len < size) {
		early_iounmap(dt, map_len);
		dt = early_memremap(initial_dtb, size);
		map_len = size;
	}

	initial_boot_params = dt;
	unflatten_and_copy_device_tree();
	early_iounmap(dt, map_len);
}
#else
static inline void x86_flattree_get_config(void) { }
#endif

void __init x86_dtb_init(void)
{
	x86_flattree_get_config();

	if (!of_have_populated_dt())
		return;

	dtb_setup_hpet();
	dtb_apic_setup();
}

#ifdef CONFIG_X86_IO_APIC

struct of_ioapic_type {
	u32 out_type;
	u32 trigger;
	u32 polarity;
};

static struct of_ioapic_type of_ioapic_type[] =
{
	{
		.out_type	= IRQ_TYPE_EDGE_RISING,
		.trigger	= IOAPIC_EDGE,
		.polarity	= 1,
	},
	{
		.out_type	= IRQ_TYPE_LEVEL_LOW,
		.trigger	= IOAPIC_LEVEL,
		.polarity	= 0,
	},
	{
		.out_type	= IRQ_TYPE_LEVEL_HIGH,
		.trigger	= IOAPIC_LEVEL,
		.polarity	= 1,
	},
	{
		.out_type	= IRQ_TYPE_EDGE_FALLING,
		.trigger	= IOAPIC_EDGE,
		.polarity	= 0,
	},
};

static int ioapic_xlate(struct irq_domain *domain,
			struct device_node *controller,
			const u32 *intspec, u32 intsize,
			irq_hw_number_t *out_hwirq, u32 *out_type)
{
	struct io_apic_irq_attr attr;
	struct of_ioapic_type *it;
	u32 line, idx;
	int rc;

	if (WARN_ON(intsize < 2))
		return -EINVAL;

	line = intspec[0];

	if (intspec[1] >= ARRAY_SIZE(of_ioapic_type))
		return -EINVAL;

	it = &of_ioapic_type[intspec[1]];

	idx = (u32) domain->host_data;
	set_io_apic_irq_attr(&attr, idx, line, it->trigger, it->polarity);

	rc = io_apic_setup_irq_pin_once(irq_find_mapping(domain, line),
					cpu_to_node(0), &attr);
	if (rc)
		return rc;

	*out_hwirq = line;
	*out_type = it->out_type;
	return 0;
}

const struct irq_domain_ops ioapic_irq_domain_ops = {
	.xlate = ioapic_xlate,
};

static void dt_add_ioapic_domain(unsigned int ioapic_num,
		struct device_node *np)
{
	struct irq_domain *id;
	struct mp_ioapic_gsi *gsi_cfg;
	int ret;
	int num;

	gsi_cfg = mp_ioapic_gsi_routing(ioapic_num);
	num = gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1;

	id = irq_domain_add_linear(np, num, &ioapic_irq_domain_ops,
			(void *)ioapic_num);
	BUG_ON(!id);
	if (gsi_cfg->gsi_base == 0) {
		/*
		 * The first NR_IRQS_LEGACY irq descs are allocated in
		 * early_irq_init() and need just a mapping. The
		 * remaining irqs need both. All of them are preallocated
		 * and assigned so we can keep the 1:1 mapping which the ioapic
		 * is having.
		 */
		irq_domain_associate_many(id, 0, 0, NR_IRQS_LEGACY);

		if (num > NR_IRQS_LEGACY) {
			ret = irq_create_strict_mappings(id, NR_IRQS_LEGACY,
					NR_IRQS_LEGACY, num - NR_IRQS_LEGACY);
			if (ret)
				pr_err("Error creating mapping for the "
						"remaining IRQs: %d\n", ret);
		}
		irq_set_default_host(id);
	} else {
		ret = irq_create_strict_mappings(id, gsi_cfg->gsi_base, 0, num);
		if (ret)
			pr_err("Error creating IRQ mapping: %d\n", ret);
	}
}

static void __init ioapic_add_ofnode(struct device_node *np)
{
	struct resource r;
	int i, ret;

	ret = of_address_to_resource(np, 0, &r);
	if (ret) {
		printk(KERN_ERR "Failed to obtain address for %s\n",
				np->full_name);
		return;
	}

	for (i = 0; i < nr_ioapics; i++) {
		if (r.start == mpc_ioapic_addr(i)) {
			dt_add_ioapic_domain(i, np);
			return;
		}
	}
	printk(KERN_ERR "IOxAPIC at %s is not registered.\n", np->full_name);
}

void __init x86_add_irq_domains(void)
{
	struct device_node *dp;

	if (!of_have_populated_dt())
		return;

	for_each_node_with_property(dp, "interrupt-controller") {
		if (of_device_is_compatible(dp, "intel,ce4100-ioapic"))
			ioapic_add_ofnode(dp);
	}
}
#else
void __init x86_add_irq_domains(void) { }
#endif
Commit	Line	Data
da6b737b SAS	1	/*
	2	* Architecture specific OF callbacks.
	3	*/
	4	#include <linux/bootmem.h>
69c60c88	5	#include <linux/export.h>
da6b737b	6	#include <linux/io.h>
b4e51854	7	#include <linux/irqdomain.h>
19c4f5f7	8	#include <linux/interrupt.h>
da6b737b SAS	9	#include <linux/list.h>
	10	#include <linux/of.h>
	11	#include <linux/of_fdt.h>
3879a6f3	12	#include <linux/of_address.h>
da6b737b	13	#include <linux/of_platform.h>
96e0a079	14	#include <linux/of_irq.h>
da6b737b	15	#include <linux/slab.h>
96e0a079 SAS	16	#include <linux/pci.h>
96e0a079 SAS	17	#include <linux/of_pci.h>
977cb76d	18	#include <linux/initrd.h>
da6b737b	19
ffb9fc68	20	#include <asm/hpet.h>
3879a6f3	21	#include <asm/apic.h>
96e0a079	22	#include <asm/pci_x86.h>
19c4f5f7	23
3879a6f3	24	__initdata u64 initial_dtb;
da6b737b	25	char __initdata cmd_line[COMMAND_LINE_SIZE];
19c4f5f7	26
3879a6f3 SAS	27	int __initdata of_ioapic;
3879a6f3 SAS	28
da6b737b SAS	29	unsigned long pci_address_to_pio(phys_addr_t address)
	30	{
	31	/*
	32	* The ioport address can be directly used by inX / outX
	33	*/
	34	BUG_ON(address >= (1 << 16));
	35	return (unsigned long)address;
	36	}
	37	EXPORT_SYMBOL_GPL(pci_address_to_pio);
	38
	39	void __init early_init_dt_scan_chosen_arch(unsigned long node)
	40	{
	41	BUG();
	42	}
	43
	44	void __init early_init_dt_add_memory_arch(u64 base, u64 size)
	45	{
	46	BUG();
	47	}
	48
	49	void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
	50	{
	51	return __alloc_bootmem(size, align, __pa(MAX_DMA_ADDRESS));
	52	}
	53
	54	void __init add_dtb(u64 data)
	55	{
3879a6f3 SAS	56	initial_dtb = data + offsetof(struct setup_data, data);
	57	}
	58
9079b353 SAS	59	/*
	60	* CE4100 ids. Will be moved to machine_device_initcall() once we have it.
	61	*/
	62	static struct of_device_id __initdata ce4100_ids[] = {
	63	{ .compatible = "intel,ce4100-cp", },
	64	{ .compatible = "isa", },
	65	{ .compatible = "pci", },
	66	{},
	67	};
	68
	69	static int __init add_bus_probe(void)
	70	{
4a66b1d9	71	if (!of_have_populated_dt())
9079b353 SAS	72	return 0;
	73
	74	return of_platform_bus_probe(NULL, ce4100_ids, NULL);
	75	}
	76	module_init(add_bus_probe);
	77
96e0a079	78	#ifdef CONFIG_PCI
3d5fe5a6 BH	79	struct device_node pcibios_get_phb_of_node(struct pci_bus bus)
	80	{
	81	struct device_node *np;
	82
	83	for_each_node_by_type(np, "pci") {
	84	const void *prop;
	85	unsigned int bus_min;
	86
	87	prop = of_get_property(np, "bus-range", NULL);
	88	if (!prop)
	89	continue;
	90	bus_min = be32_to_cpup(prop);
	91	if (bus->number == bus_min)
	92	return np;
	93	}
	94	return NULL;
	95	}
	96
96e0a079 SAS	97	static int x86_of_pci_irq_enable(struct pci_dev *dev)
	98	{
	99	struct of_irq oirq;
	100	u32 virq;
	101	int ret;
	102	u8 pin;
	103
	104	ret = pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
	105	if (ret)
	106	return ret;
	107	if (!pin)
	108	return 0;
	109
	110	ret = of_irq_map_pci(dev, &oirq);
	111	if (ret)
	112	return ret;
	113
	114	virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
	115	oirq.size);
	116	if (virq == 0)
	117	return -EINVAL;
	118	dev->irq = virq;
	119	return 0;
	120	}
	121
	122	static void x86_of_pci_irq_disable(struct pci_dev *dev)
	123	{
	124	}
	125
148f9bb8	126	void x86_of_pci_init(void)
96e0a079	127	{
96e0a079 SAS	128	pcibios_enable_irq = x86_of_pci_irq_enable;
96e0a079 SAS	129	pcibios_disable_irq = x86_of_pci_irq_disable;
96e0a079 SAS	130	}
	131	#endif
	132
ffb9fc68 SAS	133	static void __init dtb_setup_hpet(void)
ffb9fc68 SAS	134	{
4a66b1d9	135	#ifdef CONFIG_HPET_TIMER
ffb9fc68 SAS	136	struct device_node *dn;
	137	struct resource r;
	138	int ret;
	139
	140	dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-hpet");
	141	if (!dn)
	142	return;
	143	ret = of_address_to_resource(dn, 0, &r);
	144	if (ret) {
	145	WARN_ON(1);
	146	return;
	147	}
	148	hpet_address = r.start;
4a66b1d9	149	#endif
ffb9fc68 SAS	150	}
ffb9fc68 SAS	151
3879a6f3 SAS	152	static void __init dtb_lapic_setup(void)
	153	{
	154	#ifdef CONFIG_X86_LOCAL_APIC
a906fdaa TG	155	struct device_node *dn;
	156	struct resource r;
	157	int ret;
	158
	159	dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-lapic");
	160	if (!dn)
3879a6f3 SAS	161	return;
3879a6f3 SAS	162
a906fdaa TG	163	ret = of_address_to_resource(dn, 0, &r);
	164	if (WARN_ON(ret))
	165	return;
	166
	167	/* Did the boot loader setup the local APIC ? */
	168	if (!cpu_has_apic) {
	169	if (apic_force_enable(r.start))
	170	return;
	171	}
3879a6f3 SAS	172	smp_found_config = 1;
3879a6f3 SAS	173	pic_mode = 1;
a906fdaa	174	register_lapic_address(r.start);
3879a6f3	175	generic_processor_info(boot_cpu_physical_apicid,
a906fdaa	176	GET_APIC_VERSION(apic_read(APIC_LVR)));
3879a6f3 SAS	177	#endif
	178	}
	179
	180	#ifdef CONFIG_X86_IO_APIC
	181	static unsigned int ioapic_id;
	182
	183	static void __init dtb_add_ioapic(struct device_node *dn)
	184	{
	185	struct resource r;
	186	int ret;
	187
	188	ret = of_address_to_resource(dn, 0, &r);
	189	if (ret) {
	190	printk(KERN_ERR "Can't obtain address from node %s.\n",
	191	dn->full_name);
	192	return;
	193	}
	194	mp_register_ioapic(++ioapic_id, r.start, gsi_top);
	195	}
	196
	197	static void __init dtb_ioapic_setup(void)
	198	{
	199	struct device_node *dn;
	200
3879a6f3 SAS	201	for_each_compatible_node(dn, NULL, "intel,ce4100-ioapic")
	202	dtb_add_ioapic(dn);
	203
	204	if (nr_ioapics) {
	205	of_ioapic = 1;
	206	return;
	207	}
	208	printk(KERN_ERR "Error: No information about IO-APIC in OF.\n");
3879a6f3 SAS	209	}
	210	#else
	211	static void __init dtb_ioapic_setup(void) {}
	212	#endif
	213
	214	static void __init dtb_apic_setup(void)
	215	{
	216	dtb_lapic_setup();
	217	dtb_ioapic_setup();
	218	}
	219
4a66b1d9 SAS	220	#ifdef CONFIG_OF_FLATTREE
4a66b1d9 SAS	221	static void __init x86_flattree_get_config(void)
3879a6f3 SAS	222	{
3879a6f3 SAS	223	u32 size, map_len;
21c561bd	224	struct boot_param_header *dt;
3879a6f3 SAS	225
	226	if (!initial_dtb)
	227	return;
	228
	229	map_len = max(PAGE_SIZE - (initial_dtb & ~PAGE_MASK),
	230	(u64)sizeof(struct boot_param_header));
	231
21c561bd RH	232	dt = early_memremap(initial_dtb, map_len);
21c561bd RH	233	size = be32_to_cpu(dt->totalsize);
3879a6f3	234	if (map_len < size) {
21c561bd RH	235	early_iounmap(dt, map_len);
21c561bd RH	236	dt = early_memremap(initial_dtb, size);
3879a6f3 SAS	237	map_len = size;
	238	}
	239
21c561bd RH	240	initial_boot_params = dt;
	241	unflatten_and_copy_device_tree();
	242	early_iounmap(dt, map_len);
4a66b1d9 SAS	243	}
	244	#else
	245	static inline void x86_flattree_get_config(void) { }
	246	#endif
	247
a906fdaa	248	void __init x86_dtb_init(void)
4a66b1d9 SAS	249	{
	250	x86_flattree_get_config();
	251
	252	if (!of_have_populated_dt())
	253	return;
	254
ffb9fc68	255	dtb_setup_hpet();
3879a6f3	256	dtb_apic_setup();
da6b737b	257	}
bcc7c124 SAS	258
	259	#ifdef CONFIG_X86_IO_APIC
	260
	261	struct of_ioapic_type {
	262	u32 out_type;
	263	u32 trigger;
	264	u32 polarity;
	265	};
	266
	267	static struct of_ioapic_type of_ioapic_type[] =
	268	{
	269	{
	270	.out_type = IRQ_TYPE_EDGE_RISING,
	271	.trigger = IOAPIC_EDGE,
	272	.polarity = 1,
	273	},
	274	{
	275	.out_type = IRQ_TYPE_LEVEL_LOW,
	276	.trigger = IOAPIC_LEVEL,
	277	.polarity = 0,
	278	},
	279	{
	280	.out_type = IRQ_TYPE_LEVEL_HIGH,
	281	.trigger = IOAPIC_LEVEL,
	282	.polarity = 1,
	283	},
	284	{
	285	.out_type = IRQ_TYPE_EDGE_FALLING,
	286	.trigger = IOAPIC_EDGE,
	287	.polarity = 0,
	288	},
	289	};
	290
b4e51854 GL	291	static int ioapic_xlate(struct irq_domain *domain,
	292	struct device_node *controller,
	293	const u32 *intspec, u32 intsize,
	294	irq_hw_number_t out_hwirq, u32 out_type)
bcc7c124 SAS	295	{
	296	struct io_apic_irq_attr attr;
	297	struct of_ioapic_type *it;
b4e51854 GL	298	u32 line, idx;
b4e51854 GL	299	int rc;
bcc7c124	300
b4e51854	301	if (WARN_ON(intsize < 2))
bcc7c124 SAS	302	return -EINVAL;
bcc7c124 SAS	303
b4e51854	304	line = intspec[0];
bcc7c124	305
b4e51854	306	if (intspec[1] >= ARRAY_SIZE(of_ioapic_type))
bcc7c124 SAS	307	return -EINVAL;
bcc7c124 SAS	308
b4e51854	309	it = &of_ioapic_type[intspec[1]];
bcc7c124	310
b4e51854	311	idx = (u32) domain->host_data;
bcc7c124 SAS	312	set_io_apic_irq_attr(&attr, idx, line, it->trigger, it->polarity);
bcc7c124 SAS	313
b4e51854 GL	314	rc = io_apic_setup_irq_pin_once(irq_find_mapping(domain, line),
	315	cpu_to_node(0), &attr);
	316	if (rc)
	317	return rc;
	318
	319	*out_hwirq = line;
	320	*out_type = it->out_type;
	321	return 0;
bcc7c124 SAS	322	}
bcc7c124 SAS	323
b4e51854 GL	324	const struct irq_domain_ops ioapic_irq_domain_ops = {
	325	.xlate = ioapic_xlate,
	326	};
	327
ece3234a SAS	328	static void dt_add_ioapic_domain(unsigned int ioapic_num,
	329	struct device_node *np)
	330	{
	331	struct irq_domain *id;
	332	struct mp_ioapic_gsi *gsi_cfg;
	333	int ret;
	334	int num;
	335
	336	gsi_cfg = mp_ioapic_gsi_routing(ioapic_num);
	337	num = gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1;
	338
	339	id = irq_domain_add_linear(np, num, &ioapic_irq_domain_ops,
	340	(void *)ioapic_num);
	341	BUG_ON(!id);
	342	if (gsi_cfg->gsi_base == 0) {
	343	/*
	344	* The first NR_IRQS_LEGACY irq descs are allocated in
	345	* early_irq_init() and need just a mapping. The
	346	* remaining irqs need both. All of them are preallocated
	347	* and assigned so we can keep the 1:1 mapping which the ioapic
	348	* is having.
	349	*/
ddaf144c	350	irq_domain_associate_many(id, 0, 0, NR_IRQS_LEGACY);
ece3234a SAS	351
	352	if (num > NR_IRQS_LEGACY) {
	353	ret = irq_create_strict_mappings(id, NR_IRQS_LEGACY,
	354	NR_IRQS_LEGACY, num - NR_IRQS_LEGACY);
	355	if (ret)
	356	pr_err("Error creating mapping for the "
	357	"remaining IRQs: %d\n", ret);
	358	}
	359	irq_set_default_host(id);
	360	} else {
	361	ret = irq_create_strict_mappings(id, gsi_cfg->gsi_base, 0, num);
	362	if (ret)
	363	pr_err("Error creating IRQ mapping: %d\n", ret);
	364	}
	365	}
	366
bcc7c124 SAS	367	static void __init ioapic_add_ofnode(struct device_node *np)
	368	{
	369	struct resource r;
	370	int i, ret;
	371
	372	ret = of_address_to_resource(np, 0, &r);
	373	if (ret) {
	374	printk(KERN_ERR "Failed to obtain address for %s\n",
	375	np->full_name);
	376	return;
	377	}
	378
	379	for (i = 0; i < nr_ioapics; i++) {
d5371430	380	if (r.start == mpc_ioapic_addr(i)) {
ece3234a	381	dt_add_ioapic_domain(i, np);
bcc7c124 SAS	382	return;
	383	}
	384	}
	385	printk(KERN_ERR "IOxAPIC at %s is not registered.\n", np->full_name);
	386	}
	387
	388	void __init x86_add_irq_domains(void)
	389	{
	390	struct device_node *dp;
	391
4a66b1d9	392	if (!of_have_populated_dt())
bcc7c124 SAS	393	return;
	394
	395	for_each_node_with_property(dp, "interrupt-controller") {
	396	if (of_device_is_compatible(dp, "intel,ce4100-ioapic"))
	397	ioapic_add_ofnode(dp);
	398	}
	399	}
	400	#else
	401	void __init x86_add_irq_domains(void) { }
	402	#endif