x86: don't use module_init in non-modular intel_mid_vrtc.c
[deliverable/linux.git] / arch / x86 / kernel / devicetree.c
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da6b737b
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1/*
2 * Architecture specific OF callbacks.
3 */
4#include <linux/bootmem.h>
69c60c88 5#include <linux/export.h>
da6b737b 6#include <linux/io.h>
b4e51854 7#include <linux/irqdomain.h>
19c4f5f7 8#include <linux/interrupt.h>
da6b737b
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9#include <linux/list.h>
10#include <linux/of.h>
11#include <linux/of_fdt.h>
3879a6f3 12#include <linux/of_address.h>
da6b737b 13#include <linux/of_platform.h>
96e0a079 14#include <linux/of_irq.h>
da6b737b 15#include <linux/slab.h>
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16#include <linux/pci.h>
17#include <linux/of_pci.h>
977cb76d 18#include <linux/initrd.h>
da6b737b 19
ffb9fc68 20#include <asm/hpet.h>
3879a6f3 21#include <asm/apic.h>
96e0a079 22#include <asm/pci_x86.h>
ba904f06 23#include <asm/setup.h>
95d76acc 24#include <asm/i8259.h>
19c4f5f7 25
3879a6f3 26__initdata u64 initial_dtb;
da6b737b 27char __initdata cmd_line[COMMAND_LINE_SIZE];
19c4f5f7 28
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29int __initdata of_ioapic;
30
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31void __init early_init_dt_scan_chosen_arch(unsigned long node)
32{
33 BUG();
34}
35
36void __init early_init_dt_add_memory_arch(u64 base, u64 size)
37{
38 BUG();
39}
40
41void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
42{
43 return __alloc_bootmem(size, align, __pa(MAX_DMA_ADDRESS));
44}
45
46void __init add_dtb(u64 data)
47{
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48 initial_dtb = data + offsetof(struct setup_data, data);
49}
50
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51/*
52 * CE4100 ids. Will be moved to machine_device_initcall() once we have it.
53 */
54static struct of_device_id __initdata ce4100_ids[] = {
55 { .compatible = "intel,ce4100-cp", },
56 { .compatible = "isa", },
57 { .compatible = "pci", },
58 {},
59};
60
61static int __init add_bus_probe(void)
62{
4a66b1d9 63 if (!of_have_populated_dt())
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64 return 0;
65
66 return of_platform_bus_probe(NULL, ce4100_ids, NULL);
67}
68module_init(add_bus_probe);
69
96e0a079 70#ifdef CONFIG_PCI
3d5fe5a6
BH
71struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
72{
73 struct device_node *np;
74
75 for_each_node_by_type(np, "pci") {
76 const void *prop;
77 unsigned int bus_min;
78
79 prop = of_get_property(np, "bus-range", NULL);
80 if (!prop)
81 continue;
82 bus_min = be32_to_cpup(prop);
83 if (bus->number == bus_min)
84 return np;
85 }
86 return NULL;
87}
88
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89static int x86_of_pci_irq_enable(struct pci_dev *dev)
90{
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91 u32 virq;
92 int ret;
93 u8 pin;
94
95 ret = pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
96 if (ret)
97 return ret;
98 if (!pin)
99 return 0;
100
16b84e5a 101 virq = of_irq_parse_and_map_pci(dev, 0, 0);
96e0a079
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102 if (virq == 0)
103 return -EINVAL;
104 dev->irq = virq;
105 return 0;
106}
107
108static void x86_of_pci_irq_disable(struct pci_dev *dev)
109{
110}
111
148f9bb8 112void x86_of_pci_init(void)
96e0a079 113{
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114 pcibios_enable_irq = x86_of_pci_irq_enable;
115 pcibios_disable_irq = x86_of_pci_irq_disable;
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116}
117#endif
118
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119static void __init dtb_setup_hpet(void)
120{
4a66b1d9 121#ifdef CONFIG_HPET_TIMER
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122 struct device_node *dn;
123 struct resource r;
124 int ret;
125
126 dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-hpet");
127 if (!dn)
128 return;
129 ret = of_address_to_resource(dn, 0, &r);
130 if (ret) {
131 WARN_ON(1);
132 return;
133 }
134 hpet_address = r.start;
4a66b1d9 135#endif
ffb9fc68
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136}
137
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138static void __init dtb_lapic_setup(void)
139{
140#ifdef CONFIG_X86_LOCAL_APIC
a906fdaa
TG
141 struct device_node *dn;
142 struct resource r;
143 int ret;
144
145 dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-lapic");
146 if (!dn)
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147 return;
148
a906fdaa
TG
149 ret = of_address_to_resource(dn, 0, &r);
150 if (WARN_ON(ret))
151 return;
152
153 /* Did the boot loader setup the local APIC ? */
154 if (!cpu_has_apic) {
155 if (apic_force_enable(r.start))
156 return;
157 }
3879a6f3
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158 smp_found_config = 1;
159 pic_mode = 1;
a906fdaa 160 register_lapic_address(r.start);
3879a6f3 161 generic_processor_info(boot_cpu_physical_apicid,
a906fdaa 162 GET_APIC_VERSION(apic_read(APIC_LVR)));
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163#endif
164}
165
166#ifdef CONFIG_X86_IO_APIC
167static unsigned int ioapic_id;
168
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169struct of_ioapic_type {
170 u32 out_type;
171 u32 trigger;
172 u32 polarity;
173};
174
175static struct of_ioapic_type of_ioapic_type[] =
176{
177 {
178 .out_type = IRQ_TYPE_EDGE_RISING,
179 .trigger = IOAPIC_EDGE,
180 .polarity = 1,
181 },
182 {
183 .out_type = IRQ_TYPE_LEVEL_LOW,
184 .trigger = IOAPIC_LEVEL,
185 .polarity = 0,
186 },
187 {
188 .out_type = IRQ_TYPE_LEVEL_HIGH,
189 .trigger = IOAPIC_LEVEL,
190 .polarity = 1,
191 },
192 {
193 .out_type = IRQ_TYPE_EDGE_FALLING,
194 .trigger = IOAPIC_EDGE,
195 .polarity = 0,
196 },
197};
198
b4e51854
GL
199static int ioapic_xlate(struct irq_domain *domain,
200 struct device_node *controller,
201 const u32 *intspec, u32 intsize,
202 irq_hw_number_t *out_hwirq, u32 *out_type)
bcc7c124 203{
bcc7c124 204 struct of_ioapic_type *it;
795aacf6 205 u32 line, idx, gsi;
bcc7c124 206
b4e51854 207 if (WARN_ON(intsize < 2))
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208 return -EINVAL;
209
b4e51854 210 line = intspec[0];
bcc7c124 211
b4e51854 212 if (intspec[1] >= ARRAY_SIZE(of_ioapic_type))
bcc7c124
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213 return -EINVAL;
214
b4e51854 215 it = &of_ioapic_type[intspec[1]];
bcc7c124 216
facd8fdb 217 idx = (u32)(long)domain->host_data;
795aacf6
JL
218 gsi = mp_pin_to_gsi(idx, line);
219 if (mp_set_gsi_attr(gsi, it->trigger, it->polarity, cpu_to_node(0)))
220 return -EBUSY;
b4e51854
GL
221
222 *out_hwirq = line;
223 *out_type = it->out_type;
224 return 0;
bcc7c124
SAS
225}
226
b4e51854 227const struct irq_domain_ops ioapic_irq_domain_ops = {
795aacf6 228 .map = mp_irqdomain_map,
00f49c29 229 .unmap = mp_irqdomain_unmap,
b4e51854
GL
230 .xlate = ioapic_xlate,
231};
232
facd8fdb 233static void __init dtb_add_ioapic(struct device_node *dn)
ece3234a 234{
facd8fdb 235 struct resource r;
ece3234a 236 int ret;
facd8fdb
JL
237 struct ioapic_domain_cfg cfg = {
238 .type = IOAPIC_DOMAIN_DYNAMIC,
239 .ops = &ioapic_irq_domain_ops,
240 .dev = dn,
241 };
242
243 ret = of_address_to_resource(dn, 0, &r);
244 if (ret) {
245 printk(KERN_ERR "Can't obtain address from node %s.\n",
246 dn->full_name);
247 return;
ece3234a 248 }
facd8fdb 249 mp_register_ioapic(++ioapic_id, r.start, gsi_top, &cfg);
ece3234a
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250}
251
facd8fdb 252static void __init dtb_ioapic_setup(void)
bcc7c124 253{
facd8fdb 254 struct device_node *dn;
bcc7c124 255
facd8fdb
JL
256 for_each_compatible_node(dn, NULL, "intel,ce4100-ioapic")
257 dtb_add_ioapic(dn);
258
259 if (nr_ioapics) {
260 of_ioapic = 1;
bcc7c124
SAS
261 return;
262 }
facd8fdb
JL
263 printk(KERN_ERR "Error: No information about IO-APIC in OF.\n");
264}
265#else
266static void __init dtb_ioapic_setup(void) {}
267#endif
bcc7c124 268
facd8fdb
JL
269static void __init dtb_apic_setup(void)
270{
271 dtb_lapic_setup();
272 dtb_ioapic_setup();
bcc7c124
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273}
274
facd8fdb
JL
275#ifdef CONFIG_OF_FLATTREE
276static void __init x86_flattree_get_config(void)
bcc7c124 277{
facd8fdb
JL
278 u32 size, map_len;
279 void *dt;
bcc7c124 280
facd8fdb 281 if (!initial_dtb)
bcc7c124
SAS
282 return;
283
facd8fdb
JL
284 map_len = max(PAGE_SIZE - (initial_dtb & ~PAGE_MASK), (u64)128);
285
286 initial_boot_params = dt = early_memremap(initial_dtb, map_len);
287 size = of_get_flat_dt_size();
288 if (map_len < size) {
8d4a40bc 289 early_memunmap(dt, map_len);
facd8fdb
JL
290 initial_boot_params = dt = early_memremap(initial_dtb, size);
291 map_len = size;
bcc7c124 292 }
facd8fdb
JL
293
294 unflatten_and_copy_device_tree();
8d4a40bc 295 early_memunmap(dt, map_len);
bcc7c124
SAS
296}
297#else
facd8fdb 298static inline void x86_flattree_get_config(void) { }
bcc7c124 299#endif
facd8fdb
JL
300
301void __init x86_dtb_init(void)
302{
303 x86_flattree_get_config();
304
305 if (!of_have_populated_dt())
306 return;
307
308 dtb_setup_hpet();
309 dtb_apic_setup();
310}
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