Commit | Line | Data |
---|---|---|
da6b737b SAS |
1 | /* |
2 | * Architecture specific OF callbacks. | |
3 | */ | |
4 | #include <linux/bootmem.h> | |
69c60c88 | 5 | #include <linux/export.h> |
da6b737b | 6 | #include <linux/io.h> |
b4e51854 | 7 | #include <linux/irqdomain.h> |
19c4f5f7 | 8 | #include <linux/interrupt.h> |
da6b737b SAS |
9 | #include <linux/list.h> |
10 | #include <linux/of.h> | |
11 | #include <linux/of_fdt.h> | |
3879a6f3 | 12 | #include <linux/of_address.h> |
da6b737b | 13 | #include <linux/of_platform.h> |
96e0a079 | 14 | #include <linux/of_irq.h> |
da6b737b | 15 | #include <linux/slab.h> |
96e0a079 SAS |
16 | #include <linux/pci.h> |
17 | #include <linux/of_pci.h> | |
977cb76d | 18 | #include <linux/initrd.h> |
da6b737b | 19 | |
ffb9fc68 | 20 | #include <asm/hpet.h> |
3879a6f3 | 21 | #include <asm/apic.h> |
96e0a079 | 22 | #include <asm/pci_x86.h> |
19c4f5f7 | 23 | |
3879a6f3 | 24 | __initdata u64 initial_dtb; |
da6b737b | 25 | char __initdata cmd_line[COMMAND_LINE_SIZE]; |
19c4f5f7 | 26 | |
3879a6f3 SAS |
27 | int __initdata of_ioapic; |
28 | ||
da6b737b SAS |
29 | unsigned long pci_address_to_pio(phys_addr_t address) |
30 | { | |
31 | /* | |
32 | * The ioport address can be directly used by inX / outX | |
33 | */ | |
34 | BUG_ON(address >= (1 << 16)); | |
35 | return (unsigned long)address; | |
36 | } | |
37 | EXPORT_SYMBOL_GPL(pci_address_to_pio); | |
38 | ||
39 | void __init early_init_dt_scan_chosen_arch(unsigned long node) | |
40 | { | |
41 | BUG(); | |
42 | } | |
43 | ||
44 | void __init early_init_dt_add_memory_arch(u64 base, u64 size) | |
45 | { | |
46 | BUG(); | |
47 | } | |
48 | ||
49 | void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align) | |
50 | { | |
51 | return __alloc_bootmem(size, align, __pa(MAX_DMA_ADDRESS)); | |
52 | } | |
53 | ||
977cb76d FF |
54 | #ifdef CONFIG_BLK_DEV_INITRD |
55 | void __init early_init_dt_setup_initrd_arch(unsigned long start, | |
56 | unsigned long end) | |
57 | { | |
58 | initrd_start = (unsigned long)__va(start); | |
59 | initrd_end = (unsigned long)__va(end); | |
60 | initrd_below_start_ok = 1; | |
61 | } | |
62 | #endif | |
63 | ||
da6b737b SAS |
64 | void __init add_dtb(u64 data) |
65 | { | |
3879a6f3 SAS |
66 | initial_dtb = data + offsetof(struct setup_data, data); |
67 | } | |
68 | ||
9079b353 SAS |
69 | /* |
70 | * CE4100 ids. Will be moved to machine_device_initcall() once we have it. | |
71 | */ | |
72 | static struct of_device_id __initdata ce4100_ids[] = { | |
73 | { .compatible = "intel,ce4100-cp", }, | |
74 | { .compatible = "isa", }, | |
75 | { .compatible = "pci", }, | |
76 | {}, | |
77 | }; | |
78 | ||
79 | static int __init add_bus_probe(void) | |
80 | { | |
4a66b1d9 | 81 | if (!of_have_populated_dt()) |
9079b353 SAS |
82 | return 0; |
83 | ||
84 | return of_platform_bus_probe(NULL, ce4100_ids, NULL); | |
85 | } | |
86 | module_init(add_bus_probe); | |
87 | ||
96e0a079 | 88 | #ifdef CONFIG_PCI |
3d5fe5a6 BH |
89 | struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus) |
90 | { | |
91 | struct device_node *np; | |
92 | ||
93 | for_each_node_by_type(np, "pci") { | |
94 | const void *prop; | |
95 | unsigned int bus_min; | |
96 | ||
97 | prop = of_get_property(np, "bus-range", NULL); | |
98 | if (!prop) | |
99 | continue; | |
100 | bus_min = be32_to_cpup(prop); | |
101 | if (bus->number == bus_min) | |
102 | return np; | |
103 | } | |
104 | return NULL; | |
105 | } | |
106 | ||
96e0a079 SAS |
107 | static int x86_of_pci_irq_enable(struct pci_dev *dev) |
108 | { | |
109 | struct of_irq oirq; | |
110 | u32 virq; | |
111 | int ret; | |
112 | u8 pin; | |
113 | ||
114 | ret = pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); | |
115 | if (ret) | |
116 | return ret; | |
117 | if (!pin) | |
118 | return 0; | |
119 | ||
120 | ret = of_irq_map_pci(dev, &oirq); | |
121 | if (ret) | |
122 | return ret; | |
123 | ||
124 | virq = irq_create_of_mapping(oirq.controller, oirq.specifier, | |
125 | oirq.size); | |
126 | if (virq == 0) | |
127 | return -EINVAL; | |
128 | dev->irq = virq; | |
129 | return 0; | |
130 | } | |
131 | ||
132 | static void x86_of_pci_irq_disable(struct pci_dev *dev) | |
133 | { | |
134 | } | |
135 | ||
148f9bb8 | 136 | void x86_of_pci_init(void) |
96e0a079 | 137 | { |
96e0a079 SAS |
138 | pcibios_enable_irq = x86_of_pci_irq_enable; |
139 | pcibios_disable_irq = x86_of_pci_irq_disable; | |
96e0a079 SAS |
140 | } |
141 | #endif | |
142 | ||
ffb9fc68 SAS |
143 | static void __init dtb_setup_hpet(void) |
144 | { | |
4a66b1d9 | 145 | #ifdef CONFIG_HPET_TIMER |
ffb9fc68 SAS |
146 | struct device_node *dn; |
147 | struct resource r; | |
148 | int ret; | |
149 | ||
150 | dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-hpet"); | |
151 | if (!dn) | |
152 | return; | |
153 | ret = of_address_to_resource(dn, 0, &r); | |
154 | if (ret) { | |
155 | WARN_ON(1); | |
156 | return; | |
157 | } | |
158 | hpet_address = r.start; | |
4a66b1d9 | 159 | #endif |
ffb9fc68 SAS |
160 | } |
161 | ||
3879a6f3 SAS |
162 | static void __init dtb_lapic_setup(void) |
163 | { | |
164 | #ifdef CONFIG_X86_LOCAL_APIC | |
a906fdaa TG |
165 | struct device_node *dn; |
166 | struct resource r; | |
167 | int ret; | |
168 | ||
169 | dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-lapic"); | |
170 | if (!dn) | |
3879a6f3 SAS |
171 | return; |
172 | ||
a906fdaa TG |
173 | ret = of_address_to_resource(dn, 0, &r); |
174 | if (WARN_ON(ret)) | |
175 | return; | |
176 | ||
177 | /* Did the boot loader setup the local APIC ? */ | |
178 | if (!cpu_has_apic) { | |
179 | if (apic_force_enable(r.start)) | |
180 | return; | |
181 | } | |
3879a6f3 SAS |
182 | smp_found_config = 1; |
183 | pic_mode = 1; | |
a906fdaa | 184 | register_lapic_address(r.start); |
3879a6f3 | 185 | generic_processor_info(boot_cpu_physical_apicid, |
a906fdaa | 186 | GET_APIC_VERSION(apic_read(APIC_LVR))); |
3879a6f3 SAS |
187 | #endif |
188 | } | |
189 | ||
190 | #ifdef CONFIG_X86_IO_APIC | |
191 | static unsigned int ioapic_id; | |
192 | ||
193 | static void __init dtb_add_ioapic(struct device_node *dn) | |
194 | { | |
195 | struct resource r; | |
196 | int ret; | |
197 | ||
198 | ret = of_address_to_resource(dn, 0, &r); | |
199 | if (ret) { | |
200 | printk(KERN_ERR "Can't obtain address from node %s.\n", | |
201 | dn->full_name); | |
202 | return; | |
203 | } | |
204 | mp_register_ioapic(++ioapic_id, r.start, gsi_top); | |
205 | } | |
206 | ||
207 | static void __init dtb_ioapic_setup(void) | |
208 | { | |
209 | struct device_node *dn; | |
210 | ||
3879a6f3 SAS |
211 | for_each_compatible_node(dn, NULL, "intel,ce4100-ioapic") |
212 | dtb_add_ioapic(dn); | |
213 | ||
214 | if (nr_ioapics) { | |
215 | of_ioapic = 1; | |
216 | return; | |
217 | } | |
218 | printk(KERN_ERR "Error: No information about IO-APIC in OF.\n"); | |
3879a6f3 SAS |
219 | } |
220 | #else | |
221 | static void __init dtb_ioapic_setup(void) {} | |
222 | #endif | |
223 | ||
224 | static void __init dtb_apic_setup(void) | |
225 | { | |
226 | dtb_lapic_setup(); | |
227 | dtb_ioapic_setup(); | |
228 | } | |
229 | ||
4a66b1d9 SAS |
230 | #ifdef CONFIG_OF_FLATTREE |
231 | static void __init x86_flattree_get_config(void) | |
3879a6f3 SAS |
232 | { |
233 | u32 size, map_len; | |
234 | void *new_dtb; | |
235 | ||
236 | if (!initial_dtb) | |
237 | return; | |
238 | ||
239 | map_len = max(PAGE_SIZE - (initial_dtb & ~PAGE_MASK), | |
240 | (u64)sizeof(struct boot_param_header)); | |
241 | ||
242 | initial_boot_params = early_memremap(initial_dtb, map_len); | |
243 | size = be32_to_cpu(initial_boot_params->totalsize); | |
244 | if (map_len < size) { | |
245 | early_iounmap(initial_boot_params, map_len); | |
246 | initial_boot_params = early_memremap(initial_dtb, size); | |
247 | map_len = size; | |
248 | } | |
249 | ||
250 | new_dtb = alloc_bootmem(size); | |
251 | memcpy(new_dtb, initial_boot_params, size); | |
252 | early_iounmap(initial_boot_params, map_len); | |
253 | ||
254 | initial_boot_params = new_dtb; | |
255 | ||
256 | /* root level address cells */ | |
257 | of_scan_flat_dt(early_init_dt_scan_root, NULL); | |
258 | ||
259 | unflatten_device_tree(); | |
4a66b1d9 SAS |
260 | } |
261 | #else | |
262 | static inline void x86_flattree_get_config(void) { } | |
263 | #endif | |
264 | ||
a906fdaa | 265 | void __init x86_dtb_init(void) |
4a66b1d9 SAS |
266 | { |
267 | x86_flattree_get_config(); | |
268 | ||
269 | if (!of_have_populated_dt()) | |
270 | return; | |
271 | ||
ffb9fc68 | 272 | dtb_setup_hpet(); |
3879a6f3 | 273 | dtb_apic_setup(); |
da6b737b | 274 | } |
bcc7c124 SAS |
275 | |
276 | #ifdef CONFIG_X86_IO_APIC | |
277 | ||
278 | struct of_ioapic_type { | |
279 | u32 out_type; | |
280 | u32 trigger; | |
281 | u32 polarity; | |
282 | }; | |
283 | ||
284 | static struct of_ioapic_type of_ioapic_type[] = | |
285 | { | |
286 | { | |
287 | .out_type = IRQ_TYPE_EDGE_RISING, | |
288 | .trigger = IOAPIC_EDGE, | |
289 | .polarity = 1, | |
290 | }, | |
291 | { | |
292 | .out_type = IRQ_TYPE_LEVEL_LOW, | |
293 | .trigger = IOAPIC_LEVEL, | |
294 | .polarity = 0, | |
295 | }, | |
296 | { | |
297 | .out_type = IRQ_TYPE_LEVEL_HIGH, | |
298 | .trigger = IOAPIC_LEVEL, | |
299 | .polarity = 1, | |
300 | }, | |
301 | { | |
302 | .out_type = IRQ_TYPE_EDGE_FALLING, | |
303 | .trigger = IOAPIC_EDGE, | |
304 | .polarity = 0, | |
305 | }, | |
306 | }; | |
307 | ||
b4e51854 GL |
308 | static int ioapic_xlate(struct irq_domain *domain, |
309 | struct device_node *controller, | |
310 | const u32 *intspec, u32 intsize, | |
311 | irq_hw_number_t *out_hwirq, u32 *out_type) | |
bcc7c124 SAS |
312 | { |
313 | struct io_apic_irq_attr attr; | |
314 | struct of_ioapic_type *it; | |
b4e51854 GL |
315 | u32 line, idx; |
316 | int rc; | |
bcc7c124 | 317 | |
b4e51854 | 318 | if (WARN_ON(intsize < 2)) |
bcc7c124 SAS |
319 | return -EINVAL; |
320 | ||
b4e51854 | 321 | line = intspec[0]; |
bcc7c124 | 322 | |
b4e51854 | 323 | if (intspec[1] >= ARRAY_SIZE(of_ioapic_type)) |
bcc7c124 SAS |
324 | return -EINVAL; |
325 | ||
b4e51854 | 326 | it = &of_ioapic_type[intspec[1]]; |
bcc7c124 | 327 | |
b4e51854 | 328 | idx = (u32) domain->host_data; |
bcc7c124 SAS |
329 | set_io_apic_irq_attr(&attr, idx, line, it->trigger, it->polarity); |
330 | ||
b4e51854 GL |
331 | rc = io_apic_setup_irq_pin_once(irq_find_mapping(domain, line), |
332 | cpu_to_node(0), &attr); | |
333 | if (rc) | |
334 | return rc; | |
335 | ||
336 | *out_hwirq = line; | |
337 | *out_type = it->out_type; | |
338 | return 0; | |
bcc7c124 SAS |
339 | } |
340 | ||
b4e51854 GL |
341 | const struct irq_domain_ops ioapic_irq_domain_ops = { |
342 | .xlate = ioapic_xlate, | |
343 | }; | |
344 | ||
ece3234a SAS |
345 | static void dt_add_ioapic_domain(unsigned int ioapic_num, |
346 | struct device_node *np) | |
347 | { | |
348 | struct irq_domain *id; | |
349 | struct mp_ioapic_gsi *gsi_cfg; | |
350 | int ret; | |
351 | int num; | |
352 | ||
353 | gsi_cfg = mp_ioapic_gsi_routing(ioapic_num); | |
354 | num = gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1; | |
355 | ||
356 | id = irq_domain_add_linear(np, num, &ioapic_irq_domain_ops, | |
357 | (void *)ioapic_num); | |
358 | BUG_ON(!id); | |
359 | if (gsi_cfg->gsi_base == 0) { | |
360 | /* | |
361 | * The first NR_IRQS_LEGACY irq descs are allocated in | |
362 | * early_irq_init() and need just a mapping. The | |
363 | * remaining irqs need both. All of them are preallocated | |
364 | * and assigned so we can keep the 1:1 mapping which the ioapic | |
365 | * is having. | |
366 | */ | |
ddaf144c | 367 | irq_domain_associate_many(id, 0, 0, NR_IRQS_LEGACY); |
ece3234a SAS |
368 | |
369 | if (num > NR_IRQS_LEGACY) { | |
370 | ret = irq_create_strict_mappings(id, NR_IRQS_LEGACY, | |
371 | NR_IRQS_LEGACY, num - NR_IRQS_LEGACY); | |
372 | if (ret) | |
373 | pr_err("Error creating mapping for the " | |
374 | "remaining IRQs: %d\n", ret); | |
375 | } | |
376 | irq_set_default_host(id); | |
377 | } else { | |
378 | ret = irq_create_strict_mappings(id, gsi_cfg->gsi_base, 0, num); | |
379 | if (ret) | |
380 | pr_err("Error creating IRQ mapping: %d\n", ret); | |
381 | } | |
382 | } | |
383 | ||
bcc7c124 SAS |
384 | static void __init ioapic_add_ofnode(struct device_node *np) |
385 | { | |
386 | struct resource r; | |
387 | int i, ret; | |
388 | ||
389 | ret = of_address_to_resource(np, 0, &r); | |
390 | if (ret) { | |
391 | printk(KERN_ERR "Failed to obtain address for %s\n", | |
392 | np->full_name); | |
393 | return; | |
394 | } | |
395 | ||
396 | for (i = 0; i < nr_ioapics; i++) { | |
d5371430 | 397 | if (r.start == mpc_ioapic_addr(i)) { |
ece3234a | 398 | dt_add_ioapic_domain(i, np); |
bcc7c124 SAS |
399 | return; |
400 | } | |
401 | } | |
402 | printk(KERN_ERR "IOxAPIC at %s is not registered.\n", np->full_name); | |
403 | } | |
404 | ||
405 | void __init x86_add_irq_domains(void) | |
406 | { | |
407 | struct device_node *dp; | |
408 | ||
4a66b1d9 | 409 | if (!of_have_populated_dt()) |
bcc7c124 SAS |
410 | return; |
411 | ||
412 | for_each_node_with_property(dp, "interrupt-controller") { | |
413 | if (of_device_is_compatible(dp, "intel,ce4100-ioapic")) | |
414 | ioapic_add_ofnode(dp); | |
415 | } | |
416 | } | |
417 | #else | |
418 | void __init x86_add_irq_domains(void) { } | |
419 | #endif |