Commit | Line | Data |
---|---|---|
dc1e35c6 SS |
1 | /* |
2 | * xsave/xrstor support. | |
3 | * | |
4 | * Author: Suresh Siddha <suresh.b.siddha@intel.com> | |
5 | */ | |
6 | #include <linux/bootmem.h> | |
7 | #include <linux/compat.h> | |
7e7ce87f | 8 | #include <linux/cpu.h> |
df6b35f4 | 9 | #include <asm/fpu/api.h> |
78f7f1e5 | 10 | #include <asm/fpu/internal.h> |
72a671ce | 11 | #include <asm/sigframe.h> |
375074cc | 12 | #include <asm/tlbflush.h> |
6152e4b1 | 13 | #include <asm/xcr.h> |
dc1e35c6 SS |
14 | |
15 | /* | |
614df7fb | 16 | * Mask of xstate features supported by the CPU and the kernel: |
dc1e35c6 | 17 | */ |
614df7fb | 18 | u64 xfeatures_mask; |
dc1e35c6 | 19 | |
45c2d7f4 RR |
20 | /* |
21 | * Represents init state for the supported extended state. | |
22 | */ | |
304bceda | 23 | struct xsave_struct *init_xstate_buf; |
45c2d7f4 | 24 | |
72a671ce | 25 | static struct _fpx_sw_bytes fx_sw_reserved, fx_sw_reserved_ia32; |
7e7ce87f | 26 | static unsigned int *xstate_offsets, *xstate_sizes; |
614df7fb | 27 | static unsigned int xstate_comp_offsets[sizeof(xfeatures_mask)*8]; |
84246fe4 IM |
28 | |
29 | /* The number of supported xfeatures in xfeatures_mask: */ | |
30 | static unsigned int xfeatures_nr; | |
a1488f8b | 31 | |
29104e10 SS |
32 | /* |
33 | * If a processor implementation discern that a processor state component is | |
34 | * in its initialized state it may modify the corresponding bit in the | |
3a54450b | 35 | * header.xstate_bv as '0', with out modifying the corresponding memory |
29104e10 SS |
36 | * layout in the case of xsaveopt. While presenting the xstate information to |
37 | * the user, we always ensure that the memory layout of a feature will be in | |
38 | * the init state if the corresponding header bit is zero. This is to ensure | |
39 | * that the user doesn't see some stale state in the memory layout during | |
40 | * signal handling, debugging etc. | |
41 | */ | |
42 | void __sanitize_i387_state(struct task_struct *tsk) | |
43 | { | |
29104e10 | 44 | struct i387_fxsave_struct *fx = &tsk->thread.fpu.state->fxsave; |
72a671ce SS |
45 | int feature_bit = 0x2; |
46 | u64 xstate_bv; | |
29104e10 SS |
47 | |
48 | if (!fx) | |
49 | return; | |
50 | ||
3a54450b | 51 | xstate_bv = tsk->thread.fpu.state->xsave.header.xstate_bv; |
29104e10 SS |
52 | |
53 | /* | |
54 | * None of the feature bits are in init state. So nothing else | |
0d2eb44f | 55 | * to do for us, as the memory layout is up to date. |
29104e10 | 56 | */ |
614df7fb | 57 | if ((xstate_bv & xfeatures_mask) == xfeatures_mask) |
29104e10 SS |
58 | return; |
59 | ||
60 | /* | |
61 | * FP is in init state | |
62 | */ | |
63 | if (!(xstate_bv & XSTATE_FP)) { | |
64 | fx->cwd = 0x37f; | |
65 | fx->swd = 0; | |
66 | fx->twd = 0; | |
67 | fx->fop = 0; | |
68 | fx->rip = 0; | |
69 | fx->rdp = 0; | |
70 | memset(&fx->st_space[0], 0, 128); | |
71 | } | |
72 | ||
73 | /* | |
74 | * SSE is in init state | |
75 | */ | |
76 | if (!(xstate_bv & XSTATE_SSE)) | |
77 | memset(&fx->xmm_space[0], 0, 256); | |
78 | ||
614df7fb | 79 | xstate_bv = (xfeatures_mask & ~xstate_bv) >> 2; |
29104e10 SS |
80 | |
81 | /* | |
82 | * Update all the other memory layouts for which the corresponding | |
83 | * header bit is in the init state. | |
84 | */ | |
85 | while (xstate_bv) { | |
86 | if (xstate_bv & 0x1) { | |
87 | int offset = xstate_offsets[feature_bit]; | |
88 | int size = xstate_sizes[feature_bit]; | |
89 | ||
90 | memcpy(((void *) fx) + offset, | |
91 | ((void *) init_xstate_buf) + offset, | |
92 | size); | |
93 | } | |
94 | ||
95 | xstate_bv >>= 1; | |
96 | feature_bit++; | |
97 | } | |
98 | } | |
99 | ||
c37b5efe SS |
100 | /* |
101 | * Check for the presence of extended state information in the | |
102 | * user fpstate pointer in the sigcontext. | |
103 | */ | |
72a671ce SS |
104 | static inline int check_for_xstate(struct i387_fxsave_struct __user *buf, |
105 | void __user *fpstate, | |
106 | struct _fpx_sw_bytes *fx_sw) | |
c37b5efe SS |
107 | { |
108 | int min_xstate_size = sizeof(struct i387_fxsave_struct) + | |
3a54450b | 109 | sizeof(struct xstate_header); |
c37b5efe | 110 | unsigned int magic2; |
c37b5efe | 111 | |
72a671ce SS |
112 | if (__copy_from_user(fx_sw, &buf->sw_reserved[0], sizeof(*fx_sw))) |
113 | return -1; | |
c37b5efe | 114 | |
72a671ce SS |
115 | /* Check for the first magic field and other error scenarios. */ |
116 | if (fx_sw->magic1 != FP_XSTATE_MAGIC1 || | |
117 | fx_sw->xstate_size < min_xstate_size || | |
118 | fx_sw->xstate_size > xstate_size || | |
119 | fx_sw->xstate_size > fx_sw->extended_size) | |
120 | return -1; | |
c37b5efe | 121 | |
c37b5efe SS |
122 | /* |
123 | * Check for the presence of second magic word at the end of memory | |
124 | * layout. This detects the case where the user just copied the legacy | |
125 | * fpstate layout with out copying the extended state information | |
126 | * in the memory layout. | |
127 | */ | |
72a671ce SS |
128 | if (__get_user(magic2, (__u32 __user *)(fpstate + fx_sw->xstate_size)) |
129 | || magic2 != FP_XSTATE_MAGIC2) | |
130 | return -1; | |
c37b5efe SS |
131 | |
132 | return 0; | |
133 | } | |
134 | ||
ab513701 SS |
135 | /* |
136 | * Signal frame handlers. | |
137 | */ | |
72a671ce SS |
138 | static inline int save_fsave_header(struct task_struct *tsk, void __user *buf) |
139 | { | |
140 | if (use_fxsr()) { | |
141 | struct xsave_struct *xsave = &tsk->thread.fpu.state->xsave; | |
142 | struct user_i387_ia32_struct env; | |
143 | struct _fpstate_ia32 __user *fp = buf; | |
ab513701 | 144 | |
72a671ce SS |
145 | convert_from_fxsr(&env, tsk); |
146 | ||
147 | if (__copy_to_user(buf, &env, sizeof(env)) || | |
148 | __put_user(xsave->i387.swd, &fp->status) || | |
149 | __put_user(X86_FXSR_MAGIC, &fp->magic)) | |
150 | return -1; | |
151 | } else { | |
152 | struct i387_fsave_struct __user *fp = buf; | |
153 | u32 swd; | |
154 | if (__get_user(swd, &fp->swd) || __put_user(swd, &fp->status)) | |
155 | return -1; | |
156 | } | |
157 | ||
158 | return 0; | |
159 | } | |
160 | ||
161 | static inline int save_xstate_epilog(void __user *buf, int ia32_frame) | |
ab513701 | 162 | { |
72a671ce SS |
163 | struct xsave_struct __user *x = buf; |
164 | struct _fpx_sw_bytes *sw_bytes; | |
165 | u32 xstate_bv; | |
166 | int err; | |
ab513701 | 167 | |
72a671ce SS |
168 | /* Setup the bytes not touched by the [f]xsave and reserved for SW. */ |
169 | sw_bytes = ia32_frame ? &fx_sw_reserved_ia32 : &fx_sw_reserved; | |
170 | err = __copy_to_user(&x->i387.sw_reserved, sw_bytes, sizeof(*sw_bytes)); | |
ab513701 | 171 | |
72a671ce SS |
172 | if (!use_xsave()) |
173 | return err; | |
ab513701 | 174 | |
72a671ce | 175 | err |= __put_user(FP_XSTATE_MAGIC2, (__u32 *)(buf + xstate_size)); |
ab513701 | 176 | |
72a671ce SS |
177 | /* |
178 | * Read the xstate_bv which we copied (directly from the cpu or | |
179 | * from the state in task struct) to the user buffers. | |
180 | */ | |
3a54450b | 181 | err |= __get_user(xstate_bv, (__u32 *)&x->header.xstate_bv); |
06c38d5e | 182 | |
72a671ce SS |
183 | /* |
184 | * For legacy compatible, we always set FP/SSE bits in the bit | |
185 | * vector while saving the state to the user context. This will | |
186 | * enable us capturing any changes(during sigreturn) to | |
187 | * the FP/SSE bits by the legacy applications which don't touch | |
188 | * xstate_bv in the xsave header. | |
189 | * | |
190 | * xsave aware apps can change the xstate_bv in the xsave | |
191 | * header as well as change any contents in the memory layout. | |
192 | * xrestore as part of sigreturn will capture all the changes. | |
193 | */ | |
194 | xstate_bv |= XSTATE_FPSSE; | |
c37b5efe | 195 | |
3a54450b | 196 | err |= __put_user(xstate_bv, (__u32 *)&x->header.xstate_bv); |
72a671ce SS |
197 | |
198 | return err; | |
199 | } | |
200 | ||
201 | static inline int save_user_xstate(struct xsave_struct __user *buf) | |
202 | { | |
203 | int err; | |
204 | ||
205 | if (use_xsave()) | |
206 | err = xsave_user(buf); | |
207 | else if (use_fxsr()) | |
208 | err = fxsave_user((struct i387_fxsave_struct __user *) buf); | |
209 | else | |
210 | err = fsave_user((struct i387_fsave_struct __user *) buf); | |
211 | ||
212 | if (unlikely(err) && __clear_user(buf, xstate_size)) | |
213 | err = -EFAULT; | |
214 | return err; | |
215 | } | |
216 | ||
217 | /* | |
218 | * Save the fpu, extended register state to the user signal frame. | |
219 | * | |
220 | * 'buf_fx' is the 64-byte aligned pointer at which the [f|fx|x]save | |
221 | * state is copied. | |
222 | * 'buf' points to the 'buf_fx' or to the fsave header followed by 'buf_fx'. | |
223 | * | |
224 | * buf == buf_fx for 64-bit frames and 32-bit fsave frame. | |
225 | * buf != buf_fx for 32-bit frames with fxstate. | |
226 | * | |
227 | * If the fpu, extended register state is live, save the state directly | |
228 | * to the user frame pointed by the aligned pointer 'buf_fx'. Otherwise, | |
229 | * copy the thread's fpu state to the user frame starting at 'buf_fx'. | |
230 | * | |
231 | * If this is a 32-bit frame with fxstate, put a fsave header before | |
232 | * the aligned state at 'buf_fx'. | |
233 | * | |
234 | * For [f]xsave state, update the SW reserved fields in the [f]xsave frame | |
235 | * indicating the absence/presence of the extended state to the user. | |
236 | */ | |
237 | int save_xstate_sig(void __user *buf, void __user *buf_fx, int size) | |
238 | { | |
239 | struct xsave_struct *xsave = ¤t->thread.fpu.state->xsave; | |
240 | struct task_struct *tsk = current; | |
241 | int ia32_fxstate = (buf != buf_fx); | |
242 | ||
243 | ia32_fxstate &= (config_enabled(CONFIG_X86_32) || | |
244 | config_enabled(CONFIG_IA32_EMULATION)); | |
245 | ||
246 | if (!access_ok(VERIFY_WRITE, buf, size)) | |
247 | return -EACCES; | |
248 | ||
60e019eb | 249 | if (!static_cpu_has(X86_FEATURE_FPU)) |
72a671ce SS |
250 | return fpregs_soft_get(current, NULL, 0, |
251 | sizeof(struct user_i387_ia32_struct), NULL, | |
252 | (struct _fpstate_ia32 __user *) buf) ? -1 : 1; | |
253 | ||
254 | if (user_has_fpu()) { | |
255 | /* Save the live register state to the user directly. */ | |
256 | if (save_user_xstate(buf_fx)) | |
257 | return -1; | |
258 | /* Update the thread's fxstate to save the fsave header. */ | |
259 | if (ia32_fxstate) | |
260 | fpu_fxsave(&tsk->thread.fpu); | |
ab513701 | 261 | } else { |
29104e10 | 262 | sanitize_i387_state(tsk); |
72a671ce | 263 | if (__copy_to_user(buf_fx, xsave, xstate_size)) |
ab513701 SS |
264 | return -1; |
265 | } | |
c37b5efe | 266 | |
72a671ce SS |
267 | /* Save the fsave header for the 32-bit frames. */ |
268 | if ((ia32_fxstate || !use_fxsr()) && save_fsave_header(tsk, buf)) | |
269 | return -1; | |
06c38d5e | 270 | |
72a671ce SS |
271 | if (use_fxsr() && save_xstate_epilog(buf_fx, ia32_fxstate)) |
272 | return -1; | |
273 | ||
72a671ce SS |
274 | return 0; |
275 | } | |
c37b5efe | 276 | |
72a671ce SS |
277 | static inline void |
278 | sanitize_restored_xstate(struct task_struct *tsk, | |
279 | struct user_i387_ia32_struct *ia32_env, | |
280 | u64 xstate_bv, int fx_only) | |
281 | { | |
282 | struct xsave_struct *xsave = &tsk->thread.fpu.state->xsave; | |
3a54450b | 283 | struct xstate_header *header = &xsave->header; |
c37b5efe | 284 | |
72a671ce SS |
285 | if (use_xsave()) { |
286 | /* These bits must be zero. */ | |
3a54450b | 287 | memset(header->reserved, 0, 48); |
04944b79 SS |
288 | |
289 | /* | |
72a671ce SS |
290 | * Init the state that is not present in the memory |
291 | * layout and not enabled by the OS. | |
04944b79 | 292 | */ |
72a671ce | 293 | if (fx_only) |
3a54450b | 294 | header->xstate_bv = XSTATE_FPSSE; |
72a671ce | 295 | else |
3a54450b | 296 | header->xstate_bv &= (xfeatures_mask & xstate_bv); |
72a671ce | 297 | } |
04944b79 | 298 | |
72a671ce | 299 | if (use_fxsr()) { |
04944b79 | 300 | /* |
72a671ce SS |
301 | * mscsr reserved bits must be masked to zero for security |
302 | * reasons. | |
04944b79 | 303 | */ |
72a671ce | 304 | xsave->i387.mxcsr &= mxcsr_feature_mask; |
04944b79 | 305 | |
72a671ce | 306 | convert_to_fxsr(tsk, ia32_env); |
c37b5efe | 307 | } |
ab513701 SS |
308 | } |
309 | ||
c37b5efe | 310 | /* |
72a671ce | 311 | * Restore the extended state if present. Otherwise, restore the FP/SSE state. |
c37b5efe | 312 | */ |
72a671ce | 313 | static inline int restore_user_xstate(void __user *buf, u64 xbv, int fx_only) |
c37b5efe | 314 | { |
72a671ce SS |
315 | if (use_xsave()) { |
316 | if ((unsigned long)buf % 64 || fx_only) { | |
614df7fb | 317 | u64 init_bv = xfeatures_mask & ~XSTATE_FPSSE; |
72a671ce | 318 | xrstor_state(init_xstate_buf, init_bv); |
e139e955 | 319 | return fxrstor_user(buf); |
72a671ce | 320 | } else { |
614df7fb | 321 | u64 init_bv = xfeatures_mask & ~xbv; |
72a671ce SS |
322 | if (unlikely(init_bv)) |
323 | xrstor_state(init_xstate_buf, init_bv); | |
324 | return xrestore_user(buf, xbv); | |
325 | } | |
326 | } else if (use_fxsr()) { | |
e139e955 | 327 | return fxrstor_user(buf); |
72a671ce | 328 | } else |
e139e955 | 329 | return frstor_user(buf); |
c37b5efe SS |
330 | } |
331 | ||
72a671ce | 332 | int __restore_xstate_sig(void __user *buf, void __user *buf_fx, int size) |
ab513701 | 333 | { |
72a671ce | 334 | int ia32_fxstate = (buf != buf_fx); |
ab513701 | 335 | struct task_struct *tsk = current; |
c5bedc68 | 336 | struct fpu *fpu = &tsk->thread.fpu; |
72a671ce SS |
337 | int state_size = xstate_size; |
338 | u64 xstate_bv = 0; | |
339 | int fx_only = 0; | |
340 | ||
341 | ia32_fxstate &= (config_enabled(CONFIG_X86_32) || | |
342 | config_enabled(CONFIG_IA32_EMULATION)); | |
ab513701 SS |
343 | |
344 | if (!buf) { | |
af2d94fd | 345 | fpu_reset_state(fpu); |
ab513701 | 346 | return 0; |
72a671ce SS |
347 | } |
348 | ||
349 | if (!access_ok(VERIFY_READ, buf, size)) | |
350 | return -EACCES; | |
351 | ||
db2b1d3a | 352 | if (!fpu->fpstate_active && fpstate_alloc_init(fpu)) |
72a671ce | 353 | return -1; |
ab513701 | 354 | |
60e019eb | 355 | if (!static_cpu_has(X86_FEATURE_FPU)) |
72a671ce SS |
356 | return fpregs_soft_set(current, NULL, |
357 | 0, sizeof(struct user_i387_ia32_struct), | |
358 | NULL, buf) != 0; | |
ab513701 | 359 | |
72a671ce SS |
360 | if (use_xsave()) { |
361 | struct _fpx_sw_bytes fx_sw_user; | |
362 | if (unlikely(check_for_xstate(buf_fx, buf_fx, &fx_sw_user))) { | |
363 | /* | |
364 | * Couldn't find the extended state information in the | |
365 | * memory layout. Restore just the FP/SSE and init all | |
366 | * the other extended state. | |
367 | */ | |
368 | state_size = sizeof(struct i387_fxsave_struct); | |
369 | fx_only = 1; | |
370 | } else { | |
371 | state_size = fx_sw_user.xstate_size; | |
372 | xstate_bv = fx_sw_user.xstate_bv; | |
373 | } | |
374 | } | |
375 | ||
376 | if (ia32_fxstate) { | |
377 | /* | |
378 | * For 32-bit frames with fxstate, copy the user state to the | |
379 | * thread's fpu state, reconstruct fxstate from the fsave | |
380 | * header. Sanitize the copied state etc. | |
381 | */ | |
a7c80ebc | 382 | struct fpu *fpu = &tsk->thread.fpu; |
72a671ce | 383 | struct user_i387_ia32_struct env; |
304bceda | 384 | int err = 0; |
72a671ce | 385 | |
304bceda | 386 | /* |
c5bedc68 | 387 | * Drop the current fpu which clears fpu->fpstate_active. This ensures |
304bceda SS |
388 | * that any context-switch during the copy of the new state, |
389 | * avoids the intermediate state from getting restored/saved. | |
390 | * Thus avoiding the new restored state from getting corrupted. | |
391 | * We will be ready to restore/save the state only after | |
c5bedc68 | 392 | * fpu->fpstate_active is again set. |
304bceda | 393 | */ |
ca6787ba | 394 | drop_fpu(fpu); |
72a671ce | 395 | |
a7c80ebc | 396 | if (__copy_from_user(&fpu->state->xsave, buf_fx, state_size) || |
304bceda | 397 | __copy_from_user(&env, buf, sizeof(env))) { |
c0ee2cf6 | 398 | fpstate_init(fpu); |
304bceda SS |
399 | err = -1; |
400 | } else { | |
401 | sanitize_restored_xstate(tsk, &env, xstate_bv, fx_only); | |
304bceda | 402 | } |
72a671ce | 403 | |
c5bedc68 | 404 | fpu->fpstate_active = 1; |
df24fb85 ON |
405 | if (use_eager_fpu()) { |
406 | preempt_disable(); | |
3a0aee48 | 407 | fpu__restore(); |
df24fb85 ON |
408 | preempt_enable(); |
409 | } | |
304bceda SS |
410 | |
411 | return err; | |
72a671ce | 412 | } else { |
ab513701 | 413 | /* |
72a671ce SS |
414 | * For 64-bit frames and 32-bit fsave frames, restore the user |
415 | * state to the registers directly (with exceptions handled). | |
ab513701 | 416 | */ |
72a671ce SS |
417 | user_fpu_begin(); |
418 | if (restore_user_xstate(buf_fx, xstate_bv, fx_only)) { | |
af2d94fd | 419 | fpu_reset_state(fpu); |
72a671ce SS |
420 | return -1; |
421 | } | |
ab513701 | 422 | } |
72a671ce SS |
423 | |
424 | return 0; | |
ab513701 | 425 | } |
ab513701 | 426 | |
c37b5efe SS |
427 | /* |
428 | * Prepare the SW reserved portion of the fxsave memory layout, indicating | |
429 | * the presence of the extended state information in the memory layout | |
430 | * pointed by the fpstate pointer in the sigcontext. | |
431 | * This will be saved when ever the FP and extended state context is | |
432 | * saved on the user stack during the signal handler delivery to the user. | |
433 | */ | |
8bcad30f | 434 | static void prepare_fx_sw_frame(void) |
c37b5efe | 435 | { |
72a671ce SS |
436 | int fsave_header_size = sizeof(struct i387_fsave_struct); |
437 | int size = xstate_size + FP_XSTATE_MAGIC2_SIZE; | |
c37b5efe | 438 | |
72a671ce SS |
439 | if (config_enabled(CONFIG_X86_32)) |
440 | size += fsave_header_size; | |
c37b5efe SS |
441 | |
442 | fx_sw_reserved.magic1 = FP_XSTATE_MAGIC1; | |
72a671ce | 443 | fx_sw_reserved.extended_size = size; |
614df7fb | 444 | fx_sw_reserved.xstate_bv = xfeatures_mask; |
c37b5efe | 445 | fx_sw_reserved.xstate_size = xstate_size; |
c37b5efe | 446 | |
72a671ce SS |
447 | if (config_enabled(CONFIG_IA32_EMULATION)) { |
448 | fx_sw_reserved_ia32 = fx_sw_reserved; | |
449 | fx_sw_reserved_ia32.extended_size += fsave_header_size; | |
450 | } | |
451 | } | |
3c1c7f10 | 452 | |
dc1e35c6 SS |
453 | /* |
454 | * Enable the extended processor state save/restore feature | |
455 | */ | |
1cff92d8 | 456 | static inline void xstate_enable(void) |
dc1e35c6 | 457 | { |
375074cc | 458 | cr4_set_bits(X86_CR4_OSXSAVE); |
614df7fb | 459 | xsetbv(XCR_XFEATURE_ENABLED_MASK, xfeatures_mask); |
dc1e35c6 SS |
460 | } |
461 | ||
a1488f8b SS |
462 | /* |
463 | * Record the offsets and sizes of different state managed by the xsave | |
464 | * memory layout. | |
465 | */ | |
4995b9db | 466 | static void __init setup_xstate_features(void) |
a1488f8b SS |
467 | { |
468 | int eax, ebx, ecx, edx, leaf = 0x2; | |
469 | ||
84246fe4 IM |
470 | xfeatures_nr = fls64(xfeatures_mask); |
471 | xstate_offsets = alloc_bootmem(xfeatures_nr * sizeof(int)); | |
472 | xstate_sizes = alloc_bootmem(xfeatures_nr * sizeof(int)); | |
a1488f8b SS |
473 | |
474 | do { | |
ee813d53 | 475 | cpuid_count(XSTATE_CPUID, leaf, &eax, &ebx, &ecx, &edx); |
a1488f8b SS |
476 | |
477 | if (eax == 0) | |
478 | break; | |
479 | ||
480 | xstate_offsets[leaf] = ebx; | |
481 | xstate_sizes[leaf] = eax; | |
482 | ||
483 | leaf++; | |
484 | } while (1); | |
485 | } | |
486 | ||
69496e10 IM |
487 | static void print_xstate_feature(u64 xstate_mask, const char *desc) |
488 | { | |
614df7fb | 489 | if (xfeatures_mask & xstate_mask) { |
69496e10 IM |
490 | int xstate_feature = fls64(xstate_mask)-1; |
491 | ||
492 | pr_info("x86/fpu: Supporting XSAVE feature %2d: '%s'\n", xstate_feature, desc); | |
493 | } | |
494 | } | |
495 | ||
496 | /* | |
497 | * Print out all the supported xstate features: | |
498 | */ | |
499 | static void print_xstate_features(void) | |
500 | { | |
501 | print_xstate_feature(XSTATE_FP, "x87 floating point registers"); | |
502 | print_xstate_feature(XSTATE_SSE, "SSE registers"); | |
503 | print_xstate_feature(XSTATE_YMM, "AVX registers"); | |
504 | print_xstate_feature(XSTATE_BNDREGS, "MPX bounds registers"); | |
505 | print_xstate_feature(XSTATE_BNDCSR, "MPX CSR"); | |
506 | print_xstate_feature(XSTATE_OPMASK, "AVX-512 opmask"); | |
507 | print_xstate_feature(XSTATE_ZMM_Hi256, "AVX-512 Hi256"); | |
508 | print_xstate_feature(XSTATE_Hi16_ZMM, "AVX-512 ZMM_Hi256"); | |
509 | } | |
510 | ||
7496d645 FY |
511 | /* |
512 | * This function sets up offsets and sizes of all extended states in | |
513 | * xsave area. This supports both standard format and compacted format | |
514 | * of the xsave aread. | |
515 | * | |
516 | * Input: void | |
517 | * Output: void | |
518 | */ | |
519 | void setup_xstate_comp(void) | |
520 | { | |
614df7fb | 521 | unsigned int xstate_comp_sizes[sizeof(xfeatures_mask)*8]; |
7496d645 FY |
522 | int i; |
523 | ||
8ff925e1 FY |
524 | /* |
525 | * The FP xstates and SSE xstates are legacy states. They are always | |
526 | * in the fixed offsets in the xsave area in either compacted form | |
527 | * or standard form. | |
528 | */ | |
529 | xstate_comp_offsets[0] = 0; | |
530 | xstate_comp_offsets[1] = offsetof(struct i387_fxsave_struct, xmm_space); | |
7496d645 FY |
531 | |
532 | if (!cpu_has_xsaves) { | |
84246fe4 | 533 | for (i = 2; i < xfeatures_nr; i++) { |
614df7fb | 534 | if (test_bit(i, (unsigned long *)&xfeatures_mask)) { |
7496d645 FY |
535 | xstate_comp_offsets[i] = xstate_offsets[i]; |
536 | xstate_comp_sizes[i] = xstate_sizes[i]; | |
537 | } | |
538 | } | |
539 | return; | |
540 | } | |
541 | ||
542 | xstate_comp_offsets[2] = FXSAVE_SIZE + XSAVE_HDR_SIZE; | |
543 | ||
84246fe4 | 544 | for (i = 2; i < xfeatures_nr; i++) { |
614df7fb | 545 | if (test_bit(i, (unsigned long *)&xfeatures_mask)) |
7496d645 FY |
546 | xstate_comp_sizes[i] = xstate_sizes[i]; |
547 | else | |
548 | xstate_comp_sizes[i] = 0; | |
549 | ||
550 | if (i > 2) | |
551 | xstate_comp_offsets[i] = xstate_comp_offsets[i-1] | |
552 | + xstate_comp_sizes[i-1]; | |
553 | ||
554 | } | |
555 | } | |
556 | ||
dc1e35c6 SS |
557 | /* |
558 | * setup the xstate image representing the init state | |
559 | */ | |
5d2bd700 | 560 | static void __init setup_init_fpu_buf(void) |
dc1e35c6 | 561 | { |
29104e10 SS |
562 | /* |
563 | * Setup init_xstate_buf to represent the init state of | |
564 | * all the features managed by the xsave | |
565 | */ | |
10340ae1 SS |
566 | init_xstate_buf = alloc_bootmem_align(xstate_size, |
567 | __alignof__(struct xsave_struct)); | |
5d2bd700 SS |
568 | fx_finit(&init_xstate_buf->i387); |
569 | ||
570 | if (!cpu_has_xsave) | |
571 | return; | |
572 | ||
573 | setup_xstate_features(); | |
69496e10 | 574 | print_xstate_features(); |
a1488f8b | 575 | |
47c2f292 | 576 | if (cpu_has_xsaves) { |
3a54450b | 577 | init_xstate_buf->header.xcomp_bv = |
614df7fb | 578 | (u64)1 << 63 | xfeatures_mask; |
3a54450b | 579 | init_xstate_buf->header.xstate_bv = xfeatures_mask; |
47c2f292 FY |
580 | } |
581 | ||
29104e10 SS |
582 | /* |
583 | * Init all the features state with header_bv being 0x0 | |
584 | */ | |
47c2f292 | 585 | xrstor_state_booting(init_xstate_buf, -1); |
3e261c14 | 586 | |
29104e10 SS |
587 | /* |
588 | * Dump the init state again. This is to identify the init state | |
589 | * of any feature which is not represented by all zero's. | |
590 | */ | |
3e261c14 | 591 | xsave_state_booting(init_xstate_buf); |
dc1e35c6 SS |
592 | } |
593 | ||
e0022981 | 594 | static enum { AUTO, ENABLE, DISABLE } eagerfpu = AUTO; |
5d2bd700 SS |
595 | static int __init eager_fpu_setup(char *s) |
596 | { | |
597 | if (!strcmp(s, "on")) | |
e0022981 | 598 | eagerfpu = ENABLE; |
5d2bd700 | 599 | else if (!strcmp(s, "off")) |
e0022981 SS |
600 | eagerfpu = DISABLE; |
601 | else if (!strcmp(s, "auto")) | |
602 | eagerfpu = AUTO; | |
5d2bd700 SS |
603 | return 1; |
604 | } | |
605 | __setup("eagerfpu=", eager_fpu_setup); | |
606 | ||
7e7ce87f FY |
607 | |
608 | /* | |
614df7fb | 609 | * Calculate total size of enabled xstates in XCR0/xfeatures_mask. |
7e7ce87f FY |
610 | */ |
611 | static void __init init_xstate_size(void) | |
612 | { | |
613 | unsigned int eax, ebx, ecx, edx; | |
614 | int i; | |
615 | ||
616 | if (!cpu_has_xsaves) { | |
617 | cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx); | |
618 | xstate_size = ebx; | |
619 | return; | |
620 | } | |
621 | ||
622 | xstate_size = FXSAVE_SIZE + XSAVE_HDR_SIZE; | |
623 | for (i = 2; i < 64; i++) { | |
614df7fb | 624 | if (test_bit(i, (unsigned long *)&xfeatures_mask)) { |
7e7ce87f FY |
625 | cpuid_count(XSTATE_CPUID, i, &eax, &ebx, &ecx, &edx); |
626 | xstate_size += eax; | |
627 | } | |
628 | } | |
629 | } | |
630 | ||
dc1e35c6 SS |
631 | /* |
632 | * Enable and initialize the xsave feature. | |
c0841e34 IM |
633 | * |
634 | * ( Not marked __init because of false positive section warnings | |
635 | * generated by xsave_init(). ) | |
dc1e35c6 | 636 | */ |
c0841e34 | 637 | static void /* __init */ xstate_enable_boot_cpu(void) |
dc1e35c6 SS |
638 | { |
639 | unsigned int eax, ebx, ecx, edx; | |
640 | ||
ee813d53 | 641 | if (boot_cpu_data.cpuid_level < XSTATE_CPUID) { |
32d4d9cc | 642 | WARN(1, "x86/fpu: XSTATE_CPUID missing!\n"); |
ee813d53 RR |
643 | return; |
644 | } | |
645 | ||
646 | cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx); | |
614df7fb | 647 | xfeatures_mask = eax + ((u64)edx << 32); |
dc1e35c6 | 648 | |
614df7fb IM |
649 | if ((xfeatures_mask & XSTATE_FPSSE) != XSTATE_FPSSE) { |
650 | pr_err("x86/fpu: FP/SSE not present amongst the CPU's xstate features: 0x%llx.\n", xfeatures_mask); | |
dc1e35c6 SS |
651 | BUG(); |
652 | } | |
653 | ||
654 | /* | |
a30469e7 | 655 | * Support only the state known to OS. |
dc1e35c6 | 656 | */ |
614df7fb | 657 | xfeatures_mask = xfeatures_mask & XCNTXT_MASK; |
97e80a70 | 658 | |
1cff92d8 | 659 | xstate_enable(); |
dc1e35c6 SS |
660 | |
661 | /* | |
662 | * Recompute the context size for enabled features | |
663 | */ | |
7e7ce87f | 664 | init_xstate_size(); |
dc1e35c6 | 665 | |
614df7fb | 666 | update_regset_xstate_info(xstate_size, xfeatures_mask); |
c37b5efe | 667 | prepare_fx_sw_frame(); |
5d2bd700 | 668 | setup_init_fpu_buf(); |
dc1e35c6 | 669 | |
e0022981 SS |
670 | /* Auto enable eagerfpu for xsaveopt */ |
671 | if (cpu_has_xsaveopt && eagerfpu != DISABLE) | |
672 | eagerfpu = ENABLE; | |
212b0212 | 673 | |
614df7fb | 674 | if (xfeatures_mask & XSTATE_EAGER) { |
e7d820a5 | 675 | if (eagerfpu == DISABLE) { |
32d4d9cc | 676 | pr_err("x86/fpu: eagerfpu switching disabled, disabling the following xstate features: 0x%llx.\n", |
614df7fb IM |
677 | xfeatures_mask & XSTATE_EAGER); |
678 | xfeatures_mask &= ~XSTATE_EAGER; | |
e7d820a5 QR |
679 | } else { |
680 | eagerfpu = ENABLE; | |
681 | } | |
682 | } | |
683 | ||
32d4d9cc | 684 | pr_info("x86/fpu: Enabled xstate features 0x%llx, context size is 0x%x bytes, using '%s' format.\n", |
614df7fb | 685 | xfeatures_mask, |
32d4d9cc IM |
686 | xstate_size, |
687 | cpu_has_xsaves ? "compacted" : "standard"); | |
dc1e35c6 | 688 | } |
82d4150c | 689 | |
1cff92d8 PA |
690 | /* |
691 | * For the very first instance, this calls xstate_enable_boot_cpu(); | |
692 | * for all subsequent instances, this calls xstate_enable(). | |
1cff92d8 | 693 | */ |
148f9bb8 | 694 | void xsave_init(void) |
82d4150c | 695 | { |
c0841e34 | 696 | static char on_boot_cpu = 1; |
1cff92d8 | 697 | |
32d4d9cc IM |
698 | if (!cpu_has_xsave) { |
699 | if (on_boot_cpu) { | |
700 | on_boot_cpu = 0; | |
701 | pr_info("x86/fpu: Legacy x87 FPU detected.\n"); | |
702 | } | |
0e49bf66 | 703 | return; |
32d4d9cc | 704 | } |
0e49bf66 | 705 | |
c0841e34 IM |
706 | if (on_boot_cpu) { |
707 | on_boot_cpu = 0; | |
708 | xstate_enable_boot_cpu(); | |
709 | } else { | |
710 | xstate_enable(); | |
711 | } | |
82d4150c | 712 | } |
5d2bd700 | 713 | |
7fc253e2 ON |
714 | /* |
715 | * setup_init_fpu_buf() is __init and it is OK to call it here because | |
716 | * init_xstate_buf will be unset only once during boot. | |
717 | */ | |
718 | void __init_refok eager_fpu_init(void) | |
5d2bd700 | 719 | { |
c5bedc68 | 720 | WARN_ON(current->thread.fpu.fpstate_active); |
5d2bd700 | 721 | current_thread_info()->status = 0; |
e0022981 SS |
722 | |
723 | if (eagerfpu == ENABLE) | |
724 | setup_force_cpu_cap(X86_FEATURE_EAGER_FPU); | |
725 | ||
9a89b029 IM |
726 | printk_once(KERN_INFO "x86/fpu: Using '%s' FPU context switches.\n", eagerfpu == ENABLE ? "eager" : "lazy"); |
727 | ||
5d2bd700 SS |
728 | if (!cpu_has_eager_fpu) { |
729 | stts(); | |
730 | return; | |
731 | } | |
732 | ||
7fc253e2 ON |
733 | if (!init_xstate_buf) |
734 | setup_init_fpu_buf(); | |
5d2bd700 | 735 | } |
7496d645 | 736 | |
9254aaa0 IM |
737 | /* |
738 | * Restore minimal FPU state after suspend: | |
739 | */ | |
740 | void fpu__resume_cpu(void) | |
741 | { | |
742 | /* | |
743 | * Restore XCR0 on xsave capable CPUs: | |
744 | */ | |
745 | if (cpu_has_xsave) | |
746 | xsetbv(XCR_XFEATURE_ENABLED_MASK, xfeatures_mask); | |
747 | } | |
748 | ||
7496d645 FY |
749 | /* |
750 | * Given the xsave area and a state inside, this function returns the | |
751 | * address of the state. | |
752 | * | |
753 | * This is the API that is called to get xstate address in either | |
754 | * standard format or compacted format of xsave area. | |
755 | * | |
756 | * Inputs: | |
757 | * xsave: base address of the xsave area; | |
758 | * xstate: state which is defined in xsave.h (e.g. XSTATE_FP, XSTATE_SSE, | |
759 | * etc.) | |
760 | * Output: | |
761 | * address of the state in the xsave area. | |
762 | */ | |
763 | void *get_xsave_addr(struct xsave_struct *xsave, int xstate) | |
764 | { | |
765 | int feature = fls64(xstate) - 1; | |
614df7fb | 766 | if (!test_bit(feature, (unsigned long *)&xfeatures_mask)) |
7496d645 FY |
767 | return NULL; |
768 | ||
769 | return (void *)xsave + xstate_comp_offsets[feature]; | |
770 | } | |
ba7b3920 | 771 | EXPORT_SYMBOL_GPL(get_xsave_addr); |