Commit | Line | Data |
---|---|---|
dc1e35c6 SS |
1 | /* |
2 | * xsave/xrstor support. | |
3 | * | |
4 | * Author: Suresh Siddha <suresh.b.siddha@intel.com> | |
5 | */ | |
dc1e35c6 | 6 | #include <linux/compat.h> |
7e7ce87f | 7 | #include <linux/cpu.h> |
df6b35f4 | 8 | #include <asm/fpu/api.h> |
78f7f1e5 | 9 | #include <asm/fpu/internal.h> |
72a671ce | 10 | #include <asm/sigframe.h> |
375074cc | 11 | #include <asm/tlbflush.h> |
6152e4b1 | 12 | #include <asm/xcr.h> |
dc1e35c6 SS |
13 | |
14 | /* | |
614df7fb | 15 | * Mask of xstate features supported by the CPU and the kernel: |
dc1e35c6 | 16 | */ |
614df7fb | 17 | u64 xfeatures_mask; |
dc1e35c6 | 18 | |
45c2d7f4 RR |
19 | /* |
20 | * Represents init state for the supported extended state. | |
21 | */ | |
3e5e1267 | 22 | struct xsave_struct init_xstate_ctx; |
45c2d7f4 | 23 | |
72a671ce | 24 | static struct _fpx_sw_bytes fx_sw_reserved, fx_sw_reserved_ia32; |
966ece61 | 25 | static unsigned int xstate_offsets[XFEATURES_NR_MAX], xstate_sizes[XFEATURES_NR_MAX]; |
614df7fb | 26 | static unsigned int xstate_comp_offsets[sizeof(xfeatures_mask)*8]; |
84246fe4 IM |
27 | |
28 | /* The number of supported xfeatures in xfeatures_mask: */ | |
29 | static unsigned int xfeatures_nr; | |
a1488f8b | 30 | |
29104e10 | 31 | /* |
73a3aeb3 IM |
32 | * When executing XSAVEOPT (optimized XSAVE), if a processor implementation |
33 | * detects that an FPU state component is still (or is again) in its | |
34 | * initialized state, it may clear the corresponding bit in the header.xfeatures | |
35 | * field, and can skip the writeout of registers to the corresponding memory layout. | |
36 | * | |
37 | * This means that when the bit is zero, the state component might still contain | |
38 | * some previous - non-initialized register state. | |
39 | * | |
40 | * Before writing xstate information to user-space we sanitize those components, | |
41 | * to always ensure that the memory layout of a feature will be in the init state | |
42 | * if the corresponding header bit is zero. This is to ensure that user-space doesn't | |
43 | * see some stale state in the memory layout during signal handling, debugging etc. | |
29104e10 SS |
44 | */ |
45 | void __sanitize_i387_state(struct task_struct *tsk) | |
46 | { | |
29104e10 | 47 | struct i387_fxsave_struct *fx = &tsk->thread.fpu.state->fxsave; |
73a3aeb3 | 48 | int feature_bit; |
400e4b20 | 49 | u64 xfeatures; |
29104e10 SS |
50 | |
51 | if (!fx) | |
52 | return; | |
53 | ||
400e4b20 | 54 | xfeatures = tsk->thread.fpu.state->xsave.header.xfeatures; |
29104e10 SS |
55 | |
56 | /* | |
57 | * None of the feature bits are in init state. So nothing else | |
0d2eb44f | 58 | * to do for us, as the memory layout is up to date. |
29104e10 | 59 | */ |
400e4b20 | 60 | if ((xfeatures & xfeatures_mask) == xfeatures_mask) |
29104e10 SS |
61 | return; |
62 | ||
63 | /* | |
64 | * FP is in init state | |
65 | */ | |
400e4b20 | 66 | if (!(xfeatures & XSTATE_FP)) { |
29104e10 SS |
67 | fx->cwd = 0x37f; |
68 | fx->swd = 0; | |
69 | fx->twd = 0; | |
70 | fx->fop = 0; | |
71 | fx->rip = 0; | |
72 | fx->rdp = 0; | |
73 | memset(&fx->st_space[0], 0, 128); | |
74 | } | |
75 | ||
76 | /* | |
77 | * SSE is in init state | |
78 | */ | |
400e4b20 | 79 | if (!(xfeatures & XSTATE_SSE)) |
29104e10 SS |
80 | memset(&fx->xmm_space[0], 0, 256); |
81 | ||
73a3aeb3 IM |
82 | /* |
83 | * First two features are FPU and SSE, which above we handled | |
84 | * in a special way already: | |
85 | */ | |
86 | feature_bit = 0x2; | |
400e4b20 | 87 | xfeatures = (xfeatures_mask & ~xfeatures) >> 2; |
29104e10 SS |
88 | |
89 | /* | |
73a3aeb3 IM |
90 | * Update all the remaining memory layouts according to their |
91 | * standard xstate layout, if their header bit is in the init | |
92 | * state: | |
29104e10 | 93 | */ |
400e4b20 IM |
94 | while (xfeatures) { |
95 | if (xfeatures & 0x1) { | |
29104e10 SS |
96 | int offset = xstate_offsets[feature_bit]; |
97 | int size = xstate_sizes[feature_bit]; | |
98 | ||
73a3aeb3 | 99 | memcpy((void *)fx + offset, |
3e5e1267 | 100 | (void *)&init_xstate_ctx + offset, |
29104e10 SS |
101 | size); |
102 | } | |
103 | ||
400e4b20 | 104 | xfeatures >>= 1; |
29104e10 SS |
105 | feature_bit++; |
106 | } | |
107 | } | |
108 | ||
c37b5efe SS |
109 | /* |
110 | * Check for the presence of extended state information in the | |
111 | * user fpstate pointer in the sigcontext. | |
112 | */ | |
72a671ce SS |
113 | static inline int check_for_xstate(struct i387_fxsave_struct __user *buf, |
114 | void __user *fpstate, | |
115 | struct _fpx_sw_bytes *fx_sw) | |
c37b5efe SS |
116 | { |
117 | int min_xstate_size = sizeof(struct i387_fxsave_struct) + | |
3a54450b | 118 | sizeof(struct xstate_header); |
c37b5efe | 119 | unsigned int magic2; |
c37b5efe | 120 | |
72a671ce SS |
121 | if (__copy_from_user(fx_sw, &buf->sw_reserved[0], sizeof(*fx_sw))) |
122 | return -1; | |
c37b5efe | 123 | |
72a671ce SS |
124 | /* Check for the first magic field and other error scenarios. */ |
125 | if (fx_sw->magic1 != FP_XSTATE_MAGIC1 || | |
126 | fx_sw->xstate_size < min_xstate_size || | |
127 | fx_sw->xstate_size > xstate_size || | |
128 | fx_sw->xstate_size > fx_sw->extended_size) | |
129 | return -1; | |
c37b5efe | 130 | |
c37b5efe SS |
131 | /* |
132 | * Check for the presence of second magic word at the end of memory | |
133 | * layout. This detects the case where the user just copied the legacy | |
134 | * fpstate layout with out copying the extended state information | |
135 | * in the memory layout. | |
136 | */ | |
72a671ce SS |
137 | if (__get_user(magic2, (__u32 __user *)(fpstate + fx_sw->xstate_size)) |
138 | || magic2 != FP_XSTATE_MAGIC2) | |
139 | return -1; | |
c37b5efe SS |
140 | |
141 | return 0; | |
142 | } | |
143 | ||
ab513701 SS |
144 | /* |
145 | * Signal frame handlers. | |
146 | */ | |
72a671ce SS |
147 | static inline int save_fsave_header(struct task_struct *tsk, void __user *buf) |
148 | { | |
149 | if (use_fxsr()) { | |
150 | struct xsave_struct *xsave = &tsk->thread.fpu.state->xsave; | |
151 | struct user_i387_ia32_struct env; | |
152 | struct _fpstate_ia32 __user *fp = buf; | |
ab513701 | 153 | |
72a671ce SS |
154 | convert_from_fxsr(&env, tsk); |
155 | ||
156 | if (__copy_to_user(buf, &env, sizeof(env)) || | |
157 | __put_user(xsave->i387.swd, &fp->status) || | |
158 | __put_user(X86_FXSR_MAGIC, &fp->magic)) | |
159 | return -1; | |
160 | } else { | |
161 | struct i387_fsave_struct __user *fp = buf; | |
162 | u32 swd; | |
163 | if (__get_user(swd, &fp->swd) || __put_user(swd, &fp->status)) | |
164 | return -1; | |
165 | } | |
166 | ||
167 | return 0; | |
168 | } | |
169 | ||
170 | static inline int save_xstate_epilog(void __user *buf, int ia32_frame) | |
ab513701 | 171 | { |
72a671ce SS |
172 | struct xsave_struct __user *x = buf; |
173 | struct _fpx_sw_bytes *sw_bytes; | |
400e4b20 | 174 | u32 xfeatures; |
72a671ce | 175 | int err; |
ab513701 | 176 | |
72a671ce SS |
177 | /* Setup the bytes not touched by the [f]xsave and reserved for SW. */ |
178 | sw_bytes = ia32_frame ? &fx_sw_reserved_ia32 : &fx_sw_reserved; | |
179 | err = __copy_to_user(&x->i387.sw_reserved, sw_bytes, sizeof(*sw_bytes)); | |
ab513701 | 180 | |
72a671ce SS |
181 | if (!use_xsave()) |
182 | return err; | |
ab513701 | 183 | |
72a671ce | 184 | err |= __put_user(FP_XSTATE_MAGIC2, (__u32 *)(buf + xstate_size)); |
ab513701 | 185 | |
72a671ce | 186 | /* |
400e4b20 | 187 | * Read the xfeatures which we copied (directly from the cpu or |
72a671ce SS |
188 | * from the state in task struct) to the user buffers. |
189 | */ | |
400e4b20 | 190 | err |= __get_user(xfeatures, (__u32 *)&x->header.xfeatures); |
06c38d5e | 191 | |
72a671ce SS |
192 | /* |
193 | * For legacy compatible, we always set FP/SSE bits in the bit | |
194 | * vector while saving the state to the user context. This will | |
195 | * enable us capturing any changes(during sigreturn) to | |
196 | * the FP/SSE bits by the legacy applications which don't touch | |
400e4b20 | 197 | * xfeatures in the xsave header. |
72a671ce | 198 | * |
400e4b20 | 199 | * xsave aware apps can change the xfeatures in the xsave |
72a671ce SS |
200 | * header as well as change any contents in the memory layout. |
201 | * xrestore as part of sigreturn will capture all the changes. | |
202 | */ | |
400e4b20 | 203 | xfeatures |= XSTATE_FPSSE; |
c37b5efe | 204 | |
400e4b20 | 205 | err |= __put_user(xfeatures, (__u32 *)&x->header.xfeatures); |
72a671ce SS |
206 | |
207 | return err; | |
208 | } | |
209 | ||
210 | static inline int save_user_xstate(struct xsave_struct __user *buf) | |
211 | { | |
212 | int err; | |
213 | ||
214 | if (use_xsave()) | |
215 | err = xsave_user(buf); | |
216 | else if (use_fxsr()) | |
217 | err = fxsave_user((struct i387_fxsave_struct __user *) buf); | |
218 | else | |
219 | err = fsave_user((struct i387_fsave_struct __user *) buf); | |
220 | ||
221 | if (unlikely(err) && __clear_user(buf, xstate_size)) | |
222 | err = -EFAULT; | |
223 | return err; | |
224 | } | |
225 | ||
226 | /* | |
227 | * Save the fpu, extended register state to the user signal frame. | |
228 | * | |
229 | * 'buf_fx' is the 64-byte aligned pointer at which the [f|fx|x]save | |
230 | * state is copied. | |
231 | * 'buf' points to the 'buf_fx' or to the fsave header followed by 'buf_fx'. | |
232 | * | |
233 | * buf == buf_fx for 64-bit frames and 32-bit fsave frame. | |
234 | * buf != buf_fx for 32-bit frames with fxstate. | |
235 | * | |
236 | * If the fpu, extended register state is live, save the state directly | |
237 | * to the user frame pointed by the aligned pointer 'buf_fx'. Otherwise, | |
238 | * copy the thread's fpu state to the user frame starting at 'buf_fx'. | |
239 | * | |
240 | * If this is a 32-bit frame with fxstate, put a fsave header before | |
241 | * the aligned state at 'buf_fx'. | |
242 | * | |
243 | * For [f]xsave state, update the SW reserved fields in the [f]xsave frame | |
244 | * indicating the absence/presence of the extended state to the user. | |
245 | */ | |
246 | int save_xstate_sig(void __user *buf, void __user *buf_fx, int size) | |
247 | { | |
248 | struct xsave_struct *xsave = ¤t->thread.fpu.state->xsave; | |
249 | struct task_struct *tsk = current; | |
250 | int ia32_fxstate = (buf != buf_fx); | |
251 | ||
252 | ia32_fxstate &= (config_enabled(CONFIG_X86_32) || | |
253 | config_enabled(CONFIG_IA32_EMULATION)); | |
254 | ||
255 | if (!access_ok(VERIFY_WRITE, buf, size)) | |
256 | return -EACCES; | |
257 | ||
60e019eb | 258 | if (!static_cpu_has(X86_FEATURE_FPU)) |
72a671ce SS |
259 | return fpregs_soft_get(current, NULL, 0, |
260 | sizeof(struct user_i387_ia32_struct), NULL, | |
261 | (struct _fpstate_ia32 __user *) buf) ? -1 : 1; | |
262 | ||
263 | if (user_has_fpu()) { | |
264 | /* Save the live register state to the user directly. */ | |
265 | if (save_user_xstate(buf_fx)) | |
266 | return -1; | |
267 | /* Update the thread's fxstate to save the fsave header. */ | |
268 | if (ia32_fxstate) | |
269 | fpu_fxsave(&tsk->thread.fpu); | |
ab513701 | 270 | } else { |
29104e10 | 271 | sanitize_i387_state(tsk); |
72a671ce | 272 | if (__copy_to_user(buf_fx, xsave, xstate_size)) |
ab513701 SS |
273 | return -1; |
274 | } | |
c37b5efe | 275 | |
72a671ce SS |
276 | /* Save the fsave header for the 32-bit frames. */ |
277 | if ((ia32_fxstate || !use_fxsr()) && save_fsave_header(tsk, buf)) | |
278 | return -1; | |
06c38d5e | 279 | |
72a671ce SS |
280 | if (use_fxsr() && save_xstate_epilog(buf_fx, ia32_fxstate)) |
281 | return -1; | |
282 | ||
72a671ce SS |
283 | return 0; |
284 | } | |
c37b5efe | 285 | |
72a671ce SS |
286 | static inline void |
287 | sanitize_restored_xstate(struct task_struct *tsk, | |
288 | struct user_i387_ia32_struct *ia32_env, | |
400e4b20 | 289 | u64 xfeatures, int fx_only) |
72a671ce SS |
290 | { |
291 | struct xsave_struct *xsave = &tsk->thread.fpu.state->xsave; | |
3a54450b | 292 | struct xstate_header *header = &xsave->header; |
c37b5efe | 293 | |
72a671ce SS |
294 | if (use_xsave()) { |
295 | /* These bits must be zero. */ | |
3a54450b | 296 | memset(header->reserved, 0, 48); |
04944b79 SS |
297 | |
298 | /* | |
72a671ce SS |
299 | * Init the state that is not present in the memory |
300 | * layout and not enabled by the OS. | |
04944b79 | 301 | */ |
72a671ce | 302 | if (fx_only) |
400e4b20 | 303 | header->xfeatures = XSTATE_FPSSE; |
72a671ce | 304 | else |
400e4b20 | 305 | header->xfeatures &= (xfeatures_mask & xfeatures); |
72a671ce | 306 | } |
04944b79 | 307 | |
72a671ce | 308 | if (use_fxsr()) { |
04944b79 | 309 | /* |
72a671ce SS |
310 | * mscsr reserved bits must be masked to zero for security |
311 | * reasons. | |
04944b79 | 312 | */ |
72a671ce | 313 | xsave->i387.mxcsr &= mxcsr_feature_mask; |
04944b79 | 314 | |
72a671ce | 315 | convert_to_fxsr(tsk, ia32_env); |
c37b5efe | 316 | } |
ab513701 SS |
317 | } |
318 | ||
c37b5efe | 319 | /* |
72a671ce | 320 | * Restore the extended state if present. Otherwise, restore the FP/SSE state. |
c37b5efe | 321 | */ |
72a671ce | 322 | static inline int restore_user_xstate(void __user *buf, u64 xbv, int fx_only) |
c37b5efe | 323 | { |
72a671ce SS |
324 | if (use_xsave()) { |
325 | if ((unsigned long)buf % 64 || fx_only) { | |
614df7fb | 326 | u64 init_bv = xfeatures_mask & ~XSTATE_FPSSE; |
3e5e1267 | 327 | xrstor_state(&init_xstate_ctx, init_bv); |
e139e955 | 328 | return fxrstor_user(buf); |
72a671ce | 329 | } else { |
614df7fb | 330 | u64 init_bv = xfeatures_mask & ~xbv; |
72a671ce | 331 | if (unlikely(init_bv)) |
3e5e1267 | 332 | xrstor_state(&init_xstate_ctx, init_bv); |
72a671ce SS |
333 | return xrestore_user(buf, xbv); |
334 | } | |
335 | } else if (use_fxsr()) { | |
e139e955 | 336 | return fxrstor_user(buf); |
72a671ce | 337 | } else |
e139e955 | 338 | return frstor_user(buf); |
c37b5efe SS |
339 | } |
340 | ||
72a671ce | 341 | int __restore_xstate_sig(void __user *buf, void __user *buf_fx, int size) |
ab513701 | 342 | { |
72a671ce | 343 | int ia32_fxstate = (buf != buf_fx); |
ab513701 | 344 | struct task_struct *tsk = current; |
c5bedc68 | 345 | struct fpu *fpu = &tsk->thread.fpu; |
72a671ce | 346 | int state_size = xstate_size; |
400e4b20 | 347 | u64 xfeatures = 0; |
72a671ce SS |
348 | int fx_only = 0; |
349 | ||
350 | ia32_fxstate &= (config_enabled(CONFIG_X86_32) || | |
351 | config_enabled(CONFIG_IA32_EMULATION)); | |
ab513701 SS |
352 | |
353 | if (!buf) { | |
af2d94fd | 354 | fpu_reset_state(fpu); |
ab513701 | 355 | return 0; |
72a671ce SS |
356 | } |
357 | ||
358 | if (!access_ok(VERIFY_READ, buf, size)) | |
359 | return -EACCES; | |
360 | ||
db2b1d3a | 361 | if (!fpu->fpstate_active && fpstate_alloc_init(fpu)) |
72a671ce | 362 | return -1; |
ab513701 | 363 | |
60e019eb | 364 | if (!static_cpu_has(X86_FEATURE_FPU)) |
72a671ce SS |
365 | return fpregs_soft_set(current, NULL, |
366 | 0, sizeof(struct user_i387_ia32_struct), | |
367 | NULL, buf) != 0; | |
ab513701 | 368 | |
72a671ce SS |
369 | if (use_xsave()) { |
370 | struct _fpx_sw_bytes fx_sw_user; | |
371 | if (unlikely(check_for_xstate(buf_fx, buf_fx, &fx_sw_user))) { | |
372 | /* | |
373 | * Couldn't find the extended state information in the | |
374 | * memory layout. Restore just the FP/SSE and init all | |
375 | * the other extended state. | |
376 | */ | |
377 | state_size = sizeof(struct i387_fxsave_struct); | |
378 | fx_only = 1; | |
379 | } else { | |
380 | state_size = fx_sw_user.xstate_size; | |
400e4b20 | 381 | xfeatures = fx_sw_user.xfeatures; |
72a671ce SS |
382 | } |
383 | } | |
384 | ||
385 | if (ia32_fxstate) { | |
386 | /* | |
387 | * For 32-bit frames with fxstate, copy the user state to the | |
388 | * thread's fpu state, reconstruct fxstate from the fsave | |
389 | * header. Sanitize the copied state etc. | |
390 | */ | |
a7c80ebc | 391 | struct fpu *fpu = &tsk->thread.fpu; |
72a671ce | 392 | struct user_i387_ia32_struct env; |
304bceda | 393 | int err = 0; |
72a671ce | 394 | |
304bceda | 395 | /* |
c5bedc68 | 396 | * Drop the current fpu which clears fpu->fpstate_active. This ensures |
304bceda SS |
397 | * that any context-switch during the copy of the new state, |
398 | * avoids the intermediate state from getting restored/saved. | |
399 | * Thus avoiding the new restored state from getting corrupted. | |
400 | * We will be ready to restore/save the state only after | |
c5bedc68 | 401 | * fpu->fpstate_active is again set. |
304bceda | 402 | */ |
ca6787ba | 403 | drop_fpu(fpu); |
72a671ce | 404 | |
a7c80ebc | 405 | if (__copy_from_user(&fpu->state->xsave, buf_fx, state_size) || |
304bceda | 406 | __copy_from_user(&env, buf, sizeof(env))) { |
c0ee2cf6 | 407 | fpstate_init(fpu); |
304bceda SS |
408 | err = -1; |
409 | } else { | |
400e4b20 | 410 | sanitize_restored_xstate(tsk, &env, xfeatures, fx_only); |
304bceda | 411 | } |
72a671ce | 412 | |
c5bedc68 | 413 | fpu->fpstate_active = 1; |
df24fb85 ON |
414 | if (use_eager_fpu()) { |
415 | preempt_disable(); | |
3a0aee48 | 416 | fpu__restore(); |
df24fb85 ON |
417 | preempt_enable(); |
418 | } | |
304bceda SS |
419 | |
420 | return err; | |
72a671ce | 421 | } else { |
ab513701 | 422 | /* |
72a671ce SS |
423 | * For 64-bit frames and 32-bit fsave frames, restore the user |
424 | * state to the registers directly (with exceptions handled). | |
ab513701 | 425 | */ |
72a671ce | 426 | user_fpu_begin(); |
400e4b20 | 427 | if (restore_user_xstate(buf_fx, xfeatures, fx_only)) { |
af2d94fd | 428 | fpu_reset_state(fpu); |
72a671ce SS |
429 | return -1; |
430 | } | |
ab513701 | 431 | } |
72a671ce SS |
432 | |
433 | return 0; | |
ab513701 | 434 | } |
ab513701 | 435 | |
c37b5efe SS |
436 | /* |
437 | * Prepare the SW reserved portion of the fxsave memory layout, indicating | |
438 | * the presence of the extended state information in the memory layout | |
439 | * pointed by the fpstate pointer in the sigcontext. | |
440 | * This will be saved when ever the FP and extended state context is | |
441 | * saved on the user stack during the signal handler delivery to the user. | |
442 | */ | |
8bcad30f | 443 | static void prepare_fx_sw_frame(void) |
c37b5efe | 444 | { |
72a671ce SS |
445 | int fsave_header_size = sizeof(struct i387_fsave_struct); |
446 | int size = xstate_size + FP_XSTATE_MAGIC2_SIZE; | |
c37b5efe | 447 | |
72a671ce SS |
448 | if (config_enabled(CONFIG_X86_32)) |
449 | size += fsave_header_size; | |
c37b5efe SS |
450 | |
451 | fx_sw_reserved.magic1 = FP_XSTATE_MAGIC1; | |
72a671ce | 452 | fx_sw_reserved.extended_size = size; |
400e4b20 | 453 | fx_sw_reserved.xfeatures = xfeatures_mask; |
c37b5efe | 454 | fx_sw_reserved.xstate_size = xstate_size; |
c37b5efe | 455 | |
72a671ce SS |
456 | if (config_enabled(CONFIG_IA32_EMULATION)) { |
457 | fx_sw_reserved_ia32 = fx_sw_reserved; | |
458 | fx_sw_reserved_ia32.extended_size += fsave_header_size; | |
459 | } | |
460 | } | |
3c1c7f10 | 461 | |
dc1e35c6 | 462 | /* |
55cc4678 IM |
463 | * Enable the extended processor state save/restore feature. |
464 | * Called once per CPU onlining. | |
dc1e35c6 | 465 | */ |
55cc4678 | 466 | void fpu__init_cpu_xstate(void) |
dc1e35c6 | 467 | { |
e84611fc | 468 | if (!cpu_has_xsave || !xfeatures_mask) |
55cc4678 IM |
469 | return; |
470 | ||
375074cc | 471 | cr4_set_bits(X86_CR4_OSXSAVE); |
614df7fb | 472 | xsetbv(XCR_XFEATURE_ENABLED_MASK, xfeatures_mask); |
dc1e35c6 SS |
473 | } |
474 | ||
a1488f8b SS |
475 | /* |
476 | * Record the offsets and sizes of different state managed by the xsave | |
477 | * memory layout. | |
478 | */ | |
4995b9db | 479 | static void __init setup_xstate_features(void) |
a1488f8b SS |
480 | { |
481 | int eax, ebx, ecx, edx, leaf = 0x2; | |
482 | ||
84246fe4 | 483 | xfeatures_nr = fls64(xfeatures_mask); |
a1488f8b SS |
484 | |
485 | do { | |
ee813d53 | 486 | cpuid_count(XSTATE_CPUID, leaf, &eax, &ebx, &ecx, &edx); |
a1488f8b SS |
487 | |
488 | if (eax == 0) | |
489 | break; | |
490 | ||
491 | xstate_offsets[leaf] = ebx; | |
492 | xstate_sizes[leaf] = eax; | |
493 | ||
494 | leaf++; | |
495 | } while (1); | |
496 | } | |
497 | ||
69496e10 IM |
498 | static void print_xstate_feature(u64 xstate_mask, const char *desc) |
499 | { | |
614df7fb | 500 | if (xfeatures_mask & xstate_mask) { |
69496e10 IM |
501 | int xstate_feature = fls64(xstate_mask)-1; |
502 | ||
503 | pr_info("x86/fpu: Supporting XSAVE feature %2d: '%s'\n", xstate_feature, desc); | |
504 | } | |
505 | } | |
506 | ||
507 | /* | |
508 | * Print out all the supported xstate features: | |
509 | */ | |
510 | static void print_xstate_features(void) | |
511 | { | |
512 | print_xstate_feature(XSTATE_FP, "x87 floating point registers"); | |
513 | print_xstate_feature(XSTATE_SSE, "SSE registers"); | |
514 | print_xstate_feature(XSTATE_YMM, "AVX registers"); | |
515 | print_xstate_feature(XSTATE_BNDREGS, "MPX bounds registers"); | |
516 | print_xstate_feature(XSTATE_BNDCSR, "MPX CSR"); | |
517 | print_xstate_feature(XSTATE_OPMASK, "AVX-512 opmask"); | |
518 | print_xstate_feature(XSTATE_ZMM_Hi256, "AVX-512 Hi256"); | |
519 | print_xstate_feature(XSTATE_Hi16_ZMM, "AVX-512 ZMM_Hi256"); | |
520 | } | |
521 | ||
7496d645 FY |
522 | /* |
523 | * This function sets up offsets and sizes of all extended states in | |
524 | * xsave area. This supports both standard format and compacted format | |
525 | * of the xsave aread. | |
526 | * | |
527 | * Input: void | |
528 | * Output: void | |
529 | */ | |
530 | void setup_xstate_comp(void) | |
531 | { | |
614df7fb | 532 | unsigned int xstate_comp_sizes[sizeof(xfeatures_mask)*8]; |
7496d645 FY |
533 | int i; |
534 | ||
8ff925e1 FY |
535 | /* |
536 | * The FP xstates and SSE xstates are legacy states. They are always | |
537 | * in the fixed offsets in the xsave area in either compacted form | |
538 | * or standard form. | |
539 | */ | |
540 | xstate_comp_offsets[0] = 0; | |
541 | xstate_comp_offsets[1] = offsetof(struct i387_fxsave_struct, xmm_space); | |
7496d645 FY |
542 | |
543 | if (!cpu_has_xsaves) { | |
84246fe4 | 544 | for (i = 2; i < xfeatures_nr; i++) { |
614df7fb | 545 | if (test_bit(i, (unsigned long *)&xfeatures_mask)) { |
7496d645 FY |
546 | xstate_comp_offsets[i] = xstate_offsets[i]; |
547 | xstate_comp_sizes[i] = xstate_sizes[i]; | |
548 | } | |
549 | } | |
550 | return; | |
551 | } | |
552 | ||
553 | xstate_comp_offsets[2] = FXSAVE_SIZE + XSAVE_HDR_SIZE; | |
554 | ||
84246fe4 | 555 | for (i = 2; i < xfeatures_nr; i++) { |
614df7fb | 556 | if (test_bit(i, (unsigned long *)&xfeatures_mask)) |
7496d645 FY |
557 | xstate_comp_sizes[i] = xstate_sizes[i]; |
558 | else | |
559 | xstate_comp_sizes[i] = 0; | |
560 | ||
561 | if (i > 2) | |
562 | xstate_comp_offsets[i] = xstate_comp_offsets[i-1] | |
563 | + xstate_comp_sizes[i-1]; | |
564 | ||
565 | } | |
566 | } | |
567 | ||
dc1e35c6 SS |
568 | /* |
569 | * setup the xstate image representing the init state | |
570 | */ | |
26b1f5d0 | 571 | static void setup_init_fpu_buf(void) |
dc1e35c6 | 572 | { |
26b1f5d0 IM |
573 | static int on_boot_cpu = 1; |
574 | ||
575 | if (!on_boot_cpu) | |
576 | return; | |
577 | on_boot_cpu = 0; | |
578 | ||
29104e10 | 579 | /* |
3e5e1267 | 580 | * Setup init_xstate_ctx to represent the init state of |
29104e10 SS |
581 | * all the features managed by the xsave |
582 | */ | |
3e5e1267 | 583 | fx_finit(&init_xstate_ctx.i387); |
5d2bd700 SS |
584 | |
585 | if (!cpu_has_xsave) | |
586 | return; | |
587 | ||
588 | setup_xstate_features(); | |
69496e10 | 589 | print_xstate_features(); |
a1488f8b | 590 | |
47c2f292 | 591 | if (cpu_has_xsaves) { |
3e5e1267 IM |
592 | init_xstate_ctx.header.xcomp_bv = (u64)1 << 63 | xfeatures_mask; |
593 | init_xstate_ctx.header.xfeatures = xfeatures_mask; | |
47c2f292 FY |
594 | } |
595 | ||
29104e10 SS |
596 | /* |
597 | * Init all the features state with header_bv being 0x0 | |
598 | */ | |
3e5e1267 | 599 | xrstor_state_booting(&init_xstate_ctx, -1); |
3e261c14 | 600 | |
29104e10 SS |
601 | /* |
602 | * Dump the init state again. This is to identify the init state | |
603 | * of any feature which is not represented by all zero's. | |
604 | */ | |
3e5e1267 | 605 | xsave_state_booting(&init_xstate_ctx); |
dc1e35c6 SS |
606 | } |
607 | ||
e0022981 | 608 | static enum { AUTO, ENABLE, DISABLE } eagerfpu = AUTO; |
5d2bd700 SS |
609 | static int __init eager_fpu_setup(char *s) |
610 | { | |
611 | if (!strcmp(s, "on")) | |
e0022981 | 612 | eagerfpu = ENABLE; |
5d2bd700 | 613 | else if (!strcmp(s, "off")) |
e0022981 SS |
614 | eagerfpu = DISABLE; |
615 | else if (!strcmp(s, "auto")) | |
616 | eagerfpu = AUTO; | |
5d2bd700 SS |
617 | return 1; |
618 | } | |
619 | __setup("eagerfpu=", eager_fpu_setup); | |
620 | ||
7e7ce87f FY |
621 | |
622 | /* | |
614df7fb | 623 | * Calculate total size of enabled xstates in XCR0/xfeatures_mask. |
7e7ce87f FY |
624 | */ |
625 | static void __init init_xstate_size(void) | |
626 | { | |
627 | unsigned int eax, ebx, ecx, edx; | |
628 | int i; | |
629 | ||
630 | if (!cpu_has_xsaves) { | |
631 | cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx); | |
632 | xstate_size = ebx; | |
633 | return; | |
634 | } | |
635 | ||
636 | xstate_size = FXSAVE_SIZE + XSAVE_HDR_SIZE; | |
637 | for (i = 2; i < 64; i++) { | |
614df7fb | 638 | if (test_bit(i, (unsigned long *)&xfeatures_mask)) { |
7e7ce87f FY |
639 | cpuid_count(XSTATE_CPUID, i, &eax, &ebx, &ecx, &edx); |
640 | xstate_size += eax; | |
641 | } | |
642 | } | |
643 | } | |
644 | ||
dc1e35c6 SS |
645 | /* |
646 | * Enable and initialize the xsave feature. | |
55cc4678 | 647 | * Called once per system bootup. |
c0841e34 IM |
648 | * |
649 | * ( Not marked __init because of false positive section warnings | |
650 | * generated by xsave_init(). ) | |
dc1e35c6 | 651 | */ |
55cc4678 | 652 | void fpu__init_system_xstate(void) |
dc1e35c6 SS |
653 | { |
654 | unsigned int eax, ebx, ecx, edx; | |
655 | ||
e9dbfd67 IM |
656 | if (!cpu_has_xsave) { |
657 | pr_info("x86/fpu: Legacy x87 FPU detected.\n"); | |
658 | return; | |
659 | } | |
660 | ||
ee813d53 | 661 | if (boot_cpu_data.cpuid_level < XSTATE_CPUID) { |
32d4d9cc | 662 | WARN(1, "x86/fpu: XSTATE_CPUID missing!\n"); |
ee813d53 RR |
663 | return; |
664 | } | |
665 | ||
666 | cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx); | |
614df7fb | 667 | xfeatures_mask = eax + ((u64)edx << 32); |
dc1e35c6 | 668 | |
614df7fb IM |
669 | if ((xfeatures_mask & XSTATE_FPSSE) != XSTATE_FPSSE) { |
670 | pr_err("x86/fpu: FP/SSE not present amongst the CPU's xstate features: 0x%llx.\n", xfeatures_mask); | |
dc1e35c6 SS |
671 | BUG(); |
672 | } | |
673 | ||
674 | /* | |
a30469e7 | 675 | * Support only the state known to OS. |
dc1e35c6 | 676 | */ |
614df7fb | 677 | xfeatures_mask = xfeatures_mask & XCNTXT_MASK; |
97e80a70 | 678 | |
55cc4678 IM |
679 | /* Enable xstate instructions to be able to continue with initialization: */ |
680 | fpu__init_cpu_xstate(); | |
dc1e35c6 SS |
681 | |
682 | /* | |
683 | * Recompute the context size for enabled features | |
684 | */ | |
7e7ce87f | 685 | init_xstate_size(); |
dc1e35c6 | 686 | |
614df7fb | 687 | update_regset_xstate_info(xstate_size, xfeatures_mask); |
c37b5efe | 688 | prepare_fx_sw_frame(); |
5d2bd700 | 689 | setup_init_fpu_buf(); |
dc1e35c6 | 690 | |
e0022981 SS |
691 | /* Auto enable eagerfpu for xsaveopt */ |
692 | if (cpu_has_xsaveopt && eagerfpu != DISABLE) | |
693 | eagerfpu = ENABLE; | |
212b0212 | 694 | |
614df7fb | 695 | if (xfeatures_mask & XSTATE_EAGER) { |
e7d820a5 | 696 | if (eagerfpu == DISABLE) { |
32d4d9cc | 697 | pr_err("x86/fpu: eagerfpu switching disabled, disabling the following xstate features: 0x%llx.\n", |
614df7fb IM |
698 | xfeatures_mask & XSTATE_EAGER); |
699 | xfeatures_mask &= ~XSTATE_EAGER; | |
e7d820a5 QR |
700 | } else { |
701 | eagerfpu = ENABLE; | |
702 | } | |
703 | } | |
704 | ||
32d4d9cc | 705 | pr_info("x86/fpu: Enabled xstate features 0x%llx, context size is 0x%x bytes, using '%s' format.\n", |
614df7fb | 706 | xfeatures_mask, |
32d4d9cc IM |
707 | xstate_size, |
708 | cpu_has_xsaves ? "compacted" : "standard"); | |
dc1e35c6 | 709 | } |
82d4150c | 710 | |
1cff92d8 | 711 | /* |
55cc4678 IM |
712 | * For the very first instance, this calls fpu__init_system_xstate(); |
713 | * for all subsequent instances, this calls fpu__init_cpu_xstate(). | |
1cff92d8 | 714 | */ |
148f9bb8 | 715 | void xsave_init(void) |
82d4150c | 716 | { |
c0841e34 | 717 | static char on_boot_cpu = 1; |
1cff92d8 | 718 | |
c0841e34 IM |
719 | if (on_boot_cpu) { |
720 | on_boot_cpu = 0; | |
55cc4678 | 721 | fpu__init_system_xstate(); |
c0841e34 | 722 | } else { |
55cc4678 | 723 | fpu__init_cpu_xstate(); |
c0841e34 | 724 | } |
82d4150c | 725 | } |
5d2bd700 | 726 | |
7fc253e2 ON |
727 | /* |
728 | * setup_init_fpu_buf() is __init and it is OK to call it here because | |
3e5e1267 | 729 | * init_xstate_ctx will be unset only once during boot. |
7fc253e2 ON |
730 | */ |
731 | void __init_refok eager_fpu_init(void) | |
5d2bd700 | 732 | { |
c5bedc68 | 733 | WARN_ON(current->thread.fpu.fpstate_active); |
5d2bd700 | 734 | current_thread_info()->status = 0; |
e0022981 SS |
735 | |
736 | if (eagerfpu == ENABLE) | |
737 | setup_force_cpu_cap(X86_FEATURE_EAGER_FPU); | |
738 | ||
9a89b029 IM |
739 | printk_once(KERN_INFO "x86/fpu: Using '%s' FPU context switches.\n", eagerfpu == ENABLE ? "eager" : "lazy"); |
740 | ||
5d2bd700 SS |
741 | if (!cpu_has_eager_fpu) { |
742 | stts(); | |
743 | return; | |
744 | } | |
745 | ||
26b1f5d0 | 746 | setup_init_fpu_buf(); |
5d2bd700 | 747 | } |
7496d645 | 748 | |
9254aaa0 IM |
749 | /* |
750 | * Restore minimal FPU state after suspend: | |
751 | */ | |
752 | void fpu__resume_cpu(void) | |
753 | { | |
754 | /* | |
755 | * Restore XCR0 on xsave capable CPUs: | |
756 | */ | |
757 | if (cpu_has_xsave) | |
758 | xsetbv(XCR_XFEATURE_ENABLED_MASK, xfeatures_mask); | |
759 | } | |
760 | ||
7496d645 FY |
761 | /* |
762 | * Given the xsave area and a state inside, this function returns the | |
763 | * address of the state. | |
764 | * | |
765 | * This is the API that is called to get xstate address in either | |
766 | * standard format or compacted format of xsave area. | |
767 | * | |
768 | * Inputs: | |
769 | * xsave: base address of the xsave area; | |
770 | * xstate: state which is defined in xsave.h (e.g. XSTATE_FP, XSTATE_SSE, | |
771 | * etc.) | |
772 | * Output: | |
773 | * address of the state in the xsave area. | |
774 | */ | |
775 | void *get_xsave_addr(struct xsave_struct *xsave, int xstate) | |
776 | { | |
777 | int feature = fls64(xstate) - 1; | |
614df7fb | 778 | if (!test_bit(feature, (unsigned long *)&xfeatures_mask)) |
7496d645 FY |
779 | return NULL; |
780 | ||
781 | return (void *)xsave + xstate_comp_offsets[feature]; | |
782 | } | |
ba7b3920 | 783 | EXPORT_SYMBOL_GPL(get_xsave_addr); |