Commit | Line | Data |
---|---|---|
dc1e35c6 SS |
1 | /* |
2 | * xsave/xrstor support. | |
3 | * | |
4 | * Author: Suresh Siddha <suresh.b.siddha@intel.com> | |
5 | */ | |
dc1e35c6 | 6 | #include <linux/compat.h> |
7e7ce87f | 7 | #include <linux/cpu.h> |
df6b35f4 | 8 | #include <asm/fpu/api.h> |
78f7f1e5 | 9 | #include <asm/fpu/internal.h> |
72a671ce | 10 | #include <asm/sigframe.h> |
375074cc | 11 | #include <asm/tlbflush.h> |
dc1e35c6 | 12 | |
5b073430 IM |
13 | static const char *xfeature_names[] = |
14 | { | |
15 | "x87 floating point registers" , | |
16 | "SSE registers" , | |
17 | "AVX registers" , | |
18 | "MPX bounds registers" , | |
19 | "MPX CSR" , | |
20 | "AVX-512 opmask" , | |
21 | "AVX-512 Hi256" , | |
22 | "AVX-512 ZMM_Hi256" , | |
23 | "unknown xstate feature" , | |
24 | }; | |
25 | ||
dc1e35c6 | 26 | /* |
614df7fb | 27 | * Mask of xstate features supported by the CPU and the kernel: |
dc1e35c6 | 28 | */ |
5b073430 | 29 | u64 xfeatures_mask __read_mostly; |
dc1e35c6 | 30 | |
45c2d7f4 RR |
31 | /* |
32 | * Represents init state for the supported extended state. | |
33 | */ | |
3e5e1267 | 34 | struct xsave_struct init_xstate_ctx; |
45c2d7f4 | 35 | |
72a671ce | 36 | static struct _fpx_sw_bytes fx_sw_reserved, fx_sw_reserved_ia32; |
966ece61 | 37 | static unsigned int xstate_offsets[XFEATURES_NR_MAX], xstate_sizes[XFEATURES_NR_MAX]; |
614df7fb | 38 | static unsigned int xstate_comp_offsets[sizeof(xfeatures_mask)*8]; |
84246fe4 IM |
39 | |
40 | /* The number of supported xfeatures in xfeatures_mask: */ | |
41 | static unsigned int xfeatures_nr; | |
a1488f8b | 42 | |
5b073430 IM |
43 | /* |
44 | * Return whether the system supports a given xfeature. | |
45 | * | |
46 | * Also return the name of the (most advanced) feature that the caller requested: | |
47 | */ | |
48 | int cpu_has_xfeatures(u64 xfeatures_needed, const char **feature_name) | |
49 | { | |
50 | u64 xfeatures_missing = xfeatures_needed & ~xfeatures_mask; | |
51 | ||
52 | if (unlikely(feature_name)) { | |
53 | long xfeature_idx, max_idx; | |
54 | u64 xfeatures_print; | |
55 | /* | |
56 | * So we use FLS here to be able to print the most advanced | |
57 | * feature that was requested but is missing. So if a driver | |
58 | * asks about "XSTATE_SSE | XSTATE_YMM" we'll print the | |
59 | * missing AVX feature - this is the most informative message | |
60 | * to users: | |
61 | */ | |
62 | if (xfeatures_missing) | |
63 | xfeatures_print = xfeatures_missing; | |
64 | else | |
65 | xfeatures_print = xfeatures_needed; | |
66 | ||
67 | xfeature_idx = fls64(xfeatures_print)-1; | |
68 | max_idx = ARRAY_SIZE(xfeature_names)-1; | |
69 | xfeature_idx = min(xfeature_idx, max_idx); | |
70 | ||
71 | *feature_name = xfeature_names[xfeature_idx]; | |
72 | } | |
73 | ||
74 | if (xfeatures_missing) | |
75 | return 0; | |
76 | ||
77 | return 1; | |
78 | } | |
79 | EXPORT_SYMBOL_GPL(cpu_has_xfeatures); | |
80 | ||
29104e10 | 81 | /* |
73a3aeb3 IM |
82 | * When executing XSAVEOPT (optimized XSAVE), if a processor implementation |
83 | * detects that an FPU state component is still (or is again) in its | |
84 | * initialized state, it may clear the corresponding bit in the header.xfeatures | |
85 | * field, and can skip the writeout of registers to the corresponding memory layout. | |
86 | * | |
87 | * This means that when the bit is zero, the state component might still contain | |
88 | * some previous - non-initialized register state. | |
89 | * | |
90 | * Before writing xstate information to user-space we sanitize those components, | |
91 | * to always ensure that the memory layout of a feature will be in the init state | |
92 | * if the corresponding header bit is zero. This is to ensure that user-space doesn't | |
93 | * see some stale state in the memory layout during signal handling, debugging etc. | |
29104e10 | 94 | */ |
d0903193 | 95 | void __fpstate_sanitize_xstate(struct task_struct *tsk) |
29104e10 | 96 | { |
7366ed77 | 97 | struct i387_fxsave_struct *fx = &tsk->thread.fpu.state.fxsave; |
73a3aeb3 | 98 | int feature_bit; |
400e4b20 | 99 | u64 xfeatures; |
29104e10 SS |
100 | |
101 | if (!fx) | |
102 | return; | |
103 | ||
7366ed77 | 104 | xfeatures = tsk->thread.fpu.state.xsave.header.xfeatures; |
29104e10 SS |
105 | |
106 | /* | |
107 | * None of the feature bits are in init state. So nothing else | |
0d2eb44f | 108 | * to do for us, as the memory layout is up to date. |
29104e10 | 109 | */ |
400e4b20 | 110 | if ((xfeatures & xfeatures_mask) == xfeatures_mask) |
29104e10 SS |
111 | return; |
112 | ||
113 | /* | |
114 | * FP is in init state | |
115 | */ | |
400e4b20 | 116 | if (!(xfeatures & XSTATE_FP)) { |
29104e10 SS |
117 | fx->cwd = 0x37f; |
118 | fx->swd = 0; | |
119 | fx->twd = 0; | |
120 | fx->fop = 0; | |
121 | fx->rip = 0; | |
122 | fx->rdp = 0; | |
123 | memset(&fx->st_space[0], 0, 128); | |
124 | } | |
125 | ||
126 | /* | |
127 | * SSE is in init state | |
128 | */ | |
400e4b20 | 129 | if (!(xfeatures & XSTATE_SSE)) |
29104e10 SS |
130 | memset(&fx->xmm_space[0], 0, 256); |
131 | ||
73a3aeb3 IM |
132 | /* |
133 | * First two features are FPU and SSE, which above we handled | |
134 | * in a special way already: | |
135 | */ | |
136 | feature_bit = 0x2; | |
400e4b20 | 137 | xfeatures = (xfeatures_mask & ~xfeatures) >> 2; |
29104e10 SS |
138 | |
139 | /* | |
73a3aeb3 IM |
140 | * Update all the remaining memory layouts according to their |
141 | * standard xstate layout, if their header bit is in the init | |
142 | * state: | |
29104e10 | 143 | */ |
400e4b20 IM |
144 | while (xfeatures) { |
145 | if (xfeatures & 0x1) { | |
29104e10 SS |
146 | int offset = xstate_offsets[feature_bit]; |
147 | int size = xstate_sizes[feature_bit]; | |
148 | ||
73a3aeb3 | 149 | memcpy((void *)fx + offset, |
3e5e1267 | 150 | (void *)&init_xstate_ctx + offset, |
29104e10 SS |
151 | size); |
152 | } | |
153 | ||
400e4b20 | 154 | xfeatures >>= 1; |
29104e10 SS |
155 | feature_bit++; |
156 | } | |
157 | } | |
158 | ||
c37b5efe SS |
159 | /* |
160 | * Check for the presence of extended state information in the | |
161 | * user fpstate pointer in the sigcontext. | |
162 | */ | |
72a671ce SS |
163 | static inline int check_for_xstate(struct i387_fxsave_struct __user *buf, |
164 | void __user *fpstate, | |
165 | struct _fpx_sw_bytes *fx_sw) | |
c37b5efe SS |
166 | { |
167 | int min_xstate_size = sizeof(struct i387_fxsave_struct) + | |
3a54450b | 168 | sizeof(struct xstate_header); |
c37b5efe | 169 | unsigned int magic2; |
c37b5efe | 170 | |
72a671ce SS |
171 | if (__copy_from_user(fx_sw, &buf->sw_reserved[0], sizeof(*fx_sw))) |
172 | return -1; | |
c37b5efe | 173 | |
72a671ce SS |
174 | /* Check for the first magic field and other error scenarios. */ |
175 | if (fx_sw->magic1 != FP_XSTATE_MAGIC1 || | |
176 | fx_sw->xstate_size < min_xstate_size || | |
177 | fx_sw->xstate_size > xstate_size || | |
178 | fx_sw->xstate_size > fx_sw->extended_size) | |
179 | return -1; | |
c37b5efe | 180 | |
c37b5efe SS |
181 | /* |
182 | * Check for the presence of second magic word at the end of memory | |
183 | * layout. This detects the case where the user just copied the legacy | |
184 | * fpstate layout with out copying the extended state information | |
185 | * in the memory layout. | |
186 | */ | |
72a671ce SS |
187 | if (__get_user(magic2, (__u32 __user *)(fpstate + fx_sw->xstate_size)) |
188 | || magic2 != FP_XSTATE_MAGIC2) | |
189 | return -1; | |
c37b5efe SS |
190 | |
191 | return 0; | |
192 | } | |
193 | ||
ab513701 SS |
194 | /* |
195 | * Signal frame handlers. | |
196 | */ | |
72a671ce SS |
197 | static inline int save_fsave_header(struct task_struct *tsk, void __user *buf) |
198 | { | |
199 | if (use_fxsr()) { | |
7366ed77 | 200 | struct xsave_struct *xsave = &tsk->thread.fpu.state.xsave; |
72a671ce SS |
201 | struct user_i387_ia32_struct env; |
202 | struct _fpstate_ia32 __user *fp = buf; | |
ab513701 | 203 | |
72a671ce SS |
204 | convert_from_fxsr(&env, tsk); |
205 | ||
206 | if (__copy_to_user(buf, &env, sizeof(env)) || | |
207 | __put_user(xsave->i387.swd, &fp->status) || | |
208 | __put_user(X86_FXSR_MAGIC, &fp->magic)) | |
209 | return -1; | |
210 | } else { | |
211 | struct i387_fsave_struct __user *fp = buf; | |
212 | u32 swd; | |
213 | if (__get_user(swd, &fp->swd) || __put_user(swd, &fp->status)) | |
214 | return -1; | |
215 | } | |
216 | ||
217 | return 0; | |
218 | } | |
219 | ||
220 | static inline int save_xstate_epilog(void __user *buf, int ia32_frame) | |
ab513701 | 221 | { |
72a671ce SS |
222 | struct xsave_struct __user *x = buf; |
223 | struct _fpx_sw_bytes *sw_bytes; | |
400e4b20 | 224 | u32 xfeatures; |
72a671ce | 225 | int err; |
ab513701 | 226 | |
72a671ce SS |
227 | /* Setup the bytes not touched by the [f]xsave and reserved for SW. */ |
228 | sw_bytes = ia32_frame ? &fx_sw_reserved_ia32 : &fx_sw_reserved; | |
229 | err = __copy_to_user(&x->i387.sw_reserved, sw_bytes, sizeof(*sw_bytes)); | |
ab513701 | 230 | |
72a671ce SS |
231 | if (!use_xsave()) |
232 | return err; | |
ab513701 | 233 | |
72a671ce | 234 | err |= __put_user(FP_XSTATE_MAGIC2, (__u32 *)(buf + xstate_size)); |
ab513701 | 235 | |
72a671ce | 236 | /* |
400e4b20 | 237 | * Read the xfeatures which we copied (directly from the cpu or |
72a671ce SS |
238 | * from the state in task struct) to the user buffers. |
239 | */ | |
400e4b20 | 240 | err |= __get_user(xfeatures, (__u32 *)&x->header.xfeatures); |
06c38d5e | 241 | |
72a671ce SS |
242 | /* |
243 | * For legacy compatible, we always set FP/SSE bits in the bit | |
244 | * vector while saving the state to the user context. This will | |
245 | * enable us capturing any changes(during sigreturn) to | |
246 | * the FP/SSE bits by the legacy applications which don't touch | |
400e4b20 | 247 | * xfeatures in the xsave header. |
72a671ce | 248 | * |
400e4b20 | 249 | * xsave aware apps can change the xfeatures in the xsave |
72a671ce SS |
250 | * header as well as change any contents in the memory layout. |
251 | * xrestore as part of sigreturn will capture all the changes. | |
252 | */ | |
400e4b20 | 253 | xfeatures |= XSTATE_FPSSE; |
c37b5efe | 254 | |
400e4b20 | 255 | err |= __put_user(xfeatures, (__u32 *)&x->header.xfeatures); |
72a671ce SS |
256 | |
257 | return err; | |
258 | } | |
259 | ||
260 | static inline int save_user_xstate(struct xsave_struct __user *buf) | |
261 | { | |
262 | int err; | |
263 | ||
264 | if (use_xsave()) | |
265 | err = xsave_user(buf); | |
266 | else if (use_fxsr()) | |
267 | err = fxsave_user((struct i387_fxsave_struct __user *) buf); | |
268 | else | |
269 | err = fsave_user((struct i387_fsave_struct __user *) buf); | |
270 | ||
271 | if (unlikely(err) && __clear_user(buf, xstate_size)) | |
272 | err = -EFAULT; | |
273 | return err; | |
274 | } | |
275 | ||
276 | /* | |
277 | * Save the fpu, extended register state to the user signal frame. | |
278 | * | |
279 | * 'buf_fx' is the 64-byte aligned pointer at which the [f|fx|x]save | |
280 | * state is copied. | |
281 | * 'buf' points to the 'buf_fx' or to the fsave header followed by 'buf_fx'. | |
282 | * | |
283 | * buf == buf_fx for 64-bit frames and 32-bit fsave frame. | |
284 | * buf != buf_fx for 32-bit frames with fxstate. | |
285 | * | |
286 | * If the fpu, extended register state is live, save the state directly | |
287 | * to the user frame pointed by the aligned pointer 'buf_fx'. Otherwise, | |
288 | * copy the thread's fpu state to the user frame starting at 'buf_fx'. | |
289 | * | |
290 | * If this is a 32-bit frame with fxstate, put a fsave header before | |
291 | * the aligned state at 'buf_fx'. | |
292 | * | |
293 | * For [f]xsave state, update the SW reserved fields in the [f]xsave frame | |
294 | * indicating the absence/presence of the extended state to the user. | |
295 | */ | |
296 | int save_xstate_sig(void __user *buf, void __user *buf_fx, int size) | |
297 | { | |
7366ed77 | 298 | struct xsave_struct *xsave = ¤t->thread.fpu.state.xsave; |
72a671ce SS |
299 | struct task_struct *tsk = current; |
300 | int ia32_fxstate = (buf != buf_fx); | |
301 | ||
302 | ia32_fxstate &= (config_enabled(CONFIG_X86_32) || | |
303 | config_enabled(CONFIG_IA32_EMULATION)); | |
304 | ||
305 | if (!access_ok(VERIFY_WRITE, buf, size)) | |
306 | return -EACCES; | |
307 | ||
60e019eb | 308 | if (!static_cpu_has(X86_FEATURE_FPU)) |
72a671ce SS |
309 | return fpregs_soft_get(current, NULL, 0, |
310 | sizeof(struct user_i387_ia32_struct), NULL, | |
311 | (struct _fpstate_ia32 __user *) buf) ? -1 : 1; | |
312 | ||
313 | if (user_has_fpu()) { | |
314 | /* Save the live register state to the user directly. */ | |
315 | if (save_user_xstate(buf_fx)) | |
316 | return -1; | |
317 | /* Update the thread's fxstate to save the fsave header. */ | |
318 | if (ia32_fxstate) | |
319 | fpu_fxsave(&tsk->thread.fpu); | |
ab513701 | 320 | } else { |
d0903193 | 321 | fpstate_sanitize_xstate(tsk); |
72a671ce | 322 | if (__copy_to_user(buf_fx, xsave, xstate_size)) |
ab513701 SS |
323 | return -1; |
324 | } | |
c37b5efe | 325 | |
72a671ce SS |
326 | /* Save the fsave header for the 32-bit frames. */ |
327 | if ((ia32_fxstate || !use_fxsr()) && save_fsave_header(tsk, buf)) | |
328 | return -1; | |
06c38d5e | 329 | |
72a671ce SS |
330 | if (use_fxsr() && save_xstate_epilog(buf_fx, ia32_fxstate)) |
331 | return -1; | |
332 | ||
72a671ce SS |
333 | return 0; |
334 | } | |
c37b5efe | 335 | |
72a671ce SS |
336 | static inline void |
337 | sanitize_restored_xstate(struct task_struct *tsk, | |
338 | struct user_i387_ia32_struct *ia32_env, | |
400e4b20 | 339 | u64 xfeatures, int fx_only) |
72a671ce | 340 | { |
7366ed77 | 341 | struct xsave_struct *xsave = &tsk->thread.fpu.state.xsave; |
3a54450b | 342 | struct xstate_header *header = &xsave->header; |
c37b5efe | 343 | |
72a671ce SS |
344 | if (use_xsave()) { |
345 | /* These bits must be zero. */ | |
3a54450b | 346 | memset(header->reserved, 0, 48); |
04944b79 SS |
347 | |
348 | /* | |
72a671ce SS |
349 | * Init the state that is not present in the memory |
350 | * layout and not enabled by the OS. | |
04944b79 | 351 | */ |
72a671ce | 352 | if (fx_only) |
400e4b20 | 353 | header->xfeatures = XSTATE_FPSSE; |
72a671ce | 354 | else |
400e4b20 | 355 | header->xfeatures &= (xfeatures_mask & xfeatures); |
72a671ce | 356 | } |
04944b79 | 357 | |
72a671ce | 358 | if (use_fxsr()) { |
04944b79 | 359 | /* |
72a671ce SS |
360 | * mscsr reserved bits must be masked to zero for security |
361 | * reasons. | |
04944b79 | 362 | */ |
72a671ce | 363 | xsave->i387.mxcsr &= mxcsr_feature_mask; |
04944b79 | 364 | |
72a671ce | 365 | convert_to_fxsr(tsk, ia32_env); |
c37b5efe | 366 | } |
ab513701 SS |
367 | } |
368 | ||
c37b5efe | 369 | /* |
72a671ce | 370 | * Restore the extended state if present. Otherwise, restore the FP/SSE state. |
c37b5efe | 371 | */ |
72a671ce | 372 | static inline int restore_user_xstate(void __user *buf, u64 xbv, int fx_only) |
c37b5efe | 373 | { |
72a671ce SS |
374 | if (use_xsave()) { |
375 | if ((unsigned long)buf % 64 || fx_only) { | |
614df7fb | 376 | u64 init_bv = xfeatures_mask & ~XSTATE_FPSSE; |
3e5e1267 | 377 | xrstor_state(&init_xstate_ctx, init_bv); |
e139e955 | 378 | return fxrstor_user(buf); |
72a671ce | 379 | } else { |
614df7fb | 380 | u64 init_bv = xfeatures_mask & ~xbv; |
72a671ce | 381 | if (unlikely(init_bv)) |
3e5e1267 | 382 | xrstor_state(&init_xstate_ctx, init_bv); |
72a671ce SS |
383 | return xrestore_user(buf, xbv); |
384 | } | |
385 | } else if (use_fxsr()) { | |
e139e955 | 386 | return fxrstor_user(buf); |
72a671ce | 387 | } else |
e139e955 | 388 | return frstor_user(buf); |
c37b5efe SS |
389 | } |
390 | ||
72a671ce | 391 | int __restore_xstate_sig(void __user *buf, void __user *buf_fx, int size) |
ab513701 | 392 | { |
72a671ce | 393 | int ia32_fxstate = (buf != buf_fx); |
ab513701 | 394 | struct task_struct *tsk = current; |
c5bedc68 | 395 | struct fpu *fpu = &tsk->thread.fpu; |
72a671ce | 396 | int state_size = xstate_size; |
400e4b20 | 397 | u64 xfeatures = 0; |
72a671ce SS |
398 | int fx_only = 0; |
399 | ||
400 | ia32_fxstate &= (config_enabled(CONFIG_X86_32) || | |
401 | config_enabled(CONFIG_IA32_EMULATION)); | |
ab513701 SS |
402 | |
403 | if (!buf) { | |
af2d94fd | 404 | fpu_reset_state(fpu); |
ab513701 | 405 | return 0; |
72a671ce SS |
406 | } |
407 | ||
408 | if (!access_ok(VERIFY_READ, buf, size)) | |
409 | return -EACCES; | |
410 | ||
c4d72e2d | 411 | fpu__activate_curr(fpu); |
ab513701 | 412 | |
60e019eb | 413 | if (!static_cpu_has(X86_FEATURE_FPU)) |
72a671ce SS |
414 | return fpregs_soft_set(current, NULL, |
415 | 0, sizeof(struct user_i387_ia32_struct), | |
416 | NULL, buf) != 0; | |
ab513701 | 417 | |
72a671ce SS |
418 | if (use_xsave()) { |
419 | struct _fpx_sw_bytes fx_sw_user; | |
420 | if (unlikely(check_for_xstate(buf_fx, buf_fx, &fx_sw_user))) { | |
421 | /* | |
422 | * Couldn't find the extended state information in the | |
423 | * memory layout. Restore just the FP/SSE and init all | |
424 | * the other extended state. | |
425 | */ | |
426 | state_size = sizeof(struct i387_fxsave_struct); | |
427 | fx_only = 1; | |
428 | } else { | |
429 | state_size = fx_sw_user.xstate_size; | |
400e4b20 | 430 | xfeatures = fx_sw_user.xfeatures; |
72a671ce SS |
431 | } |
432 | } | |
433 | ||
434 | if (ia32_fxstate) { | |
435 | /* | |
436 | * For 32-bit frames with fxstate, copy the user state to the | |
437 | * thread's fpu state, reconstruct fxstate from the fsave | |
438 | * header. Sanitize the copied state etc. | |
439 | */ | |
a7c80ebc | 440 | struct fpu *fpu = &tsk->thread.fpu; |
72a671ce | 441 | struct user_i387_ia32_struct env; |
304bceda | 442 | int err = 0; |
72a671ce | 443 | |
304bceda | 444 | /* |
c5bedc68 | 445 | * Drop the current fpu which clears fpu->fpstate_active. This ensures |
304bceda SS |
446 | * that any context-switch during the copy of the new state, |
447 | * avoids the intermediate state from getting restored/saved. | |
448 | * Thus avoiding the new restored state from getting corrupted. | |
449 | * We will be ready to restore/save the state only after | |
c5bedc68 | 450 | * fpu->fpstate_active is again set. |
304bceda | 451 | */ |
ca6787ba | 452 | drop_fpu(fpu); |
72a671ce | 453 | |
7366ed77 | 454 | if (__copy_from_user(&fpu->state.xsave, buf_fx, state_size) || |
304bceda | 455 | __copy_from_user(&env, buf, sizeof(env))) { |
c0ee2cf6 | 456 | fpstate_init(fpu); |
304bceda SS |
457 | err = -1; |
458 | } else { | |
400e4b20 | 459 | sanitize_restored_xstate(tsk, &env, xfeatures, fx_only); |
304bceda | 460 | } |
72a671ce | 461 | |
c5bedc68 | 462 | fpu->fpstate_active = 1; |
df24fb85 ON |
463 | if (use_eager_fpu()) { |
464 | preempt_disable(); | |
3a0aee48 | 465 | fpu__restore(); |
df24fb85 ON |
466 | preempt_enable(); |
467 | } | |
304bceda SS |
468 | |
469 | return err; | |
72a671ce | 470 | } else { |
ab513701 | 471 | /* |
72a671ce SS |
472 | * For 64-bit frames and 32-bit fsave frames, restore the user |
473 | * state to the registers directly (with exceptions handled). | |
ab513701 | 474 | */ |
72a671ce | 475 | user_fpu_begin(); |
400e4b20 | 476 | if (restore_user_xstate(buf_fx, xfeatures, fx_only)) { |
af2d94fd | 477 | fpu_reset_state(fpu); |
72a671ce SS |
478 | return -1; |
479 | } | |
ab513701 | 480 | } |
72a671ce SS |
481 | |
482 | return 0; | |
ab513701 | 483 | } |
ab513701 | 484 | |
c37b5efe SS |
485 | /* |
486 | * Prepare the SW reserved portion of the fxsave memory layout, indicating | |
487 | * the presence of the extended state information in the memory layout | |
488 | * pointed by the fpstate pointer in the sigcontext. | |
489 | * This will be saved when ever the FP and extended state context is | |
490 | * saved on the user stack during the signal handler delivery to the user. | |
491 | */ | |
8bcad30f | 492 | static void prepare_fx_sw_frame(void) |
c37b5efe | 493 | { |
72a671ce SS |
494 | int fsave_header_size = sizeof(struct i387_fsave_struct); |
495 | int size = xstate_size + FP_XSTATE_MAGIC2_SIZE; | |
c37b5efe | 496 | |
72a671ce SS |
497 | if (config_enabled(CONFIG_X86_32)) |
498 | size += fsave_header_size; | |
c37b5efe SS |
499 | |
500 | fx_sw_reserved.magic1 = FP_XSTATE_MAGIC1; | |
72a671ce | 501 | fx_sw_reserved.extended_size = size; |
400e4b20 | 502 | fx_sw_reserved.xfeatures = xfeatures_mask; |
c37b5efe | 503 | fx_sw_reserved.xstate_size = xstate_size; |
c37b5efe | 504 | |
72a671ce SS |
505 | if (config_enabled(CONFIG_IA32_EMULATION)) { |
506 | fx_sw_reserved_ia32 = fx_sw_reserved; | |
507 | fx_sw_reserved_ia32.extended_size += fsave_header_size; | |
508 | } | |
509 | } | |
3c1c7f10 | 510 | |
dc1e35c6 | 511 | /* |
55cc4678 IM |
512 | * Enable the extended processor state save/restore feature. |
513 | * Called once per CPU onlining. | |
dc1e35c6 | 514 | */ |
55cc4678 | 515 | void fpu__init_cpu_xstate(void) |
dc1e35c6 | 516 | { |
e84611fc | 517 | if (!cpu_has_xsave || !xfeatures_mask) |
55cc4678 IM |
518 | return; |
519 | ||
375074cc | 520 | cr4_set_bits(X86_CR4_OSXSAVE); |
614df7fb | 521 | xsetbv(XCR_XFEATURE_ENABLED_MASK, xfeatures_mask); |
dc1e35c6 SS |
522 | } |
523 | ||
a1488f8b SS |
524 | /* |
525 | * Record the offsets and sizes of different state managed by the xsave | |
526 | * memory layout. | |
527 | */ | |
4995b9db | 528 | static void __init setup_xstate_features(void) |
a1488f8b SS |
529 | { |
530 | int eax, ebx, ecx, edx, leaf = 0x2; | |
531 | ||
84246fe4 | 532 | xfeatures_nr = fls64(xfeatures_mask); |
a1488f8b SS |
533 | |
534 | do { | |
ee813d53 | 535 | cpuid_count(XSTATE_CPUID, leaf, &eax, &ebx, &ecx, &edx); |
a1488f8b SS |
536 | |
537 | if (eax == 0) | |
538 | break; | |
539 | ||
540 | xstate_offsets[leaf] = ebx; | |
541 | xstate_sizes[leaf] = eax; | |
542 | ||
543 | leaf++; | |
544 | } while (1); | |
545 | } | |
546 | ||
33588b52 | 547 | static void print_xstate_feature(u64 xstate_mask) |
69496e10 | 548 | { |
33588b52 | 549 | const char *feature_name; |
69496e10 | 550 | |
33588b52 IM |
551 | if (cpu_has_xfeatures(xstate_mask, &feature_name)) |
552 | pr_info("x86/fpu: Supporting XSAVE feature 0x%02Lx: '%s'\n", xstate_mask, feature_name); | |
69496e10 IM |
553 | } |
554 | ||
555 | /* | |
556 | * Print out all the supported xstate features: | |
557 | */ | |
558 | static void print_xstate_features(void) | |
559 | { | |
33588b52 IM |
560 | print_xstate_feature(XSTATE_FP); |
561 | print_xstate_feature(XSTATE_SSE); | |
562 | print_xstate_feature(XSTATE_YMM); | |
563 | print_xstate_feature(XSTATE_BNDREGS); | |
564 | print_xstate_feature(XSTATE_BNDCSR); | |
565 | print_xstate_feature(XSTATE_OPMASK); | |
566 | print_xstate_feature(XSTATE_ZMM_Hi256); | |
567 | print_xstate_feature(XSTATE_Hi16_ZMM); | |
69496e10 IM |
568 | } |
569 | ||
7496d645 FY |
570 | /* |
571 | * This function sets up offsets and sizes of all extended states in | |
572 | * xsave area. This supports both standard format and compacted format | |
573 | * of the xsave aread. | |
574 | * | |
575 | * Input: void | |
576 | * Output: void | |
577 | */ | |
578 | void setup_xstate_comp(void) | |
579 | { | |
614df7fb | 580 | unsigned int xstate_comp_sizes[sizeof(xfeatures_mask)*8]; |
7496d645 FY |
581 | int i; |
582 | ||
8ff925e1 FY |
583 | /* |
584 | * The FP xstates and SSE xstates are legacy states. They are always | |
585 | * in the fixed offsets in the xsave area in either compacted form | |
586 | * or standard form. | |
587 | */ | |
588 | xstate_comp_offsets[0] = 0; | |
589 | xstate_comp_offsets[1] = offsetof(struct i387_fxsave_struct, xmm_space); | |
7496d645 FY |
590 | |
591 | if (!cpu_has_xsaves) { | |
84246fe4 | 592 | for (i = 2; i < xfeatures_nr; i++) { |
614df7fb | 593 | if (test_bit(i, (unsigned long *)&xfeatures_mask)) { |
7496d645 FY |
594 | xstate_comp_offsets[i] = xstate_offsets[i]; |
595 | xstate_comp_sizes[i] = xstate_sizes[i]; | |
596 | } | |
597 | } | |
598 | return; | |
599 | } | |
600 | ||
601 | xstate_comp_offsets[2] = FXSAVE_SIZE + XSAVE_HDR_SIZE; | |
602 | ||
84246fe4 | 603 | for (i = 2; i < xfeatures_nr; i++) { |
614df7fb | 604 | if (test_bit(i, (unsigned long *)&xfeatures_mask)) |
7496d645 FY |
605 | xstate_comp_sizes[i] = xstate_sizes[i]; |
606 | else | |
607 | xstate_comp_sizes[i] = 0; | |
608 | ||
609 | if (i > 2) | |
610 | xstate_comp_offsets[i] = xstate_comp_offsets[i-1] | |
611 | + xstate_comp_sizes[i-1]; | |
612 | ||
613 | } | |
614 | } | |
615 | ||
dc1e35c6 SS |
616 | /* |
617 | * setup the xstate image representing the init state | |
618 | */ | |
26b1f5d0 | 619 | static void setup_init_fpu_buf(void) |
dc1e35c6 | 620 | { |
26b1f5d0 IM |
621 | static int on_boot_cpu = 1; |
622 | ||
623 | if (!on_boot_cpu) | |
624 | return; | |
625 | on_boot_cpu = 0; | |
626 | ||
5d2bd700 SS |
627 | if (!cpu_has_xsave) |
628 | return; | |
629 | ||
630 | setup_xstate_features(); | |
69496e10 | 631 | print_xstate_features(); |
a1488f8b | 632 | |
47c2f292 | 633 | if (cpu_has_xsaves) { |
3e5e1267 IM |
634 | init_xstate_ctx.header.xcomp_bv = (u64)1 << 63 | xfeatures_mask; |
635 | init_xstate_ctx.header.xfeatures = xfeatures_mask; | |
47c2f292 FY |
636 | } |
637 | ||
29104e10 SS |
638 | /* |
639 | * Init all the features state with header_bv being 0x0 | |
640 | */ | |
3e5e1267 | 641 | xrstor_state_booting(&init_xstate_ctx, -1); |
3e261c14 | 642 | |
29104e10 SS |
643 | /* |
644 | * Dump the init state again. This is to identify the init state | |
645 | * of any feature which is not represented by all zero's. | |
646 | */ | |
3e5e1267 | 647 | xsave_state_booting(&init_xstate_ctx); |
dc1e35c6 SS |
648 | } |
649 | ||
7e7ce87f | 650 | /* |
614df7fb | 651 | * Calculate total size of enabled xstates in XCR0/xfeatures_mask. |
7e7ce87f FY |
652 | */ |
653 | static void __init init_xstate_size(void) | |
654 | { | |
655 | unsigned int eax, ebx, ecx, edx; | |
656 | int i; | |
657 | ||
658 | if (!cpu_has_xsaves) { | |
659 | cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx); | |
660 | xstate_size = ebx; | |
661 | return; | |
662 | } | |
663 | ||
664 | xstate_size = FXSAVE_SIZE + XSAVE_HDR_SIZE; | |
665 | for (i = 2; i < 64; i++) { | |
614df7fb | 666 | if (test_bit(i, (unsigned long *)&xfeatures_mask)) { |
7e7ce87f FY |
667 | cpuid_count(XSTATE_CPUID, i, &eax, &ebx, &ecx, &edx); |
668 | xstate_size += eax; | |
669 | } | |
670 | } | |
671 | } | |
672 | ||
dc1e35c6 SS |
673 | /* |
674 | * Enable and initialize the xsave feature. | |
55cc4678 | 675 | * Called once per system bootup. |
c0841e34 | 676 | * |
c42103b2 | 677 | * ( Not marked __init because of false positive section warnings. ) |
dc1e35c6 | 678 | */ |
55cc4678 | 679 | void fpu__init_system_xstate(void) |
dc1e35c6 SS |
680 | { |
681 | unsigned int eax, ebx, ecx, edx; | |
62db6871 IM |
682 | static bool on_boot_cpu = 1; |
683 | ||
684 | if (!on_boot_cpu) | |
685 | return; | |
686 | on_boot_cpu = 0; | |
dc1e35c6 | 687 | |
e9dbfd67 IM |
688 | if (!cpu_has_xsave) { |
689 | pr_info("x86/fpu: Legacy x87 FPU detected.\n"); | |
690 | return; | |
691 | } | |
692 | ||
ee813d53 | 693 | if (boot_cpu_data.cpuid_level < XSTATE_CPUID) { |
32d4d9cc | 694 | WARN(1, "x86/fpu: XSTATE_CPUID missing!\n"); |
ee813d53 RR |
695 | return; |
696 | } | |
697 | ||
698 | cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx); | |
614df7fb | 699 | xfeatures_mask = eax + ((u64)edx << 32); |
dc1e35c6 | 700 | |
614df7fb IM |
701 | if ((xfeatures_mask & XSTATE_FPSSE) != XSTATE_FPSSE) { |
702 | pr_err("x86/fpu: FP/SSE not present amongst the CPU's xstate features: 0x%llx.\n", xfeatures_mask); | |
dc1e35c6 SS |
703 | BUG(); |
704 | } | |
705 | ||
706 | /* | |
a30469e7 | 707 | * Support only the state known to OS. |
dc1e35c6 | 708 | */ |
614df7fb | 709 | xfeatures_mask = xfeatures_mask & XCNTXT_MASK; |
97e80a70 | 710 | |
55cc4678 IM |
711 | /* Enable xstate instructions to be able to continue with initialization: */ |
712 | fpu__init_cpu_xstate(); | |
dc1e35c6 SS |
713 | |
714 | /* | |
715 | * Recompute the context size for enabled features | |
716 | */ | |
7e7ce87f | 717 | init_xstate_size(); |
dc1e35c6 | 718 | |
614df7fb | 719 | update_regset_xstate_info(xstate_size, xfeatures_mask); |
c37b5efe | 720 | prepare_fx_sw_frame(); |
5d2bd700 | 721 | setup_init_fpu_buf(); |
dc1e35c6 | 722 | |
32d4d9cc | 723 | pr_info("x86/fpu: Enabled xstate features 0x%llx, context size is 0x%x bytes, using '%s' format.\n", |
614df7fb | 724 | xfeatures_mask, |
32d4d9cc IM |
725 | xstate_size, |
726 | cpu_has_xsaves ? "compacted" : "standard"); | |
dc1e35c6 | 727 | } |
82d4150c | 728 | |
9254aaa0 IM |
729 | /* |
730 | * Restore minimal FPU state after suspend: | |
731 | */ | |
732 | void fpu__resume_cpu(void) | |
733 | { | |
734 | /* | |
735 | * Restore XCR0 on xsave capable CPUs: | |
736 | */ | |
737 | if (cpu_has_xsave) | |
738 | xsetbv(XCR_XFEATURE_ENABLED_MASK, xfeatures_mask); | |
739 | } | |
740 | ||
7496d645 FY |
741 | /* |
742 | * Given the xsave area and a state inside, this function returns the | |
743 | * address of the state. | |
744 | * | |
745 | * This is the API that is called to get xstate address in either | |
746 | * standard format or compacted format of xsave area. | |
747 | * | |
748 | * Inputs: | |
749 | * xsave: base address of the xsave area; | |
750 | * xstate: state which is defined in xsave.h (e.g. XSTATE_FP, XSTATE_SSE, | |
751 | * etc.) | |
752 | * Output: | |
753 | * address of the state in the xsave area. | |
754 | */ | |
755 | void *get_xsave_addr(struct xsave_struct *xsave, int xstate) | |
756 | { | |
757 | int feature = fls64(xstate) - 1; | |
614df7fb | 758 | if (!test_bit(feature, (unsigned long *)&xfeatures_mask)) |
7496d645 FY |
759 | return NULL; |
760 | ||
761 | return (void *)xsave + xstate_comp_offsets[feature]; | |
762 | } | |
ba7b3920 | 763 | EXPORT_SYMBOL_GPL(get_xsave_addr); |