Commit | Line | Data |
---|---|---|
dc1e35c6 SS |
1 | /* |
2 | * xsave/xrstor support. | |
3 | * | |
4 | * Author: Suresh Siddha <suresh.b.siddha@intel.com> | |
5 | */ | |
dc1e35c6 | 6 | #include <linux/compat.h> |
7e7ce87f | 7 | #include <linux/cpu.h> |
59a36d16 | 8 | |
df6b35f4 | 9 | #include <asm/fpu/api.h> |
78f7f1e5 | 10 | #include <asm/fpu/internal.h> |
fcbc99c4 | 11 | #include <asm/fpu/signal.h> |
59a36d16 | 12 | #include <asm/fpu/regset.h> |
b992c660 | 13 | |
375074cc | 14 | #include <asm/tlbflush.h> |
dc1e35c6 | 15 | |
5b073430 IM |
16 | static const char *xfeature_names[] = |
17 | { | |
18 | "x87 floating point registers" , | |
19 | "SSE registers" , | |
20 | "AVX registers" , | |
21 | "MPX bounds registers" , | |
22 | "MPX CSR" , | |
23 | "AVX-512 opmask" , | |
24 | "AVX-512 Hi256" , | |
25 | "AVX-512 ZMM_Hi256" , | |
26 | "unknown xstate feature" , | |
27 | }; | |
28 | ||
dc1e35c6 | 29 | /* |
614df7fb | 30 | * Mask of xstate features supported by the CPU and the kernel: |
dc1e35c6 | 31 | */ |
5b073430 | 32 | u64 xfeatures_mask __read_mostly; |
dc1e35c6 | 33 | |
966ece61 | 34 | static unsigned int xstate_offsets[XFEATURES_NR_MAX], xstate_sizes[XFEATURES_NR_MAX]; |
614df7fb | 35 | static unsigned int xstate_comp_offsets[sizeof(xfeatures_mask)*8]; |
84246fe4 IM |
36 | |
37 | /* The number of supported xfeatures in xfeatures_mask: */ | |
38 | static unsigned int xfeatures_nr; | |
a1488f8b | 39 | |
5b073430 IM |
40 | /* |
41 | * Return whether the system supports a given xfeature. | |
42 | * | |
43 | * Also return the name of the (most advanced) feature that the caller requested: | |
44 | */ | |
45 | int cpu_has_xfeatures(u64 xfeatures_needed, const char **feature_name) | |
46 | { | |
47 | u64 xfeatures_missing = xfeatures_needed & ~xfeatures_mask; | |
48 | ||
49 | if (unlikely(feature_name)) { | |
50 | long xfeature_idx, max_idx; | |
51 | u64 xfeatures_print; | |
52 | /* | |
53 | * So we use FLS here to be able to print the most advanced | |
54 | * feature that was requested but is missing. So if a driver | |
55 | * asks about "XSTATE_SSE | XSTATE_YMM" we'll print the | |
56 | * missing AVX feature - this is the most informative message | |
57 | * to users: | |
58 | */ | |
59 | if (xfeatures_missing) | |
60 | xfeatures_print = xfeatures_missing; | |
61 | else | |
62 | xfeatures_print = xfeatures_needed; | |
63 | ||
64 | xfeature_idx = fls64(xfeatures_print)-1; | |
65 | max_idx = ARRAY_SIZE(xfeature_names)-1; | |
66 | xfeature_idx = min(xfeature_idx, max_idx); | |
67 | ||
68 | *feature_name = xfeature_names[xfeature_idx]; | |
69 | } | |
70 | ||
71 | if (xfeatures_missing) | |
72 | return 0; | |
73 | ||
74 | return 1; | |
75 | } | |
76 | EXPORT_SYMBOL_GPL(cpu_has_xfeatures); | |
77 | ||
29104e10 | 78 | /* |
aeb997b9 IM |
79 | * When executing XSAVEOPT (or other optimized XSAVE instructions), if |
80 | * a processor implementation detects that an FPU state component is still | |
81 | * (or is again) in its initialized state, it may clear the corresponding | |
82 | * bit in the header.xfeatures field, and can skip the writeout of registers | |
83 | * to the corresponding memory layout. | |
73a3aeb3 IM |
84 | * |
85 | * This means that when the bit is zero, the state component might still contain | |
86 | * some previous - non-initialized register state. | |
87 | * | |
88 | * Before writing xstate information to user-space we sanitize those components, | |
89 | * to always ensure that the memory layout of a feature will be in the init state | |
90 | * if the corresponding header bit is zero. This is to ensure that user-space doesn't | |
91 | * see some stale state in the memory layout during signal handling, debugging etc. | |
29104e10 | 92 | */ |
36e49e7f | 93 | void fpstate_sanitize_xstate(struct fpu *fpu) |
29104e10 | 94 | { |
c47ada30 | 95 | struct fxregs_state *fx = &fpu->state.fxsave; |
73a3aeb3 | 96 | int feature_bit; |
400e4b20 | 97 | u64 xfeatures; |
29104e10 | 98 | |
1ac91a76 | 99 | if (!use_xsaveopt()) |
29104e10 SS |
100 | return; |
101 | ||
36e49e7f | 102 | xfeatures = fpu->state.xsave.header.xfeatures; |
29104e10 SS |
103 | |
104 | /* | |
105 | * None of the feature bits are in init state. So nothing else | |
0d2eb44f | 106 | * to do for us, as the memory layout is up to date. |
29104e10 | 107 | */ |
400e4b20 | 108 | if ((xfeatures & xfeatures_mask) == xfeatures_mask) |
29104e10 SS |
109 | return; |
110 | ||
111 | /* | |
112 | * FP is in init state | |
113 | */ | |
400e4b20 | 114 | if (!(xfeatures & XSTATE_FP)) { |
29104e10 SS |
115 | fx->cwd = 0x37f; |
116 | fx->swd = 0; | |
117 | fx->twd = 0; | |
118 | fx->fop = 0; | |
119 | fx->rip = 0; | |
120 | fx->rdp = 0; | |
121 | memset(&fx->st_space[0], 0, 128); | |
122 | } | |
123 | ||
124 | /* | |
125 | * SSE is in init state | |
126 | */ | |
400e4b20 | 127 | if (!(xfeatures & XSTATE_SSE)) |
29104e10 SS |
128 | memset(&fx->xmm_space[0], 0, 256); |
129 | ||
73a3aeb3 IM |
130 | /* |
131 | * First two features are FPU and SSE, which above we handled | |
132 | * in a special way already: | |
133 | */ | |
134 | feature_bit = 0x2; | |
400e4b20 | 135 | xfeatures = (xfeatures_mask & ~xfeatures) >> 2; |
29104e10 SS |
136 | |
137 | /* | |
73a3aeb3 IM |
138 | * Update all the remaining memory layouts according to their |
139 | * standard xstate layout, if their header bit is in the init | |
140 | * state: | |
29104e10 | 141 | */ |
400e4b20 IM |
142 | while (xfeatures) { |
143 | if (xfeatures & 0x1) { | |
29104e10 SS |
144 | int offset = xstate_offsets[feature_bit]; |
145 | int size = xstate_sizes[feature_bit]; | |
146 | ||
73a3aeb3 | 147 | memcpy((void *)fx + offset, |
6f575023 | 148 | (void *)&init_fpstate.xsave + offset, |
29104e10 SS |
149 | size); |
150 | } | |
151 | ||
400e4b20 | 152 | xfeatures >>= 1; |
29104e10 SS |
153 | feature_bit++; |
154 | } | |
155 | } | |
156 | ||
dc1e35c6 | 157 | /* |
55cc4678 IM |
158 | * Enable the extended processor state save/restore feature. |
159 | * Called once per CPU onlining. | |
dc1e35c6 | 160 | */ |
55cc4678 | 161 | void fpu__init_cpu_xstate(void) |
dc1e35c6 | 162 | { |
e84611fc | 163 | if (!cpu_has_xsave || !xfeatures_mask) |
55cc4678 IM |
164 | return; |
165 | ||
375074cc | 166 | cr4_set_bits(X86_CR4_OSXSAVE); |
614df7fb | 167 | xsetbv(XCR_XFEATURE_ENABLED_MASK, xfeatures_mask); |
dc1e35c6 SS |
168 | } |
169 | ||
a1488f8b | 170 | /* |
39f1acd2 IM |
171 | * Record the offsets and sizes of various xstates contained |
172 | * in the XSAVE state memory layout. | |
173 | * | |
174 | * ( Note that certain features might be non-present, for them | |
175 | * we'll have 0 offset and 0 size. ) | |
a1488f8b | 176 | */ |
4995b9db | 177 | static void __init setup_xstate_features(void) |
a1488f8b | 178 | { |
39f1acd2 | 179 | u32 eax, ebx, ecx, edx, leaf; |
a1488f8b | 180 | |
84246fe4 | 181 | xfeatures_nr = fls64(xfeatures_mask); |
a1488f8b | 182 | |
39f1acd2 | 183 | for (leaf = 2; leaf < xfeatures_nr; leaf++) { |
ee813d53 | 184 | cpuid_count(XSTATE_CPUID, leaf, &eax, &ebx, &ecx, &edx); |
a1488f8b | 185 | |
a1488f8b SS |
186 | xstate_offsets[leaf] = ebx; |
187 | xstate_sizes[leaf] = eax; | |
188 | ||
39f1acd2 | 189 | printk(KERN_INFO "x86/fpu: xstate_offset[%d]: %04x, xstate_sizes[%d]: %04x\n", leaf, ebx, leaf, eax); |
a1488f8b | 190 | leaf++; |
39f1acd2 | 191 | } |
a1488f8b SS |
192 | } |
193 | ||
32231879 | 194 | static void __init print_xstate_feature(u64 xstate_mask) |
69496e10 | 195 | { |
33588b52 | 196 | const char *feature_name; |
69496e10 | 197 | |
33588b52 IM |
198 | if (cpu_has_xfeatures(xstate_mask, &feature_name)) |
199 | pr_info("x86/fpu: Supporting XSAVE feature 0x%02Lx: '%s'\n", xstate_mask, feature_name); | |
69496e10 IM |
200 | } |
201 | ||
202 | /* | |
203 | * Print out all the supported xstate features: | |
204 | */ | |
32231879 | 205 | static void __init print_xstate_features(void) |
69496e10 | 206 | { |
33588b52 IM |
207 | print_xstate_feature(XSTATE_FP); |
208 | print_xstate_feature(XSTATE_SSE); | |
209 | print_xstate_feature(XSTATE_YMM); | |
210 | print_xstate_feature(XSTATE_BNDREGS); | |
211 | print_xstate_feature(XSTATE_BNDCSR); | |
212 | print_xstate_feature(XSTATE_OPMASK); | |
213 | print_xstate_feature(XSTATE_ZMM_Hi256); | |
214 | print_xstate_feature(XSTATE_Hi16_ZMM); | |
69496e10 IM |
215 | } |
216 | ||
7496d645 FY |
217 | /* |
218 | * This function sets up offsets and sizes of all extended states in | |
219 | * xsave area. This supports both standard format and compacted format | |
220 | * of the xsave aread. | |
7496d645 | 221 | */ |
32231879 | 222 | static void __init setup_xstate_comp(void) |
7496d645 | 223 | { |
614df7fb | 224 | unsigned int xstate_comp_sizes[sizeof(xfeatures_mask)*8]; |
7496d645 FY |
225 | int i; |
226 | ||
8ff925e1 FY |
227 | /* |
228 | * The FP xstates and SSE xstates are legacy states. They are always | |
229 | * in the fixed offsets in the xsave area in either compacted form | |
230 | * or standard form. | |
231 | */ | |
232 | xstate_comp_offsets[0] = 0; | |
c47ada30 | 233 | xstate_comp_offsets[1] = offsetof(struct fxregs_state, xmm_space); |
7496d645 FY |
234 | |
235 | if (!cpu_has_xsaves) { | |
84246fe4 | 236 | for (i = 2; i < xfeatures_nr; i++) { |
614df7fb | 237 | if (test_bit(i, (unsigned long *)&xfeatures_mask)) { |
7496d645 FY |
238 | xstate_comp_offsets[i] = xstate_offsets[i]; |
239 | xstate_comp_sizes[i] = xstate_sizes[i]; | |
240 | } | |
241 | } | |
242 | return; | |
243 | } | |
244 | ||
245 | xstate_comp_offsets[2] = FXSAVE_SIZE + XSAVE_HDR_SIZE; | |
246 | ||
84246fe4 | 247 | for (i = 2; i < xfeatures_nr; i++) { |
614df7fb | 248 | if (test_bit(i, (unsigned long *)&xfeatures_mask)) |
7496d645 FY |
249 | xstate_comp_sizes[i] = xstate_sizes[i]; |
250 | else | |
251 | xstate_comp_sizes[i] = 0; | |
252 | ||
253 | if (i > 2) | |
254 | xstate_comp_offsets[i] = xstate_comp_offsets[i-1] | |
255 | + xstate_comp_sizes[i-1]; | |
256 | ||
257 | } | |
258 | } | |
259 | ||
dc1e35c6 SS |
260 | /* |
261 | * setup the xstate image representing the init state | |
262 | */ | |
32231879 | 263 | static void __init setup_init_fpu_buf(void) |
dc1e35c6 | 264 | { |
e97131a8 IM |
265 | static int on_boot_cpu = 1; |
266 | ||
267 | WARN_ON_FPU(!on_boot_cpu); | |
268 | on_boot_cpu = 0; | |
269 | ||
5d2bd700 SS |
270 | if (!cpu_has_xsave) |
271 | return; | |
272 | ||
273 | setup_xstate_features(); | |
69496e10 | 274 | print_xstate_features(); |
a1488f8b | 275 | |
47c2f292 | 276 | if (cpu_has_xsaves) { |
6f575023 IM |
277 | init_fpstate.xsave.header.xcomp_bv = (u64)1 << 63 | xfeatures_mask; |
278 | init_fpstate.xsave.header.xfeatures = xfeatures_mask; | |
47c2f292 FY |
279 | } |
280 | ||
29104e10 SS |
281 | /* |
282 | * Init all the features state with header_bv being 0x0 | |
283 | */ | |
d65fcd60 | 284 | copy_kernel_to_xregs_booting(&init_fpstate.xsave); |
3e261c14 | 285 | |
29104e10 SS |
286 | /* |
287 | * Dump the init state again. This is to identify the init state | |
288 | * of any feature which is not represented by all zero's. | |
289 | */ | |
c6813144 | 290 | copy_xregs_to_kernel_booting(&init_fpstate.xsave); |
dc1e35c6 SS |
291 | } |
292 | ||
7e7ce87f | 293 | /* |
614df7fb | 294 | * Calculate total size of enabled xstates in XCR0/xfeatures_mask. |
7e7ce87f FY |
295 | */ |
296 | static void __init init_xstate_size(void) | |
297 | { | |
298 | unsigned int eax, ebx, ecx, edx; | |
299 | int i; | |
300 | ||
301 | if (!cpu_has_xsaves) { | |
302 | cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx); | |
303 | xstate_size = ebx; | |
304 | return; | |
305 | } | |
306 | ||
307 | xstate_size = FXSAVE_SIZE + XSAVE_HDR_SIZE; | |
308 | for (i = 2; i < 64; i++) { | |
614df7fb | 309 | if (test_bit(i, (unsigned long *)&xfeatures_mask)) { |
7e7ce87f FY |
310 | cpuid_count(XSTATE_CPUID, i, &eax, &ebx, &ecx, &edx); |
311 | xstate_size += eax; | |
312 | } | |
313 | } | |
314 | } | |
315 | ||
dc1e35c6 SS |
316 | /* |
317 | * Enable and initialize the xsave feature. | |
55cc4678 | 318 | * Called once per system bootup. |
dc1e35c6 | 319 | */ |
32231879 | 320 | void __init fpu__init_system_xstate(void) |
dc1e35c6 SS |
321 | { |
322 | unsigned int eax, ebx, ecx, edx; | |
e97131a8 IM |
323 | static int on_boot_cpu = 1; |
324 | ||
325 | WARN_ON_FPU(!on_boot_cpu); | |
326 | on_boot_cpu = 0; | |
dc1e35c6 | 327 | |
e9dbfd67 IM |
328 | if (!cpu_has_xsave) { |
329 | pr_info("x86/fpu: Legacy x87 FPU detected.\n"); | |
330 | return; | |
331 | } | |
332 | ||
ee813d53 | 333 | if (boot_cpu_data.cpuid_level < XSTATE_CPUID) { |
e97131a8 | 334 | WARN_ON_FPU(1); |
ee813d53 RR |
335 | return; |
336 | } | |
337 | ||
338 | cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx); | |
614df7fb | 339 | xfeatures_mask = eax + ((u64)edx << 32); |
dc1e35c6 | 340 | |
614df7fb IM |
341 | if ((xfeatures_mask & XSTATE_FPSSE) != XSTATE_FPSSE) { |
342 | pr_err("x86/fpu: FP/SSE not present amongst the CPU's xstate features: 0x%llx.\n", xfeatures_mask); | |
dc1e35c6 SS |
343 | BUG(); |
344 | } | |
345 | ||
6e553594 | 346 | /* Support only the state known to the OS: */ |
614df7fb | 347 | xfeatures_mask = xfeatures_mask & XCNTXT_MASK; |
97e80a70 | 348 | |
55cc4678 IM |
349 | /* Enable xstate instructions to be able to continue with initialization: */ |
350 | fpu__init_cpu_xstate(); | |
dc1e35c6 | 351 | |
6e553594 | 352 | /* Recompute the context size for enabled features: */ |
7e7ce87f | 353 | init_xstate_size(); |
dc1e35c6 | 354 | |
614df7fb | 355 | update_regset_xstate_info(xstate_size, xfeatures_mask); |
b992c660 | 356 | fpu__init_prepare_fx_sw_frame(); |
5d2bd700 | 357 | setup_init_fpu_buf(); |
5fd402df | 358 | setup_xstate_comp(); |
dc1e35c6 | 359 | |
32d4d9cc | 360 | pr_info("x86/fpu: Enabled xstate features 0x%llx, context size is 0x%x bytes, using '%s' format.\n", |
614df7fb | 361 | xfeatures_mask, |
32d4d9cc IM |
362 | xstate_size, |
363 | cpu_has_xsaves ? "compacted" : "standard"); | |
dc1e35c6 | 364 | } |
82d4150c | 365 | |
9254aaa0 IM |
366 | /* |
367 | * Restore minimal FPU state after suspend: | |
368 | */ | |
369 | void fpu__resume_cpu(void) | |
370 | { | |
371 | /* | |
372 | * Restore XCR0 on xsave capable CPUs: | |
373 | */ | |
374 | if (cpu_has_xsave) | |
375 | xsetbv(XCR_XFEATURE_ENABLED_MASK, xfeatures_mask); | |
376 | } | |
377 | ||
7496d645 FY |
378 | /* |
379 | * Given the xsave area and a state inside, this function returns the | |
380 | * address of the state. | |
381 | * | |
382 | * This is the API that is called to get xstate address in either | |
383 | * standard format or compacted format of xsave area. | |
384 | * | |
385 | * Inputs: | |
386 | * xsave: base address of the xsave area; | |
387 | * xstate: state which is defined in xsave.h (e.g. XSTATE_FP, XSTATE_SSE, | |
388 | * etc.) | |
389 | * Output: | |
390 | * address of the state in the xsave area. | |
391 | */ | |
c47ada30 | 392 | void *get_xsave_addr(struct xregs_state *xsave, int xstate) |
7496d645 FY |
393 | { |
394 | int feature = fls64(xstate) - 1; | |
614df7fb | 395 | if (!test_bit(feature, (unsigned long *)&xfeatures_mask)) |
7496d645 FY |
396 | return NULL; |
397 | ||
398 | return (void *)xsave + xstate_comp_offsets[feature]; | |
399 | } | |
ba7b3920 | 400 | EXPORT_SYMBOL_GPL(get_xsave_addr); |